From 4c8b00402941d7d5bc8221b87a9801b2a49bd59b Mon Sep 17 00:00:00 2001 From: Liphen Date: Mon, 27 Nov 2023 14:18:11 +0800 Subject: [PATCH] =?UTF-8?q?=E4=BF=AE=E6=94=B9commit=E4=BF=A1=E5=8F=B7?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/pipeline/memory/MemoryUnit.scala | 2 ++ chisel/playground/src/pipeline/writeback/WriteBackStage.scala | 1 + chisel/playground/src/pipeline/writeback/WriteBackUnit.scala | 4 ++-- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/chisel/playground/src/pipeline/memory/MemoryUnit.scala b/chisel/playground/src/pipeline/memory/MemoryUnit.scala index 81c49be..9732dda 100644 --- a/chisel/playground/src/pipeline/memory/MemoryUnit.scala +++ b/chisel/playground/src/pipeline/memory/MemoryUnit.scala @@ -58,6 +58,7 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module { io.writeBackStage.inst0.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata io.writeBackStage.inst0.ex := io.memoryStage.inst0.ex io.writeBackStage.inst0.ex.exception := io.memoryStage.inst0.ex.exception + io.writeBackStage.inst0.commit := io.memoryStage.inst0.inst_info.valid io.writeBackStage.inst1.pc := io.memoryStage.inst1.pc io.writeBackStage.inst1.inst_info := io.memoryStage.inst1.inst_info @@ -65,6 +66,7 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module { io.writeBackStage.inst1.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata io.writeBackStage.inst1.ex := io.memoryStage.inst1.ex io.writeBackStage.inst1.ex.exception := io.memoryStage.inst1.ex.exception + io.writeBackStage.inst1.commit := io.memoryStage.inst1.inst_info.valid io.csr.in.inst(0).pc := io.writeBackStage.inst0.pc io.csr.in.inst(0).ex := io.writeBackStage.inst0.ex diff --git a/chisel/playground/src/pipeline/writeback/WriteBackStage.scala b/chisel/playground/src/pipeline/writeback/WriteBackStage.scala index 1e95849..8e7e360 100644 --- a/chisel/playground/src/pipeline/writeback/WriteBackStage.scala +++ b/chisel/playground/src/pipeline/writeback/WriteBackStage.scala @@ -10,6 +10,7 @@ class MemWbInst extends Bundle { val pc = UInt(PC_WID.W) val inst_info = new InstInfo() val rd_info = new RdInfo() + val commit = Bool() val ex = new ExceptionInfo() } diff --git a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala index 243fdfd..28b6ebc 100644 --- a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala +++ b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala @@ -29,11 +29,11 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module { if (config.hasCommitBuffer) { val buffer = Module(new CommitBuffer()).io buffer.enq(0).wb_pc := io.writeBackStage.inst0.pc - buffer.enq(0).wb_rf_wen := io.regfile(0).wen + buffer.enq(0).wb_rf_wen := io.regfile(0).wen || io.writeBackStage.inst0.commit buffer.enq(0).wb_rf_wnum := io.regfile(0).waddr buffer.enq(0).wb_rf_wdata := io.regfile(0).wdata buffer.enq(1).wb_pc := io.writeBackStage.inst1.pc - buffer.enq(1).wb_rf_wen := io.regfile(1).wen + buffer.enq(1).wb_rf_wen := io.regfile(1).wen || io.writeBackStage.inst1.commit buffer.enq(1).wb_rf_wnum := io.regfile(1).waddr buffer.enq(1).wb_rf_wdata := io.regfile(1).wdata buffer.flush := io.ctrl.do_flush