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修改debug信号的wen为commit

This commit is contained in:
Liphen 2024-05-09 19:16:02 +08:00
parent be93752841
commit 4a9e3dc05f
4 changed files with 4 additions and 4 deletions
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2
chisel/playground/resources/top_sram_wrapper.v
View File

@ -45,7 +45,7 @@ PuaCpu core(
.io_data_sram_rdata (data_sram_rdata), .io_data_sram_rdata (data_sram_rdata),
// debug // debug
.io_debug_wb_pc (debug_pc), .io_debug_wb_pc (debug_pc),
.io_debug_wb_rf_wen (debug_commit), .io_debug_wb_commit (debug_commit),
.io_debug_wb_rf_wnum (debug_reg_num), .io_debug_wb_rf_wnum (debug_reg_num),
.io_debug_wb_rf_wdata (debug_wdata) .io_debug_wb_rf_wdata (debug_wdata)
); );

2
chisel/playground/src/defines/Bundles.scala
View File

@ -105,7 +105,7 @@ class DataSram extends Bundle {
class DEBUG extends Bundle { class DEBUG extends Bundle {
val wb_pc = Output(UInt(XLEN.W)) val wb_pc = Output(UInt(XLEN.W))
val wb_rf_wen = Output(Bool()) val wb_commit = Output(Bool())
val wb_rf_wnum = Output(UInt(REG_ADDR_WID.W)) val wb_rf_wnum = Output(UInt(REG_ADDR_WID.W))
val wb_rf_wdata = Output(UInt(XLEN.W)) val wb_rf_wdata = Output(UInt(XLEN.W))
} }

2
chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
View File

@ -24,7 +24,7 @@ class WriteBackUnit extends Module {
io.regfile.wdata := io.writeBackStage.data.rd_info.wdata(io.writeBackStage.data.info.fusel) io.regfile.wdata := io.writeBackStage.data.rd_info.wdata(io.writeBackStage.data.info.fusel)
io.debug.wb_pc := io.writeBackStage.data.pc io.debug.wb_pc := io.writeBackStage.data.pc
io.debug.wb_rf_wen := io.writeBackStage.data.info.valid && io.ctrl.ctrlSignal.allow_to_go io.debug.wb_commit := io.writeBackStage.data.info.valid && io.ctrl.ctrlSignal.allow_to_go
io.debug.wb_rf_wnum := io.regfile.waddr io.debug.wb_rf_wnum := io.regfile.waddr
io.debug.wb_rf_wdata := io.regfile.wdata io.debug.wb_rf_wdata := io.regfile.wdata
} }

2
difftest

@ -1 +1 @@
Subproject commit 8fb9d90b00e02be2baa7536ffa43fe0a6d6dc7f6 Subproject commit 34a01787d1c5883684aa2d30144f9793e13759a2