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删除mem_wreg

This commit is contained in:
Liphen 2023-12-10 22:23:22 +08:00
parent 5fa965062f
commit 452b8ad995
4 changed files with 11 additions and 8 deletions
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4
chisel/playground/src/cache/ICache.scala vendored
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@ -14,8 +14,8 @@ class ICache(implicit config: CpuConfig) extends Module {
val axi = new ICache_AXIInterface() val axi = new ICache_AXIInterface()
}) })
val s_idle :: s_uncached :: s_save :: Nil = Enum(3) val s_idle :: s_uncached :: s_replace :: s_save :: Nil = Enum(4)
val status = RegInit(s_idle) val status = RegInit(s_idle)
val read_next_addr = (status === s_idle || status === s_save) val read_next_addr = (status === s_idle || status === s_save)
val pc = Cat(io.cpu.addr(read_next_addr)(31, 2), 0.U(2.W)) val pc = Cat(io.cpu.addr(read_next_addr)(31, 2), 0.U(2.W))

1
chisel/playground/src/defines/Bundles.scala
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@ -40,7 +40,6 @@ class InstInfo extends Bundle {
val reg_waddr = UInt(REG_ADDR_WID.W) val reg_waddr = UInt(REG_ADDR_WID.W)
val imm = UInt(XLEN.W) val imm = UInt(XLEN.W)
val inst = UInt(INST_WID.W) val inst = UInt(INST_WID.W)
val mem_wreg = Bool()
} }
class MemRead extends Bundle { class MemRead extends Bundle {

1
chisel/playground/src/pipeline/decoder/Decoder.scala
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@ -58,5 +58,4 @@ class Decoder extends Module with HasInstrType {
) )
) )
io.out.info.inst := inst io.out.info.inst := inst
io.out.info.mem_wreg := fuType === FuType.lsu && io.out.info.reg_wen
} }

13
chisel/playground/src/pipeline/execute/ExecuteUnit.scala
View File

@ -52,9 +52,14 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
!(HasExcInt(io.executeStage.inst1.ex)) !(HasExcInt(io.executeStage.inst1.ex))
) )
io.ctrl.inst(0).mem_wreg := io.executeStage.inst0.info.mem_wreg val mem_wreg = VecInit(
io.executeStage.inst0.info.fusel===FuType.lsu && io.executeStage.inst0.info.reg_wen,
io.executeStage.inst1.info.fusel===FuType.lsu && io.executeStage.inst1.info.reg_wen
)
io.ctrl.inst(0).mem_wreg := mem_wreg(0)
io.ctrl.inst(0).reg_waddr := io.executeStage.inst0.info.reg_waddr io.ctrl.inst(0).reg_waddr := io.executeStage.inst0.info.reg_waddr
io.ctrl.inst(1).mem_wreg := io.executeStage.inst1.info.mem_wreg io.ctrl.inst(1).mem_wreg := mem_wreg(1)
io.ctrl.inst(1).reg_waddr := io.executeStage.inst1.info.reg_waddr io.ctrl.inst(1).reg_waddr := io.executeStage.inst1.info.reg_waddr
io.ctrl.flush := io.fetchUnit.flush io.ctrl.flush := io.fetchUnit.flush
@ -164,10 +169,10 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
io.decoderUnit.forward(0).exe.wen := io.memoryStage.inst0.info.reg_wen io.decoderUnit.forward(0).exe.wen := io.memoryStage.inst0.info.reg_wen
io.decoderUnit.forward(0).exe.waddr := io.memoryStage.inst0.info.reg_waddr io.decoderUnit.forward(0).exe.waddr := io.memoryStage.inst0.info.reg_waddr
io.decoderUnit.forward(0).exe.wdata := io.memoryStage.inst0.rd_info.wdata(io.memoryStage.inst0.info.fusel) io.decoderUnit.forward(0).exe.wdata := io.memoryStage.inst0.rd_info.wdata(io.memoryStage.inst0.info.fusel)
io.decoderUnit.forward(0).exe_mem_wreg := io.memoryStage.inst0.info.mem_wreg io.decoderUnit.forward(0).exe_mem_wreg := io.ctrl.inst(0).mem_wreg
io.decoderUnit.forward(1).exe.wen := io.memoryStage.inst1.info.reg_wen io.decoderUnit.forward(1).exe.wen := io.memoryStage.inst1.info.reg_wen
io.decoderUnit.forward(1).exe.waddr := io.memoryStage.inst1.info.reg_waddr io.decoderUnit.forward(1).exe.waddr := io.memoryStage.inst1.info.reg_waddr
io.decoderUnit.forward(1).exe.wdata := io.memoryStage.inst1.rd_info.wdata(io.memoryStage.inst1.info.fusel) io.decoderUnit.forward(1).exe.wdata := io.memoryStage.inst1.rd_info.wdata(io.memoryStage.inst1.info.fusel)
io.decoderUnit.forward(1).exe_mem_wreg := io.memoryStage.inst1.info.mem_wreg io.decoderUnit.forward(1).exe_mem_wreg := io.ctrl.inst(1).mem_wreg
} }