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fix: 修复访存ready信号

This commit is contained in:
Liphen 2023-12-07 17:41:47 +08:00
parent 9524ee9919
commit 44ac8853b8
3 changed files with 31 additions and 16 deletions
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2
chisel/playground/src/cache/DCache.scala vendored
View File

@ -126,7 +126,7 @@ class DCache(implicit config: CpuConfig) extends Module {
}
}
is(s_save) {
when(!io.cpu.dcache_stall && io.cpu.cpu_ready) {
when(!io.cpu.dcache_stall) {
status := s_idle
}
}

16
chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
View File

@ -109,7 +109,7 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
lsExe.in.mem_addr := src1 + imm
lsExe.in.info.op := func
lsExe.in.wdata := src2
io.memoryUnit.out.ready := lsExe.dataMemory.in.ready || scInvalid
io.memoryUnit.out.ready := lsExe.out.ready || scInvalid
state := s_idle
when(amoReq) { state := s_amo_l }
@ -124,7 +124,7 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
lsExe.in.info.op := Mux(atomWidthD, LSUOpType.ld, LSUOpType.lw)
lsExe.in.wdata := DontCare
io.memoryUnit.out.ready := false.B
when(lsExe.dataMemory.in.ready) {
when(lsExe.out.ready) {
state := s_amo_a;
}
atomMemReg := lsExe.out.rdata
@ -146,8 +146,8 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
lsExe.in.mem_addr := src1
lsExe.in.info.op := Mux(atomWidthD, LSUOpType.sd, LSUOpType.sw)
lsExe.in.wdata := atomMemReg
io.memoryUnit.out.ready := lsExe.dataMemory.in.ready
when(lsExe.dataMemory.in.ready) {
io.memoryUnit.out.ready := lsExe.out.ready
when(lsExe.out.ready) {
state := s_idle;
}
}
@ -156,8 +156,8 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
lsExe.in.mem_addr := src1
lsExe.in.info.op := Mux(atomWidthD, LSUOpType.ld, LSUOpType.lw)
lsExe.in.wdata := DontCare
io.memoryUnit.out.ready := lsExe.dataMemory.in.ready
when(lsExe.dataMemory.in.ready) {
io.memoryUnit.out.ready := lsExe.out.ready
when(lsExe.out.ready) {
state := s_idle;
}
}
@ -166,8 +166,8 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
lsExe.in.mem_addr := src1
lsExe.in.info.op := Mux(atomWidthD, LSUOpType.sd, LSUOpType.sw)
lsExe.in.wdata := src2
io.memoryUnit.out.ready := lsExe.dataMemory.in.ready
when(lsExe.dataMemory.in.ready) {
io.memoryUnit.out.ready := lsExe.out.ready
when(lsExe.out.ready) {
state := s_idle;
}
}

29
chisel/playground/src/pipeline/memory/LSExe.scala
View File

@ -21,6 +21,7 @@ class LSExe extends Module {
val loadAccessFault = Bool()
val storeAccessFault = Bool()
val rdata = UInt(DATA_WID.W)
val ready = Bool()
})
})
@ -83,13 +84,6 @@ class LSExe extends Module {
val reqWdata = if (XLEN == 32) genWdata32(io.in.wdata, size) else genWdata(io.in.wdata, size)
val reqWmask = if (XLEN == 32) genWmask32(addr, size) else genWmask(addr, size)
io.dataMemory.out.en := valid && !io.out.storeAddrMisaligned && !io.out.loadAddrMisaligned && !has_acc_err
io.dataMemory.out.rlen := size
io.dataMemory.out.wen := isStore
io.dataMemory.out.wstrb := reqWmask
io.dataMemory.out.addr := reqAddr
io.dataMemory.out.wdata := reqWdata
val rdata = io.dataMemory.in.rdata
val acc_err = io.dataMemory.in.acc_err
@ -137,7 +131,28 @@ class LSExe extends Module {
)
)
// val s_idle :: s_wait_resp :: Nil = Enum(2)
// val state = RegInit(s_idle)
// switch(state) {
// is(s_idle) {
// when(io.dataMemory.in.ready && io.dataMemory.out.en) { state := s_wait_resp }
// }
// is(s_wait_resp) {
// when(io.dataMemory.in.ready) { state := s_idle }
// }
// }
io.dataMemory.out.en := valid && !io.out.storeAddrMisaligned && !io.out.loadAddrMisaligned && !has_acc_err
io.dataMemory.out.rlen := size
io.dataMemory.out.wen := isStore
io.dataMemory.out.wstrb := reqWmask
io.dataMemory.out.addr := reqAddr
io.dataMemory.out.wdata := reqWdata
val is_amo = valid && LSUOpType.isAMO(op)
io.out.ready := io.dataMemory.in.ready
io.out.rdata := Mux(partialLoad, rdataPartialLoad, rdataSel)
io.out.loadAddrMisaligned := valid && !isStore && !is_amo && !addrAligned
io.out.loadAccessFault := valid && !isStore && !is_amo && (acc_err || has_acc_err)