diff --git a/chisel/playground/src/cache/DCache.scala b/chisel/playground/src/cache/DCache.scala
index 5346cf0..38c90b6 100644
--- a/chisel/playground/src/cache/DCache.scala
+++ b/chisel/playground/src/cache/DCache.scala
@@ -126,7 +126,7 @@ class DCache(implicit config: CpuConfig) extends Module {
       }
     }
     is(s_save) {
-      when(!io.cpu.dcache_stall && io.cpu.cpu_ready) {
+      when(!io.cpu.dcache_stall) {
         status := s_idle
       }
     }
diff --git a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
index 29bc48b..8c31959 100644
--- a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
+++ b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
@@ -109,7 +109,7 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
       lsExe.in.mem_addr       := src1 + imm
       lsExe.in.info.op        := func
       lsExe.in.wdata          := src2
-      io.memoryUnit.out.ready := lsExe.dataMemory.in.ready || scInvalid
+      io.memoryUnit.out.ready := lsExe.out.ready || scInvalid
       state                   := s_idle
 
       when(amoReq) { state := s_amo_l }
@@ -124,7 +124,7 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
       lsExe.in.info.op        := Mux(atomWidthD, LSUOpType.ld, LSUOpType.lw)
       lsExe.in.wdata          := DontCare
       io.memoryUnit.out.ready := false.B
-      when(lsExe.dataMemory.in.ready) {
+      when(lsExe.out.ready) {
         state := s_amo_a;
       }
       atomMemReg := lsExe.out.rdata
@@ -146,8 +146,8 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
       lsExe.in.mem_addr       := src1
       lsExe.in.info.op        := Mux(atomWidthD, LSUOpType.sd, LSUOpType.sw)
       lsExe.in.wdata          := atomMemReg
-      io.memoryUnit.out.ready := lsExe.dataMemory.in.ready
-      when(lsExe.dataMemory.in.ready) {
+      io.memoryUnit.out.ready := lsExe.out.ready
+      when(lsExe.out.ready) {
         state := s_idle;
       }
     }
@@ -156,8 +156,8 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
       lsExe.in.mem_addr       := src1
       lsExe.in.info.op        := Mux(atomWidthD, LSUOpType.ld, LSUOpType.lw)
       lsExe.in.wdata          := DontCare
-      io.memoryUnit.out.ready := lsExe.dataMemory.in.ready
-      when(lsExe.dataMemory.in.ready) {
+      io.memoryUnit.out.ready := lsExe.out.ready
+      when(lsExe.out.ready) {
         state := s_idle;
       }
     }
@@ -166,8 +166,8 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
       lsExe.in.mem_addr       := src1
       lsExe.in.info.op        := Mux(atomWidthD, LSUOpType.sd, LSUOpType.sw)
       lsExe.in.wdata          := src2
-      io.memoryUnit.out.ready := lsExe.dataMemory.in.ready
-      when(lsExe.dataMemory.in.ready) {
+      io.memoryUnit.out.ready := lsExe.out.ready
+      when(lsExe.out.ready) {
         state := s_idle;
       }
     }
diff --git a/chisel/playground/src/pipeline/memory/LSExe.scala b/chisel/playground/src/pipeline/memory/LSExe.scala
index 9dcacd7..10597ac 100644
--- a/chisel/playground/src/pipeline/memory/LSExe.scala
+++ b/chisel/playground/src/pipeline/memory/LSExe.scala
@@ -21,6 +21,7 @@ class LSExe extends Module {
       val loadAccessFault     = Bool()
       val storeAccessFault    = Bool()
       val rdata               = UInt(DATA_WID.W)
+      val ready               = Bool()
     })
   })
 
@@ -83,13 +84,6 @@ class LSExe extends Module {
   val reqWdata = if (XLEN == 32) genWdata32(io.in.wdata, size) else genWdata(io.in.wdata, size)
   val reqWmask = if (XLEN == 32) genWmask32(addr, size) else genWmask(addr, size)
 
-  io.dataMemory.out.en    := valid && !io.out.storeAddrMisaligned && !io.out.loadAddrMisaligned && !has_acc_err
-  io.dataMemory.out.rlen  := size
-  io.dataMemory.out.wen   := isStore
-  io.dataMemory.out.wstrb := reqWmask
-  io.dataMemory.out.addr  := reqAddr
-  io.dataMemory.out.wdata := reqWdata
-
   val rdata   = io.dataMemory.in.rdata
   val acc_err = io.dataMemory.in.acc_err
 
@@ -137,7 +131,28 @@ class LSExe extends Module {
     )
   )
 
+  // val s_idle :: s_wait_resp :: Nil = Enum(2)
+  // val state                        = RegInit(s_idle)
+
+  // switch(state) {
+  //   is(s_idle) {
+  //     when(io.dataMemory.in.ready && io.dataMemory.out.en) { state := s_wait_resp }
+  //   }
+
+  //   is(s_wait_resp) {
+  //     when(io.dataMemory.in.ready) { state := s_idle }
+  //   }
+  // }
+
+  io.dataMemory.out.en    := valid && !io.out.storeAddrMisaligned && !io.out.loadAddrMisaligned && !has_acc_err
+  io.dataMemory.out.rlen  := size
+  io.dataMemory.out.wen   := isStore
+  io.dataMemory.out.wstrb := reqWmask
+  io.dataMemory.out.addr  := reqAddr
+  io.dataMemory.out.wdata := reqWdata
+
   val is_amo = valid && LSUOpType.isAMO(op)
+  io.out.ready               := io.dataMemory.in.ready
   io.out.rdata               := Mux(partialLoad, rdataPartialLoad, rdataSel)
   io.out.loadAddrMisaligned  := valid && !isStore && !is_amo && !addrAligned
   io.out.loadAccessFault     := valid && !isStore && !is_amo && (acc_err || has_acc_err)