增加puamips的cache文件
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Liphen
parent
41da1f4c3e
commit
3134b79c54
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@ -26,3 +26,29 @@ case class CpuConfig(
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case class BranchPredictorConfig(
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val bhtDepth: Int = 5,
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val phtDepth: Int = 6)
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case class CacheConfig(
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nway: Int = 2, // 路数
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nbank: Int = 8, // bank数
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nset: Int,
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bankWidth: Int // bytes per bank
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) {
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val config = CpuConfig()
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val indexWidth = log2Ceil(nset) // 6
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val bankIndexWidth = log2Ceil(nbank) // 3
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val bankOffsetWidth = log2Ceil(bankWidth) // 3
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val offsetWidth = bankIndexWidth + bankOffsetWidth // 6
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val tagWidth = 32 - indexWidth - offsetWidth // 20
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val tagvWidth = tagWidth + 1 // 21
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val bankWidthBits = bankWidth * 8 // 64
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val burstSize = 16
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val ninst = config.instFetchNum // TODO:改成可随意修改的参数
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require(isPow2(nset))
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require(isPow2(nway))
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require(isPow2(nbank))
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require(isPow2(bankWidth))
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require(
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tagWidth + indexWidth + bankIndexWidth + bankOffsetWidth == 32,
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"basic request calculation"
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)
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}
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@ -0,0 +1,64 @@
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package cache.memory
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import chisel3._
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import chisel3.util._
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import cpu.CpuConfig
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/** LUT ram for XPM, one port for read/write, one port for read
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* @param depth
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* how many lines there are in the bank
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* @param width
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* how wide in bits each line is
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* @param config
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* implicit configuration to control generate ram for simulation or elaboration
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*/
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class LUTRam(depth: Int, width: Int)(implicit val config: CpuConfig) extends Module {
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require(isPow2(depth))
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val waddridth = log2Ceil(depth)
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val io = IO(new Bundle {
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val raddr = Input(UInt(waddridth.W))
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val rdata = Output(UInt(width.W))
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val waddr = Input(UInt(waddridth.W))
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val wdata = Input(UInt(width.W))
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val wen = Input(Bool())
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val writeOutput = Output(UInt(width.W))
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})
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if (config.build) {
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val bank = Module(
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new LUTRamIP(
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wdataidth = width,
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waddridth = waddridth,
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byteWriteWidth = width,
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numberOfLines = depth,
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),
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)
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bank.io.clka := clock
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bank.io.clkb := clock
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bank.io.rsta := reset
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bank.io.rstb := reset
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bank.io.regcea := false.B
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bank.io.regceb := false.B
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bank.io.ena := true.B
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bank.io.enb := true.B
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bank.io.addra := io.waddr
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bank.io.wea := io.wen
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bank.io.dina := io.wdata
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io.writeOutput := DontCare
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bank.io.addrb := io.raddr
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io.rdata := bank.io.doutb
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} else {
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val bank = RegInit(VecInit(Seq.fill(depth)(0.U(width.W))))
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io.rdata := bank(io.raddr)
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io.writeOutput := DontCare
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when(io.wen) {
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bank(io.waddr) := io.wdata
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}.otherwise {
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io.writeOutput := bank(io.waddr)
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}
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}
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}
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@ -0,0 +1,65 @@
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package cache.memory
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import chisel3._
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import chisel3.util.log2Ceil
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/** XPM 2019.2 XPM_MEMORY_DPDISTRAM, at page 124 of UG953(2019.2) by default, this is initialized to
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* all 0
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*
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* @param wdataidth
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* : the size of the data to store in each line, in bits
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* @param waddridth
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* : the width of request
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* @param byteWriteWidth
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* : addressable size of write
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* @param numberOfLines
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* : how many **bits** there are in the memory
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*/
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class LUTRamIP(wdataidth: Int, waddridth: Int, byteWriteWidth: Int, numberOfLines: Int)
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extends BlackBox(
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Map(
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"ADDR_WIDTH_A" -> waddridth,
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"ADDR_WIDTH_B" -> waddridth,
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"MEMORY_SIZE" -> numberOfLines * wdataidth,
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"WRITE_DATA_WIDTH_A" -> wdataidth,
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"READ_DATA_WIDTH_A" -> wdataidth,
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"READ_DATA_WIDTH_B" -> wdataidth,
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"BYTE_WRITE_WIDTH_A" -> byteWriteWidth,
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"READ_LATENCY_A" -> 0,
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"READ_LATENCY_B" -> 0,
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"READ_RESET_VALUE_A" -> 0,
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"READ_RESET_VALUE_B" -> 0,
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"CLOCKING_MODE" -> "common_clock",
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),
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) {
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override def desiredName: String = "xpm_memory_dpdistram"
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require(
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waddridth == log2Ceil(numberOfLines),
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"request width should be log 2 of number of lines to request all",
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)
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require(
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wdataidth - (wdataidth / byteWriteWidth) * byteWriteWidth == 0,
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"data width should be a multiple of byte write width",
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)
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require(waddridth <= 20, "request width should be 1 to 20")
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val io = IO(new Bundle {
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val clka = Input(Clock())
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val clkb = Input(Clock())
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val rsta = Input(Reset())
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val rstb = Input(Reset())
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val ena = Input(Bool())
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val enb = Input(Bool())
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val regcea = Input(Bool())
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val regceb = Input(Bool())
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val dina = Input(UInt(wdataidth.W))
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val addra = Input(UInt(waddridth.W))
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val addrb = Input(UInt(waddridth.W))
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val wea = Input(UInt((wdataidth / byteWriteWidth).W))
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val douta = Output(UInt(wdataidth.W))
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val doutb = Output(UInt(wdataidth.W))
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})
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}
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@ -0,0 +1,37 @@
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package cache.memory
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import chisel3._
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import chisel3.util._
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import cpu.CacheConfig
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class ReadOnlyPort[+T <: Data](gen: T)(implicit cacheConfig: CacheConfig) extends Bundle {
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val addr = Input(UInt(log2Ceil(cacheConfig.nset * cacheConfig.nbank).W))
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val data = Output(gen)
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}
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class WriteOnlyPort[+T <: Data](gen: T)(implicit cacheConfig: CacheConfig) extends Bundle {
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val addr = Input(UInt(log2Ceil(cacheConfig.nset * cacheConfig.nbank).W))
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val en = Input(Bool())
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val data = Input(gen)
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}
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class WriteOnlyMaskPort[+T <: Data](gen: T)(implicit cacheConfig: CacheConfig) extends Bundle {
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val addr = Input(UInt(log2Ceil(cacheConfig.nset * cacheConfig.nbank).W))
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val en = Input(UInt(cacheConfig.bankWidth.W))
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val data = Input(gen)
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}
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class ReadWritePort[+T <: Data](gen: T)(implicit cacheConfig: CacheConfig) extends Bundle {
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val addr = Input(UInt(log2Ceil(cacheConfig.nset * cacheConfig.nbank).W))
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val en = Input(Bool())
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val wdata = Input(gen)
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val rdata = Output(gen)
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}
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class MaskedReadWritePort[+T <: Data](gen: T)(implicit cacheConfig: CacheConfig) extends Bundle {
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val addr = Input(UInt(log2Ceil(cacheConfig.nset * cacheConfig.nbank).W))
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val writeMask = Input(UInt(cacheConfig.bankWidth.W))
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val wdata = Input(gen)
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val rdata = Output(gen)
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}
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@ -0,0 +1,91 @@
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package cache.memory
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import chisel3._
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import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
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import chisel3.util._
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import cpu.CpuConfig
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/** simple dual port ram, with a port for reading and a port for writing
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*
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* @param depth
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* how many lines there are in the ram
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* @param width
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* how wide in bits each line is
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* @param byteAddressable
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* is it byte addressable?
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* @param cpuCfg
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* the implicit configuration for simulation and elaboration
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*/
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class SimpleDualPortRam(depth: Int, width: Int, byteAddressable: Boolean)(implicit
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val config: CpuConfig,
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) extends Module {
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require(isPow2(depth))
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require(
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width % 8 == 0 || !byteAddressable,
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"if memory is byte addressable, then the adderss width must be a multiple of 8",
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)
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val waddridth = log2Ceil(depth)
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val io = IO(new Bundle {
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val raddr = Input(UInt(waddridth.W))
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val ren = Input(Bool())
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val rdata = Output(UInt(width.W))
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val waddr = Input(UInt(waddridth.W))
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val wen = Input(Bool())
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val wstrb = Input(UInt((if (byteAddressable) width / 8 else 1).W))
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val wdata = Input(UInt(width.W))
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})
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if (config.build) {
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val memory = Module(
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new SimpleDualPortRamIP(
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wdataidth = width,
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byteWriteWidth = if (byteAddressable) 8 else width,
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numberOfLines = depth,
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waddridth = waddridth,
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),
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)
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memory.io.clka := clock
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memory.io.clkb := clock
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memory.io.rstb := reset
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memory.io.addra := io.waddr
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memory.io.ena := io.wen
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memory.io.dina := io.wdata
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memory.io.wea := io.wstrb
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memory.io.addrb := io.raddr
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memory.io.enb := io.ren
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memory.io.regceb := false.B
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io.rdata := memory.io.doutb
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} else {
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assert(
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io.wstrb.orR || !io.wen,
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"when write port enable is high, write vector cannot be all 0",
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)
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if (byteAddressable) {
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val bank = SyncReadMem(depth, Vec(width / 8, UInt(8.W)))
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when(io.ren) {
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io.rdata := bank(io.raddr).asTypeOf(io.rdata)
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}.otherwise {
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io.rdata := DontCare
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}
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when(io.wen) {
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bank.write(io.waddr, io.wdata.asTypeOf(Vec(width / 8, UInt(8.W))), io.wstrb.asBools)
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}
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} else {
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val bank = SyncReadMem(depth, UInt(width.W))
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when(io.ren) {
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io.rdata := bank.read(io.raddr)
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}.otherwise {
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io.rdata := 0.U(32.W)
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}
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when(io.wen) {
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bank.write(io.waddr, io.wdata)
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}
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}
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}
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}
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@ -0,0 +1,68 @@
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package cache.memory
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import chisel3._
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import chisel3.util.log2Ceil
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/** simple dual port ram
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*
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* @param wdataidth
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* : width of every data line
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* @param byteWriteWidth
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* : how many bits to write per mask
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* @param numberOfLines
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* : how many lines of data are in the ram
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* @param waddridth
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* : how wide is the request (to cover all lines)
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* @param memoryPrimitive
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* : should I use auto, block ram or distributed ram
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*/
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class SimpleDualPortRamIP(
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wdataidth: Int = 32,
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byteWriteWidth: Int = 8,
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numberOfLines: Int,
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waddridth: Int,
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memoryPrimitive: String = "block",
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) extends BlackBox(
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Map(
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"ADDR_WIDTH_A" -> waddridth,
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"ADDR_WIDTH_B" -> waddridth,
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"WRITE_DATA_WIDTH_A" -> wdataidth,
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"READ_DATA_WIDTH_B" -> wdataidth,
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"BYTE_WRITE_WIDTH_A" -> byteWriteWidth,
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"CLOCKING_MODE" -> "common_clock",
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"READ_LATENCY_B" -> 1,
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"MEMORY_SIZE" -> numberOfLines * wdataidth,
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"MEMORY_PRIMITIVE" -> memoryPrimitive,
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),
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) {
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override def desiredName: String = "xpm_memory_sdpram"
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require(waddridth <= 20, "request width should be 1 to 20")
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require(
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wdataidth - (wdataidth / byteWriteWidth) * byteWriteWidth == 0,
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"data width should be a multiple of byte write width",
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)
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require(
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List("auto", "block", "distributed", "ultra").contains(memoryPrimitive),
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"memory primitive should be auto, block ram, dist ram or ultra ram",
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)
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require(
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waddridth == log2Ceil(numberOfLines),
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"request width should be log 2 of number of lines to request all",
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)
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val io = IO(new Bundle {
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// clock and reset
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val clka = Input(Clock())
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val clkb = Input(Clock())
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val rstb = Input(Reset())
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val addra = Input(UInt(waddridth.W))
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val dina = Input(UInt(wdataidth.W))
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val ena = Input(Bool())
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val wea = Input(UInt((wdataidth / byteWriteWidth).W))
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val addrb = Input(UInt(waddridth.W))
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val enb = Input(Bool())
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val regceb = Input(Bool())
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val doutb = Output(UInt(wdataidth.W))
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})
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}
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