fix(csr): stval只在deleg的情况下更新

chisel/playground/src/pipeline/execute/fu/Csr.scala

@@ -327,10 +327,10 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
 
   when(raise_exception) {
     val tval = mem_ex.tval(exceptionNO)
-    when(mode === ModeM) {
+    when(delegS) {
-      mtval := tval
-    }.otherwise {
       stval := tval
+    }.otherwise {
+      mtval := tval
     }
   }