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去除无用信号，修改函数名

This commit is contained in:
Liphen 2023-11-22 14:53:49 +08:00
parent cc842aff6e
commit 28d319f3cc
7 changed files with 16 additions and 24 deletions
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3
chisel/playground/src/ctrl/Ctrl.scala
View File

@ -39,8 +39,5 @@ class Ctrl(implicit val config: CpuConfig) extends Module {
io.memoryUnit.do_flush := io.memoryUnit.flush_req
io.writeBackUnit.do_flush := false.B
io.executeUnit.fu.do_flush := io.memoryUnit.do_flush
io.executeUnit.fu.eret := io.memoryUnit.eret
io.executeUnit.fu.allow_to_go := io.memoryUnit.allow_to_go
}

3
chisel/playground/src/defines/Bundles.scala
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@ -75,8 +75,6 @@ class DecoderUnitCtrl extends Bundle {
class ExecuteFuCtrl extends Bundle {
val allow_to_go = Input(Bool())
val do_flush = Input(Bool())
val eret = Input(Bool())
}
class ExecuteCtrl(implicit val config: CpuConfig) extends Bundle {
@ -92,7 +90,6 @@ class ExecuteCtrl(implicit val config: CpuConfig) extends Bundle {
class MemoryCtrl extends Bundle {
val flush_req = Output(Bool())
val eret = Output(Bool())
val allow_to_go = Input(Bool())
val do_flush = Input(Bool())

19
chisel/playground/src/pipeline/decoder/Decoder.scala
View File

@ -3,7 +3,6 @@ package cpu.pipeline.decoder
import chisel3._
import chisel3.util._
import cpu.defines._
import cpu.defines.Util._
import cpu.defines.Const._
class Decoder extends Module with HasInstrType {
@ -57,15 +56,15 @@ class Decoder extends Module with HasInstrType {
io.out.inst_info.imm := LookupTree(
instrType,
Seq(
InstrI -> signedExtend(inst(31, 20), XLEN),
InstrS -> signedExtend(Cat(inst(31, 25), inst(11, 7)), XLEN),
InstrSA -> signedExtend(Cat(inst(31, 25), inst(11, 7)), XLEN),
InstrB -> signedExtend(Cat(inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)), XLEN),
InstrU -> signedExtend(Cat(inst(31, 12), 0.U(12.W)), XLEN),
InstrJ -> signedExtend(Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)), XLEN)
InstrI -> SignedExtend(inst(31, 20), XLEN),
InstrS -> SignedExtend(Cat(inst(31, 25), inst(11, 7)), XLEN),
InstrSA -> SignedExtend(Cat(inst(31, 25), inst(11, 7)), XLEN),
InstrB -> SignedExtend(Cat(inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)), XLEN),
InstrU -> SignedExtend(Cat(inst(31, 12), 0.U(12.W)), XLEN),
InstrJ -> SignedExtend(Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)), XLEN)
)
)
io.out.inst_info.dual_issue := false.B
io.out.inst_info.inst := inst
io.out.inst_info.mem_wreg := fuType === FuType.lsu && LSUOpType.isLoad(fuOpType)
io.out.inst_info.dual_issue := false.B
io.out.inst_info.inst := inst
io.out.inst_info.mem_wreg := fuType === FuType.lsu && LSUOpType.isLoad(fuOpType)
}

10
chisel/playground/src/pipeline/execute/ALU.scala
View File

@ -37,16 +37,16 @@ class Alu extends Module {
val shsrc1 = MuxLookup(op, src1(XLEN - 1, 0))(
List(
ALUOpType.srlw -> Util.zeroExtend(src1(31, 0), XLEN),
ALUOpType.sraw -> Util.signedExtend(src1(31, 0), XLEN)
ALUOpType.srlw -> ZeroExtend(src1(31, 0), XLEN),
ALUOpType.sraw -> SignedExtend(src1(31, 0), XLEN)
)
)
val shamt = Mux(ALUOpType.isWordOp(op), src2(4, 0), if (XLEN == 64) src2(5, 0) else src2(4, 0))
val res = MuxLookup(op(3, 0), sum)(
List(
ALUOpType.sll -> ((shsrc1 << shamt)(XLEN - 1, 0)),
ALUOpType.slt -> Util.zeroExtend(slt, XLEN),
ALUOpType.sltu -> Util.zeroExtend(sltu, XLEN),
ALUOpType.slt -> ZeroExtend(slt, XLEN),
ALUOpType.sltu -> ZeroExtend(sltu, XLEN),
ALUOpType.xor -> xor,
ALUOpType.srl -> (shsrc1 >> shamt),
ALUOpType.or -> (src1 | src2),
@ -54,5 +54,5 @@ class Alu extends Module {
ALUOpType.sra -> ((shsrc1.asSInt >> shamt).asUInt)
)
)
io.result := Mux(ALUOpType.isWordOp(op), Util.signedExtend(res(31, 0), 64), res)
io.result := Mux(ALUOpType.isWordOp(op), SignedExtend(res(31, 0), 64), res)
}

2
chisel/playground/src/pipeline/execute/BranchCtrl.scala
View File

@ -31,5 +31,5 @@ class BranchCtrl extends Module {
ALUOpType.getBranchType(ALUOpType.bltu) -> sltu
)
io.out.pred_fail := io.in.pred_branch =/= io.out.branch
io.out.branch := Util.LookupTree(ALUOpType.getBranchType(op), table) ^ ALUOpType.isBranchInvert(op)
io.out.branch := LookupTree(ALUOpType.getBranchType(op), table) ^ ALUOpType.isBranchInvert(op)
}

2
chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala
View File

@ -62,7 +62,7 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
)
val addr_aligned = Wire(Vec(config.fuNum, Bool()))
for (i <- 0 until config.fuNum) {
addr_aligned(i) := Util.LookupTree(
addr_aligned(i) := LookupTree(
io.inst(i).inst_info.op(1, 0),
List(
"b00".U -> true.B, //b

1
chisel/playground/src/pipeline/memory/MemoryUnit.scala
View File

@ -86,5 +86,4 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
io.fetchUnit.flush_pc := Mux(io.csr.out.flush, io.csr.out.flush_pc, io.writeBackStage.inst0.pc + 4.U)
io.ctrl.flush_req := io.fetchUnit.flush
io.ctrl.eret := io.writeBackStage.inst0.ex.eret
}