From 28d319f3cc1d1cdea89569bfe2499703b8f25fd9 Mon Sep 17 00:00:00 2001 From: Liphen Date: Wed, 22 Nov 2023 14:53:49 +0800 Subject: [PATCH] =?UTF-8?q?=E5=8E=BB=E9=99=A4=E6=97=A0=E7=94=A8=E4=BF=A1?= =?UTF-8?q?=E5=8F=B7=EF=BC=8C=E4=BF=AE=E6=94=B9=E5=87=BD=E6=95=B0=E5=90=8D?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/ctrl/Ctrl.scala | 3 --- chisel/playground/src/defines/Bundles.scala | 3 --- .../src/pipeline/decoder/Decoder.scala | 19 +++++++++---------- .../playground/src/pipeline/execute/ALU.scala | 10 +++++----- .../src/pipeline/execute/BranchCtrl.scala | 2 +- .../pipeline/execute/ExeAccessMemCtrl.scala | 2 +- .../src/pipeline/memory/MemoryUnit.scala | 1 - 7 files changed, 16 insertions(+), 24 deletions(-) diff --git a/chisel/playground/src/ctrl/Ctrl.scala b/chisel/playground/src/ctrl/Ctrl.scala index 35289b7..ffece80 100644 --- a/chisel/playground/src/ctrl/Ctrl.scala +++ b/chisel/playground/src/ctrl/Ctrl.scala @@ -39,8 +39,5 @@ class Ctrl(implicit val config: CpuConfig) extends Module { io.memoryUnit.do_flush := io.memoryUnit.flush_req io.writeBackUnit.do_flush := false.B - io.executeUnit.fu.do_flush := io.memoryUnit.do_flush - io.executeUnit.fu.eret := io.memoryUnit.eret io.executeUnit.fu.allow_to_go := io.memoryUnit.allow_to_go - } diff --git a/chisel/playground/src/defines/Bundles.scala b/chisel/playground/src/defines/Bundles.scala index e37979b..a023d66 100644 --- a/chisel/playground/src/defines/Bundles.scala +++ b/chisel/playground/src/defines/Bundles.scala @@ -75,8 +75,6 @@ class DecoderUnitCtrl extends Bundle { class ExecuteFuCtrl extends Bundle { val allow_to_go = Input(Bool()) - val do_flush = Input(Bool()) - val eret = Input(Bool()) } class ExecuteCtrl(implicit val config: CpuConfig) extends Bundle { @@ -92,7 +90,6 @@ class ExecuteCtrl(implicit val config: CpuConfig) extends Bundle { class MemoryCtrl extends Bundle { val flush_req = Output(Bool()) - val eret = Output(Bool()) val allow_to_go = Input(Bool()) val do_flush = Input(Bool()) diff --git a/chisel/playground/src/pipeline/decoder/Decoder.scala b/chisel/playground/src/pipeline/decoder/Decoder.scala index f7d58b3..fb3df7c 100644 --- a/chisel/playground/src/pipeline/decoder/Decoder.scala +++ b/chisel/playground/src/pipeline/decoder/Decoder.scala @@ -3,7 +3,6 @@ package cpu.pipeline.decoder import chisel3._ import chisel3.util._ import cpu.defines._ -import cpu.defines.Util._ import cpu.defines.Const._ class Decoder extends Module with HasInstrType { @@ -57,15 +56,15 @@ class Decoder extends Module with HasInstrType { io.out.inst_info.imm := LookupTree( instrType, Seq( - InstrI -> signedExtend(inst(31, 20), XLEN), - InstrS -> signedExtend(Cat(inst(31, 25), inst(11, 7)), XLEN), - InstrSA -> signedExtend(Cat(inst(31, 25), inst(11, 7)), XLEN), - InstrB -> signedExtend(Cat(inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)), XLEN), - InstrU -> signedExtend(Cat(inst(31, 12), 0.U(12.W)), XLEN), - InstrJ -> signedExtend(Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)), XLEN) + InstrI -> SignedExtend(inst(31, 20), XLEN), + InstrS -> SignedExtend(Cat(inst(31, 25), inst(11, 7)), XLEN), + InstrSA -> SignedExtend(Cat(inst(31, 25), inst(11, 7)), XLEN), + InstrB -> SignedExtend(Cat(inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)), XLEN), + InstrU -> SignedExtend(Cat(inst(31, 12), 0.U(12.W)), XLEN), + InstrJ -> SignedExtend(Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)), XLEN) ) ) - io.out.inst_info.dual_issue := false.B - io.out.inst_info.inst := inst - io.out.inst_info.mem_wreg := fuType === FuType.lsu && LSUOpType.isLoad(fuOpType) + io.out.inst_info.dual_issue := false.B + io.out.inst_info.inst := inst + io.out.inst_info.mem_wreg := fuType === FuType.lsu && LSUOpType.isLoad(fuOpType) } diff --git a/chisel/playground/src/pipeline/execute/ALU.scala b/chisel/playground/src/pipeline/execute/ALU.scala index a35e758..4a54456 100644 --- a/chisel/playground/src/pipeline/execute/ALU.scala +++ b/chisel/playground/src/pipeline/execute/ALU.scala @@ -37,16 +37,16 @@ class Alu extends Module { val shsrc1 = MuxLookup(op, src1(XLEN - 1, 0))( List( - ALUOpType.srlw -> Util.zeroExtend(src1(31, 0), XLEN), - ALUOpType.sraw -> Util.signedExtend(src1(31, 0), XLEN) + ALUOpType.srlw -> ZeroExtend(src1(31, 0), XLEN), + ALUOpType.sraw -> SignedExtend(src1(31, 0), XLEN) ) ) val shamt = Mux(ALUOpType.isWordOp(op), src2(4, 0), if (XLEN == 64) src2(5, 0) else src2(4, 0)) val res = MuxLookup(op(3, 0), sum)( List( ALUOpType.sll -> ((shsrc1 << shamt)(XLEN - 1, 0)), - ALUOpType.slt -> Util.zeroExtend(slt, XLEN), - ALUOpType.sltu -> Util.zeroExtend(sltu, XLEN), + ALUOpType.slt -> ZeroExtend(slt, XLEN), + ALUOpType.sltu -> ZeroExtend(sltu, XLEN), ALUOpType.xor -> xor, ALUOpType.srl -> (shsrc1 >> shamt), ALUOpType.or -> (src1 | src2), @@ -54,5 +54,5 @@ class Alu extends Module { ALUOpType.sra -> ((shsrc1.asSInt >> shamt).asUInt) ) ) - io.result := Mux(ALUOpType.isWordOp(op), Util.signedExtend(res(31, 0), 64), res) + io.result := Mux(ALUOpType.isWordOp(op), SignedExtend(res(31, 0), 64), res) } diff --git a/chisel/playground/src/pipeline/execute/BranchCtrl.scala b/chisel/playground/src/pipeline/execute/BranchCtrl.scala index c935490..add39b3 100644 --- a/chisel/playground/src/pipeline/execute/BranchCtrl.scala +++ b/chisel/playground/src/pipeline/execute/BranchCtrl.scala @@ -31,5 +31,5 @@ class BranchCtrl extends Module { ALUOpType.getBranchType(ALUOpType.bltu) -> sltu ) io.out.pred_fail := io.in.pred_branch =/= io.out.branch - io.out.branch := Util.LookupTree(ALUOpType.getBranchType(op), table) ^ ALUOpType.isBranchInvert(op) + io.out.branch := LookupTree(ALUOpType.getBranchType(op), table) ^ ALUOpType.isBranchInvert(op) } diff --git a/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala b/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala index d2fcca8..1f93143 100644 --- a/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala +++ b/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala @@ -62,7 +62,7 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module { ) val addr_aligned = Wire(Vec(config.fuNum, Bool())) for (i <- 0 until config.fuNum) { - addr_aligned(i) := Util.LookupTree( + addr_aligned(i) := LookupTree( io.inst(i).inst_info.op(1, 0), List( "b00".U -> true.B, //b diff --git a/chisel/playground/src/pipeline/memory/MemoryUnit.scala b/chisel/playground/src/pipeline/memory/MemoryUnit.scala index 26bc31a..a8e1de6 100644 --- a/chisel/playground/src/pipeline/memory/MemoryUnit.scala +++ b/chisel/playground/src/pipeline/memory/MemoryUnit.scala @@ -86,5 +86,4 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module { io.fetchUnit.flush_pc := Mux(io.csr.out.flush, io.csr.out.flush_pc, io.writeBackStage.inst0.pc + 4.U) io.ctrl.flush_req := io.fetchUnit.flush - io.ctrl.eret := io.writeBackStage.inst0.ex.eret }