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fix(id): inst1的lui特例

This commit is contained in:
Liphen 2023-12-01 16:49:02 +08:00
parent f3a2d4e522
commit 1952e5f963
1 changed files with 6 additions and 4 deletions
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10
chisel/playground/src/pipeline/decoder/DecoderUnit.scala
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@ -149,10 +149,12 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.executeStage.inst1.pc := pc(1) io.executeStage.inst1.pc := pc(1)
io.executeStage.inst1.info := info(1) io.executeStage.inst1.info := info(1)
io.executeStage.inst1.info.valid := !io.instFifo.info.almost_empty && !io.instFifo.info.empty io.executeStage.inst1.info.valid := !io.instFifo.info.almost_empty && !io.instFifo.info.empty
io.executeStage.inst1.src_info.src1_data := Mux( io.executeStage.inst1.src_info.src1_data := MuxCase(
info(1).reg1_ren, SignedExtend(pc(1), INST_ADDR_WID),
forwardCtrl.out.inst(1).src1.rdata, Seq(
SignedExtend(pc(1), INST_ADDR_WID) info(1).reg1_ren -> forwardCtrl.out.inst(1).src1.rdata,
(info(1).inst(6, 0) === "b0110111".U) -> 0.U
)
) )
io.executeStage.inst1.src_info.src2_data := Mux( io.executeStage.inst1.src_info.src2_data := Mux(
info(1).reg2_ren, info(1).reg2_ren,