From 1952e5f963f5e1a644de1f8da32bdce5782f78ce Mon Sep 17 00:00:00 2001 From: Liphen Date: Fri, 1 Dec 2023 16:49:02 +0800 Subject: [PATCH] =?UTF-8?q?fix(id):=20inst1=E7=9A=84lui=E7=89=B9=E4=BE=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../playground/src/pipeline/decoder/DecoderUnit.scala | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala index 2d657f0..c50303e 100644 --- a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala +++ b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala @@ -149,10 +149,12 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti io.executeStage.inst1.pc := pc(1) io.executeStage.inst1.info := info(1) io.executeStage.inst1.info.valid := !io.instFifo.info.almost_empty && !io.instFifo.info.empty - io.executeStage.inst1.src_info.src1_data := Mux( - info(1).reg1_ren, - forwardCtrl.out.inst(1).src1.rdata, - SignedExtend(pc(1), INST_ADDR_WID) + io.executeStage.inst1.src_info.src1_data := MuxCase( + SignedExtend(pc(1), INST_ADDR_WID), + Seq( + info(1).reg1_ren -> forwardCtrl.out.inst(1).src1.rdata, + (info(1).inst(6, 0) === "b0110111".U) -> 0.U + ) ) io.executeStage.inst1.src_info.src2_data := Mux( info(1).reg2_ren,