yystopf
/
riscv-lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

修改issue unit

This commit is contained in:
Liphen 2023-11-19 15:34:14 +08:00
parent 8cc7e38b8b
commit 1646a4d75d
2 changed files with 55 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
chisel/playground/src/defines/isa/Instructions.scala
View File

@ -26,11 +26,11 @@ object SrcType {
object FuType { object FuType {
def num = 5 def num = 5
def alu = "b000".U def alu = "b000".U // arithmetic logic unit
def lsu = "b001".U def lsu = "b001".U // load store unit
def mdu = "b010".U def mdu = "b010".U // mul div unit
def csr = "b011".U def csr = "b011".U // control status register
def mou = "b100".U def mou = "b100".U // memory order unit
def bru = alu def bru = alu
def apply() = UInt(log2Up(num).W) def apply() = UInt(log2Up(num).W)
} }

102
chisel/playground/src/pipeline/decoder/Issue.scala
View File

@ -1,59 +1,57 @@
// package cpu.pipeline.decoder package cpu.pipeline.decoder
// import chisel3._ import chisel3._
// import chisel3.util._ import chisel3.util._
// import cpu.defines._ import cpu.defines._
// import cpu.defines.Const._ import cpu.defines.Const._
// import cpu.CpuConfig import cpu.defines.Instructions._
import cpu.CpuConfig
// class Issue(implicit val config: CpuConfig) extends Module { class Issue(implicit val config: CpuConfig) extends Module {
// val io = IO(new Bundle { val io = IO(new Bundle {
// // 输入 // 输入
// val allow_to_go = Input(Bool()) val allow_to_go = Input(Bool())
// val instFifo = Input(new Bundle { val instFifo = Input(new Bundle {
// val empty = Bool() val empty = Bool()
// val almost_empty = Bool() val almost_empty = Bool()
// }) })
// val decodeInst = Input(Vec(config.decoderNum, new InstInfo())) val decodeInst = Input(Vec(config.decoderNum, new InstInfo()))
// val execute = Input(Vec(config.fuNum, new MemRead())) val execute = Input(Vec(config.fuNum, new MemRead()))
// // 输出 // 输出
// val inst1 = Output(new Bundle { val inst1 = Output(new Bundle {
// val allow_to_go = Bool() val allow_to_go = Bool()
// }) })
// }) })
// val inst0 = io.decodeInst(0) val inst0 = io.decodeInst(0)
// val inst1 = io.decodeInst(1) val inst1 = io.decodeInst(1)
// // inst buffer是否存有至少2条指令 // inst buffer是否存有至少2条指令
// val instFifo_invalid = io.instFifo.empty || io.instFifo.almost_empty val instFifo_invalid = io.instFifo.empty || io.instFifo.almost_empty
// // 结构冲突 // 结构冲突
// val mem_conflict = inst0.fusel === FU_MEM && inst1.fusel === FU_MEM val mem_conflict = inst0.fusel === FuType.lsu && inst1.fusel === FuType.lsu
// val mul_conflict = inst0.fusel === FU_MUL && inst1.fusel === FU_MUL val mul_conflict = inst0.fusel === FuType.mdu && inst1.fusel === FuType.mdu
// val div_conflict = inst0.fusel === FU_DIV && inst1.fusel === FU_DIV val div_conflict = inst0.fusel === FuType.mdu && inst1.fusel === FuType.mdu
// val struct_conflict = mem_conflict || mul_conflict || div_conflict val csr_conflict = inst0.fusel === FuType.csr && inst1.fusel === FuType.csr
val struct_conflict = mem_conflict || mul_conflict || div_conflict || csr_conflict
// // 写后读冲突 // 写后读冲突
// val load_stall = val load_stall =
// io.execute(0).mem_wreg && (inst1.reg1_ren && inst1.reg1_raddr === io.execute(0).reg_waddr || io.execute(0).mem_wreg && (inst1.reg1_ren && inst1.reg1_raddr === io.execute(0).reg_waddr ||
// inst1.reg2_ren && inst1.reg2_raddr === io.execute(0).reg_waddr) || inst1.reg2_ren && inst1.reg2_raddr === io.execute(0).reg_waddr) ||
// io.execute(1).mem_wreg && (inst1.reg1_ren && inst1.reg1_raddr === io.execute(1).reg_waddr || io.execute(1).mem_wreg && (inst1.reg1_ren && inst1.reg1_raddr === io.execute(1).reg_waddr ||
// inst1.reg2_ren && inst1.reg2_raddr === io.execute(1).reg_waddr) inst1.reg2_ren && inst1.reg2_raddr === io.execute(1).reg_waddr)
// val raw_reg = val raw_reg =
// inst0.reg_wen && (inst0.reg_waddr === inst1.reg1_raddr && inst1.reg1_ren || inst0.reg_waddr === inst1.reg2_raddr && inst1.reg2_ren) inst0.reg_wen && (inst0.reg_waddr === inst1.reg1_raddr && inst1.reg1_ren || inst0.reg_waddr === inst1.reg2_raddr && inst1.reg2_ren)
// val raw_hilo = VecInit(FU_DIV, FU_MUL, FU_MTHILO).contains(inst0.fusel) && val data_conflict = raw_reg || load_stall
// VecInit(FU_DIV, FU_MUL, FU_MFHILO, FU_MTHILO).contains(inst1.fusel)
// val raw_csr =
// inst0.op === EXE_MTC0 && inst1.op === EXE_MFC0 && inst0.csr_addr === inst1.csr_addr
// val data_conflict = raw_reg || raw_hilo || raw_csr || load_stall
// // 指令1是否允许执行 // 指令1是否允许执行
// io.inst1.allow_to_go := io.allow_to_go && io.inst1.allow_to_go := io.allow_to_go &&
// !instFifo_invalid && !instFifo_invalid &&
// inst0.dual_issue && inst0.dual_issue &&
// inst1.dual_issue && inst1.dual_issue &&
// !struct_conflict && !struct_conflict &&
// !data_conflict && !data_conflict &&
// !VecInit(FU_BR, FU_EX).contains(io.decodeInst(1).fusel) !VecInit(FuType.bru, FuType.mou).contains(io.decodeInst(1).fusel)
// } }