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feat: 升级chisel版本至5.0

This commit is contained in:
Liphen 2024-03-22 22:56:41 +08:00
parent 6508b72858
commit 0a20a7cda9
2 changed files with 2 additions and 7 deletions
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2
chisel/build.sc
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@ -7,7 +7,7 @@ import mill.scalalib.TestModule.ScalaTest
import mill.bsp._ import mill.bsp._
object playground extends ScalaModule with ScalafmtModule { m => object playground extends ScalaModule with ScalafmtModule { m =>
val useChisel5 = false val useChisel5 = true
override def scalaVersion = "2.13.10" override def scalaVersion = "2.13.10"
override def scalacOptions = Seq( override def scalacOptions = Seq(
"-language:reflectiveCalls", "-language:reflectiveCalls",

7
chisel/playground/src/Elaborate.scala
View File

@ -4,11 +4,6 @@ import circt.stage._
object Elaborate extends App { object Elaborate extends App {
implicit val cpuConfig = new CpuConfig() implicit val cpuConfig = new CpuConfig()
def top = new PuaCpu() def top = new PuaCpu()
val useMFC = false // use MLIR-based firrtl compiler
val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top)) val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
if (useMFC) { (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
(new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
} else {
(new chisel3.stage.ChiselStage).execute(args, generator)
}
} }