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style(icache): module使用小驼峰命名法

This commit is contained in:
Liphen 2023-12-24 14:14:40 +08:00
parent 881b1eca3c
commit 03ccee30f6
1 changed files with 6 additions and 6 deletions
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12
chisel/playground/src/cache/ICache.scala vendored
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@ -173,13 +173,13 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
for { i <- 0 until nway } { for { i <- 0 until nway } {
// 实例化了nway个tag ram // 实例化了nway个tag ram
val tag_bram = Module(new LUTRam(nindex, tagWidth)) val tagBram = Module(new LUTRam(nindex, tagWidth))
tag_bram.io.raddr := tag_raddr tagBram.io.raddr := tag_raddr
tag(i) := tag_bram.io.rdata tag(i) := tagBram.io.rdata
tag_bram.io.wen := tag_wstrb(i) tagBram.io.wen := tag_wstrb(i)
tag_bram.io.waddr := replace_index tagBram.io.waddr := replace_index
tag_bram.io.wdata := tag_wdata tagBram.io.wdata := tag_wdata
} }
io.cpu.icache_stall := Mux(state === s_idle && !tlb_fill, (!cache_hit_available && io.cpu.req), state =/= s_save) io.cpu.icache_stall := Mux(state === s_idle && !tlb_fill, (!cache_hit_available && io.cpu.req), state =/= s_save)