From 03ccee30f6d0ce696b5941e35cbaa29eda484e4a Mon Sep 17 00:00:00 2001 From: Liphen Date: Sun, 24 Dec 2023 14:14:40 +0800 Subject: [PATCH] =?UTF-8?q?style(icache):=20module=E4=BD=BF=E7=94=A8?= =?UTF-8?q?=E5=B0=8F=E9=A9=BC=E5=B3=B0=E5=91=BD=E5=90=8D=E6=B3=95?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/cache/ICache.scala | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/chisel/playground/src/cache/ICache.scala b/chisel/playground/src/cache/ICache.scala index 972203a..f05d2b0 100644 --- a/chisel/playground/src/cache/ICache.scala +++ b/chisel/playground/src/cache/ICache.scala @@ -173,13 +173,13 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul for { i <- 0 until nway } { // 实例化了nway个tag ram - val tag_bram = Module(new LUTRam(nindex, tagWidth)) - tag_bram.io.raddr := tag_raddr - tag(i) := tag_bram.io.rdata + val tagBram = Module(new LUTRam(nindex, tagWidth)) + tagBram.io.raddr := tag_raddr + tag(i) := tagBram.io.rdata - tag_bram.io.wen := tag_wstrb(i) - tag_bram.io.waddr := replace_index - tag_bram.io.wdata := tag_wdata + tagBram.io.wen := tag_wstrb(i) + tagBram.io.waddr := replace_index + tagBram.io.wdata := tag_wdata } io.cpu.icache_stall := Mux(state === s_idle && !tlb_fill, (!cache_hit_available && io.cpu.req), state =/= s_save)