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Author SHA1 Message Date
openharmony_ci
636a2071f7 !221 m核增加getifaddrs接口
Merge pull request !221 from 刘建东/cherry-pick-1626140156
2021-07-14 02:48:34 +00:00
YOUR_NAME
ea7f7fb741 fixed 948501a from https://gitee.com/life-liu/kernel_liteos_m/pulls/216
feat: provide getifaddrs for liteos_m

provide getifaddrs for liteos_m

close: #I400S5

Signed-off-by: liujiandong <liujiandong1@huawei.com>
2021-07-13 09:35:56 +08:00
openharmony_ci
af41b401f5 !206 m核lwip提供gn编译脚本
Merge pull request !206 from 刘建东/OpenHarmony-v2.2-Beta
2021-06-30 07:02:22 +00:00
YOUR_NAME
57ed7daf56 chore: provide lwip gn file for liteos_m
provide lwip gn file for liteos_m

close: #I3YBI6

Signed-off-by: liujiandong <liujiandong1@huawei.com>
2021-06-30 10:18:46 +08:00
1195 changed files with 8420 additions and 47846 deletions

5
.gitignore vendored
View File

@@ -14,8 +14,3 @@ targets/cortex-m7_nucleo_f767zi_gcc/build
*.o
*.d
*.su
# Menuconfig temp files
/config.h
/.config
/.config.old

308
BUILD.gn
View File

@@ -27,282 +27,46 @@
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import("//build/lite/config/component/lite_component.gni")
LITEOS_MENUCONFIG_H = rebase_path("$root_out_dir/config.h")
declare_args() {
liteos_name = "OHOS_Image"
liteos_kernel_only = false
}
import("liteos.gni")
liteos_arch_cflags = []
if (defined(LOSCFG_ARCH_ARM)) {
mcpu = LOSCFG_ARCH_CPU
if (defined(LOSCFG_ARCH_ARM_AARCH64) && defined(LOSCFG_ARCH_FPU_DISABLE)) {
mcpu += "+nofp"
}
liteos_arch_cflags += [ "-mcpu=$mcpu" ]
if (defined(LOSCFG_ARCH_ARM_AARCH32) && defined(LOSCFG_ARCH_FPU)) {
liteos_arch_cflags += [ "-mfpu=$LOSCFG_ARCH_FPU" ]
}
}
cc = "$ohos_current_cc_command " + string_join(" ", liteos_arch_cflags)
if (ohos_build_compiler == "clang") {
cc += " --target=$target_triple"
}
config("arch_config") {
cflags = liteos_arch_cflags
asmflags = cflags
ldflags = cflags
if (defined(LOSCFG_ARCH_ARM_AARCH32)) {
if (!defined(LOSCFG_COMPILER_CLANG_LLVM)) {
cflags += [ "-mthumb-interwork" ]
}
}
if (defined(LOSCFG_THUMB)) {
cflags += [ "-mthumb" ]
if (defined(LOSCFG_COMPILER_CLANG_LLVM)) {
cflags += [ "-mimplicit-it=thumb" ]
} else {
cflags += [ "-Wa,-mimplicit-it=thumb" ]
}
}
}
config("stdinc_config") {
std_include = exec_script("//build/lite/run_shell_cmd.py",
[ "$cc -print-file-name=include" ],
"trim string")
cflags = [
"-isystem",
std_include,
]
cflags += [ "-nostdinc" ]
asmflags = cflags
if (defined(LOSCFG_LIBC_NEWLIB)) {
cflags -= [ "-nostdinc" ]
}
}
config("ssp_config") {
cflags = []
if (defined(LOSCFG_CC_STACKPROTECTOR_ALL)) {
cflags += [ "-fstack-protector-all" ]
} else if (defined(LOSCFG_CC_STACKPROTECTOR_STRONG)) {
cflags += [ "-fstack-protector-strong" ]
} else if (defined(LOSCFG_CC_STACKPROTECTOR)) {
cflags += [
"-fstack-protector",
"--param",
"ssp-buffer-size=4",
]
} else {
cflags += [ "-fno-stack-protector" ]
}
asmflags = cflags
}
config("optimize_config") {
cflags = []
if (defined(LOSCFG_COMPILE_DEBUG)) {
cflags += [
"-g",
"-gdwarf-2",
]
optimization_cflag = "-O0"
}
if (defined(LOSCFG_COMPILE_OPTIMIZE)) {
optimization_cflag = "-O2"
}
if (defined(LOSCFG_COMPILE_OPTIMIZE_SIZE)) {
if (defined(LOSCFG_COMPILER_CLANG_LLVM)) {
optimization_cflag = "-Oz"
} else {
optimization_cflag = "-Os"
}
}
if (defined(LOSCFG_COMPILE_LTO)) {
if (defined(LOSCFG_COMPILER_CLANG_LLVM)) {
cflags += [ "-flto=thin" ]
} else {
#cflags += [ "-flto" ]
}
}
cflags += [ optimization_cflag ]
asmflags = cflags
}
config("kconfig_config") {
cflags = [
"-imacros",
"$LITEOS_MENUCONFIG_H",
]
asmflags = cflags
}
config("warn_config") {
cflags = [
"-Wall",
"-Werror",
"-Wpointer-arith",
"-Wstrict-prototypes",
"-Winvalid-pch",
"-Wno-address-of-packed-member",
]
asmflags = cflags
}
config("dialect_config") {
cflags_c = [ "-std=c99" ]
cflags_cc = [ "-std=c++11" ]
}
config("misc_config") {
defines = [ "__LITEOS__" ]
defines += [ "__LITEOS_M__" ]
if (!defined(LOSCFG_DEBUG_VERSION)) {
defines += [ "NDEBUG" ]
}
cflags = [
"-fno-pic",
"-fno-builtin",
"-fms-extensions",
"-fno-strict-aliasing",
"-fno-common",
"-fsigned-char",
"-ffunction-sections",
"-fdata-sections",
"-fno-exceptions",
"-fno-omit-frame-pointer",
]
if (!defined(LOSCFG_COMPILER_CLANG_LLVM)) {
cflags += [ "-fno-aggressive-loop-optimizations" ]
}
asmflags = cflags
asmflags += [ "-DCLZ=CLZ" ]
}
config("los_config") {
configs = [
#":arch_config",
":kconfig_config",
":stdinc_config",
":dialect_config",
":optimize_config",
":ssp_config",
#":warn_config",
":misc_config",
]
}
cmd = "if [ -f $device_path/BUILD.gn ]; then echo true; else echo false; fi"
HAVE_DEVICE_SDK = exec_script("//build/lite/run_shell_cmd.py", [ cmd ], "value")
# board and soc decoupling feature, device_path should contains board
BOARD_SOC_FEATURE = device_path != string_replace(device_path, "/board/", "")
config("public") {
configs = [
"arch:public",
"kernel:public",
"kal:public",
"components:public",
"utils:public",
]
if (BOARD_SOC_FEATURE) {
configs += [ "//device/board/$device_company:public" ]
configs += [ "//device/soc/$LOSCFG_SOC_COMPANY:public" ]
} else {
if (HAVE_DEVICE_SDK) {
configs += [ "$device_path:public" ]
}
}
}
group("modules") {
deps = [
"arch",
"components",
"kal",
"kernel",
"testsuites",
"utils",
HDFTOPDIR,
]
if (BOARD_SOC_FEATURE) {
deps += [ "//device/board/$device_company" ]
deps += [ "//device/soc/$LOSCFG_SOC_COMPANY" ]
} else {
if (HAVE_DEVICE_SDK) {
deps += [ device_path ]
}
}
}
# when HAVE_DEVICE_SDK is not reached, gn raises an error. so we just use it as
# not needed
not_needed([ "HAVE_DEVICE_SDK" ])
static_library("libkernel") {
deps = [ ":modules" ]
complete_static_lib = false
enable_ohos_kernel_liteos_m_cppsupport = true
enable_ohos_kernel_liteos_m_cpup = true
enable_ohos_kernel_liteos_m_exchook = true
enable_ohos_kernel_liteos_m_kal = true
enable_ohos_kernel_liteos_m_fs = true
enable_ohos_kernel_liteos_m_backtrace = true
enable_ohos_kernel_liteos_m_test = false
enable_ohos_kernel_liteos_m_lwip = false
ohos_kernel_liteos_m_lwip_path = "components/net/lwip-2.1:lwip"
}
group("kernel") {
deps = [ ":libkernel" ]
}
group("liteos_m") {
}
executable("liteos") {
configs += [
":public",
":los_config",
deps = [
"kernel:kernel",
"utils:utils",
"//third_party/bounds_checking_function:libsec_static",
]
ldflags = [
"-static",
"-Wl,--gc-sections",
"-Wl,-Map=$liteos_name.map",
]
output_dir = target_out_dir
if (liteos_kernel_only) {
deps = [ ":kernel" ]
} else {
deps = [ "//build/lite:ohos" ]
if (enable_ohos_kernel_liteos_m_cppsupport == true) {
deps += [ "components/cppsupport:cppsupport" ]
}
if (enable_ohos_kernel_liteos_m_cpup == true) {
deps += [ "components/cpup:cpup" ]
}
if (enable_ohos_kernel_liteos_m_exchook == true) {
deps += [ "components/exchook:exchook" ]
}
if (enable_ohos_kernel_liteos_m_backtrace == true) {
deps += [ "components/backtrace:backtrace" ]
}
if (enable_ohos_kernel_liteos_m_fs == true) {
deps += [ "components/fs:fs" ]
}
if (enable_ohos_kernel_liteos_m_kal == true) {
deps += [ "kal:kal" ]
}
if (enable_ohos_kernel_liteos_m_test == true) {
deps += [ "testsuits:test" ]
}
if (enable_ohos_kernel_liteos_m_lwip == true) {
deps += [ ohos_kernel_liteos_m_lwip_path ]
}
}
copy("copy_liteos") {
deps = [ ":liteos" ]
sources = [ "$target_out_dir/unstripped/bin/liteos" ]
outputs = [ "$root_out_dir/$liteos_name" ]
}
build_ext_component("build_kernel_image") {
deps = [ ":copy_liteos" ]
exec_path = rebase_path(root_out_dir)
objcopy = "${compile_prefix}objcopy$toolchain_cmd_suffix"
objdump = "${compile_prefix}objdump$toolchain_cmd_suffix"
command = "$objcopy -O binary $liteos_name $liteos_name.bin"
command +=
" && sh -c '$objdump -t $liteos_name | sort >$liteos_name.sym.sorted'"
command += " && sh -c '$objdump -d $liteos_name >$liteos_name.asm'"
}

655
Kconfig
View File

@@ -1,655 +0,0 @@
# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
# of conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mainmenu "Huawei LiteOS Configuration"
menu "Compiler"
choice
prompt "Compiler type"
default COMPILER_GCC
help
Choose compiler type.
config COMPILER_GCC
bool "GCC"
config CROSS_COMPILE
string "GCC cross-compile toolchain prefix"
depends on COMPILER_GCC
default "arm-none-eabi-" if ARCH_ARM_AARCH32
config COMPILER_CLANG_LLVM
bool "Clang"
config LLVM_TARGET
string "Clang LLVM target"
depends on COMPILER_CLANG_LLVM
default "arm-liteos-ohos" if ARCH_ARM_AARCH32
endchoice
config COMPILE_DEBUG
bool "Enable debug options"
default n
help
Answer Y to add -g option in compile command.
config COMPILE_OPTIMIZE
bool "Enable code optimization options"
default y
help
Answer Y to add optimization options for efficient code.
The final binary size will be smaller and execute faster.
But the debugging experience may be worst somehow.
config COMPILE_OPTIMIZE_SIZE
bool "Enable code size optimization options" if COMPILE_OPTIMIZE
default y
help
Answer Y to add optimization options for small code size.
The final binary size will be smaller.
But the compile time may be a bit longer.
config COMPILE_LTO
bool "Enable link time optimization (LTO)" if COMPILE_OPTIMIZE_SIZE
default y
help
Answer Y to add lto options for more smaller code size.
The final binary size will be smaller.
But the compile time may be much longer.
endmenu
menu "Platform"
######################### config options of bsp #####################
config PLATFORM
string
default "virt" if PLATFORM_QEMU_ARM_VIRT_CM7 || PLATFORM_QEMU_ARM_VIRT_CM4 || PRODUCT_QEMU_RISCV32_VIRT || PLATFORM_QEMU_CSKY_SMARTL || PLATFORM_QEMU_XTENSA_ESP32
config PRODUCT_NAME
string
default "arm_virt" if PRODUCT_QEMU_ARM
default "arm_mps2_an386" if PRODUCT_QEMU_ARM_MPS2_AN386
default "riscv32_virt" if PRODUCT_QEMU_RISCV32_VIRT
default "csky_smartl_e802" if PRODUCT_QEMU_CSKY_SMARTL_E802
default "xtensa_esp32" if PRODUCT_QEMU_XTENSA_ESP32
config DEVICE_COMPANY
string
default "qemu" if PLATFORM_QEMU_ARM_VIRT_CM7 || PLATFORM_QEMU_ARM_VIRT_CM4 || PRODUCT_QEMU_RISCV32_VIRT || PLATFORM_QEMU_CSKY_SMARTL || PLATFORM_QEMU_XTENSA_ESP32
choice
prompt "Chip"
default PLATFORM_QEMU_ARM_VIRT_CM7
help
Qemu ARM Virt variants (based on different CPU types):
- qemu_arm_virt_cm7
- qemu_arm_virt_cm4
- qemu_riscv32_virt
- qemu_csky_smartl
- qemu_xtensa_esp32
config PLATFORM_QEMU_ARM_VIRT_CM7
bool "qemu_arm_virt_cm7"
select ARCH_CORTEX_M7
help
QEMU ARM Virtual Platform using Cortex-M7 CPU.
config PLATFORM_QEMU_ARM_VIRT_CM4
bool "qemu_arm_virt_cm4"
select ARCH_CORTEX_M4
help
QEMU ARM Virtual Platform using Cortex-M4 CPU.
config PLATFORM_QEMU_RISCV32_VIRT
bool "qemu_riscv32_virt"
select ARCH_RISCV32
help
QEMU RISCV Virtual Platform using riscv32 CPU.
config PLATFORM_QEMU_CSKY_SMARTL
bool "qemu_csky_smartl"
select ARCH_CSKY
help
QEMU SmartL Virtual Platform using csky CPU.
config PLATFORM_QEMU_XTENSA_ESP32
bool "qemu_xtensa_esp32"
select ARCH_XTENSA
help
QEMU ESP32 Virtual Platform using xtensa CPU.
endchoice
choice
prompt "Product"
help
Select your target board.
config PRODUCT_QEMU_ARM
bool "arm_virt" if PLATFORM_QEMU_ARM_VIRT_CM7
config PRODUCT_QEMU_ARM_MPS2_AN386
bool "arm_mps2_an386" if PLATFORM_QEMU_ARM_VIRT_CM4
config PRODUCT_QEMU_RISCV32_VIRT
bool "riscv32_virt" if PLATFORM_QEMU_RISCV32_VIRT
config PRODUCT_QEMU_CSKY_SMARTL_E802
bool "csky_smartl_e802" if PLATFORM_QEMU_CSKY_SMARTL
config PRODUCT_QEMU_XTENSA_ESP32
bool "xtensa_esp32" if PLATFORM_QEMU_XTENSA_ESP32
endchoice
######################### config options of cpu arch ################
source "arch/Kconfig"
# Device Kconfig import
osource "$(DEVICE_PATH)/Kconfig"
config SOC_COMPANY
string "SoC company name to locate soc build path"
help
This option specifies the SoC company name, used to locate the build path for soc. This option is set by the
SoC's Kconfig file, and should be exactly the same with SoC company path, and the user should generally avoid
modifying it via the menu configuration.
orsource "../../device/board/*/Kconfig.liteos_m.shields"
orsource "../../device/board/$(BOARD_COMPANY)/Kconfig.liteos_m.defconfig.boards"
choice
prompt "Board Selection"
orsource "../../device/board/$(BOARD_COMPANY)/Kconfig.liteos_m.boards"
endchoice
orsource "../../device/soc/*/Kconfig.liteos_m.defconfig"
choice
prompt "SoC Series Selection"
orsource "../../device/soc/*/Kconfig.liteos_m.series"
endchoice
orsource "../../device/soc/*/Kconfig.liteos_m.soc"
config QUICK_START
bool "Enable QUICK_START"
default n
depends on DRIVERS && FS_VFS
help
Answer Y to enable LiteOS support quick start.
endmenu
######################### config options of kernel #####################
menu "Kernel"
######################### config options of extended #####################
config KERNEL_EXTKERNEL
bool "Enable Extend Kernel"
default y
help
This option will enable extend Kernel of LiteOS. Extend kernel include
cppsupport, cpup, etc. You can select one or some
of them.
config KERNEL_BACKTRACE
bool "Enable Backtrace"
default n
depends on KERNEL_EXTKERNEL
help
If you wish to build LiteOS with support for backtrace.
choice
prompt "Select Backtrace Type"
depends on KERNEL_BACKTRACE
config BACKTRACE_TYPE_1
bool "1: Call stack analysis for cortex-m series by scanning the stack"
depends on ARCH_ARM && !ARCH_ARM9
config BACKTRACE_TYPE_2
bool "2: Call stack analysis for risc-v by using frame pointer"
depends on ARCH_RISCV
config BACKTRACE_TYPE_3
bool "3: Call stack analysis for risc-v by scanning the stack"
depends on ARCH_RISCV
config BACKTRACE_TYPE_4
bool "4: Call stack analysis for xtensa by scanning the stack"
depends on ARCH_XTENSA
config BACKTRACE_TYPE_5
bool "5: Call stack analysis for c-sky by scanning the stack"
depends on ARCH_CSKY
config BACKTRACE_TYPE_6
bool "6: Call stack analysis for arm9 by scanning the stack"
depends on ARCH_ARM9
endchoice
config BACKTRACE_TYPE
int
default 0 if ! KERNEL_BACKTRACE
default 1 if BACKTRACE_TYPE_1
default 2 if BACKTRACE_TYPE_2
default 3 if BACKTRACE_TYPE_3
default 4 if BACKTRACE_TYPE_4
default 5 if BACKTRACE_TYPE_5
default 6 if BACKTRACE_TYPE_6
config BACKTRACE_DEPTH
int "Backtrace depth"
default 15
depends on KERNEL_BACKTRACE
config KERNEL_CPPSUPPORT
bool "Enable C++ Support"
default n
depends on KERNEL_EXTKERNEL
help
If you wish to build LiteOS with support for C++.
config BASE_CORE_CPUP
bool
default n
config KERNEL_CPUP
bool "Enable Cpup"
default n
depends on KERNEL_EXTKERNEL
select BASE_CORE_CPUP
help
If you wish to build LiteOS with support for cpup.
config CPUP_INCLUDE_IRQ
bool "Enable Cpup include irq"
default y
depends on KERNEL_CPUP
help
If you wish to include irq usage for cpup.
config DYNLINK
bool "Enable Dynamic Link Feature"
default n
depends on KERNEL_EXTKERNEL && ARCH_ARM
help
If you wish to build LiteOS with support for dynamic link.
config KERNEL_PM
bool "Enable Power Management"
default n
depends on KERNEL_EXTKERNEL
help
Configuration item for low power frame tailoring.
If you wish to build LiteOS with support for power management.
config KERNEL_PM_TASK_PTIORITY
int "Power Management Task Priority"
default 1
range 1 31
depends on KERNEL_PM
help
Configuration item for priority of low-power task.
config KERNEL_PM_TASK_STACKSIZE
int "Power Management Task Stack Size"
default 1024
depends on KERNEL_PM
help
Configuration item for stack size of low-power task.
config KERNEL_PM_DEBUG
bool "Power Management Debug"
default n
depends on KERNEL_PM
help
Configuration item for low power frame debug tailoring.
config DEBUG_HOOK
bool
default n
config PLATFORM_EXC
bool "Enable Hook Feature"
default n
depends on KERNEL_EXTKERNEL
select DEBUG_HOOK
config KERNEL_LMK
bool "Enable Low Memory Killer"
default n
depends on KERNEL_EXTKERNEL
help
Configuration item for low momery killer tailoring.
If you wish to build LiteOS with support for low memory killer.
config KERNEL_LMK_DEBUG
bool "Low Memory Killer Debug"
default n
depends on KERNEL_LMK
help
Configuration item forlow memory killer debug tailoring.
######################### config options of trace #########################
source "components/trace/Kconfig"
######################### config options of lms #########################
source "components/lms/Kconfig"
endmenu
######################### config options of lib ########################
menu "Lib"
config LIB_LIBC
bool "Enable Libc"
default y
help
Answer Y to enable libc for full code.
endmenu
######################### config options of compatibility ##############
menu "Compat"
rsource "kal/Kconfig"
endmenu
######################## config options of filesystem ##################
menu "FileSystem"
rsource "components/fs/Kconfig"
endmenu
######################## config options of net ############################
menu "Net"
config NET_LWIP
bool "Enable Lwip"
default n
select NET_LWIP_SACK
help
Answer Y to enable LiteOS support lwip.
config NET_LWIP_SACK
bool
default n
endmenu
######################## config options of debug ########################
menu "Debug"
config GDB
bool "Enable gdb functions"
default n
help
Answer Y to enable gdb functions.
config PLATFORM_ADAPT
bool "Enable Os_adapt"
default y
help
Answer Y to add os_adapt.c to LiteOS.
config ENABLE_OOM_LOOP_TASK
bool "Enable Oom loop task"
default n
depends on KERNEL_VM
help
Answer Y to enable oom loop kthread to check system out of memory.
config DO_ALIGN
bool "Enable do align for hi3518e"
default y
depends on PLATFORM_HI3518EV200
help
Answer Y to enable do align for hi3518e.
config ENABLE_MAGICKEY
bool "Enable MAGIC KEY"
default y
help
Answer Y to enable LiteOS Magic key.
ctrl + r : Magic key check switch;
ctrl + z : Show all magic op key;
ctrl + t : Show task information;
ctrl + p : System panic;
ctrl + e : Check system memory pool.
config THUMB
bool "Enable Thumb"
default n
depends on ARCH_ARM
help
Answer Y to build thumb version. This will make LiteOS smaller.
config PLATFORM_DVFS
bool "Enable Dvfs"
default n
depends on COMPAT_LINUXKPI
help
Answer Y to enable LiteOS support dynamic voltage and frequency scaling feature for
low power consumption.
config SAVE_EXCINFO
bool "Enable Saving Exception Information"
default n
help
Answer Y to enable LiteOS support saving exception information to storage medium.
config DEBUG_VERSION
bool "Enable a Debug Version"
default y
help
If you do not select this option that means you enable a release version for LiteOS.
It also means you do not want to use debug modules, like shell,telnet,tftp,nfs and
memory check, etc.
If you select this option that means you enable a debug version for LiteOS.
That means you want a opposite behaviour compared to release version.
config DEBUG_KERNEL
bool "Enable Debug LiteOS Kernel Resource"
default n
depends on DEBUG_VERSION
help
If you select this option that means you enable debugging kernel resource.
It also means you want to get queue, mutex, semaphore, memory debug information.
That means you want a opposite behaviour compared to release version.
config DEBUG_QUEUE
bool "Enable Queue Debugging"
default n
depends on DEBUG_KERNEL
help
Answer Y to enable debug queue.
config DEBUG_DEADLOCK
bool "Enable Mutex Deadlock Debugging"
default n
depends on DEBUG_KERNEL
help
Answer Y to enable debug mutex deadlock.
config DEBUG_SEMAPHORE
bool "Enable Semaphore Debugging"
default n
depends on DEBUG_KERNEL
help
Answer Y to enable debug semaphore.
source "components/shell/Kconfig"
config NET_LWIP_SACK_TFTP
bool "Enable Tftp"
default y
depends on SHELL && NET_LWIP_SACK && DEBUG_VERSION
help
Answer Y to enable LiteOS support tftp cmd and tftp tool.
osource "net/telnet/Kconfig"
config SCHED_DEBUG
bool "Enable sched debug Feature"
default n
depends on DEBUG_VERSION
help
If you wish to build LiteOS with support for sched debug.
config USER_INIT_DEBUG
bool "Enable user init Debug"
default n
depends on DEBUG_VERSION
config SHELL_CMD_DEBUG
bool "Enable shell cmd Debug"
default n
depends on DEBUG_VERSION && SHELL
config USB_DEBUG
bool "Enable USB Debug"
default n
depends on SHELL && DRIVERS_USB && DEBUG_VERSION
help
Answer Y to enable LiteOS support usb debug.
use shell command to open the specified debug level print.
config MEM_DEBUG
bool "Enable MEM Debug"
default n
depends on DEBUG_VERSION
help
Answer Y to enable LiteOS support mem debug.
config MEM_LEAKCHECK
bool "Enable Function call stack of Mem operation recorded"
default n
depends on DEBUG_VERSION && MEM_DEBUG
select KERNEL_BACKTRACE
help
Answer Y to enable record the LR of Function call stack of Mem operation, it can check the mem leak through the infomations of mem node.
config BASE_MEM_NODE_INTEGRITY_CHECK
bool "Enable integrity check or not"
default n
depends on DEBUG_VERSION && MEM_DEBUG
config MEM_WATERLINE
bool "Enable memory pool waterline or not"
default n
depends on DEBUG_VERSION && MEM_DEBUG
config VM_OVERLAP_CHECK
bool "Enable VM overlap check or not"
default n
depends on DEBUG_VERSION && MEM_DEBUG
help
Answer Y to enable vm overlap check.
endmenu
######################## config options os drivers ########################
menu "Driver"
source "drivers/Kconfig"
endmenu
######################## config options os security #######################
menu "Security"
osource "security/Kconfig"
config SECURE_TRUSTZONE
bool "Enable ARM TrustZone"
default n
depends on ARCH_ARM
config SECURE_HEAP_SIZE
int "TrustZone Heap Size (bytes)"
default 2048
depends on SECURE_TRUSTZONE
config SECURE_STACK_DEFAULT_SIZE
int "TrustZone Stack Size (bytes)"
default 512
depends on SECURE_TRUSTZONE
help
The secure stack must be allocated before the task calls non-secure functions.
endmenu
menu "Test"
config TEST
bool
default n
config KERNEL_TEST
bool "Enable Kernel Test"
default n
select TEST
config KERNEL_TEST_FULL
bool "Full Kernel Test"
default n
depends on KERNEL_TEST
endmenu
menu "Stack Smashing Protector (SSP) Compiler Feature"
choice
prompt "Enable stack buffer overflow detection"
default CC_STACKPROTECTOR_STRONG
---help---
This option turns on the -fstack-protector GCC feature. This
feature puts, at the beginning of functions, a canary value on
the stack just before the return address, and validates
the value just before actually returning. Stack based buffer
overflows (that need to overwrite this return address) now also
overwrite the canary, which gets detected and the attack is then
neutralized via a kernel panic.
This feature requires gcc version 4.2 or above, or a distribution
gcc with the feature backported. Older versions are automatically
detected and for those versions, this configuration option is
ignored. (and a warning is printed during bootup)
config CC_NO_STACKPROTECTOR
bool "-fno-stack-protector"
config CC_STACKPROTECTOR
bool "-fstack-protector"
config CC_STACKPROTECTOR_STRONG
bool "-fstack-protector-strong"
config CC_STACKPROTECTOR_ALL
bool "-fstack-protector-all"
endchoice
endmenu

122
Makefile
View File

@@ -1,122 +0,0 @@
# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
# of conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
LITEOSTOPDIR := $(realpath $(dir $(lastword $(MAKEFILE_LIST))))
export LITEOSTOPDIR
LITEOS_TARGET = liteos
HIDE := @
KCONFIG_CMDS := $(notdir $(wildcard $(dir $(shell which menuconfig))*config))
ohos_kernel ?= liteos_m
$(foreach line,$(shell hb env | sed 's/\[OHOS INFO\]/ohos/g;s/ /_/g;s/:_/=/g' || true),$(eval $(line)))
ifneq ($(ohos_kernel),liteos_m)
$(error The selected product ($(ohos_product)) is not a liteos_m kernel type product)
endif
ifeq ($(PRODUCT_PATH),)
PRODUCT_PATH:=$(ohos_product_path)
endif
ifeq ($(DEVICE_PATH),)
DEVICE_PATH:=$(ohos_device_path)
endif
ifeq ($(BOARD_COMPANY),)
BOARD_COMPANY:=$(ohos_device_company)
endif
ifeq ($(TEE:1=y),y)
tee = _tee
endif
ifeq ($(RELEASE:1=y),y)
CONFIG ?= $(PRODUCT_PATH)/kernel_configs/release$(tee).config
else
CONFIG ?= $(PRODUCT_PATH)/kernel_configs/debug$(tee).config
endif
KCONFIG_CONFIG ?= $(CONFIG)
LITEOS_MENUCONFIG_H ?= $(LITEOSTOPDIR)/config.h
LITEOS_CONFIG_FILE ?= $(LITEOSTOPDIR)/.config
# export los_config.mk related environment variables
export LITEOS_MENUCONFIG_H
export LITEOS_CONFIG_FILE
export BOARD_COMPANY
export DEVICE_PATH
export PRODUCT_PATH
# export kconfig related environment variables
export CONFIG_=LOSCFG_
export srctree=$(LITEOSTOPDIR)
-include $(LITEOS_CONFIG_FILE)
define HELP =
Usage: make [TARGET]... [PARAMETER=VALUE]...
Targets:
help: display this help and exit
clean: clean compiled objects
cleanall: clean all build outputs
all: do build (Default target)
update_config: update product kernel config (use menuconfig)
xxconfig: invoke xxconfig command of kconfiglib (xxconfig is one of $(KCONFIG_CMDS))
Parameters:
TEE: boolean value(1 or y for true), enable tee
RELEASE: boolean value(1 or y for true), build release version
CONFIG: kernel config file to be use
args: arguments for xxconfig command
endef
export HELP
all:
$(HIDE)hb build -f --gn-args "liteos_kernel_only=true liteos_name=\"$(LITEOS_TARGET)\""
help:
$(HIDE)echo "$$HELP"
$(filter-out menuconfig,$(KCONFIG_CMDS)):
$(HIDE)$@ $(args)
$(LITEOS_CONFIG_FILE): $(KCONFIG_CONFIG)
$(HIDE)env KCONFIG_CONFIG=$< genconfig --config-out $@ --header-path $(LITEOS_MENUCONFIG_H)
update_config menuconfig:
$(HIDE)test -f "$(CONFIG)" && cp -v "$(CONFIG)" .config && menuconfig $(args) && savedefconfig --out "$(CONFIG)"
clean:
$(HIDE)hb clean
$(HIDE)echo "clean $(LOSCFG_PLATFORM) finish"
cleanall: clean
$(HIDE)echo "clean all done"
.PHONY: all clean cleanall help update_config $(KCONFIG_CMDS) $(KCONFIG_CONFIG)

86
OAT.xml
View File

@@ -1,86 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Copyright (c) 2021 Huawei Device Co., Ltd.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
This is the configuration file template for OpenHarmony OSS Audit Tool, please copy it to your project root dir and modify it refer to OpenHarmony/tools_oat/README.
-->
<configuration>
<oatconfig>
<licensefile></licensefile>
<policylist>
<policy name="projectPolicy" desc="">
<policyitem type="copyright" name="Huawei Technologies Co., Ltd. All rights reserved." path=".*" desc="original liteos copyright"/>
<policyitem type="license" name="BSD-3-Clause" path=".*" desc="Liteos kernel use bsd3 license"/>
<policyitem type="license" name="BSD-3-Clause" path=".*" desc="Liteos kernel use bsd3 license"/>
</policy>
</policylist>
<filefilterlist>
<filefilter name="defaultFilter" desc="文件属于FreeBSD仓库软连接本仓库屏蔽告警在FreeBSD仓库进行处理">
<filteritem type="filepath" name="arch/risc-v/nuclei/gcc/nmsis/Library/.*" desc="文件属于三方芯片的二进制代码,属于社区贡献,不用提供额外的说明"/>
<filteritem type="filepath" name="targets/riscv_nuclei_demo_soc_gcc/.*" desc="文件属于nuclei三方芯片的源代码文件头说明跟随liteos_m/LICENSE不用额外说明"/>
<filteritem type="filepath" name="targets/riscv_nuclei_gd32vf103_soc_gcc/.*" desc="文件属于nuclei三方芯片的源代码文件头说明跟随liteos_m/LICENSE不用额外说明"/>
<filteritem type="filepath" name="NOTICE" desc="NOTICE文件"/>
<filteritem type="filepath" name="arch/risc-v/nuclei" desc="该文件的license为apache 2.0符合"/>
</filefilter>
<filefilter name="defaultFilter" desc="Files not to check">
<!--filteritem type="filename" name="*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
<!--filteritem type="filepath" name="abcdefg/.*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
<!--filteritem type="filepath" name="projectroot/[a-zA-Z0-9]{20,}.sh" desc="Temp files"/-->
</filefilter>
<filefilter name="defaultPolicyFilter" desc="Filters for compatibilitylicense header policies">
<!--filteritem type="filename" name="*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
<!--filteritem type="filepath" name="abcdefg/.*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
<!--filteritem type="filepath" name="projectroot/[a-zA-Z0-9]{20,}.sh" desc="Temp files"/-->
</filefilter>
<filefilter name="copyrightPolicyFilter" desc="Filters for copyright header policies">
<!--filteritem type="filename" name="*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
<!--filteritem type="filepath" name="abcdefg/.*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
<!--filteritem type="filepath" name="projectroot/[a-zA-Z0-9]{20,}.sh" desc="Temp files"/-->
</filefilter>
<filefilter name="licenseFileNamePolicyFilter" desc="Filters for LICENSE file policies">
<!--filteritem type="filename" name="*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
<!--filteritem type="filepath" name="abcdefg/.*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
<!--filteritem type="filepath" name="projectroot/[a-zA-Z0-9]{20,}.sh" desc="Temp files"/-->
</filefilter>
<filefilter name="readmeFileNamePolicyFilter" desc="Filters for README file policies">
<!--filteritem type="filename" name="*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
<!--filteritem type="filepath" name="abcdefg/.*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
<!--filteritem type="filepath" name="projectroot/[a-zA-Z0-9]{20,}.sh" desc="Temp files"/-->
</filefilter>
<filefilter name="readmeOpenSourcefileNamePolicyFilter" desc="Filters for README.OpenSource file policies">
<!--filteritem type="filename" name="*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
<!--filteritem type="filepath" name="abcdefg/.*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
<!--filteritem type="filepath" name="projectroot/[a-zA-Z0-9]{20,}.sh" desc="Temp files"/-->
</filefilter>
<filefilter name="binaryFileTypePolicyFilter" desc="Filters for binary file policies">
<!--filteritem type="filename" name="*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
<!--filteritem type="filepath" name="abcdefg/.*.uvwxyz" desc="Describe the reason for filtering scan results"/-->
<!--filteritem type="filepath" name="projectroot/[a-zA-Z0-9]{20,}.sh" desc="Temp files"/-->
</filefilter>
</filefilterlist>
<licensematcherlist>
<!--licensematcher name="uvwxyz License" desc="If the scanning result is InvalidLicense, you can define matching rules here. Note that quotation marks must be escaped.">
<licensetext name="
uvwxyz license textA xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
" desc=""/>
<licensetext name="
uvwxyz license textB xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
" desc=""/>
</licensematcher-->
</licensematcherlist>
</oatconfig>
</configuration>

119
README.md
View File

@@ -1,134 +1,85 @@
# LiteOS-M Kernel<a name="EN-US_TOPIC_0000001096757661"></a>
# LiteOS Cortex-M<a name="EN-US_TOPIC_0000001096757661"></a>
- [Introduction](#section11660541593)
- [Directory Structure](#section161941989596)
- [Constraints](#section119744591305)
- [Usage](#section3732185231214)
- [Contribution](#section1371123476307)
- [Repositories Involved](#section1371113476307)
## Introduction<a name="section11660541593"></a>
OpenHarmony LiteOS-M is a lightweight operating system kernel designed for the Internet of Things (IoT) field. It features small footprint, low power consumption, and high performance. It has a simple code structure, including the minimum kernel function set, kernel abstraction layer, optional components, and project directory. The LiteOS-M kernel is divided into the hardware layer and hardware-irrelevant layers. The hardware layer provides a unified hardware abstraction layer (HAL) interface for easier hardware adaptation. A range of compilation toolchains can be used with different chip architectures to meet the expansion of diversified hardware and compilation toolchains in the Artificial Intelligence of Things (AIoT) field.
**Figure1** shows the architecture of the LiteOS-M kernel.
The OpenHarmony LiteOS Cortex-M is the kernel designed for the lightweight operating system \(OS\) for the Internet of Things \(IoT\) field. It features small size, low power consumption, and high performance. In addition, it has a simple code structure, including the minimum kernel function set, kernel abstraction layer, optional components, and project directory, and is divided into the hardware-related and hardware-irrelevant layers. The hardware-related layers provide unified hardware abstraction layer \(HAL\) interfaces to improve hardware adaptability. The combination and classification of different compilation toolchains and chip architectures meet the requirements of the Artificial Intelligence of Things \(AIoT\) field for rich hardware and compilation toolchains. [Figure1](#fig0865152210223) shows the architecture of the OpenHarmony LiteOS Cortex-M kernel.
**Figure 1** Architecture of the OpenHarmony LiteOS-M kernel<a name="fig0865152210223"></a>
![](figures/architecture-of-openharmony-the-liteos-cortex-m-kernel.png "OpenHarmony-LiteOS-M Kernel Architecture")
**Figure 1** Architecture of OpenHarmony the LiteOS Cortex-M kernel<a name="fig0865152210223"></a>
![](figures/architecture-of-openharmony-the-liteos-cortex-m-kernel.png "architecture-of-openharmony-the-liteos-cortex-m-kernel")
## Directory Structure<a name="section161941989596"></a>
The directory structure is as follows. For more details, see [arch_spec.md](arch_spec.md).
The directory structure is listed as below, for the detailed directories, please refer to [arch_spec.md](arch_spec.md).
```
/kernel/liteos_m
├── arch # Code of the kernel instruction architecture layer
│ ├── arm # Code of the ARM32 architecture
│ │ ├── arm9 # Code of the ARM9 architecture
│ │ ├── cortex-m3 # Code of the cortex-m3 architecture
│ │ ├── cortex-m33 # Code of the cortex-m33 architecture
│ │ ├── cortex-m4 # Code of the cortex-m4 architecture
│ │ ├── cortex-m7 # Code of the cortex-m7 architecture
│ │ └── include # Arm architecture public header file directory
│ ├── csky # Code of the csky architecture
│ │ └── v2 # Code of the csky v2 architecture
│ ├── include # APIs exposed externally
│ ├── risc-v # Code of the risc-v architecture
│ │ ├── nuclei # Code of the nuclei system technology risc-v architecture
│ │ └── riscv32 # Code of the risc-v architecture
│ └── xtensa # Code of the xtensa architecture
│ └── lx6 # Code of the lx6 xtensa architecture
├── components # Optional components
│ ├── backtrace # Backtrace support
│ ├── cppsupport # C++ support
│ ├── cpup # CPU percent (CPUP)
│ ├── dynlink # Dynamic loading and linking
│ ├── exchook # Exception hooks
── fs # File systems
│ ├── lmk # Low memory killer functions
│ ├── lms # Lite memory sanitizer functions
│ ├── net # Networking functions
│ ├── power # Power management
│ ├── shell # Shell function
│ ├── fs # File systems
│ └── trace # Trace tool
├── drivers # driver Kconfig
│ ├── cpup # CPU possession (CPUP)
│ ├── exchook # Exception hook
│ ├── fs # File system
── net # Network support
├── kal # Kernel abstraction layer
│ ├── cmsis # CMSIS API support
│ ├── cmsis # CMSIS-compliant API support
│ └── posix # POSIX API support
├── kernel # Minimum kernel function set
├── kernel # Minimum function set support
│ ├── arch # Code of the kernel instruction architecture layer
│ │ ├── arm # Code of the ARM32 architecture
│ │ └── include # APIs exposed externally
│ ├── include # APIs exposed externally
│ └── src # Source code of the minimum kernel function set
│ └── src # Source code of the minimum function set of the kernel
├── targets # Board-level projects
├── testsuites # Kernel testsuites
├── tools # Kernel tools
├── utils # Common directory
├── utils # Common code
```
## Constraints<a name="section119744591305"></a>
OpenHarmony LiteOS-M supports only C and C++.
Programming languages: C and C++
Applicable architecture: See the directory structure for the arch layer.
As for dynamic loading module, the shared library to be loaded needs signature verification or source restriction to ensure security.
Currently applicable architectures: Cortex-M3, Cortex-M4, Cortex-M7, and RISC-V
## Usage<a name="section3732185231214"></a>
The OpenHarmony LiteOS-M kernel build system is a modular build system based on Generate Ninja (GN) and Ninja. It supports module-based configuration, tailoring, and assembling, and helps you build custom products. This document describes how to build a LiteOS-M project based on GN and Ninja. For details about the methods such as GCC+gn, IAR, and Keil MDK, visit the community websites.
### Setting Up the Environment
Before setting up the environment for a development board, you must set up the basic system environment for OpenHarmony first. The basic system environment includes the OpenHarmony build environment and development environment. For details, see [Setting Up Development Environment](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/quick-start/quickstart-lite-env-setup.md).
### Obtaining the OpenHarmony Source Code
For details about how to obtain the source code, see [Source Code Acquisition](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/get-code/sourcecode-acquire.md). This document assumes that the clone directory is `~/openHarmony` after the complete OpenHarmony repository code is obtained.
### Example projects that are already supported
Qemu simulator: `arm_mps2_an386、esp32、riscv32_virt、SmartL_E802`, For details about how to compile and run, see [qemu guide](https://gitee.com/openharmony/device_qemu)
Bestechnic: `bes2600`, For details about how to compile and run, see [Bestechnic developer guide](https://gitee.com/openharmony/device_soc_bestechnic)
### Community Porting Project Links
The LiteOS-M kernel porting projects for specific development boards are provided by community developers. The following provides the links to these projects. If you have porting projects for more development boards, you can provide your links to share your projects.
LiteOS Cortex-M provides projects for three chip architectures, which are located in the **targets** directory. The methods of compiling and using these projects are as follows:
- Cortex-M3:
- STM32F103 https://gitee.com/rtos_lover/stm32f103_simulator_keil
This repository provides the Keil project code for building the OpenHarmony LiteOS-M kernel based on the STM32F103 chip architecture. This code supports build in Keil MDK mode.
The **kernel/liteos\_m/targets/cortex-m3\_stm32f103\_simulator\_keil** directory is the Keil project directory created based on the STM32F103 chip architecture. You can download and install Keil development tools from the Internet. To compile the Cortex-M3 project, go to the **cortex-m3\_stm32f103\_simulator\_keil/project** directory and double-click the **los\_demo.uvproj** file to open the desired project. After the compilation is successful, burn the file to the corresponding board using JLINK or STM32 ST-LINK Utility.
- Cortex-M4:
- STM32F429IGTb https://gitee.com/harylee/stm32f429ig_firechallenger
This repository provides the project code for porting the OpenHarmony LiteOS-M kernel to support the STM32F429IGTb development board. The code supports build in Ninja, GCC, and IAR modes.
The **kernel/liteos\_m/targets/cortex-m4\_stm32f429ig\_fire-challenger\_iar** directory is the IAR project directory created based on the STM32F429IG chip architecture. You can download and install IAR development tools from the Internet. To compile the Cortex-M4 project, go to the **cortex-m4\_stm32f429ig\_fire-challenger\_iar/project** directory and double-click the **los\_demo.eww** file to open the desired project. After the compilation is successful, burn the file to the corresponding board using JLINK or STM32 ST-LINK Utility.
- Cortex-M7:
- Nucleo-F767ZI https://gitee.com/harylee/nucleo_f767zi
The **kernel/liteos\_m/targets/cortex-m7\_nucleo\_f767zi\_gcc** directory is the Makefile project directory created based on the STM32F767ZI chip architecture. The compilation commands are as follows:
This repository provides the project code for porting the OpenHarmony LiteOS-M kernel to support the Nucleo-F767ZI development board. The code supports build in Ninja, GCC, and IAR modes.
```
cd kernel/liteos_m/targets/cortex-m7_nucleo_f767zi_gcc
make clean; make
```
## Contribution<a name="section1371123476307"></a>
After the compilation is successful, the executable file **NUCLEO-F767.hex** is generated in the **cortex-m7\_nucleo\_f767zi\_gcc/build** directory. Burn the file to the corresponding board using STM32 ST-LINK Utility.
[How to involve](https://gitee.com/openharmony/docs/blob/HEAD/en/contribute/contribution.md)
## Change Log
[Commit message spec](https://gitee.com/openharmony/kernel_liteos_m/wikis/Commit%20message%E8%A7%84%E8%8C%83)
v1.0.1
1. removed these KAL apis: `KalThreadGetInfo`,`KalDelayUs`,`KalTimerCreate`,`KalTimerStart`,`KalTimerChange`,`KalTimerStop`,`KalTimerDelete`,`KalTimerIsRunning`,`KalTickToMs`,`KalMsToTick`,`KalGetMemInfo`
2. add some POSIX apis
[Liteos-M kernel coding style guide](https://gitee.com/openharmony/kernel_liteos_m/wikis/OpenHarmony%E8%BD%BB%E5%86%85%E6%A0%B8%E7%BC%96%E7%A0%81%E8%A7%84%E8%8C%83)
How to contribute a chip based on Liteos-M kernel:
[ Board-Level Directory Specifications](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/porting/porting-chip-board-overview.md)
[Mini System SoC Porting Guide](https://gitee.com/openharmony/docs/blob/HEAD/en/device-dev/porting/porting-minichip.md)
v1.0
1. first release
## Repositories Involved<a name="section1371113476307"></a>
[Kernel Subsystem](https://gitee.com/openharmony/docs/blob/HEAD/en/readme/kernel-subsystem.md)
[Kernel subsystem](https://gitee.com/openharmony/docs/blob/master/en/readme/kernel.md)
**kernel\_liteos\_m**

View File

@@ -4,7 +4,6 @@
- [目录](#section161941989596)
- [约束](#section119744591305)
- [使用说明](#section3732185231214)
- [贡献](#section1371123476307)
- [相关仓](#section1371113476307)
## 简介<a name="section11660541593"></a>
@@ -20,45 +19,23 @@ OpenHarmony LiteOS-M内核是面向IoT领域构建的轻量级物联网操作系
```
/kernel/liteos_m
├── arch # 内核指令架构层目录
│ ├── arm # arm 架构代码
│ │ ├── arm9 # arm9 架构代码
│ │ ├── cortex-m3 # cortex-m3架构代码
│ │ ├── cortex-m33 # cortex-m33架构代码
│ │ ├── cortex-m4 # cortex-m4架构代码
│ │ ├── cortex-m7 # cortex-m7架构代码
│ │ └── include # arm架构公共头文件目录
│ ├── csky # csky架构代码
│ │ └── v2 # csky v2架构代码
│ ├── include # 架构层对外接口存放目录
│ ├── risc-v # risc-v 架构
│ │ ├── nuclei # 芯来科技risc-v架构代码
│ │ └── riscv32 # risc-v官方通用架构代码
│ └── xtensa # xtensa 架构代码
│ └── lx6 # xtensa lx6架构代码
├── components # 可选组件
│ ├── backtrace # 回溯功能
│ ├── backtrace # 回溯栈支持
│ ├── cppsupport # C++支持
│ ├── cpup # CPUP功能
│ ├── dynlink # 动态加载与链接
│ ├── exchook # 异常钩子
│ ├── fs # 文件系统
── lmk # Low memory killer 机制
│ ├── lms # Lite memory sanitizer 机制
│ ├── net # Network功能
│ ├── power # 低功耗管理
│ ├── shell # shell功能
│ └── trace # trace 工具
├── drivers # 驱动框架Kconfig
── net # Network功能
├── kal # 内核抽象层
│ ├── cmsis # cmsis标准接口支持
│ └── posix # posix标准接口支持
├── kernel # 内核最小功能集支持
│ ├── arch # 内核指令架构层代码
│ │ ├── arm # arm32架构的代码
│ │ └── include # 对外接口存放目录
│ ├── include # 对外接口存放目录
│ └── src # 内核最小功能集源码
├── targets # 板级工程目录
├── testsuites # 内核测试用例
├── tools # 内核工具
├── utils # 通用公共目录
```
@@ -66,28 +43,58 @@ OpenHarmony LiteOS-M内核是面向IoT领域构建的轻量级物联网操作系
开发语言C/C++
适用架构:详见目录结构arch层
动态加载模块:待加载的共享库需要验签或者限制来源,确保安全性。
适用架构:当前只适用于cortex-m3、cortex-m4、cortex-m7、risc-v芯片架构
## 使用说明<a name="section3732185231214"></a>
OpenHarmony
LiteOS-M内核的编译构建系统是一个基于gn和ninja的组件化构建系统支持按组件配置、裁剪和拼装按需构建出定制化的产品。本文主要介绍如何基于gn和ninja编译LiteOS-M工程GCC+gn、IAR、Keil MDK等编译方式可以参考社区爱好者贡献的站点。
OpenHarmony LiteOS-M内核的编译构建系统是一个基于gn和ninja的组件化构建系统支持按组件配置、裁剪和拼装按需构建出定制化的产品。编译构建系统的详细信息可以参考[轻量和小型系统编译构建指导](https://gitee.com/openharmony/docs/blob/master/zh-cn/device-dev/subsystems/%E8%BD%BB%E9%87%8F%E5%92%8C%E5%B0%8F%E5%9E%8B%E7%B3%BB%E7%BB%9F%E7%BC%96%E8%AF%91%E6%9E%84%E5%BB%BA%E6%8C%87%E5%AF%BC.md)。本文主要介绍如何基于gn和ninja编译LiteOS-M工程GCC+Makefile、IAR、Keil MDK等编译方式可以参考社区爱好者贡献的站点。
### 搭建系统基础环境
在搭建各个开发板环境前需要完成OpenHarmony系统基础环境搭建。系统基础环境主要是指OpenHarmony的编译环境和开发环境详细介绍请参考官方站点[开发环境准备](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/device-dev/quick-start/quickstart-lite-env-setup.md)。开发者需要根据环境搭建文档完成环境搭建
在搭建各个开发板环境前需要完成OpenHarmony系统基础环境搭建。系统基础环境主要是指OpenHarmony的编译环境和开发环境详细介绍请参考官方站点[Ubuntu编译环境准备](https://gitee.com/openharmony/docs/blob/master/zh-cn/device-dev/quick-start/Ubuntu%E7%BC%96%E8%AF%91%E7%8E%AF%E5%A2%83%E5%87%86%E5%A4%87.md)。开发者需要根据环境搭建文档完成下述软件的安装Python3.7+、gn、ninja、hb。对于LiteOS-M内核还需要安装Make构建工具和[ARM GCC编译工具链](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads)
### 获取OpenHarmony源码
详细的源码获取方式,请见[源码获取](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/device-dev/get-code/sourcecode-acquire.md)。获取OpenHarmony完整仓代码后假设克隆目录为`~/openHarmony`
开发者需要在Linux服务器上通过Git克隆获取OpenHarmony最新源码详细的源码获取方式,请见[源码获取](https://gitee.com/openharmony/docs/blob/master/zh-cn/device-dev/get-code/%E6%BA%90%E7%A0%81%E8%8E%B7%E5%8F%96.md)。获取OpenHarmony完整仓代码后假设克隆目录为`~/openHarmony`
### 已支持的示例工程
### 获取示例工程源码
Qemu模拟器: `arm_mps2_an386、esp32、riscv32_virt、SmartL_E802`, 编译运行详见: [Qemu指导](https://gitee.com/openharmony/device_qemu)
以开发板Nucleo-F767Zi为例演示如何编译运行`OpenHarmony LiteOS-M`内核工程。在本地目录,执行下述命令克隆示例代码。
恒玄科技: `bes2600`, 编译运行详见: [恒玄开发指导](https://gitee.com/openharmony/device_soc_bestechnic)
```
git clone https://gitee.com/harylee/nucleo_f767zi.git
```
假设克隆到的代码目录为`~/nucleo_f767zi`。 执行如下命令把代码目录的`device``vendor`目录复制到`openHarmony`工程的相应目录。
```
mkdir ~/openHarmony/device/st
cp -r ~/nucleo_f767zi/device/st/nucleo_f767zi ~/openHarmony/device/st/nucleo_f767zi
chmod +x ~/openHarmony/device/st/nucleo_f767zi/build.sh
cp -r ~/nucleo_f767zi/vendor/st ~/openHarmony/vendor/st
```
关于示例代码目录的说明,可以参考资料站点[板级目录规范](https://gitee.com/openharmony/docs/blob/master/zh-cn/device-dev/porting/%E7%A7%BB%E6%A4%8D%E6%A6%82%E8%BF%B0-0.md#section6204129143013)。如果需要自行移植开发板,请参考[板级系统移植](https://gitee.com/openharmony/docs/blob/master/zh-cn/device-dev/porting/%E6%9D%BF%E7%BA%A7%E7%B3%BB%E7%BB%9F%E7%A7%BB%E6%A4%8D.md)。
### 编译运行
编译运行前,交叉编译工具链`bin`目录配置到`PATH`环境变量中或者配置`device/st/nucleo_f767zi/liteos_m/config.gni`文件中`board_toolchain_path`配置项为交叉编译工具链`bin`目录。
`OpenHarmony`根目录,执行`hb set`设置产品路径,选择`nucleo_f767zi`产品,然后执行`hb build`开启编译。如下:
```
user@dev:~/OpenHarmony$ hb set
[OHOS INFO] Input code path: # 直接按回车然后选择nucleo_f767zi产品即可
OHOS Which product do you need? nucleo_f767zi@st
user@dev:~/OpenHarmony$ hb build
```
最终的镜像生成在`~/openHarmony/out/nucleo_f767zi/`目录中,通过`STM32 ST-LINK Utility`软件将镜像文件下载至单板查看运行效果。
### 社区移植工程链接
@@ -111,25 +118,18 @@ LiteOS-M内核移植的具体开发板的工程由社区开发者提供可以
该仓包含OpenHarmony LiteOS-M内核移植支持`Nucleo-F767ZI`开发板的工程代码支持Ninja、GCC、IAR等方式进行编译。
## 贡献<a name="section1371123476307"></a>
## 修改日志
[如何贡献](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/contribute/%E5%8F%82%E4%B8%8E%E8%B4%A1%E7%8C%AE.md)
v1.0.1
1. 删除以下KAL接口: `KalThreadGetInfo`,`KalDelayUs`,`KalTimerCreate`,`KalTimerStart`,`KalTimerChange`,`KalTimerStop`,`KalTimerDelete`,`KalTimerIsRunning`,`KalTickToMs`,`KalMsToTick`,`KalGetMemInfo`
2. 添加部分POSIX接口
[Commit message规范](https://gitee.com/openharmony/kernel_liteos_m/wikis/Commit%20message%E8%A7%84%E8%8C%83)
[Liteos-M 内核编码规范](https://gitee.com/openharmony/kernel_liteos_m/wikis/OpenHarmony%E8%BD%BB%E5%86%85%E6%A0%B8%E7%BC%96%E7%A0%81%E8%A7%84%E8%8C%83)
如何基于Liteos-M内核贡献一款芯片:
[板级目录规范](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/device-dev/porting/porting-chip-board-overview.md)
[轻量系统芯片移植指导](https://gitee.com/openharmony/docs/blob/master/zh-cn/device-dev/porting/porting-minichip.md)
[轻量系统芯片移植案例](https://gitee.com/openharmony/docs/blob/master/zh-cn/device-dev/porting/porting-minichip-cases.md)
v1.0
1. 首次发布
## 相关仓<a name="section1371113476307"></a>
[内核子系统](https://gitee.com/openharmony/docs/blob/HEAD/zh-cn/readme/%E5%86%85%E6%A0%B8%E5%AD%90%E7%B3%BB%E7%BB%9F.md)
[内核子系统](https://gitee.com/openharmony/docs/blob/master/zh-cn/readme/%E5%86%85%E6%A0%B8%E5%AD%90%E7%B3%BB%E7%BB%9F.md)
**kernel\_liteos\_m**

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@@ -1,52 +0,0 @@
# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
# of conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import("//kernel/liteos_m/liteos.gni")
config("arch_config") {
include_dirs = [ "include" ]
}
module_group("arch") {
modules = []
if ("$board_cpu" == "arm9" || "$board_cpu" == "cortex-m3" ||
"$board_cpu" == "cortex-m4" || "$board_cpu" == "cortex-m7" ||
"$board_cpu" == "cortex-m33") {
modules += [ "arm" ]
} else if ("$board_cpu" == "ck802" || "$board_cpu" == "e802") {
modules += [ "csky" ]
} else if ("$board_cpu" == "") {
if ("$board_arch" == "rv32imac" || "$board_arch" == "rv32imafdc") {
modules += [ "risc-v" ]
} else if ("$board" == "esp32") {
modules += [ "xtensa" ]
}
}
configs = [ ":arch_config" ]
}

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@@ -1,53 +0,0 @@
config ARCH_ARM
bool
rsource "arm/Kconfig"
config ARCH_CSKY
bool
config ARCH_RISCV
bool
config ARCH_RISCV32
bool
select ARCH_RISCV
config ARCH_XTENSA
bool
comment "Extra Configurations"
config ARCH_FPU_DISABLE
bool "Disable Floating Pointer Unit"
default n
help
This option will bypass floating procedure in system.
config ARCH_SECURE_MONITOR_MODE
bool "Run On Secure Monitor Mode"
default n
depends on ARCH_ARM_AARCH64
help
This option will make the system run on EL3.
config ARCH_INTERRUPT_PREEMPTION
bool "Enable Interrupt Preemption"
default n
depends on ARCH_ARM_AARCH64
help
This option will support high priority interrupt preemption.
config IRQ_USE_STANDALONE_STACK
bool "Use Interrupt Stack"
default y
depends on ARCH_ARM_AARCH64 || ARCH_ARM_AARCH32
help
This option will support using standalone interrupt stack.
config ARCH_UNALIGNED_EXC
bool "Enable Unaligned Exception"
default y
depends on ARCH_ARM
help
This option will enable unaligned exception.

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@@ -1,39 +0,0 @@
# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
# of conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import("//kernel/liteos_m/liteos.gni")
config("arm_config") {
include_dirs = [ "include" ]
}
module_group("arm") {
modules = [ "$board_cpu/gcc" ]
configs = [ ":arm_config" ]
}

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@@ -1,108 +0,0 @@
# ARM Architecture
#
# ARM has 32-bit(Aarch32) and 64-bit(Aarch64) implementations
#
config ARCH_ARM_AARCH32
bool
select ARCH_ARM
help
32-bit ARM architecture implementations, Except the M-profile.
It is not limited to ARMv7-A but also ARMv7-R, ARMv8-A 32-bit and etc.
#
# Architecture Versions
#
config ARCH_ARM_V7M
bool
config ARCH_ARM_V5TE
bool
config ARCH_ARM_VER
string
default "armv7-m" if ARCH_ARM_V7M
default "armv5te" if ARCH_ARM_V5TE
#
# VFP Hardware
#
config ARCH_FPU_VFP_V3
bool
help
An optional extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles.
VFPv3U is a variant of VFPv3 that supports the trapping of floating-point exceptions to support code.
config ARCH_FPU_VFP_V4
bool
help
An optional extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles.
VFPv4U is a variant of VFPv4 that supports the trapping of floating-point exceptions to support code.
VFPv4 and VFPv4U add both the Half-precision Extension and the fused multiply-add instructions to the features of VFPv3.
config ARCH_FPU_VFP_D16
bool
depends on ARCH_ARM_AARCH32
help
VPU implemented with 16 doubleword registers (16 x 64-bit).
config ARCH_FPU_VFP_D32
bool
depends on ARCH_ARM_AARCH32
help
VPU implemented with 32 doubleword registers (32 x 64-bit).
config ARCH_FPU_VFP_NEON
bool
help
Advanced SIMD extension (NEON) support.
config ARCH_FPU
string
default "vfpv3" if ARCH_FPU_VFP_V3 && ARCH_FPU_VFP_D32
default "vfpv3-d16" if ARCH_FPU_VFP_V3 && ARCH_FPU_VFP_D16
default "neon-vfpv4" if ARCH_FPU_VFP_V4 && ARCH_FPU_VFP_D32 && ARCH_FPU_VFP_NEON
default "vfpv4" if ARCH_FPU_VFP_V4 && ARCH_FPU_VFP_D32
default "vfpv4-d16" if ARCH_FPU_VFP_V4 && ARCH_FPU_VFP_D16
#
# Supported Processor Cores
#
config ARCH_CORTEX_M3
bool
select ARCH_ARM_V7M
select ARCH_ARM_AARCH32
config ARCH_CORTEX_M4
bool
select ARCH_ARM_V7M
select ARCH_ARM_AARCH32
config ARCH_CORTEX_M7
bool
select ARCH_ARM_V7M
select ARCH_ARM_AARCH32
select ARCH_FPU_VFP_V4
select ARCH_FPU_VFP_D32
select ARCH_FPU_VFP_NEON
config ARCH_CORTEX_M33
bool
select ARCH_ARM_V7M
select ARCH_ARM_AARCH32
select ARCH_FPU_VFP_V4
select ARCH_FPU_VFP_D32
select ARCH_FPU_VFP_NEON
config ARCH_ARM9
bool
select ARCH_ARM_V5TE
select ARCH_ARM_AARCH32
config ARCH_CPU
string
default "cortex-m3" if ARCH_CORTEX_M3
default "cortex-m4" if ARCH_CORTEX_M4
default "cortex-m7" if ARCH_CORTEX_M7
default "cortex-m33" if ARCH_CORTEX_M33
default "arm9" if ARCH_ARM9

View File

@@ -1,46 +0,0 @@
# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
# of conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import("//kernel/liteos_m/liteos.gni")
module_name = "arch"
kernel_module(module_name) {
sources = [
"los_context.c",
"los_dispatch.S",
"los_exc.S",
"los_interrupt.c",
"los_timer.c",
"reset_vector.S",
]
}
config("public") {
include_dirs = [ "." ]
}

View File

@@ -1,237 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_ATOMIC_H
#define _LOS_ARCH_ATOMIC_H
#include "los_compiler.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
{
UINT32 intSave;
intSave = LOS_IntLock();
LOS_IntRestore(intSave);
return *v;
}
STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
{
UINT32 intSave;
intSave = LOS_IntLock();
*v = setVal;
LOS_IntRestore(intSave);
}
STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
{
INT32 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v += addVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
{
INT32 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v -= subVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomicInc(Atomic *v)
{
(VOID)ArchAtomicAdd(v, 1);
}
STATIC INLINE VOID ArchAtomicDec(Atomic *v)
{
(VOID)ArchAtomicSub(v, 1);
}
STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
{
return ArchAtomicAdd(v, 1);
}
STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
{
return ArchAtomicSub(v, 1);
}
STATIC INLINE INT32 ArchAtomicXchg32bits(Atomic *v, INT32 val)
{
INT32 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
*v = val;
LOS_IntRestore(intSave);
return prevVal;
}
STATIC INLINE BOOL ArchAtomicCmpXchg32bits(Atomic *v, INT32 val, INT32 oldVal)
{
INT32 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
if (prevVal == oldVal) {
*v = val;
}
LOS_IntRestore(intSave);
return prevVal != oldVal;
}
STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
{
UINT32 intSave;
intSave = LOS_IntLock();
*v = setVal;
LOS_IntRestore(intSave);
}
STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v += addVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v -= subVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
{
(VOID)ArchAtomic64Add(v, 1);
}
STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
{
return ArchAtomic64Add(v, 1);
}
STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
{
(VOID)ArchAtomic64Sub(v, 1);
}
STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
{
return ArchAtomic64Sub(v, 1);
}
STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
{
INT64 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
*v = val;
LOS_IntRestore(intSave);
return prevVal;
}
STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
{
INT64 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
if (prevVal == oldVal) {
*v = val;
}
LOS_IntRestore(intSave);
return prevVal != oldVal;
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_ATOMIC_H */

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@@ -1,181 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_CONTEXT_H
#define _LOS_ARCH_CONTEXT_H
#include "los_config.h"
#include "los_compiler.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#define PSR_T_ARM 0x00000000U
#define PSR_T_THUMB 0x00000020U
#define PSR_MODE_SVC 0x00000013U
#define PSR_MODE_SYS 0x0000001FU
#define PSR_MODE_SVC_THUMB (PSR_MODE_SVC | PSR_T_THUMB)
#define PSR_MODE_SVC_ARM (PSR_MODE_SVC | PSR_T_ARM)
#define PSR_MODE_SYS_THUMB (PSR_MODE_SYS | PSR_T_THUMB)
#define PSR_MODE_SYS_ARM (PSR_MODE_SYS | PSR_T_ARM)
VOID OsTaskEntryArm(VOID);
VOID OsTaskEntryThumb(VOID);
typedef struct TagTskContext {
UINT32 spsr;
UINT32 r0;
UINT32 r1;
UINT32 r2;
UINT32 r3;
UINT32 r4;
UINT32 r5;
UINT32 r6;
UINT32 r7;
UINT32 r8;
UINT32 r9;
UINT32 r10;
UINT32 r11;
UINT32 r12;
UINT32 sp;
UINT32 lr;
UINT32 pc;
} TaskContext;
/**
* @ingroup los_config
* @brief: Task start running function.
*
* @par Description:
* This API is used to start a task.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param: None.
*
* @retval None.
*
* @par Dependency:
* <ul><li>los_config.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID HalStartToRun(VOID);
/**
* @ingroup los_arch_context
* @brief Wait for interrupt.
*
* @par Description:
* <ul>
* <li>This API is used to suspend execution until interrupt or a debug request occurs.</li>
* </ul>
* @attention None.
*
* @param None.
*
* @retval: None.
*
* @par Dependency:
* los_arch_context.h: the header file that contains the API declaration.
* @see None.
*/
extern VOID wfi(VOID);
/**
* @ingroup los_arch_context
* @brief: mem fence function.
*
* @par Description:
* This API is used to fence for memory.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param: None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_arch_context.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID dmb(VOID);
/**
* @ingroup los_arch_context
* @brief: mem fence function.
*
* @par Description:
* This API is same as dmb, it just for adaptation.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param: None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_arch_context.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID dsb(VOID);
/**
* @ingroup los_arch_context
* @brief: instruction fence function.
*
* @par Description:
* This API is used to fence for instruction.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param: None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_arch_context.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID isb(VOID);
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_CONTEXT_H */

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@@ -1,353 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_INTERRUPT_H
#define _LOS_ARCH_INTERRUPT_H
#include "los_config.h"
#include "los_compiler.h"
#include "los_interrupt.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
/* *
* @ingroup los_arch_interrupt
* Maximum number of used hardware interrupts.
*/
#ifndef OS_HWI_MAX_NUM
#define OS_HWI_MAX_NUM LOSCFG_PLATFORM_HWI_LIMIT
#endif
/* *
* @ingroup los_arch_interrupt
* Highest priority of a hardware interrupt.
*/
#ifndef OS_HWI_PRIO_HIGHEST
#define OS_HWI_PRIO_HIGHEST 0
#endif
/* *
* @ingroup los_arch_interrupt
* Lowest priority of a hardware interrupt.
*/
#ifndef OS_HWI_PRIO_LOWEST
#define OS_HWI_PRIO_LOWEST 7
#endif
/* *
* @ingroup los_arch_interrupt
* Define the type of a hardware interrupt vector table function.
*/
typedef VOID (**HWI_VECTOR_FUNC)(void);
/* *
* @ingroup los_arch_interrupt
* Count of interrupts.
*/
extern UINT32 g_intCount;
/* *
* @ingroup los_arch_interrupt
* Count of arm9 system interrupt vector.
*/
#define OS_SYS_VECTOR_CNT 0
/* *
* @ingroup los_arch_interrupt
* Count of arm9 interrupt vector.
*/
#define OS_VECTOR_CNT (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Invalid interrupt number.
*
* Value: 0x02000900
*
* Solution: Ensure that the interrupt number is valid. The value range of the interrupt number applicable for a Cortex-A7 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
*/
#define OS_ERRNO_HWI_NUM_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Null hardware interrupt handling function.
*
* Value: 0x02000901
*
* Solution: Pass in a valid non-null hardware interrupt handling function.
*/
#define OS_ERRNO_HWI_PROC_FUNC_NULL LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
*
* Value: 0x02000902
*
* Solution: Increase the configured maximum number of supported hardware interrupts.
*/
#define OS_ERRNO_HWI_CB_UNAVAILABLE LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
*
* Value: 0x02000903
*
* Solution: Expand the configured memory.
*/
#define OS_ERRNO_HWI_NO_MEMORY LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: The interrupt has already been created.
*
* Value: 0x02000904
*
* Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
*/
#define OS_ERRNO_HWI_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Invalid interrupt priority.
*
* Value: 0x02000905
*
* Solution: Ensure that the interrupt priority is valid. The value range of the interrupt priority applicable for a Cortex-A7 platform is [0,15].
*/
#define OS_ERRNO_HWI_PRIO_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Incorrect interrupt creation mode.
*
* Value: 0x02000906
*
* Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or OS_HWI_MODE_FAST of which the value can be 0 or 1.
*/
#define OS_ERRNO_HWI_MODE_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
*
* Value: 0x02000907
*
* Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
*/
#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
/* *
* @ingroup los_hwi
* Set interrupt vector table.
*/
extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg);
#else
/* *
* @ingroup los_hwi
* Set interrupt vector table.
*/
extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
#endif
/* *
* @ingroup los_arch_interrupt
* @brief: Hardware interrupt entry function.
*
* @par Description:
* This API is used as all hardware interrupt handling function entry.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param:None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID HalInterrupt(VOID);
/* *
* @ingroup los_arch_interrupt
* @brief: Get an interrupt number.
*
* @par Description:
* This API is used to get the current interrupt number.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param: None.
*
* @retval: Interrupt Indexes number.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern UINT32 HalIntNumGet(VOID);
/* *
* @ingroup los_arch_interrupt
* @brief: Default vector handling function.
*
* @par Description:
* This API is used to configure interrupt for null function.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param:None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li
></ul>
* @see None.
*/
extern VOID HalHwiDefaultHandler(VOID);
#define OS_EXC_IN_INIT 0
#define OS_EXC_IN_TASK 1
#define OS_EXC_IN_HWI 2
#define OS_EXC_FLAG_FAULTADDR_VALID 0x01
#define OS_EXC_FLAG_IN_HWI 0x02
#define OS_EXC_IMPRECISE_ACCESS_ADDR 0xABABABAB
/**
* @ingroup los_exc
* the struct of register files
*
* description: the register files that saved when exception triggered
*
* notes:the following register with prefix 'uw' correspond to the registers in the cpu data sheet.
*/
typedef struct TagExcContext {
UINT32 spsr;
UINT32 r0;
UINT32 r1;
UINT32 r2;
UINT32 r3;
UINT32 r4;
UINT32 r5;
UINT32 r6;
UINT32 r7;
UINT32 r8;
UINT32 r9;
UINT32 r10;
UINT32 r11;
UINT32 r12;
UINT32 sp;
UINT32 lr;
UINT32 pc;
} EXC_CONTEXT_S;
typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
VOID HalHwiInit(VOID);
/**
* @ingroup los_exc
* exception types: undefined instruction exception.
*/
#define OS_EXCEPT_UNDEF_INSTR 1
/**
* @ingroup los_exc
* exception types: software interrupt.
*/
#define OS_EXCEPT_SWI 2
/**
* @ingroup los_exc
* exception types: prefetch abort exception.
*/
#define OS_EXCEPT_PREFETCH_ABORT 3
/**
* @ingroup los_exc
* exception types: data abort exception.
*/
#define OS_EXCEPT_DATA_ABORT 4
/**
* @ingroup los_exc
* exception types: FIQ exception.
*/
#define OS_EXCEPT_FIQ 5
/**
* @ingroup los_exc
* Exception information structure
*
* Description: Exception information saved when an exception is triggered on the Cortex-M4 platform.
*
*/
typedef struct TagExcInfo {
/**< Exception occurrence phase: 0 means that an exception occurs in initialization,
* 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
UINT16 phase;
/**< Exception type. When exceptions occur, check the numbers 1 - 19 listed above */
UINT16 type;
/**< If the exact address access error indicates the wrong access address when the exception occurred */
UINT32 faultAddr;
/**< An exception occurs in an interrupt, indicating the interrupt number.
* An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
UINT32 thrdPid;
/**< Number of nested exceptions. Currently only registered hook functions are supported
* when an exception is entered for the first time */
UINT16 nestCnt;
/**< reserve */
UINT16 reserved;
/**< Hardware context at the time an exception to the automatic stack floating-point register occurs */
EXC_CONTEXT_S *context;
} ExcInfo;
extern UINT32 g_intCount;
extern ExcInfo g_excInfo;
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_INTERRUPT_H */

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@@ -1,51 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_TIMER_H
#define _LOS_ARCH_TIMER_H
#include "los_config.h"
#include "los_compiler.h"
#include "los_timer.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_TIMER_H */

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@@ -1,151 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_context.h"
#include "securec.h"
#include "los_arch_context.h"
#include "los_arch_interrupt.h"
#include "los_task.h"
#include "los_sched.h"
#include "los_interrupt.h"
#include "los_debug.h"
/* ****************************************************************************
Function : ArchInit
Description : arch init function
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
{
HalHwiInit();
}
/* ****************************************************************************
Function : ArchSysExit
Description : Task exit function
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
{
LOS_IntLock();
while (1) {
}
}
/* ****************************************************************************
Function : ArchTskStackInit
Description : Task stack initialization function
Input : taskID --- TaskID
stackSize --- Total size of the stack
topStack --- Top of task's stack
Output : None
Return : Context pointer
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
{
TaskContext *context = NULL;
LosTaskCB *taskCB = OS_TCB_FROM_TID(taskID);
errno_t result;
/* initialize the task stack, write magic num to stack top */
result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize);
if (result != EOK) {
PRINT_ERR("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__);
}
*((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD;
context = (TaskContext *)(((UINTPTR)topStack + stackSize) - sizeof(TaskContext));
context->r0 = taskID;
context->r1 = 0x01010101L;
context->r2 = 0x02020202L;
context->r3 = 0x03030303L;
context->r4 = 0x04040404L;
context->r5 = 0x05050505L;
context->r6 = 0x06060606L;
context->r7 = 0x07070707L;
context->r8 = 0x08080808L;
context->r9 = 0x09090909L;
context->r10 = 0x10101010L;
context->r11 = 0x11111111L;
context->r12 = 0x12121212L;
context->sp = (UINTPTR)topStack + stackSize;
context->lr = (UINTPTR)ArchSysExit;
if ((UINTPTR)taskCB->taskEntry & 0x01) {
context->pc = (UINTPTR)OsTaskEntryThumb;
context->spsr = PSR_MODE_SYS_THUMB; /* thumb mode */
} else {
context->pc = (UINTPTR)OsTaskEntryArm;
context->spsr = PSR_MODE_SYS_ARM; /* arm mode */
}
return (VOID *)context;
}
LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
{
(VOID)LOS_IntLock();
OsSchedStart();
HalStartToRun();
return LOS_OK; /* never return */
}
LITE_OS_SEC_TEXT_INIT VOID ArchTaskSchedule(VOID)
{
__asm__ __volatile__("swi 0");
}
LITE_OS_SEC_TEXT_INIT VOID dmb(VOID)
{
__asm__ __volatile__("" : : : "memory");
}
LITE_OS_SEC_TEXT_INIT VOID dsb(VOID)
{
__asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(0) : "memory");
}
LITE_OS_SEC_TEXT_INIT VOID isb(VOID)
{
__asm__ __volatile__("" : : : "memory");
}
LITE_OS_SEC_TEXT_INIT VOID wfi(VOID)
{
__asm__ __volatile__("mcr p15, 0, %0, c7, c0, 4" : : "r"(0) : "memory");
}

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@@ -1,182 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.equ OS_PSR_THUMB, 0x20
.equ OS_PSR_INT_DIS, 0xC0
.equ OS_PSR_FIQ_DIS, 0x40
.equ OS_PSR_IRQ_DIS, 0x80
.equ OS_PSR_MODE_MASK, 0x1F
.equ OS_PSR_MODE_USR, 0x10
.equ OS_PSR_MODE_FIQ, 0x11
.equ OS_PSR_MODE_IRQ, 0x12
.equ OS_PSR_MODE_SVC, 0x13
.equ OS_PSR_MODE_ABT, 0x17
.equ OS_PSR_MODE_UND, 0x1B
.equ OS_PSR_MODE_SYS, 0x1F
.global HalStartToRun
.global OsTaskEntryArm
.global OsTaskEntryThumb
.global HalExceptSwiHdl
.global HalExceptFiqHdl
.global HalExceptIrqHdl
.extern OsTaskEntry
.extern OsSchedTaskSwitch
.extern HalInterrupt
.extern g_losTask
.code 32
.text
.macro SAVE_CONTEXT
STMFD SP!, {R0}
MRS R0, SPSR
AND R0, R0, #OS_PSR_MODE_SYS
CMP R0, #OS_PSR_MODE_SYS
BNE 1f
STMFD SP!, {SP}^
LDMFD SP!, {R0}
STMFD R0!, {LR}
MOV LR, R0
LDMFD SP!, {R0}
STMFD LR, {R0-R14}^
SUB LR, LR, #60
MRS R0, SPSR
STMFD LR!, {R0}
LDR R1, =g_losTask
LDR R1, [R1]
STR LR, [R1]
B 2f
1:
LDMFD SP!, {R0}
STMFD SP!, {R0-R12, LR}
MRS R0, SPSR
STMFD SP!, {R0}
2:
.endm
.macro RETSORE_CONTEXT
MRS R0, SPSR
AND R0, R0, #OS_PSR_MODE_SYS
CMP R0, #OS_PSR_MODE_SYS
BNE 3f
LDR R1, =g_losTask
LDR R1, [R1]
LDR LR, [R1]
LDMFD LR!, {R0}
MSR SPSR_cxsf, R0
LDMFD LR, {R0-R14}^
ADD LR, LR, #60
LDMFD LR!, {PC}^
3:
LDMFD SP!, {R0}
MSR SPSR_cxsf, R0
LDMFD SP!, {R0-R12, LR}
MOVS PC, LR
.endm
.macro TASK_SWITCH
MRS R0, CPSR
ORR R0, R0, #OS_PSR_INT_DIS
MSR CPSR, R0
BLX OsSchedTaskSwitch
CMP R0, #0
BEQ 4f
LDR R0, =g_losTask
LDR R1, [R0, #4]
STR R1, [R0]
4:
.endm
HalStartToRun:
LDR R1, =g_losTask
LDR R0, [R1, #4]
LDR LR, [R0]
LDMFD LR!, {R0}
MSR SPSR_cxsf, R0
LDMFD LR, {R0-R14}^
ADD LR, LR, #60
LDMFD LR!, {PC}^
HalExceptSwiHdl:
SAVE_CONTEXT
TASK_SWITCH
RETSORE_CONTEXT
HalExceptFiqHdl:
SUB LR, LR, #4
SAVE_CONTEXT
BLX HalInterrupt
RETSORE_CONTEXT
HalExceptIrqHdl:
SUB LR, LR, #4
SAVE_CONTEXT
BLX HalInterrupt
RETSORE_CONTEXT
OsTaskEntryArm:
STMFD SP!, {LR}
BL OsTaskEntry
LDMFD SP!, {LR}
BX LR
.code 16
.text
OsTaskEntryThumb:
PUSH {LR}
BL OsTaskEntry
POP {R0}
MOV LR, R0
BX LR

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@@ -1,132 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.equ OS_PSR_INT_DIS, 0xC0
.equ OS_PSR_FIQ_DIS, 0x40
.equ OS_PSR_IRQ_DIS, 0x80
.equ OS_PSR_MODE_MASK, 0x1F
.equ OS_PSR_MODE_USR, 0x10
.equ OS_PSR_MODE_FIQ, 0x11
.equ OS_PSR_MODE_IRQ, 0x12
.equ OS_PSR_MODE_SVC, 0x13
.equ OS_PSR_MODE_ABT, 0x17
.equ OS_PSR_MODE_UND, 0x1B
.equ OS_PSR_MODE_SYS, 0x1F
.equ OS_EXCEPT_RESET, 0x00
.equ OS_EXCEPT_UNDEF_INSTR, 0x01
.equ OS_EXCEPT_SWI, 0x02
.equ OS_EXCEPT_PREFETCH_ABORT, 0x03
.equ OS_EXCEPT_DATA_ABORT, 0x04
.equ OS_EXCEPT_FIQ, 0x05
.equ OS_EXCEPT_ADDR_ABORT, 0x06
.equ OS_EXCEPT_IRQ, 0x07
.global HalExceptAddrAbortHdl
.global HalExceptDataAbortHdl
.global HalExceptPrefetchAbortHdl
.global HalExceptUndefInstrHdl
.extern HalExcHandleEntry
.extern __exc_stack_top
.code 32
.text
HalExceptUndefInstrHdl:
STMFD SP!, {R0-R5}
MOV R0, #OS_EXCEPT_UNDEF_INSTR
B _osExceptDispatch
HalExceptPrefetchAbortHdl:
SUB LR, LR, #4
STMFD SP!, {R0-R5}
MOV R0, #OS_EXCEPT_PREFETCH_ABORT
B _osExceptDispatch
HalExceptDataAbortHdl:
SUB LR, LR, #4
STMFD SP!, {R0-R5}
MOV R0, #OS_EXCEPT_DATA_ABORT
B _osExceptDispatch
HalExceptAddrAbortHdl:
SUB LR, LR, #8
STMFD SP!, {R0-R5}
MOV R0, #OS_EXCEPT_ADDR_ABORT
B _osExceptDispatch
_osExceptDispatch:
MRS R1, SPSR
MOV R2, LR
MOV R4, SP
ADD SP, SP, #(6 * 4)
MSR CPSR_c, #(OS_PSR_INT_DIS | OS_PSR_MODE_SVC)
MOV R3, SP
LDR SP, =__exc_stack_top
STMFD SP!, {R2}
STMFD SP!, {LR}
STMFD SP!, {R3}
STMFD SP!, {R6-R12}
LDMFD R4!, {R6-R12}
STMFD SP!, {R6-R11}
STMFD SP!, {R1}
MOV R3, SP
_osExceptionGetSP:
STMFD SP!, {R1}
LDR R2, =HalExcHandleEntry
MOV LR, PC
BX R2
LDMFD SP!, {R1}
MOV SP, R1
LDMFD SP!, {R1}
MSR CPSR, R1
LDMFD SP!, {R0-R12}
ADD SP, SP, #(4 * 2)
LDMFD SP!, {LR}
SUB SP, SP, #(4 * 3)
LDMFD SP, {SP}
ADD LR, LR, #4
MOV PC, LR
.end

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@@ -1,481 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_interrupt.h"
#include <stdarg.h>
#include "securec.h"
#include "los_context.h"
#include "los_arch_interrupt.h"
#include "los_debug.h"
#include "los_hook.h"
#include "los_task.h"
#include "los_sched.h"
#include "los_memory.h"
#include "los_membox.h"
#include "los_reg.h"
#define OS_INT_IRQ_ENABLE (1U << 0)
#define OS_INT_FIQ_ENABLE (1U << 1)
#define OS_INT_REG_BASE 0x00802040UL
#define OS_INT_GLOBAL_ENABLE_ADDR (OS_INT_REG_BASE + 4)
#define OS_INT_ENABLE_ADDR (OS_INT_REG_BASE)
#define OS_INT_STATUS_ADDR (OS_INT_REG_BASE + 12)
#define OS_INT_ENABLE(num) (*((volatile UINT32 *)OS_INT_ENABLE_ADDR) |= (1U << (num)))
#define OS_INT_DISABLE(num) (*((volatile UINT32 *)OS_INT_ENABLE_ADDR ) &= ~(1U << (num)))
#define OS_INSTR_SET_MASK 0x01000020U
#define OS_ARM_INSTR_LEN 4
#define OS_THUMB_INSTR_LEN 2
UINT32 g_intCount = 0;
ExcInfo g_excInfo = {0};
/* *
* @ingroup los_hwi
* hardware interrupt form mapping handling function array.
*/
STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
typedef struct {
HWI_PROC_FUNC pfnHandler;
VOID *pParm;
} HWI_HANDLER_FUNC;
/* *
* @ingroup los_hwi
* hardware interrupt handler form mapping handling function array.
*/
STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
/* *
* @ingroup los_hwi
* Set interrupt vector table.
*/
VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg)
{
if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalInterrupt;
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector;
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg;
}
}
#else
/* *
* @ingroup los_hwi
* hardware interrupt handler form mapping handling function array.
*/
STATIC HWI_PROC_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {0};
/* *
* @ingroup los_hwi
* Set interrupt vector table.
*/
VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
{
if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
g_hwiForm[num + OS_SYS_VECTOR_CNT] = HalInterrupt;
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector;
}
}
#endif
/* ****************************************************************************
Function : HalIntNumGet
Description : Get an interrupt number
Input : None
Output : None
Return : Interrupt Indexes number
**************************************************************************** */
LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
{
UINT32 status;
READ_UINT32(status, OS_INT_STATUS_ADDR);
return (31 - CLZ(status));
}
inline UINT32 ArchIsIntActive(VOID)
{
return (g_intCount > 0);
}
/* ****************************************************************************
Function : HalHwiDefaultHandler
Description : default handler of the hardware interrupt
Input : None
Output : None
Return : None
**************************************************************************** */
/*lint -e529*/
LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
{
UINT32 irqNum = HalIntNumGet();
PRINT_ERR("%s irqnum:%d\n", __FUNCTION__, irqNum);
while (1) {}
}
WEAK VOID HalPreInterruptHandler(UINT32 arg)
{
return;
}
WEAK VOID HalAftInterruptHandler(UINT32 arg)
{
return;
}
/* ****************************************************************************
Function : HalInterrupt
Description : Hardware interrupt entry function
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
{
UINT32 intSave;
UINT32 hwiIndex;
intSave = LOS_IntLock();
g_intCount++;
LOS_IntRestore(intSave);
#if (LOSCFG_BASE_CORE_SCHED_SLEEP == 1)
OsSchedUpdateSleepTime();
#endif
hwiIndex = HalIntNumGet();
OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
HalPreInterruptHandler(hwiIndex);
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
}
#else
if (g_hwiHandlerForm[hwiIndex] != 0) {
g_hwiHandlerForm[hwiIndex]();
}
#endif
HalAftInterruptHandler(hwiIndex);
OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
intSave = LOS_IntLock();
g_intCount--;
LOS_IntRestore(intSave);
}
/* ****************************************************************************
Function : ArchHwiCreate
Description : create hardware interrupt
Input : hwiNum --- hwi num to create
hwiPrio --- priority of the hwi
mode --- unused
handler --- hwi handler
arg --- param of the hwi handler
Output : None
Return : LOS_OK on success or error code on failure
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
HWI_PRIOR_T hwiPrio,
HWI_MODE_T mode,
HWI_PROC_FUNC handler,
HWI_ARG_T arg)
{
UINT32 intSave;
if (handler == NULL) {
return OS_ERRNO_HWI_PROC_FUNC_NULL;
}
if (hwiNum >= OS_HWI_MAX_NUM) {
return OS_ERRNO_HWI_NUM_INVALID;
}
if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
return OS_ERRNO_HWI_ALREADY_CREATED;
}
intSave = LOS_IntLock();
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
OsSetVector(hwiNum, handler, arg);
#else
OsSetVector(hwiNum, handler);
#endif
OS_INT_ENABLE(hwiNum);
LOS_IntRestore(intSave);
return LOS_OK;
}
/* ****************************************************************************
Function : ArchHwiDelete
Description : Delete hardware interrupt
Input : hwiNum --- hwi num to delete
Output : None
Return : LOS_OK on success or error code on failure
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
{
UINT32 intSave;
if (hwiNum >= OS_HWI_MAX_NUM) {
return OS_ERRNO_HWI_NUM_INVALID;
}
OS_INT_DISABLE(hwiNum);
intSave = LOS_IntLock();
g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
LOS_IntRestore(intSave);
return LOS_OK;
}
#if (LOSCFG_KERNEL_PRINTF != 0)
STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
{
CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
PRINTK("Type = %d\n", excInfo->type);
PRINTK("ThrdPid = %d\n", excInfo->thrdPid);
PRINTK("Phase = %s\n", phaseStr[excInfo->phase]);
PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
}
STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
{
PRINTK("Current task info:\n");
if (excInfo->phase == OS_EXC_IN_TASK) {
LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
PRINTK("Task name = %s\n", taskCB->taskName);
PRINTK("Task ID = %d\n", taskCB->taskID);
PRINTK("Task SP = 0x%x\n", taskCB->stackPointer);
PRINTK("Task ST = 0x%x\n", taskCB->topOfStack);
PRINTK("Task SS = 0x%x\n", taskCB->stackSize);
} else if (excInfo->phase == OS_EXC_IN_HWI) {
PRINTK("Exception occur in interrupt phase!\n");
} else {
PRINTK("Exception occur in system init phase!\n");
}
}
STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
{
PRINTK("Exception reg dump:\n");
PRINTK("PC = 0x%x\n", excInfo->context->pc);
PRINTK("LR = 0x%x\n", excInfo->context->lr);
PRINTK("R0 = 0x%x\n", excInfo->context->r0);
PRINTK("R1 = 0x%x\n", excInfo->context->r1);
PRINTK("R2 = 0x%x\n", excInfo->context->r2);
PRINTK("R3 = 0x%x\n", excInfo->context->r3);
PRINTK("R4 = 0x%x\n", excInfo->context->r4);
PRINTK("R5 = 0x%x\n", excInfo->context->r5);
PRINTK("R6 = 0x%x\n", excInfo->context->r6);
PRINTK("R7 = 0x%x\n", excInfo->context->r7);
PRINTK("R8 = 0x%x\n", excInfo->context->r8);
PRINTK("R9 = 0x%x\n", excInfo->context->r9);
PRINTK("R10 = 0x%x\n", excInfo->context->r10);
PRINTK("R11 = 0x%x\n", excInfo->context->r11);
PRINTK("R12 = 0x%x\n", excInfo->context->r12);
PRINTK("xPSR = 0x%x\n", excInfo->context->spsr);
}
STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
{
UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
UINT32 index;
OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->sp);
PRINTK("----- backtrace start -----\n");
for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
if (LR[index] == 0) {
break;
}
PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]);
}
PRINTK("----- backtrace end -----\n");
}
STATIC VOID OsExcMemPoolCheckInfo(VOID)
{
PRINTK("\r\nmemory pools check:\n");
#if (LOSCFG_PLATFORM_EXC == 1)
MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
UINT32 errCnt;
UINT32 i;
(VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
if (errCnt < OS_SYS_MEM_NUM) {
errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
}
if (errCnt == 0) {
PRINTK("all memory pool check passed!\n");
return;
}
for (i = 0; i < errCnt; i++) {
PRINTK("pool num = %d\n", i);
PRINTK("pool type = %d\n", memExcInfo[i].type);
PRINTK("pool addr = 0x%x\n", memExcInfo[i].startAddr);
PRINTK("pool size = 0x%x\n", memExcInfo[i].size);
PRINTK("pool free = 0x%x\n", memExcInfo[i].free);
PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize);
PRINTK("pool error node addr = 0x%x\n", memExcInfo[i].errorAddr);
PRINTK("pool error node len = 0x%x\n", memExcInfo[i].errorLen);
PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner);
}
#endif
UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
if (ret == LOS_OK) {
PRINTK("system heap memcheck over, all passed!\n");
}
PRINTK("memory pool check end!\n");
}
#endif
STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
{
#if (LOSCFG_KERNEL_PRINTF != 0)
PRINTK("*************Exception Information**************\n");
OsExcTypeInfo(excInfo);
OsExcCurTaskInfo(excInfo);
OsExcRegInfo(excInfo);
OsExcBackTraceInfo(excInfo);
OsGetAllTskInfo();
OsExcMemPoolCheckInfo();
#endif
}
LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr)
{
g_intCount++;
g_excInfo.nestCnt++;
g_excInfo.type = excType;
if ((excType == OS_EXCEPT_UNDEF_INSTR) || (excType == OS_EXCEPT_SWI)) {
if ((excBufAddr->spsr & OS_INSTR_SET_MASK) == 0) { /* Work status: ARM */
excBufAddr->pc -= OS_ARM_INSTR_LEN;
} else if ((excBufAddr->spsr & OS_INSTR_SET_MASK) == 0x20) { /* Work status: Thumb */
excBufAddr->pc -= OS_THUMB_INSTR_LEN;
}
}
g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
if (g_losTask.runTask != NULL) {
g_excInfo.phase = OS_EXC_IN_TASK;
g_excInfo.thrdPid = g_losTask.runTask->taskID;
} else {
g_excInfo.phase = OS_EXC_IN_INIT;
g_excInfo.thrdPid = OS_NULL_INT;
}
g_excInfo.context = excBufAddr;
OsDoExcHook(EXC_INTERRUPT);
OsExcInfoDisplay(&g_excInfo);
ArchSysExit();
}
/* ****************************************************************************
Function : HalHwiInit
Description : initialization of the hardware interrupt
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
{
#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
UINT32 reg;
UINT32 val;
for (val = OS_SYS_VECTOR_CNT; val < OS_VECTOR_CNT; val++) {
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
g_hwiForm[val].pfnHook = HalHwiDefaultHandler;
g_hwiForm[val].uwParam = 0;
#else
g_hwiForm[val] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
#endif
}
val = OS_INT_IRQ_ENABLE | OS_INT_FIQ_ENABLE;
READ_UINT32(reg, OS_INT_GLOBAL_ENABLE_ADDR);
reg |= val;
WRITE_UINT32(reg, OS_INT_GLOBAL_ENABLE_ADDR);
#endif
return;
}
UINT32 ArchIntLock(VOID)
{
UINT32 ret;
UINT32 temp;
__asm__ __volatile__("MRS %0, CPSR\n"
"ORR %1, %0, #0xC0\n"
"MSR CPSR_c, %1"
: "=r"(ret), "=r"(temp)
:
: "memory");
return ret;
}
VOID ArchIntRestore(UINT32 intSave)
{
__asm__ __volatile__("MSR CPSR_c, %0" : : "r"(intSave));
}
UINT32 ArchIntUnLock(VOID)
{
UINT32 intSave;
__asm__ __volatile__("MRS %0, CPSR\n"
"BIC %0, %0, #0xC0\n"
"MSR CPSR_c, %0"
: "=r"(intSave)
:
: "memory");
return intSave;
}

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@@ -1,168 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_timer.h"
#include "los_config.h"
#include "los_arch_context.h"
#include "los_arch_interrupt.h"
#include "los_reg.h"
#define OS_TIMER_CLKDIV_POS 3
#define OS_TIMER_CLKDIV_MASK 7
#define OS_TIMER_INT_POS 7
#define OS_TIMER_INT_MASK 7
#define OS_TIMER_IRQ_NUM 8
#define OS_TIMER_ENABLE (1U << 0)
#define OS_TIMER_32K_CLK_BIT (1U << 21)
#define OS_TIMER_CNT_READ_BIT (1U << 0)
#define OS_TIMER_REG_BASE 0x00802A40UL
#define OS_TIMER_CLK_PWD_ADDR 0x00802008UL
#define OS_TIMER_PERIOD_REG_ADDR (OS_TIMER_REG_BASE)
#define OS_TIMER_CTL_REG_ADDR (OS_TIMER_REG_BASE + 12)
#define OS_TIMER_READ_CTL_ADDR (OS_TIMER_REG_BASE + 16)
#define OS_TIMER_READ_VAL_ADDR (OS_TIMER_REG_BASE + 20)
STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
STATIC VOID SysTickReload(UINT64 nextResponseTime);
STATIC UINT64 SysTickCycleGet(UINT32 *period);
STATIC VOID SysTickLock(VOID);
STATIC VOID SysTickUnlock(VOID);
STATIC ArchTickTimer g_archTickTimer = {
.freq = 0,
.irqNum = OS_TIMER_IRQ_NUM,
.init = SysTickStart,
.getCycle = SysTickCycleGet,
.reload = SysTickReload,
.lock = SysTickLock,
.unlock = SysTickUnlock,
.tickHandler = NULL,
};
STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
{
UINT32 intSave = LOS_IntLock();
UINT32 value;
ArchTickTimer *tick = &g_archTickTimer;
tick->freq = OS_SYS_CLOCK;
READ_UINT32(value, OS_TIMER_CLK_PWD_ADDR);
value &= ~(OS_TIMER_32K_CLK_BIT);
WRITE_UINT32(value, OS_TIMER_CLK_PWD_ADDR);
value = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX;
WRITE_UINT32(value, OS_TIMER_PERIOD_REG_ADDR);
READ_UINT32(value, OS_TIMER_CTL_REG_ADDR);
value &= ~(OS_TIMER_CLKDIV_MASK << OS_TIMER_CLKDIV_POS); // The default is 1, and the clock does not divide.
value &= ~(OS_TIMER_INT_MASK << OS_TIMER_INT_POS); // Clearing interruption.
value |= 0x1 << OS_TIMER_INT_POS;
value |= OS_TIMER_ENABLE; // Enable timer.
WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR);
(VOID)ArchHwiCreate(OS_TIMER_IRQ_NUM, 0, 0, (HWI_PROC_FUNC)handler, 0);
LOS_IntRestore(intSave);
return LOS_OK;
}
STATIC VOID SysTickClockIrqClear(VOID)
{
UINT32 mask = OS_TIMER_INT_MASK << OS_TIMER_INT_POS;
UINT32 status;
do {
WRITE_UINT32(mask, OS_TIMER_CTL_REG_ADDR);
READ_UINT32(status, OS_TIMER_CTL_REG_ADDR);
} while (status & mask);
}
STATIC VOID SysTickReload(UINT64 nextResponseTime)
{
SysTickLock();
WRITE_UINT32(nextResponseTime, OS_TIMER_PERIOD_REG_ADDR);
SysTickClockIrqClear();
SysTickUnlock();
}
STATIC UINT64 SysTickCycleGet(UINT32 *period)
{
UINT32 val;
READ_UINT32(*period, OS_TIMER_PERIOD_REG_ADDR);
WRITE_UINT32(OS_TIMER_CNT_READ_BIT, OS_TIMER_READ_CTL_ADDR);
do {
READ_UINT32(val, OS_TIMER_READ_CTL_ADDR);
} while (val & OS_TIMER_CNT_READ_BIT); // Wait for the setting to take effect.
READ_UINT32(val, OS_TIMER_READ_VAL_ADDR);
return (UINT64)val;
}
STATIC VOID SysTickLock(VOID)
{
UINT32 value;
READ_UINT32(value, OS_TIMER_CTL_REG_ADDR);
value &= ~OS_TIMER_ENABLE;
value &= ~(OS_TIMER_INT_MASK << OS_TIMER_INT_POS);
value |= 0x1 << OS_TIMER_INT_POS;
WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR);
}
STATIC VOID SysTickUnlock(VOID)
{
UINT32 value;
READ_UINT32(value, OS_TIMER_CTL_REG_ADDR);
value |= OS_TIMER_ENABLE;
value &= ~(OS_TIMER_INT_MASK << OS_TIMER_INT_POS);
value |= 0x1 << OS_TIMER_INT_POS;
WRITE_UINT32(value, OS_TIMER_CTL_REG_ADDR);
}
ArchTickTimer *ArchSysTickTimerGet(VOID)
{
return &g_archTickTimer;
}
UINT32 ArchEnterSleep(VOID)
{
dsb();
wfi();
isb();
return LOS_OK;
}

View File

@@ -1,149 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.equ CPSR_IRQ_DISABLE, 0x80
.equ CPSR_FIQ_DISABLE, 0x40
.equ CPSR_THUMB_ENABLE, 0x20
.equ CPSR_USER_MODE, 0x10
.equ CPSR_FIQ_MODE, 0x11
.equ CPSR_IRQ_MODE, 0x12
.equ CPSR_SVC_MODE, 0x13
.equ CPSR_ABT_MODE, 0x17
.equ CPSR_UNDEF_MODE, 0x1B
.global __exc_stack_top
.global __irq_stack_top
.global __fiq_stack_top
.global __svc_stack_top
.global __abt_stack_top
.global __undef_stack_top
.global __exc_stack
.global __irq_stack
.global __fiq_stack
.global __svc_stack
.global __abt_stack
.global __undef_stack
.global main
.extern HalExceptFiqHdl
.extern HalExceptAddrAbortHdl
.extern HalExceptDataAbortHdl
.extern HalExceptPrefetchAbortHdl
.extern HalExceptSwiHdl
.extern HalExceptUndefInstrHdl
.extern HalExceptIrqHdl
.extern _bss_start
.extern _bss_end
.code 32
.text
.section ".vectors", "ax"
.global _vector_start
_vector_start:
B HalResetVector
B HalExceptUndefInstrHdl
B HalExceptSwiHdl
B HalExceptPrefetchAbortHdl
B HalExceptDataAbortHdl
B HalExceptAddrAbortHdl
B HalExceptIrqHdl
B HalExceptFiqHdl
.globl HalResetVector
.section ".boot", "ax"
HalResetVector:
MOV R0, #(CPSR_IRQ_DISABLE | CPSR_FIQ_DISABLE | CPSR_IRQ_MODE)
MSR CPSR, R0
LDR SP, =__irq_stack_top
MOV R0, #(CPSR_IRQ_DISABLE | CPSR_FIQ_DISABLE | CPSR_UNDEF_MODE)
MSR CPSR, R0
LDR SP, =__undef_stack_top
MOV R0, #(CPSR_IRQ_DISABLE | CPSR_FIQ_DISABLE | CPSR_ABT_MODE)
MSR CPSR, R0
LDR SP, =__abt_stack_top
MOV R0, #(CPSR_IRQ_DISABLE | CPSR_FIQ_DISABLE | CPSR_FIQ_MODE)
MSR CPSR, R0
LDR SP, =__fiq_stack_top
MOV R0, #(CPSR_IRQ_DISABLE | CPSR_FIQ_DISABLE | CPSR_SVC_MODE)
MSR CPSR, R0
MSR SPSR, R0
LDR SP, =__svc_stack_top
BL OsBssInit
B main
B .
OsBssInit:
LDR R0, =_bss_start
LDR R1, =_bss_end
MOV R3, R1
MOV R4, R0
MOV R2, #0
1: CMP R4, R3
STRLO R2, [R4], #4
BLO 1b
BX LR
.section ".bss", "wa", %nobits
.align 3
__undef_stack:
.space 32
__undef_stack_top:
__abt_stack:
.space 32
__abt_stack_top:
__irq_stack:
.space 1024
__irq_stack_top:
__fiq_stack:
.space 1024
__fiq_stack_top:
__svc_stack:
.space 1024
__svc_stack_top:
__exc_stack:
.space 512
__exc_stack_top:

View File

@@ -1,38 +0,0 @@
# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
# of conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import("//kernel/liteos_m/liteos.gni")
module_group("gcc") {
if (defined(LOSCFG_SECURE_TRUSTZONE)) {
modules = [ "TZ" ]
} else {
modules = [ "NTZ" ]
}
}

View File

@@ -1,699 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_INTERRUPT_H
#define _LOS_ARCH_INTERRUPT_H
#include "los_config.h"
#include "los_compiler.h"
#include "los_interrupt.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
/* *
* @ingroup los_arch_interrupt
* Maximum number of used hardware interrupts.
*/
#ifndef OS_HWI_MAX_NUM
#define OS_HWI_MAX_NUM LOSCFG_PLATFORM_HWI_LIMIT
#endif
/* *
* @ingroup los_arch_interrupt
* Highest priority of a hardware interrupt.
*/
#ifndef OS_HWI_PRIO_HIGHEST
#define OS_HWI_PRIO_HIGHEST 0
#endif
/* *
* @ingroup los_arch_interrupt
* Lowest priority of a hardware interrupt.
*/
#ifndef OS_HWI_PRIO_LOWEST
#define OS_HWI_PRIO_LOWEST 7
#endif
/* *
* @ingroup los_arch_interrupt
* Define the type of a hardware interrupt vector table function.
*/
typedef VOID (**HWI_VECTOR_FUNC)(void);
/* *
* @ingroup los_arch_interrupt
* Count of interrupts.
*/
extern UINT32 g_intCount;
/* *
* @ingroup los_arch_interrupt
* Count of M-Core system interrupt vector.
*/
#define OS_SYS_VECTOR_CNT 16
/* *
* @ingroup los_arch_interrupt
* Count of M-Core interrupt vector.
*/
#define OS_VECTOR_CNT (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
/* *
* @ingroup los_arch_interrupt
* AIRCR register priority group parameter .
*/
#define OS_NVIC_AIRCR_PRIGROUP 7
/* *
* @ingroup los_arch_interrupt
* Boot interrupt vector table.
*/
extern UINT32 _BootVectors[];
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Invalid interrupt number.
*
* Value: 0x02000900
*
* Solution: Ensure that the interrupt number is valid. The value range of the interrupt number applicable for a Cortex-A7 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
*/
#define OS_ERRNO_HWI_NUM_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Null hardware interrupt handling function.
*
* Value: 0x02000901
*
* Solution: Pass in a valid non-null hardware interrupt handling function.
*/
#define OS_ERRNO_HWI_PROC_FUNC_NULL LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
*
* Value: 0x02000902
*
* Solution: Increase the configured maximum number of supported hardware interrupts.
*/
#define OS_ERRNO_HWI_CB_UNAVAILABLE LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
*
* Value: 0x02000903
*
* Solution: Expand the configured memory.
*/
#define OS_ERRNO_HWI_NO_MEMORY LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: The interrupt has already been created.
*
* Value: 0x02000904
*
* Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
*/
#define OS_ERRNO_HWI_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Invalid interrupt priority.
*
* Value: 0x02000905
*
* Solution: Ensure that the interrupt priority is valid. The value range of the interrupt priority applicable for a Cortex-A7 platform is [0,15].
*/
#define OS_ERRNO_HWI_PRIO_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Incorrect interrupt creation mode.
*
* Value: 0x02000906
*
* Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or OS_HWI_MODE_FAST of which the value can be 0 or 1.
*/
#define OS_ERRNO_HWI_MODE_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
*
* Value: 0x02000907
*
* Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
*/
#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
/* *
* @ingroup los_arch_interrupt
* SysTick control and status register.
*/
#define OS_SYSTICK_CONTROL_REG 0xE000E010
/* *
* @ingroup los_hw
* SysTick current value register.
*/
#define OS_SYSTICK_CURRENT_REG 0xE000E018
/* *
* @ingroup los_arch_interrupt
* Interrupt Priority-Level Registers.
*/
#define OS_NVIC_PRI_BASE 0xE000E400
/* *
* @ingroup los_arch_interrupt
* Interrupt enable register for 0-31.
*/
#define OS_NVIC_SETENA_BASE 0xE000E100
/* *
* @ingroup los_arch_interrupt
* interrupt pending register.
*/
#define OS_NVIC_SETPEND_BASE 0xE000E200
/* *
* @ingroup los_arch_interrupt
* Interrupt active register.
*/
#define OS_NVIC_INT_ACT_BASE 0xE000E300
/* *
* @ingroup los_arch_interrupt
* Interrupt disable register for 0-31.
*/
#define OS_NVIC_CLRENA_BASE 0xE000E180
/* *
* @ingroup los_arch_interrupt
* Interrupt control and status register.
*/
#define OS_NVIC_INT_CTRL 0xE000ED04
/* *
* @ingroup los_arch_interrupt
* Vector table offset register.
*/
#define OS_NVIC_VTOR 0xE000ED08
/* *
* @ingroup los_arch_interrupt
* Application interrupt and reset control register
*/
#define OS_NVIC_AIRCR 0xE000ED0C
/* *
* @ingroup los_arch_interrupt
* System exception priority register.
*/
#define OS_NVIC_EXCPRI_BASE 0xE000ED18
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 1 :reset.
*/
#define OS_EXC_RESET 1
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 2 :Non-Maskable Interrupt.
*/
#define OS_EXC_NMI 2
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 3 :(hard)fault.
*/
#define OS_EXC_HARD_FAULT 3
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 4 :MemManage fault.
*/
#define OS_EXC_MPU_FAULT 4
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 5 :Bus fault.
*/
#define OS_EXC_BUS_FAULT 5
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 6 :Usage fault.
*/
#define OS_EXC_USAGE_FAULT 6
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 11 :SVCall.
*/
#define OS_EXC_SVC_CALL 11
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 12 :Debug monitor.
*/
#define OS_EXC_DBG_MONITOR 12
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 14 :PendSV.
*/
#define OS_EXC_PEND_SV 14
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 15 :SysTick.
*/
#define OS_EXC_SYS_TICK 15
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
/* *
* @ingroup los_arch_interrupt
* Set interrupt vector table.
*/
extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg);
#else
/* *
* @ingroup los_arch_interrupt
* Set interrupt vector table.
*/
extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
#endif
/* *
* @ingroup los_arch_interrupt
* @brief: Hardware interrupt entry function.
*
* @par Description:
* This API is used as all hardware interrupt handling function entry.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param:None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID HalInterrupt(VOID);
/* *
* @ingroup los_arch_interrupt
* @brief: Get an interrupt number.
*
* @par Description:
* This API is used to get the current interrupt number.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param: None.
*
* @retval: Interrupt Indexes number.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern UINT32 HalIntNumGet(VOID);
/* *
* @ingroup los_arch_interrupt
* @brief: Default vector handling function.
*
* @par Description:
* This API is used to configure interrupt for null function.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param:None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID HalHwiDefaultHandler(VOID);
/* *
* @ingroup los_arch_interrupt
* @brief: Reset the vector table.
*
* @par Description:
* This API is used to reset the vector table.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param:None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID Reset_Handler(VOID);
/* *
* @ingroup los_arch_interrupt
* @brief: Pended System Call.
*
* @par Description:
* PendSV can be pended and is useful for an OS to pend an exception
* so that an action can be performed after other important tasks are completed.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param:None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID HalPendSV(VOID);
#define OS_EXC_IN_INIT 0
#define OS_EXC_IN_TASK 1
#define OS_EXC_IN_HWI 2
#define OS_EXC_MAX_BUF_LEN 25
#define OS_EXC_MAX_NEST_DEPTH 1
#define OS_NVIC_SHCSR 0xE000ED24
#define OS_NVIC_CCR 0xE000ED14
#define OS_NVIC_INT_ENABLE_SIZE 0x20
#define OS_NVIC_INT_PRI_SIZE 0xF0
#define OS_NVIC_EXCPRI_SIZE 0xC
#define OS_NVIC_INT_CTRL_SIZE 4
#define OS_NVIC_SHCSR_SIZE 4
#define OS_NVIC_INT_PEND_SIZE OS_NVIC_INT_ACT_SIZE
#define OS_NVIC_INT_ACT_SIZE OS_NVIC_INT_ENABLE_SIZE
#define OS_EXC_FLAG_NO_FLOAT 0x10000000
#define OS_EXC_FLAG_FAULTADDR_VALID 0x01
#define OS_EXC_FLAG_IN_HWI 0x02
#define OS_EXC_IMPRECISE_ACCESS_ADDR 0xABABABAB
#define OS_EXC_EVENT 0x00000001
/**
* @ingroup los_exc
* the struct of register files
*
* description: the register files that saved when exception triggered
*
* notes:the following register with prefix 'uw' correspond to the registers in the cpu data sheet.
*/
typedef struct TagExcContext {
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
UINT32 S16;
UINT32 S17;
UINT32 S18;
UINT32 S19;
UINT32 S20;
UINT32 S21;
UINT32 S22;
UINT32 S23;
UINT32 S24;
UINT32 S25;
UINT32 S26;
UINT32 S27;
UINT32 S28;
UINT32 S29;
UINT32 S30;
UINT32 S31;
#endif
UINT32 uwR4;
UINT32 uwR5;
UINT32 uwR6;
UINT32 uwR7;
UINT32 uwR8;
UINT32 uwR9;
UINT32 uwR10;
UINT32 uwR11;
UINT32 uwPriMask;
/* auto save */
UINT32 uwSP;
UINT32 uwR0;
UINT32 uwR1;
UINT32 uwR2;
UINT32 uwR3;
UINT32 uwR12;
UINT32 uwLR;
UINT32 uwPC;
UINT32 uwxPSR;
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED) && (__FPU_USED== 1U)))
UINT32 S0;
UINT32 S1;
UINT32 S2;
UINT32 S3;
UINT32 S4;
UINT32 S5;
UINT32 S6;
UINT32 S7;
UINT32 S8;
UINT32 S9;
UINT32 S10;
UINT32 S11;
UINT32 S12;
UINT32 S13;
UINT32 S14;
UINT32 S15;
UINT32 FPSCR;
UINT32 NO_NAME;
#endif
} EXC_CONTEXT_S;
typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
VOID HalExcNMI(VOID);
VOID HalExcHardFault(VOID);
VOID HalExcMemFault(VOID);
VOID HalExcBusFault(VOID);
VOID HalExcUsageFault(VOID);
VOID HalSVCHandler(VOID);
VOID HalHwiInit(VOID);
/**
* @ingroup los_exc
* Cortex-M exception types: An error occurred while the bus status register was being pushed.
*/
#define OS_EXC_BF_STKERR 1
/**
* @ingroup los_exc
* Cortex-M exception types: An error occurred while the bus status register was out of the stack.
*/
#define OS_EXC_BF_UNSTKERR 2
/**
* @ingroup los_exc
* Cortex-M exception types: Bus status register imprecise data access violation.
*/
#define OS_EXC_BF_IMPRECISERR 3
/**
* @ingroup los_exc
* Cortex-M exception types: Bus status register exact data access violation.
*/
#define OS_EXC_BF_PRECISERR 4
/**
* @ingroup los_exc
* Cortex-M exception types: Bus status register access violation while pointing.
*/
#define OS_EXC_BF_IBUSERR 5
/**
* @ingroup los_exc
* Cortex-M exception types: An error occurred while the memory management status register was being pushed.
*/
#define OS_EXC_MF_MSTKERR 6
/**
* @ingroup los_exc
* Cortex-M exception types: An error occurred while the memory management status register was out of the stack.
*/
#define OS_EXC_MF_MUNSTKERR 7
/**
* @ingroup los_exc
* Cortex-M exception types: Memory management status register data access violation.
*/
#define OS_EXC_MF_DACCVIOL 8
/**
* @ingroup los_exc
* Cortex-M exception types: Memory management status register access violation.
*/
#define OS_EXC_MF_IACCVIOL 9
/**
* @ingroup los_exc
* Cortex-M exception types: Incorrect usage indicating that the divisor is zero during the division operation.
*/
#define OS_EXC_UF_DIVBYZERO 10
/**
* @ingroup los_exc
* Cortex-M exception types: Usage error, error caused by unaligned access.
*/
#define OS_EXC_UF_UNALIGNED 11
/**
* @ingroup los_exc
* Cortex-M exception types: Incorrect usage attempting to execute coprocessor related instruction.
*/
#define OS_EXC_UF_NOCP 12
/**
* @ingroup los_exc
* Cortex-M exception types: Usage error attempting to load EXC_RETURN to PC illegally on exception return.
*/
#define OS_EXC_UF_INVPC 13
/**
* @ingroup los_exc
* Cortex-M exception types: Incorrect usage, attempting to cut to ARM state.
*/
#define OS_EXC_UF_INVSTATE 14
/**
* @ingroup los_exc
* Cortex-M exception types: Incorrect usage. Executed instruction whose code is undefined.
*/
#define OS_EXC_UF_UNDEFINSTR 15
/**
* @ingroup los_exc
* Cortex-M exception types: NMI
*/
#define OS_EXC_CAUSE_NMI 16
/**
* @ingroup los_exc
* Cortex-M exception types: hard fault
*/
#define OS_EXC_CAUSE_HARDFAULT 17
/**
* @ingroup los_exc
* Cortex-M exception types: The task handler exits.
*/
#define OS_EXC_CAUSE_TASK_EXIT 18
/**
* @ingroup los_exc
* Cortex-M exception types: A fatal error.
*/
#define OS_EXC_CAUSE_FATAL_ERR 19
/**
* @ingroup los_exc
* Cortex-M exception types: Hard Fault caused by a debug event.
*/
#define OS_EXC_CAUSE_DEBUGEVT 20
/**
* @ingroup los_exc
* Cortex-M exception types: A hard fault that occurs when a quantity is oriented.
*/
#define OS_EXC_CAUSE_VECTBL 21
/**
* @ingroup los_exc
* Exception information structure
*
* Description: Exception information saved when an exception is triggered on the Cortex-M33 platform.
*
*/
typedef struct TagExcInfo {
/**< Exception occurrence phase: 0 means that an exception occurs in initialization,
* 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
UINT16 phase;
/**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
UINT16 type;
/**< If the exact address access error indicates the wrong access address when the exception occurred */
UINT32 faultAddr;
/**< An exception occurs in an interrupt, indicating the interrupt number.
* An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
UINT32 thrdPid;
/**< Number of nested exceptions. Currently only registered hook functions are supported
* when an exception is entered for the first time */
UINT16 nestCnt;
/**< reserve */
UINT16 reserved;
/**< Hardware context at the time an exception to the automatic stack floating-point register occurs */
EXC_CONTEXT_S *context;
} ExcInfo;
extern UINT32 g_curNestCount;
extern UINT32 g_intCount;
extern UINT8 g_uwExcTbl[32];
extern ExcInfo g_excInfo;
#define MAX_INT_INFO_SIZE (8 + 0x164)
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_INTERRUPT_H */

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@@ -1,524 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_interrupt.h"
#include <stdarg.h>
#include "securec.h"
#include "los_context.h"
#include "los_arch_interrupt.h"
#include "los_debug.h"
#include "los_hook.h"
#include "los_task.h"
#include "los_sched.h"
#include "los_memory.h"
#include "los_membox.h"
/*lint -save -e40 -e522 -e533*/
UINT32 g_intCount = 0;
/*lint -restore*/
/* *
* @ingroup los_hwi
* Hardware interrupt form mapping handling function array.
*/
STATIC HWI_PROC_FUNC __attribute__((aligned(LOSCFG_ARCH_HWI_VECTOR_ALIGN))) g_hwiForm[OS_VECTOR_CNT] = {0};
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
typedef struct {
HWI_PROC_FUNC pfnHandler;
VOID *pParm;
} HWI_HANDLER_FUNC;
/* *
* @ingroup los_hwi
* Hardware interrupt handler form mapping handling function array.
*/
STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
/* *
* @ingroup los_hwi
* Set interrupt vector table.
*/
VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg)
{
if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalInterrupt;
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector;
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg;
}
}
#else
/* *
* @ingroup los_hwi
* hardware interrupt handler form mapping handling function array.
*/
STATIC HWI_PROC_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {0};
/* *
* @ingroup los_hwi
* Set interrupt vector table.
*/
VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
{
if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
g_hwiForm[num + OS_SYS_VECTOR_CNT] = HalInterrupt;
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector;
}
}
#endif
/* ****************************************************************************
Function : HalIntNumGet
Description : Get an interrupt number
Input : None
Output : None
Return : Interrupt Indexes number
**************************************************************************** */
LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
{
return __get_IPSR();
}
inline UINT32 ArchIsIntActive(VOID)
{
return (g_intCount > 0);
}
/* ****************************************************************************
Function : HalHwiDefaultHandler
Description : default handler of the hardware interrupt
Input : None
Output : None
Return : None
**************************************************************************** */
/*lint -e529*/
LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
{
UINT32 irqNum = HalIntNumGet();
PRINT_ERR("%s irqnum:%d\n", __FUNCTION__, irqNum);
while (1) {}
}
WEAK VOID HalPreInterruptHandler(UINT32 arg)
{
return;
}
WEAK VOID HalAftInterruptHandler(UINT32 arg)
{
return;
}
/* ****************************************************************************
Function : HalInterrupt
Description : Hardware interrupt entry function
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
{
UINT32 hwiIndex;
UINT32 intSave;
#if (LOSCFG_KERNEL_RUNSTOP == 1)
SCB->SCR &= (UINT32) ~((UINT32)SCB_SCR_SLEEPDEEP_Msk);
#endif
intSave = LOS_IntLock();
g_intCount++;
LOS_IntRestore(intSave);
hwiIndex = HalIntNumGet();
OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
HalPreInterruptHandler(hwiIndex);
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
}
#else
if (g_hwiHandlerForm[hwiIndex] != 0) {
g_hwiHandlerForm[hwiIndex]();
}
#endif
HalAftInterruptHandler(hwiIndex);
OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
intSave = LOS_IntLock();
g_intCount--;
LOS_IntRestore(intSave);
}
/* ****************************************************************************
Function : ArchHwiCreate
Description : create hardware interrupt
Input : hwiNum --- hwi num to create
hwiPrio --- priority of the hwi
mode --- unused
handler --- hwi handler
arg --- param of the hwi handler
Output : None
Return : LOS_OK on success or error code on failure
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
HWI_PRIOR_T hwiPrio,
HWI_MODE_T mode,
HWI_PROC_FUNC handler,
HWI_ARG_T arg)
{
UINT32 intSave;
if (handler == NULL) {
return OS_ERRNO_HWI_PROC_FUNC_NULL;
}
if (hwiNum >= OS_HWI_MAX_NUM) {
return OS_ERRNO_HWI_NUM_INVALID;
}
if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
return OS_ERRNO_HWI_ALREADY_CREATED;
}
if (hwiPrio > OS_HWI_PRIO_LOWEST) {
return OS_ERRNO_HWI_PRIO_INVALID;
}
intSave = LOS_IntLock();
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
OsSetVector(hwiNum, handler, arg);
#else
OsSetVector(hwiNum, handler);
#endif
NVIC_EnableIRQ((IRQn_Type)hwiNum);
NVIC_SetPriority((IRQn_Type)hwiNum, hwiPrio);
LOS_IntRestore(intSave);
return LOS_OK;
}
/* ****************************************************************************
Function : ArchHwiDelete
Description : Delete hardware interrupt
Input : hwiNum --- hwi num to delete
Output : None
Return : LOS_OK on success or error code on failure
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
{
UINT32 intSave;
if (hwiNum >= OS_HWI_MAX_NUM) {
return OS_ERRNO_HWI_NUM_INVALID;
}
NVIC_DisableIRQ((IRQn_Type)hwiNum);
intSave = LOS_IntLock();
g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
LOS_IntRestore(intSave);
return LOS_OK;
}
#define FAULT_STATUS_REG_BIT 32
#define USGFAULT (1 << 18)
#define BUSFAULT (1 << 17)
#define MEMFAULT (1 << 16)
#define DIV0FAULT (1 << 4)
#define UNALIGNFAULT (1 << 3)
#define HARDFAULT_IRQN (-13)
ExcInfo g_excInfo = {0};
UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = {
0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED,
0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR,
0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR,
0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL
};
#if (LOSCFG_KERNEL_PRINTF != 0)
STATIC VOID OsExcNvicDump(VOID)
{
#define OS_NR_NVIC_EXC_DUMP_TYPES 7
UINT32 *base = NULL;
UINT32 len, i, j;
UINT32 rgNvicBases[OS_NR_NVIC_EXC_DUMP_TYPES] = {
OS_NVIC_SETENA_BASE, OS_NVIC_SETPEND_BASE, OS_NVIC_INT_ACT_BASE,
OS_NVIC_PRI_BASE, OS_NVIC_EXCPRI_BASE, OS_NVIC_SHCSR, OS_NVIC_INT_CTRL
};
UINT32 rgNvicLens[OS_NR_NVIC_EXC_DUMP_TYPES] = {
OS_NVIC_INT_ENABLE_SIZE, OS_NVIC_INT_PEND_SIZE, OS_NVIC_INT_ACT_SIZE,
OS_NVIC_INT_PRI_SIZE, OS_NVIC_EXCPRI_SIZE, OS_NVIC_SHCSR_SIZE,
OS_NVIC_INT_CTRL_SIZE
};
CHAR strRgEnable[] = "enable";
CHAR strRgPending[] = "pending";
CHAR strRgActive[] = "active";
CHAR strRgPriority[] = "priority";
CHAR strRgException[] = "exception";
CHAR strRgShcsr[] = "shcsr";
CHAR strRgIntCtrl[] = "control";
CHAR *strRgs[] = {
strRgEnable, strRgPending, strRgActive, strRgPriority,
strRgException, strRgShcsr, strRgIntCtrl
};
PRINTK("\r\nOS exception NVIC dump:\n");
for (i = 0; i < OS_NR_NVIC_EXC_DUMP_TYPES; i++) {
base = (UINT32 *)rgNvicBases[i];
len = rgNvicLens[i];
PRINTK("interrupt %s register, base address: %p, size: 0x%x\n", strRgs[i], base, len);
len = (len >> 2); /* 2: Gets the next register offset */
for (j = 0; j < len; j++) {
PRINTK("0x%x ", *(base + j));
if ((j != 0) && ((j % 16) == 0)) { /* 16: print wrap line */
PRINTK("\n");
}
}
PRINTK("\n");
}
}
STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
{
CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
PRINTK("Type = %d\n", excInfo->type);
PRINTK("ThrdPid = %d\n", excInfo->thrdPid);
PRINTK("Phase = %s\n", phaseStr[excInfo->phase]);
PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
}
STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
{
PRINTK("Current task info:\n");
if (excInfo->phase == OS_EXC_IN_TASK) {
LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
PRINTK("Task name = %s\n", taskCB->taskName);
PRINTK("Task ID = %d\n", taskCB->taskID);
PRINTK("Task SP = %p\n", taskCB->stackPointer);
PRINTK("Task ST = 0x%x\n", taskCB->topOfStack);
PRINTK("Task SS = 0x%x\n", taskCB->stackSize);
} else if (excInfo->phase == OS_EXC_IN_HWI) {
PRINTK("Exception occur in interrupt phase!\n");
} else {
PRINTK("Exception occur in system init phase!\n");
}
}
STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
{
PRINTK("Exception reg dump:\n");
PRINTK("PC = 0x%x\n", excInfo->context->uwPC);
PRINTK("LR = 0x%x\n", excInfo->context->uwLR);
PRINTK("SP = 0x%x\n", excInfo->context->uwSP);
PRINTK("R0 = 0x%x\n", excInfo->context->uwR0);
PRINTK("R1 = 0x%x\n", excInfo->context->uwR1);
PRINTK("R2 = 0x%x\n", excInfo->context->uwR2);
PRINTK("R3 = 0x%x\n", excInfo->context->uwR3);
PRINTK("R4 = 0x%x\n", excInfo->context->uwR4);
PRINTK("R5 = 0x%x\n", excInfo->context->uwR5);
PRINTK("R6 = 0x%x\n", excInfo->context->uwR6);
PRINTK("R7 = 0x%x\n", excInfo->context->uwR7);
PRINTK("R8 = 0x%x\n", excInfo->context->uwR8);
PRINTK("R9 = 0x%x\n", excInfo->context->uwR9);
PRINTK("R10 = 0x%x\n", excInfo->context->uwR10);
PRINTK("R11 = 0x%x\n", excInfo->context->uwR11);
PRINTK("R12 = 0x%x\n", excInfo->context->uwR12);
PRINTK("PriMask = 0x%x\n", excInfo->context->uwPriMask);
PRINTK("xPSR = 0x%x\n", excInfo->context->uwxPSR);
}
STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
{
UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
UINT32 index;
OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->uwSP);
PRINTK("----- backtrace start -----\n");
for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
if (LR[index] == 0) {
break;
}
PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]);
}
PRINTK("----- backtrace end -----\n");
}
STATIC VOID OsExcMemPoolCheckInfo(VOID)
{
PRINTK("\r\nmemory pools check:\n");
#if (LOSCFG_PLATFORM_EXC == 1)
MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
UINT32 errCnt;
UINT32 i;
(VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
if (errCnt < OS_SYS_MEM_NUM) {
errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
}
if (errCnt == 0) {
PRINTK("all memory pool check passed!\n");
return;
}
for (i = 0; i < errCnt; i++) {
PRINTK("pool num = %d\n", i);
PRINTK("pool type = %d\n", memExcInfo[i].type);
PRINTK("pool addr = 0x%x\n", memExcInfo[i].startAddr);
PRINTK("pool size = 0x%x\n", memExcInfo[i].size);
PRINTK("pool free = 0x%x\n", memExcInfo[i].free);
PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize);
PRINTK("pool error node addr = 0x%x\n", memExcInfo[i].errorAddr);
PRINTK("pool error node len = 0x%x\n", memExcInfo[i].errorLen);
PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner);
}
#endif
UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
if (ret == LOS_OK) {
PRINTK("system heap memcheck over, all passed!\n");
}
PRINTK("memory pool check end!\n");
}
#endif
STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
{
#if (LOSCFG_KERNEL_PRINTF != 0)
PRINTK("*************Exception Information**************\n");
OsExcTypeInfo(excInfo);
OsExcCurTaskInfo(excInfo);
OsExcRegInfo(excInfo);
OsExcBackTraceInfo(excInfo);
OsGetAllTskInfo();
OsExcNvicDump();
OsExcMemPoolCheckInfo();
#endif
}
LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr)
{
UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT; /* 16: Get Exception Type */
g_intCount++;
g_excInfo.nestCnt++;
g_excInfo.type = excType & OS_NULL_SHORT;
if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) {
g_excInfo.faultAddr = faultAddr;
} else {
g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
}
if (g_losTask.runTask != NULL) {
if (tmpFlag & OS_EXC_FLAG_IN_HWI) {
g_excInfo.phase = OS_EXC_IN_HWI;
g_excInfo.thrdPid = pid;
} else {
g_excInfo.phase = OS_EXC_IN_TASK;
g_excInfo.thrdPid = g_losTask.runTask->taskID;
}
} else {
g_excInfo.phase = OS_EXC_IN_INIT;
g_excInfo.thrdPid = OS_NULL_INT;
}
if (excType & OS_EXC_FLAG_NO_FLOAT) {
g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4));
} else {
g_excInfo.context = excBufAddr;
}
OsDoExcHook(EXC_INTERRUPT);
OsExcInfoDisplay(&g_excInfo);
ArchSysExit();
}
/* ****************************************************************************
Function : HalHwiInit
Description : initialization of the hardware interrupt
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
{
#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
UINT32 index;
g_hwiForm[0] = 0; /* [0] Top of Stack */
g_hwiForm[1] = 0; /* [1] reset */
for (index = 2; index < OS_VECTOR_CNT; index++) {
g_hwiForm[index] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
}
/* Exception handler register */
g_hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT] = HalExcNMI;
g_hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT] = HalExcHardFault;
g_hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = HalExcMemFault;
g_hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT] = HalExcBusFault;
g_hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT] = HalExcUsageFault;
g_hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT] = HalSVCHandler;
g_hwiForm[PendSV_IRQn + OS_SYS_VECTOR_CNT] = HalPendSV;
g_hwiForm[SysTick_IRQn + OS_SYS_VECTOR_CNT] = OsTickHandler;
/* Interrupt vector table location */
SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm;
#endif
#if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
#endif
/* Enable USGFAULT, BUSFAULT, MEMFAULT */
*(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
/* Enable DIV 0 and unaligned exception */
#ifdef LOSCFG_ARCH_UNALIGNED_EXC
*(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
#else
*(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT);
#endif
return;
}

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@@ -1,51 +0,0 @@
# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
# of conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import("//kernel/liteos_m/liteos.gni")
module_name = "arch"
kernel_module(module_name) {
sources = [
"non_secure/los_context.c",
"non_secure/los_dispatch.S",
"non_secure/los_exc.S",
"non_secure/los_interrupt.c",
"non_secure/los_timer.c",
"non_secure/los_trustzone.c",
]
include_dirs = [
"non_secure",
"secure",
]
}
config("public") {
include_dirs = [ "non_secure" ]
}

View File

@@ -1,133 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_CONTEXT_H
#define _LOS_ARCH_CONTEXT_H
#include "los_config.h"
#include "los_compiler.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
typedef struct TagTskContext {
UINT32 secureContext;
UINT32 stackLimit;
UINT32 excReturn;
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined(__FPU_USED) && (__FPU_USED == 1U)))
UINT32 S16;
UINT32 S17;
UINT32 S18;
UINT32 S19;
UINT32 S20;
UINT32 S21;
UINT32 S22;
UINT32 S23;
UINT32 S24;
UINT32 S25;
UINT32 S26;
UINT32 S27;
UINT32 S28;
UINT32 S29;
UINT32 S30;
UINT32 S31;
#endif
UINT32 uwR4;
UINT32 uwR5;
UINT32 uwR6;
UINT32 uwR7;
UINT32 uwR8;
UINT32 uwR9;
UINT32 uwR10;
UINT32 uwR11;
UINT32 uwPriMask;
UINT32 uwR0;
UINT32 uwR1;
UINT32 uwR2;
UINT32 uwR3;
UINT32 uwR12;
UINT32 uwLR;
UINT32 uwPC;
UINT32 uwxPSR;
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined(__FPU_USED) && (__FPU_USED == 1U)))
UINT32 S0;
UINT32 S1;
UINT32 S2;
UINT32 S3;
UINT32 S4;
UINT32 S5;
UINT32 S6;
UINT32 S7;
UINT32 S8;
UINT32 S9;
UINT32 S10;
UINT32 S11;
UINT32 S12;
UINT32 S13;
UINT32 S14;
UINT32 S15;
UINT32 FPSCR;
UINT32 NO_NAME;
#endif
} TaskContext;
/**
* @ingroup los_config
* @brief: Task start running function.
*
* @par Description:
* This API is used to start a task.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param: None.
*
* @retval None.
*
* @par Dependency:
* <ul><li>los_config.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID HalStartToRun(VOID);
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_CONTEXT_H */

View File

@@ -1,699 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_INTERRUPT_H
#define _LOS_ARCH_INTERRUPT_H
#include "los_config.h"
#include "los_compiler.h"
#include "los_interrupt.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
/* *
* @ingroup los_arch_interrupt
* Maximum number of used hardware interrupts.
*/
#ifndef OS_HWI_MAX_NUM
#define OS_HWI_MAX_NUM LOSCFG_PLATFORM_HWI_LIMIT
#endif
/* *
* @ingroup los_arch_interrupt
* Highest priority of a hardware interrupt.
*/
#ifndef OS_HWI_PRIO_HIGHEST
#define OS_HWI_PRIO_HIGHEST 0
#endif
/* *
* @ingroup los_arch_interrupt
* Lowest priority of a hardware interrupt.
*/
#ifndef OS_HWI_PRIO_LOWEST
#define OS_HWI_PRIO_LOWEST 7
#endif
/* *
* @ingroup los_arch_interrupt
* Define the type of a hardware interrupt vector table function.
*/
typedef VOID (**HWI_VECTOR_FUNC)(void);
/* *
* @ingroup los_arch_interrupt
* Count of interrupts.
*/
extern UINT32 g_intCount;
/* *
* @ingroup los_arch_interrupt
* Count of M-Core system interrupt vector.
*/
#define OS_SYS_VECTOR_CNT 16
/* *
* @ingroup los_arch_interrupt
* Count of M-Core interrupt vector.
*/
#define OS_VECTOR_CNT (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
/* *
* @ingroup los_arch_interrupt
* AIRCR register priority group parameter .
*/
#define OS_NVIC_AIRCR_PRIGROUP 7
/* *
* @ingroup los_arch_interrupt
* Boot interrupt vector table.
*/
extern UINT32 _BootVectors[];
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Invalid interrupt number.
*
* Value: 0x02000900
*
* Solution: Ensure that the interrupt number is valid. The value range of the interrupt number applicable for a Cortex-A7 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
*/
#define OS_ERRNO_HWI_NUM_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Null hardware interrupt handling function.
*
* Value: 0x02000901
*
* Solution: Pass in a valid non-null hardware interrupt handling function.
*/
#define OS_ERRNO_HWI_PROC_FUNC_NULL LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
*
* Value: 0x02000902
*
* Solution: Increase the configured maximum number of supported hardware interrupts.
*/
#define OS_ERRNO_HWI_CB_UNAVAILABLE LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
*
* Value: 0x02000903
*
* Solution: Expand the configured memory.
*/
#define OS_ERRNO_HWI_NO_MEMORY LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: The interrupt has already been created.
*
* Value: 0x02000904
*
* Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
*/
#define OS_ERRNO_HWI_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Invalid interrupt priority.
*
* Value: 0x02000905
*
* Solution: Ensure that the interrupt priority is valid. The value range of the interrupt priority applicable for a Cortex-A7 platform is [0,15].
*/
#define OS_ERRNO_HWI_PRIO_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Incorrect interrupt creation mode.
*
* Value: 0x02000906
*
* Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or OS_HWI_MODE_FAST of which the value can be 0 or 1.
*/
#define OS_ERRNO_HWI_MODE_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
*
* Value: 0x02000907
*
* Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
*/
#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
/* *
* @ingroup los_arch_interrupt
* SysTick control and status register.
*/
#define OS_SYSTICK_CONTROL_REG 0xE000E010
/* *
* @ingroup los_hw
* SysTick current value register.
*/
#define OS_SYSTICK_CURRENT_REG 0xE000E018
/* *
* @ingroup los_arch_interrupt
* Interrupt Priority-Level Registers.
*/
#define OS_NVIC_PRI_BASE 0xE000E400
/* *
* @ingroup los_arch_interrupt
* Interrupt enable register for 0-31.
*/
#define OS_NVIC_SETENA_BASE 0xE000E100
/* *
* @ingroup los_arch_interrupt
* interrupt pending register.
*/
#define OS_NVIC_SETPEND_BASE 0xE000E200
/* *
* @ingroup los_arch_interrupt
* Interrupt active register.
*/
#define OS_NVIC_INT_ACT_BASE 0xE000E300
/* *
* @ingroup los_arch_interrupt
* Interrupt disable register for 0-31.
*/
#define OS_NVIC_CLRENA_BASE 0xE000E180
/* *
* @ingroup los_arch_interrupt
* Interrupt control and status register.
*/
#define OS_NVIC_INT_CTRL 0xE000ED04
/* *
* @ingroup los_arch_interrupt
* Vector table offset register.
*/
#define OS_NVIC_VTOR 0xE000ED08
/* *
* @ingroup los_arch_interrupt
* Application interrupt and reset control register
*/
#define OS_NVIC_AIRCR 0xE000ED0C
/* *
* @ingroup los_arch_interrupt
* System exception priority register.
*/
#define OS_NVIC_EXCPRI_BASE 0xE000ED18
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 1 :reset.
*/
#define OS_EXC_RESET 1
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 2 :Non-Maskable Interrupt.
*/
#define OS_EXC_NMI 2
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 3 :(hard)fault.
*/
#define OS_EXC_HARD_FAULT 3
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 4 :MemManage fault.
*/
#define OS_EXC_MPU_FAULT 4
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 5 :Bus fault.
*/
#define OS_EXC_BUS_FAULT 5
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 6 :Usage fault.
*/
#define OS_EXC_USAGE_FAULT 6
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 11 :SVCall.
*/
#define OS_EXC_SVC_CALL 11
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 12 :Debug monitor.
*/
#define OS_EXC_DBG_MONITOR 12
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 14 :PendSV.
*/
#define OS_EXC_PEND_SV 14
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 15 :SysTick.
*/
#define OS_EXC_SYS_TICK 15
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
/* *
* @ingroup los_arch_interrupt
* Set interrupt vector table.
*/
extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg);
#else
/* *
* @ingroup los_arch_interrupt
* Set interrupt vector table.
*/
extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
#endif
/* *
* @ingroup los_arch_interrupt
* @brief: Hardware interrupt entry function.
*
* @par Description:
* This API is used as all hardware interrupt handling function entry.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param:None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID HalInterrupt(VOID);
/* *
* @ingroup los_arch_interrupt
* @brief: Get an interrupt number.
*
* @par Description:
* This API is used to get the current interrupt number.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param: None.
*
* @retval: Interrupt Indexes number.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern UINT32 HalIntNumGet(VOID);
/* *
* @ingroup los_arch_interrupt
* @brief: Default vector handling function.
*
* @par Description:
* This API is used to configure interrupt for null function.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param:None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID HalHwiDefaultHandler(VOID);
/* *
* @ingroup los_arch_interrupt
* @brief: Reset the vector table.
*
* @par Description:
* This API is used to reset the vector table.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param:None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID Reset_Handler(VOID);
/* *
* @ingroup los_arch_interrupt
* @brief: Pended System Call.
*
* @par Description:
* PendSV can be pended and is useful for an OS to pend an exception
* so that an action can be performed after other important tasks are completed.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param:None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID HalPendSV(VOID);
#define OS_EXC_IN_INIT 0
#define OS_EXC_IN_TASK 1
#define OS_EXC_IN_HWI 2
#define OS_EXC_MAX_BUF_LEN 25
#define OS_EXC_MAX_NEST_DEPTH 1
#define OS_NVIC_SHCSR 0xE000ED24
#define OS_NVIC_CCR 0xE000ED14
#define OS_NVIC_INT_ENABLE_SIZE 0x20
#define OS_NVIC_INT_PRI_SIZE 0xF0
#define OS_NVIC_EXCPRI_SIZE 0xC
#define OS_NVIC_INT_CTRL_SIZE 4
#define OS_NVIC_SHCSR_SIZE 4
#define OS_NVIC_INT_PEND_SIZE OS_NVIC_INT_ACT_SIZE
#define OS_NVIC_INT_ACT_SIZE OS_NVIC_INT_ENABLE_SIZE
#define OS_EXC_FLAG_NO_FLOAT 0x10000000
#define OS_EXC_FLAG_FAULTADDR_VALID 0x01
#define OS_EXC_FLAG_IN_HWI 0x02
#define OS_EXC_IMPRECISE_ACCESS_ADDR 0xABABABAB
#define OS_EXC_EVENT 0x00000001
/**
* @ingroup los_exc
* the struct of register files
*
* description: the register files that saved when exception triggered
*
* notes:the following register with prefix 'uw' correspond to the registers in the cpu data sheet.
*/
typedef struct TagExcContext {
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
UINT32 S16;
UINT32 S17;
UINT32 S18;
UINT32 S19;
UINT32 S20;
UINT32 S21;
UINT32 S22;
UINT32 S23;
UINT32 S24;
UINT32 S25;
UINT32 S26;
UINT32 S27;
UINT32 S28;
UINT32 S29;
UINT32 S30;
UINT32 S31;
#endif
UINT32 uwR4;
UINT32 uwR5;
UINT32 uwR6;
UINT32 uwR7;
UINT32 uwR8;
UINT32 uwR9;
UINT32 uwR10;
UINT32 uwR11;
UINT32 uwPriMask;
/* auto save */
UINT32 uwSP;
UINT32 uwR0;
UINT32 uwR1;
UINT32 uwR2;
UINT32 uwR3;
UINT32 uwR12;
UINT32 uwLR;
UINT32 uwPC;
UINT32 uwxPSR;
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED) && (__FPU_USED== 1U)))
UINT32 S0;
UINT32 S1;
UINT32 S2;
UINT32 S3;
UINT32 S4;
UINT32 S5;
UINT32 S6;
UINT32 S7;
UINT32 S8;
UINT32 S9;
UINT32 S10;
UINT32 S11;
UINT32 S12;
UINT32 S13;
UINT32 S14;
UINT32 S15;
UINT32 FPSCR;
UINT32 NO_NAME;
#endif
} EXC_CONTEXT_S;
typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
VOID HalExcNMI(VOID);
VOID HalExcHardFault(VOID);
VOID HalExcMemFault(VOID);
VOID HalExcBusFault(VOID);
VOID HalExcUsageFault(VOID);
VOID HalSVCHandler(VOID);
VOID HalHwiInit(VOID);
/**
* @ingroup los_exc
* Cortex-M exception types: An error occurred while the bus status register was being pushed.
*/
#define OS_EXC_BF_STKERR 1
/**
* @ingroup los_exc
* Cortex-M exception types: An error occurred while the bus status register was out of the stack.
*/
#define OS_EXC_BF_UNSTKERR 2
/**
* @ingroup los_exc
* Cortex-M exception types: Bus status register imprecise data access violation.
*/
#define OS_EXC_BF_IMPRECISERR 3
/**
* @ingroup los_exc
* Cortex-M exception types: Bus status register exact data access violation.
*/
#define OS_EXC_BF_PRECISERR 4
/**
* @ingroup los_exc
* Cortex-M exception types: Bus status register access violation while pointing.
*/
#define OS_EXC_BF_IBUSERR 5
/**
* @ingroup los_exc
* Cortex-M exception types: An error occurred while the memory management status register was being pushed.
*/
#define OS_EXC_MF_MSTKERR 6
/**
* @ingroup los_exc
* Cortex-M exception types: An error occurred while the memory management status register was out of the stack.
*/
#define OS_EXC_MF_MUNSTKERR 7
/**
* @ingroup los_exc
* Cortex-M exception types: Memory management status register data access violation.
*/
#define OS_EXC_MF_DACCVIOL 8
/**
* @ingroup los_exc
* Cortex-M exception types: Memory management status register access violation.
*/
#define OS_EXC_MF_IACCVIOL 9
/**
* @ingroup los_exc
* Cortex-M exception types: Incorrect usage indicating that the divisor is zero during the division operation.
*/
#define OS_EXC_UF_DIVBYZERO 10
/**
* @ingroup los_exc
* Cortex-M exception types: Usage error, error caused by unaligned access.
*/
#define OS_EXC_UF_UNALIGNED 11
/**
* @ingroup los_exc
* Cortex-M exception types: Incorrect usage attempting to execute coprocessor related instruction.
*/
#define OS_EXC_UF_NOCP 12
/**
* @ingroup los_exc
* Cortex-M exception types: Usage error attempting to load EXC_RETURN to PC illegally on exception return.
*/
#define OS_EXC_UF_INVPC 13
/**
* @ingroup los_exc
* Cortex-M exception types: Incorrect usage, attempting to cut to ARM state.
*/
#define OS_EXC_UF_INVSTATE 14
/**
* @ingroup los_exc
* Cortex-M exception types: Incorrect usage. Executed instruction whose code is undefined.
*/
#define OS_EXC_UF_UNDEFINSTR 15
/**
* @ingroup los_exc
* Cortex-M exception types: NMI
*/
#define OS_EXC_CAUSE_NMI 16
/**
* @ingroup los_exc
* Cortex-M exception types: hard fault
*/
#define OS_EXC_CAUSE_HARDFAULT 17
/**
* @ingroup los_exc
* Cortex-M exception types: The task handler exits.
*/
#define OS_EXC_CAUSE_TASK_EXIT 18
/**
* @ingroup los_exc
* Cortex-M exception types: A fatal error.
*/
#define OS_EXC_CAUSE_FATAL_ERR 19
/**
* @ingroup los_exc
* Cortex-M exception types: Hard Fault caused by a debug event.
*/
#define OS_EXC_CAUSE_DEBUGEVT 20
/**
* @ingroup los_exc
* Cortex-M exception types: A hard fault that occurs when a quantity is oriented.
*/
#define OS_EXC_CAUSE_VECTBL 21
/**
* @ingroup los_exc
* Exception information structure
*
* Description: Exception information saved when an exception is triggered on the Cortex-M33 platform.
*
*/
typedef struct TagExcInfo {
/**< Exception occurrence phase: 0 means that an exception occurs in initialization,
* 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
UINT16 phase;
/**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
UINT16 type;
/**< If the exact address access error indicates the wrong access address when the exception occurred */
UINT32 faultAddr;
/**< An exception occurs in an interrupt, indicating the interrupt number.
* An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
UINT32 thrdPid;
/**< Number of nested exceptions. Currently only registered hook functions are supported
* when an exception is entered for the first time */
UINT16 nestCnt;
/**< reserve */
UINT16 reserved;
/**< Hardware context at the time an exception to the automatic stack floating-point register occurs */
EXC_CONTEXT_S *context;
} ExcInfo;
extern UINT32 g_curNestCount;
extern UINT32 g_intCount;
extern UINT8 g_uwExcTbl[32];
extern ExcInfo g_excInfo;
#define MAX_INT_INFO_SIZE (8 + 0x164)
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_INTERRUPT_H */

View File

@@ -1,51 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_TIMER_H
#define _LOS_ARCH_TIMER_H
#include "los_config.h"
#include "los_compiler.h"
#include "los_timer.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_TIMER_H */

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@@ -1,159 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_context.h"
#include "securec.h"
#include "los_arch_context.h"
#include "los_arch_interrupt.h"
#include "los_task.h"
#include "los_sched.h"
#include "los_interrupt.h"
#include "los_debug.h"
/* ****************************************************************************
Function : ArchInit
Description : arch init function
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
{
HalHwiInit();
}
/* ****************************************************************************
Function : ArchSysExit
Description : Task exit function
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
{
LOS_IntLock();
while (1) {
}
}
/* ****************************************************************************
Function : ArchTskStackInit
Description : Task stack initialization function
Input : taskID --- TaskID
stackSize --- Total size of the stack
topStack --- Top of task's stack
Output : None
Return : Context pointer
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
{
TaskContext *context = NULL;
errno_t result;
/* initialize the task stack, write magic num to stack top */
result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize);
if (result != EOK) {
printf("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__);
}
*((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD;
context = (TaskContext *)(((UINTPTR)topStack + stackSize) - sizeof(TaskContext));
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined(__FPU_USED) && (__FPU_USED == 1U)))
context->S16 = 0xAA000010;
context->S17 = 0xAA000011;
context->S18 = 0xAA000012;
context->S19 = 0xAA000013;
context->S20 = 0xAA000014;
context->S21 = 0xAA000015;
context->S22 = 0xAA000016;
context->S23 = 0xAA000017;
context->S24 = 0xAA000018;
context->S25 = 0xAA000019;
context->S26 = 0xAA00001A;
context->S27 = 0xAA00001B;
context->S28 = 0xAA00001C;
context->S29 = 0xAA00001D;
context->S30 = 0xAA00001E;
context->S31 = 0xAA00001F;
context->S0 = 0xAA000000;
context->S1 = 0xAA000001;
context->S2 = 0xAA000002;
context->S3 = 0xAA000003;
context->S4 = 0xAA000004;
context->S5 = 0xAA000005;
context->S6 = 0xAA000006;
context->S7 = 0xAA000007;
context->S8 = 0xAA000008;
context->S9 = 0xAA000009;
context->S10 = 0xAA00000A;
context->S11 = 0xAA00000B;
context->S12 = 0xAA00000C;
context->S13 = 0xAA00000D;
context->S14 = 0xAA00000E;
context->S15 = 0xAA00000F;
context->FPSCR = 0x00000000;
context->NO_NAME = 0xAA000011;
#endif
context->secureContext = 0UL;
context->stackLimit = (UINT32)topStack;
context->excReturn = 0xFFFFFFBC;
context->uwR4 = 0x04040404L;
context->uwR5 = 0x05050505L;
context->uwR6 = 0x06060606L;
context->uwR7 = 0x07070707L;
context->uwR8 = 0x08080808L;
context->uwR9 = 0x09090909L;
context->uwR10 = 0x10101010L;
context->uwR11 = 0x11111111L;
context->uwPriMask = 0;
context->uwR0 = taskID;
context->uwR1 = 0x01010101L;
context->uwR2 = 0x02020202L;
context->uwR3 = 0x03030303L;
context->uwR12 = 0x12121212L;
context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
context->uwxPSR = 0x01000000L;
return (VOID *)context;
}
LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
{
(VOID)LOS_IntLock();
OsSchedStart();
HalStartToRun();
return LOS_OK; /* never return */
}

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@@ -1,258 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.syntax unified
.arch armv7e-m
.thumb
.fpu fpv5-d16
.equ OS_FPU_CPACR, 0xE000ED88
.equ OS_FPU_CPACR_ENABLE, 0x00F00000
.equ OS_NVIC_INT_CTRL, 0xE000ED04
.equ OS_NVIC_SYSPRI2, 0xE000ED20
.equ OS_NVIC_PENDSV_PRI, 0xF0F00000
.equ OS_NVIC_PENDSVSET, 0x10000000
.equ OS_TASK_STATUS_RUNNING, 0x0010
.section .text
.thumb
.type HalStartFirstTask, %function
.global HalStartFirstTask
HalStartFirstTask:
MOV R0, #2
MSR CONTROL, R0
LDR R1, =g_losTask
LDR R0, [R1, #4]
LDR R12, [R0] /* Get the stack pointer of the current task. */
LDMFD R12!, {R1-R3} /* Read from stack: R1 = secureContext, R2 = stackLmit and R3 = excReturn.*/
LDR R4, =g_secureContext
STR R1, [R4] /* Set the secureContext to g_secureContext handler. */
MSR PSPLIM, R2 /* Set the stackLmit for the PSPLIM about current task. */
ISB
LDR.W R1, =OS_FPU_CPACR
LDR R1, [R1]
AND R1, R1, #OS_FPU_CPACR_ENABLE
CMP R1, #OS_FPU_CPACR_ENABLE
BNE __DisabledFPU1
ADD R12, R12, #64
VPUSH {S0}
VPOP {S0}
__DisabledFPU1:
ADD R12, R12, #36
MSR PSP, R12
CPSIE I
BX R3
.type ArchIntLock, %function
.global ArchIntLock
ArchIntLock:
.fnstart
.cantunwind
MRS R0, PRIMASK
CPSID I
BX LR
.fnend
.type ArchIntUnLock, %function
.global ArchIntUnLock
ArchIntUnLock:
.fnstart
.cantunwind
MRS R0, PRIMASK
CPSIE I
BX LR
.fnend
.type ArchIntRestore, %function
.global ArchIntRestore
ArchIntRestore:
.fnstart
.cantunwind
MSR PRIMASK, R0
BX LR
.fnend
.type ArchTaskSchedule, %function
.global ArchTaskSchedule
ArchTaskSchedule:
.fnstart
.cantunwind
ldr r0, =OS_NVIC_INT_CTRL
ldr r1, =OS_NVIC_PENDSVSET
str r1, [r0]
dsb
isb
bx lr
.fnend
.type HalPendSV, %function
.global HalPendSV
HalPendSV:
.fnstart
.cantunwind
mrs r12, PRIMASK
cpsid I
HalTaskSwitch:
push {r12, lr}
blx OsSchedTaskSwitch
pop {r12, lr}
cmp r0, #0
mov r0, lr
bne TaskContextSwitch
msr PRIMASK, r12
bx lr
TaskContextSwitch:
mov lr, r0
mrs r0, psp
LDR R2, =g_secureContext
LDR R1, [R2]
CBZ R1, __SaveNSContext /* If the g_secureContext is NULL, so no secure context to save. */
PUSH {R0-R1, R12, R14} /* Store registers, include LR, PRIMASK. */
BL HalSecureContextSave /* Store the secure context to g_secureContext->curStackPointer. */
POP {R0-R3}
MOV LR, R3
MOV R12, R2 /* R2 = PRIMASK. */
__SaveNSContext:
STMFD R0!, {R4-R12}
LDR.W R3, =OS_FPU_CPACR
LDR R3, [R3]
AND R3, R3, #OS_FPU_CPACR_ENABLE
CMP R3, #OS_FPU_CPACR_ENABLE
BNE __DisabledFPU2
VSTMDB R0!, {D8-D15}
__DisabledFPU2:
LDR R5, =g_losTask
LDR R6, [R5] /* Get the stackPointer handler of the current task. */
SUBS R0, R0, #12
STR R0, [R6] /* Save the new top of stack in TCB. */
MRS R2, PSPLIM
MOV R3, LR
STMIA R0!, {R1, R2-R3} /* Store g_secureContext, PSPLIM and LR on the stack of current task. */
LDR R0, [R5, #4]
STR R0, [R5]
LDR R1, [R0]
LDMIA R1!, {R0, R2-R3} /* Restore secureContext, PSPLIM and LR from the current task stack. */
MSR PSPLIM, R2
MOV LR, R3
LDR R2, =g_secureContext
STR R0, [R2] /* Set the secureContext of the new task to g_secureContext. */
CBZ R0, __RestoreNSContext /* If there is no secure context for the new task, so restore from the non-secure context. */
PUSH {R1, R3}
BL HalSecureContextLoad /* Restore the secure context. */
POP {R1, R3}
MOV LR, R3
__RestoreNSContext:
LDR.W R3, =OS_FPU_CPACR
LDR R3, [R3]
AND R3, R3, #OS_FPU_CPACR_ENABLE
CMP R3, #OS_FPU_CPACR_ENABLE
BNE __DisabledFPU3
VLDMIA R1!, {D8-D15}
__DisabledFPU3:
LDMFD R1!, {R4-R12}
MSR PSP, R1
MSR PRIMASK, R12
BX LR
.fnend
.type HalSVCStartSchedule, %function
.global HalSVCStartSchedule
HalSVCStartSchedule:
.fnstart
.cantunwind
LDR R4, =OS_NVIC_SYSPRI2
LDR R5, =OS_NVIC_PENDSV_PRI
STR R5, [R4]
CPSIE I
DSB
ISB
SVC 2
.fnend
.type HalSVCSecureContextAlloc, %function
.global HalSVCSecureContextAlloc
HalSVCSecureContextAlloc:
.fnstart
.cantunwind
SVC 0
BX LR
.fnend
.type HalSVCSecureContextFree, %function
.global HalSVCSecureContextFree
HalSVCSecureContextFree:
.fnstart
.cantunwind
SVC 1
BX LR
.fnend
.type HalSVCHandler, %function
.global HalSVCHandler
HalSVCHandler:
.fnstart
.cantunwind
TST LR, #0x04
ITE EQ
MRSEQ R1, MSP
MRSNE R1, PSP
LDR R0, [R1, #24]
LDRB R0, [R0, #-2] /* Get the SVC number. */
PUSH {LR}
MOV R2, R1 /* Get the stack for R2. */
LDMFD R2!, {R1} /* Get the input arg for HalSecureSVCHandler. */
STMFD R2!, {R1}
BL HalSecureSVCHandler
POP {LR}
BX LR
.fnend

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@@ -1,368 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.syntax unified
.arch armv7e-m
.thumb
.fpu fpv5-d16
.section .text
.global HalExcNMI
.global HalExcHardFault
.global HalExcMemFault
.global HalExcBusFault
.global HalExcUsageFault
.extern HalExcHandleEntry
.extern g_uwExcTbl
.extern g_taskScheduled
.equ OS_FLG_BGD_ACTIVE, 0x0002
.equ OS_EXC_CAUSE_NMI, 16
.equ OS_EXC_CAUSE_HARDFAULT, 17
.equ HF_DEBUGEVT, 20
.equ HF_VECTBL, 21
.equ FLAG_ADDR_VALID, 0x10000
.equ FLAG_HWI_ACTIVE, 0x20000
.equ FLAG_NO_FLOAT, 0x10000000
.equ OS_NVIC_FSR , 0xE000ED28 //include BusFault/MemFault/UsageFault State Register
.equ OS_NVIC_HFSR , 0xE000ED2C //HardFault State Register
.equ OS_NVIC_BFAR , 0xE000ED38
.equ OS_NVIC_MMAR , 0xE000ED34
.equ OS_NVIC_ACT_BASE , 0xE000E300
.equ OS_NVIC_SHCSRS , 0xE000ED24
.equ OS_NVIC_SHCSR_MASK , 0xC00
.type HalExcNMI, %function
.global HalExcNMI
HalExcNMI:
.fnstart
.cantunwind
MOV R0, #OS_EXC_CAUSE_NMI
MOV R1, #0
B osExcDispatch
.fnend
.type HalExcHardFault, %function
.global HalExcHardFault
HalExcHardFault:
.fnstart
.cantunwind
MOV R0, #OS_EXC_CAUSE_HARDFAULT
LDR R2, =OS_NVIC_HFSR
LDR R2, [R2]
MOV R1, #HF_DEBUGEVT
ORR R0, R0, R1, LSL #0x8
TST R2, #0x80000000
BNE osExcDispatch // DEBUGEVT
AND R0, R0 , #0x000000FF
MOV R1, #HF_VECTBL
ORR R0, R0, R1, LSL #0x8
TST R2, #0x00000002
BNE osExcDispatch // VECTBL
//if not DEBUGEVT and VECTBL then is FORCED
AND R0, R0, #0x000000FF
LDR R2, =OS_NVIC_FSR
LDR R2, [R2]
TST R2, #0x8000 // BFARVALID
BNE _HFBusFault // BusFault
TST R2, #0x80 // MMARVALID
BNE _HFMemFault // MemFault
MOV R12,#0
B osHFExcCommonBMU
.fnend
.type _HFBusFault, %function
_HFBusFault:
.fnstart
.cantunwind
LDR R1, =OS_NVIC_BFAR
LDR R1, [R1]
MOV R12, #FLAG_ADDR_VALID
B osHFExcCommonBMU
.fnend
.type _HFMemFault, %function
_HFMemFault:
.fnstart
.cantunwind
LDR R1, =OS_NVIC_MMAR
LDR R1, [R1]
MOV R12, #FLAG_ADDR_VALID
.fnend
.type osHFExcCommonBMU, %function
.global osHFExcCommonBMU
osHFExcCommonBMU:
.fnstart
.cantunwind
CLZ R2, R2
LDR R3, =g_uwExcTbl
ADD R3, R3, R2
LDRB R2, [R3]
ORR R0, R0, R2, LSL #0x8
ORR R0, R0 ,R12
B osExcDispatch
.fnend
.type HalExcBusFault, %function
.global HalExcBusFault
HalExcBusFault:
.fnstart
.cantunwind
LDR R0, =OS_NVIC_FSR
LDR R0, [R0]
TST R0, #0x8000 // BFARVALID
BEQ _ExcBusNoADDR
LDR R1, =OS_NVIC_BFAR
LDR R1, [R1]
MOV R12, #FLAG_ADDR_VALID
AND R0, R0, #0x1F00
B osExcCommonBMU
.fnend
.type _ExcBusNoADDR, %function
.global _ExcBusNoADDR
_ExcBusNoADDR:
.fnstart
.cantunwind
MOV R12,#0
B osExcCommonBMU
.fnend
.type HalExcMemFault, %function
.global HalExcMemFault
HalExcMemFault:
.fnstart
.cantunwind
LDR R0, =OS_NVIC_FSR
LDR R0, [R0]
TST R0, #0x80 // MMARVALID
BEQ _ExcMemNoADDR
LDR R1, =OS_NVIC_MMAR
LDR R1, [R1]
MOV R12, #FLAG_ADDR_VALID
AND R0, R0, #0x1B
B osExcCommonBMU
.fnend
.type _ExcMemNoADDR, %function
.global _ExcMemNoADDR
_ExcMemNoADDR:
.fnstart
.cantunwind
MOV R12,#0
B osExcCommonBMU
.fnend
.type HalExcUsageFault, %function
.global HalExcUsageFault
HalExcUsageFault:
.fnstart
.cantunwind
LDR R0, =OS_NVIC_FSR
LDR R0, [R0]
MOVW R1, #0x030F
LSL R1, R1, #16
AND R0, R0, R1
MOV R12, #0
.fnend
.type osExcCommonBMU, %function
.global osExcCommonBMU
osExcCommonBMU:
.fnstart
.cantunwind
CLZ R0, R0
LDR R3, =g_uwExcTbl
ADD R3, R3, R0
LDRB R0, [R3]
ORR R0, R0, R12
.fnend
// R0 -- EXCCAUSE(bit 16 is 1 if EXCADDR valid), R1 -- EXCADDR
.type osExcDispatch, %function
.global osExcDispatch
osExcDispatch:
.fnstart
.cantunwind
LDR R2, =OS_NVIC_ACT_BASE
MOV R12, #8 // R12 is hwi check loop counter
.fnend
.type _hwiActiveCheck, %function
.global _hwiActiveCheck
_hwiActiveCheck:
.fnstart
.cantunwind
LDR R3, [R2] // R3 store active hwi register when exc
CMP R3, #0
BEQ _hwiActiveCheckNext
// exc occured in IRQ
ORR R0, R0, #FLAG_HWI_ACTIVE
RBIT R2, R3
CLZ R2, R2
AND R12, R12, #1
ADD R2, R2, R12, LSL #5 // calculate R2 (hwi number) as pid
.fnend
.type _ExcInMSP, %function
.global _ExcInMSP
_ExcInMSP:
.fnstart
.cantunwind
CMP LR, #0xFFFFFFE9
BNE _NoFloatInMsp
ADD R3, R13, #104
PUSH {R3}
MRS R12, PRIMASK // store message-->exc: disable int?
PUSH {R4-R12} // store message-->exc: {R4-R12}
VPUSH {D8-D15}
B _handleEntry
.fnend
.type _NoFloatInMsp, %function
.global _NoFloatInMsp
_NoFloatInMsp:
.fnstart
.cantunwind
ADD R3, R13, #32
PUSH {R3} // save IRQ SP // store message-->exc: MSP(R13)
MRS R12, PRIMASK // store message-->exc: disable int?
PUSH {R4-R12} // store message-->exc: {R4-R12}
ORR R0, R0, #FLAG_NO_FLOAT
B _handleEntry
.fnend
.type _hwiActiveCheckNext, %function
.global _hwiActiveCheckNext
_hwiActiveCheckNext:
.fnstart
.cantunwind
ADD R2, R2, #4 // next NVIC ACT ADDR
SUBS R12, R12, #1
BNE _hwiActiveCheck
/*NMI interrupt excption*/
LDR R2, =OS_NVIC_SHCSRS
LDRH R2,[R2]
LDR R3,=OS_NVIC_SHCSR_MASK
AND R2, R2,R3
CMP R2,#0
BNE _ExcInMSP
// exc occured in Task or Init or exc
// reserved for register info from task stack
LDR R2, =g_taskScheduled
LDR R2, [R2]
TST R2, #1 // OS_FLG_BGD_ACTIVE
BEQ _ExcInMSP // if exc occured in Init then branch
CMP LR, #0xFFFFFFED //auto push floating registers
BNE _NoFloatInPsp
// exc occured in Task
MOV R2, R13
SUB R13, #96 // add 8 Bytes reg(for STMFD)
MRS R3, PSP
ADD R12, R3, #104
PUSH {R12} // save task SP
MRS R12, PRIMASK
PUSH {R4-R12}
VPUSH {D8-D15}
// copy auto saved task register
LDMFD R3!, {R4-R11} // R4-R11 store PSP reg(auto push when exc in task)
VLDMIA R3!, {D8-D15}
VSTMDB R2!, {D8-D15}
STMFD R2!, {R4-R11}
B _handleEntry
.fnend
.type _NoFloatInPsp, %function
.global _NoFloatInPsp
_NoFloatInPsp:
.fnstart
.cantunwind
MOV R2, R13 // no auto push floating registers
SUB R13, #32 // add 8 Bytes reg(for STMFD)
MRS R3, PSP
ADD R12, R3, #32
PUSH {R12} // save task SP
MRS R12, PRIMASK
PUSH {R4-R12}
LDMFD R3, {R4-R11} // R4-R11 store PSP reg(auto push when exc in task)
STMFD R2!, {R4-R11}
ORR R0, R0, #FLAG_NO_FLOAT
.fnend
.type _handleEntry, %function
.global _handleEntry
_handleEntry:
.fnstart
.cantunwind
MOV R3, R13 // R13:the 4th param
CPSID I
CPSID F
B HalExcHandleEntry
NOP
.fnend

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@@ -1,100 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.syntax unified
.arch armv7e-m
.thumb
.fpu fpv5-d16
.equ OS_SECURE_SCB_AIRCR, 0xE000ED0C
.section .text
.thumb
.type HalSecureContextInitAsm, %function
.global HalSecureContextInitAsm
HalSecureContextInitAsm:
.fnstart
.cantunwind
LDR R0, =OS_SECURE_SCB_AIRCR
LDR R1, [R0]
MOV R2, #0xFFFF
LSL R2, R2, #16
BIC R1, R1, R2
MOV R2, #0x05FA
LSL R2, R2, #16
ORR R1, R1, R2
BIC R1, R1, #0x4000
MOV R2, #0x4000
ORR R1, R1, R2
STR R1, [R0]
MOV R0, #0
MSR PSPLIM, R0
MSR PSP, R0
MOV R0, #2
MSR CONTROL, R0
BX LR
.fnend
.type HalSecureContextLoadAsm, %function
.global HalSecureContextLoadAsm
HalSecureContextLoadAsm:
.fnstart
.cantunwind
MRS R1, IPSR
CBZ R1, __ThreadMode
LDMIA R0!, {R1, R2} /* R1 = g_secureContext->curStackPointer, R2 = g_secureContext->stackLimit. */
MSR PSPLIM, R2 /* Restore PSPLIM. */
MSR PSP, R1 /* Restore PSP. */
BX LR
.fnend
.type HalSecureContextSaveAsm, %function
.global HalSecureContextSaveAsm
HalSecureContextSaveAsm:
.fnstart
.cantunwind
MRS R0, IPSR
CBZ R0, __ThreadMode
MRS R0, PSP
STR R0, [R1] /* g_secureContext->curStackPointer = R0. */
MOV R0, #0
MSR PSPLIM, R0 /* No PSPLIM for the current task. */
MSR PSP, R0 /* No secure stack for the current task. */
.fnend
__ThreadMode:
BX LR

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@@ -1,229 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_secure_heap.h"
#include "los_secure_macros.h"
#include "los_config.h"
#include "los_list.h"
STATIC UINT8 __attribute__((aligned(0x4)))g_secureHeap[LOSCFG_SECURE_HEAP_SIZE] = {0};
STATIC LOS_DL_LIST g_secureHeapFreeList = {NULL, NULL};
struct OsSecureHeapNode {
LOS_DL_LIST freeNode;
struct OsSecureHeapNode *preNode;
UINT32 size : 24;
UINT32 used : 8;
};
#define OS_SECURE_HEAP_NODE_HEAD_SIZE sizeof(struct OsSecureHeapNode)
#define OS_SECURE_HEAP_ALIGN_SIZE sizeof(UINTPTR)
#define OS_SECURE_HEAP_NODE_USED 1
#define OS_SECURE_HEAP_NODE_FREE 0
#define OS_SECURE_HEAP_FIRST_NODE ((struct OsSecureHeapNode *)g_secureHeap)
#define OS_SECURE_HEAP_NEXT_NODE(node) \
((struct OsSecureHeapNode *)((UINT8 *)(node) + (node)->size))
#define OS_SECURE_HEAP_END_NODE \
((struct OsSecureHeapNode *)((UINT8 *)g_secureHeap + LOSCFG_SECURE_HEAP_SIZE - OS_SECURE_HEAP_NODE_HEAD_SIZE))
STATIC INLINE VOID OsSecureHeapListInit(LOS_DL_LIST *head)
{
head->pstPrev = head;
head->pstNext = head;
}
STATIC INLINE VOID OsSecureHeapListDelete(LOS_DL_LIST *node)
{
node->pstNext->pstPrev = node->pstPrev;
node->pstPrev->pstNext = node->pstNext;
node->pstNext = NULL;
node->pstPrev = NULL;
}
STATIC INLINE VOID OsSecureHeapListAdd(LOS_DL_LIST *listNode, LOS_DL_LIST *node)
{
node->pstNext = listNode->pstNext;
node->pstPrev = listNode;
listNode->pstNext->pstPrev = node;
listNode->pstNext = node;
}
STATIC struct OsSecureHeapNode *OsSecureHeapFindSuitableFreeBlock(UINT32 allocSize)
{
LOS_DL_LIST *listNodeHead = &g_secureHeapFreeList;
struct OsSecureHeapNode *tmpNode = NULL;
LOS_DL_LIST_FOR_EACH_ENTRY(tmpNode, listNodeHead, struct OsSecureHeapNode, freeNode) {
if (tmpNode->size >= allocSize) {
return tmpNode;
}
}
return NULL;
}
STATIC INLINE VOID OsSecureHeapClearNode(struct OsSecureHeapNode *node)
{
node->preNode = NULL;
node->size = 0;
node->used = 0;
node->freeNode.pstPrev = NULL;
node->freeNode.pstNext = NULL;
}
STATIC INLINE VOID OsSecureHeapMergeNode(struct OsSecureHeapNode *node)
{
struct OsSecureHeapNode *nextNode = NULL;
node->preNode->size += node->size;
nextNode = (struct OsSecureHeapNode *)((UINTPTR)node + node->size);
nextNode->preNode = node->preNode;
OsSecureHeapClearNode(node);
}
STATIC INLINE VOID OsSecureHeapSplitNode(struct OsSecureHeapNode *allocNode, UINT32 allocSize)
{
struct OsSecureHeapNode *newFreeNode = NULL;
struct OsSecureHeapNode *nextNode = NULL;
newFreeNode = (struct OsSecureHeapNode *)((UINT8 *)allocNode + allocSize);
newFreeNode->preNode = allocNode;
newFreeNode->size = allocNode->size - allocSize;
newFreeNode->used = OS_SECURE_HEAP_NODE_FREE;
allocNode->size = allocSize;
nextNode = OS_SECURE_HEAP_NEXT_NODE(newFreeNode);
nextNode->preNode = newFreeNode;
if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
OsSecureHeapListDelete(&nextNode->freeNode);
OsSecureHeapMergeNode(nextNode);
}
OsSecureHeapListAdd(&g_secureHeapFreeList, &newFreeNode->freeNode);
}
STATIC INLINE VOID OsSecureHeapFreeNode(struct OsSecureHeapNode *node)
{
struct OsSecureHeapNode *nextNode = NULL;
if ((node->preNode != NULL) && (node->preNode->used == OS_SECURE_HEAP_NODE_FREE)) {
struct OsSecureHeapNode *preNode = node->preNode;
OsSecureHeapMergeNode(node);
nextNode = OS_SECURE_HEAP_NEXT_NODE(preNode);
if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
OsSecureHeapListDelete(&nextNode->freeNode);
OsSecureHeapMergeNode(nextNode);
}
OsSecureHeapListDelete(&preNode->freeNode);
preNode->used = OS_SECURE_HEAP_NODE_FREE;
OsSecureHeapListAdd(&g_secureHeapFreeList, &preNode->freeNode);
} else {
nextNode = OS_SECURE_HEAP_NEXT_NODE(node);
if (nextNode->used == OS_SECURE_HEAP_NODE_FREE) {
OsSecureHeapListDelete(&nextNode->freeNode);
OsSecureHeapMergeNode(nextNode);
}
node->used = OS_SECURE_HEAP_NODE_FREE;
OsSecureHeapListAdd(&g_secureHeapFreeList, &node->freeNode);
}
}
STATIC INLINE VOID *OsSecureHeapAllocNode(UINT32 size)
{
struct OsSecureHeapNode *allocNode = NULL;
UINT32 allocSize;
allocSize = LOS_Align(size + OS_SECURE_HEAP_NODE_HEAD_SIZE, OS_SECURE_HEAP_ALIGN_SIZE);
allocNode = OsSecureHeapFindSuitableFreeBlock(allocSize);
if (allocNode == NULL) {
return NULL;
}
if ((allocSize + OS_SECURE_HEAP_NODE_HEAD_SIZE + OS_SECURE_HEAP_ALIGN_SIZE) <= allocNode->size) {
OsSecureHeapSplitNode(allocNode, allocSize);
}
OsSecureHeapListDelete(&allocNode->freeNode);
allocNode->used = OS_SECURE_HEAP_NODE_USED;
return (allocNode + 1);
}
STATIC INLINE VOID OsSecureHeapInit(VOID)
{
struct OsSecureHeapNode *newNode = NULL;
struct OsSecureHeapNode *endNode = NULL;
newNode = OS_SECURE_HEAP_FIRST_NODE;
newNode->size = LOSCFG_SECURE_HEAP_SIZE - OS_SECURE_HEAP_NODE_HEAD_SIZE;
newNode->preNode = OS_SECURE_HEAP_END_NODE;
newNode->used = OS_SECURE_HEAP_NODE_FREE;
OsSecureHeapListInit(&g_secureHeapFreeList);
OsSecureHeapListAdd(&g_secureHeapFreeList, &newNode->freeNode);
endNode = OS_SECURE_HEAP_END_NODE;
endNode->preNode = newNode;
endNode->size = OS_SECURE_HEAP_NODE_HEAD_SIZE;
endNode->used = OS_SECURE_HEAP_NODE_USED;
}
OS_CMSE_NS_ENTRY VOID *HalSecureMalloc(UINT32 size)
{
if (size == 0) {
return NULL;
}
if ((g_secureHeapFreeList.pstPrev == NULL) &&
(g_secureHeapFreeList.pstNext == NULL)) {
OsSecureHeapInit();
}
return OsSecureHeapAllocNode(size);
}
OS_CMSE_NS_ENTRY VOID HalSecureFree(VOID *ptr)
{
struct OsSecureHeapNode *node = NULL;
if (ptr == NULL) {
return;
}
node = (struct OsSecureHeapNode *)((UINTPTR)ptr - OS_SECURE_HEAP_NODE_HEAD_SIZE);
if (node->used != OS_SECURE_HEAP_NODE_USED) {
return;
}
OsSecureHeapFreeNode(node);
}

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@@ -1,304 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_ATOMIC_H
#define _LOS_ARCH_ATOMIC_H
#include "los_compiler.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
{
INT32 val;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("ldrex %0, [%1]\n"
: "=&r"(val)
: "r"(v)
: "cc");
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
{
UINT32 status;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("1:ldrex %0, [%2]\n"
" strex %0, %3, [%2]\n"
" teq %0, #0\n"
" beq 1b"
: "=&r"(status), "+m"(*v)
: "r"(v), "r"(setVal)
: "cc");
LOS_IntRestore(intSave);
}
STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
{
INT32 val;
UINT32 status;
do {
__asm__ __volatile__("ldrex %1, [%2]\n"
"add %1, %1, %3\n"
"strex %0, %1, [%2]"
: "=&r"(status), "=&r"(val)
: "r"(v), "r"(addVal)
: "cc");
} while (__builtin_expect(status != 0, 0));
return val;
}
STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
{
INT32 val;
UINT32 status;
do {
__asm__ __volatile__("ldrex %1, [%2]\n"
"sub %1, %1, %3\n"
"strex %0, %1, [%2]"
: "=&r"(status), "=&r"(val)
: "r"(v), "r"(subVal)
: "cc");
} while (__builtin_expect(status != 0, 0));
return val;
}
STATIC INLINE VOID ArchAtomicInc(Atomic *v)
{
(VOID)ArchAtomicAdd(v, 1);
}
STATIC INLINE VOID ArchAtomicDec(Atomic *v)
{
(VOID)ArchAtomicSub(v, 1);
}
STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
{
return ArchAtomicAdd(v, 1);
}
STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
{
return ArchAtomicSub(v, 1);
}
/**
* @ingroup los_arch_atomic
* @brief Atomic exchange for 32-bit variable.
*
* @par Description:
* This API is used to implement the atomic exchange for 32-bit variable
* and return the previous value of the atomic variable.
* @attention
* <ul>The pointer v must not be NULL.</ul>
*
* @param v [IN] The variable pointer.
* @param val [IN] The exchange value.
*
* @retval #INT32 The previous value of the atomic variable
* @par Dependency:
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
* @see
*/
STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
{
INT32 prevVal = 0;
UINT32 status = 0;
do {
__asm__ __volatile__("ldrex %0, [%3]\n"
"strex %1, %4, [%3]"
: "=&r"(prevVal), "=&r"(status), "+m"(*v)
: "r"(v), "r"(val)
: "cc");
} while (__builtin_expect(status != 0, 0));
return prevVal;
}
/**
* @ingroup los_arch_atomic
* @brief Atomic exchange for 32-bit variable with compare.
*
* @par Description:
* This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
* @attention
* <ul>The pointer v must not be NULL.</ul>
*
* @param v [IN] The variable pointer.
* @param val [IN] The new value.
* @param oldVal [IN] The old value.
*
* @retval TRUE The previous value of the atomic variable is not equal to oldVal.
* @retval FALSE The previous value of the atomic variable is equal to oldVal.
* @par Dependency:
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
* @see
*/
STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
{
INT32 prevVal = 0;
UINT32 status = 0;
do {
__asm__ __volatile__("1: ldrex %0, %2\n"
" mov %1, #0\n"
" cmp %0, %3\n"
" bne 2f\n"
" strex %1, %4, %2\n"
"2:"
: "=&r"(prevVal), "=&r"(status), "+Q"(*v)
: "r"(oldVal), "r"(val)
: "cc");
} while (__builtin_expect(status != 0, 0));
return prevVal != oldVal;
}
STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
{
UINT32 intSave;
intSave = LOS_IntLock();
*v = setVal;
LOS_IntRestore(intSave);
}
STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v += addVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v -= subVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
{
(VOID)ArchAtomic64Add(v, 1);
}
STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
{
return ArchAtomic64Add(v, 1);
}
STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
{
(VOID)ArchAtomic64Sub(v, 1);
}
STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
{
return ArchAtomic64Sub(v, 1);
}
STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
{
INT64 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
*v = val;
LOS_IntRestore(intSave);
return prevVal;
}
STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
{
INT64 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
if (prevVal == oldVal) {
*v = val;
}
LOS_IntRestore(intSave);
return prevVal != oldVal;
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_ATOMIC_H */

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@@ -1,82 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_trustzone.h"
#include "los_secure_macros.h"
#include "los_secure_context.h"
#include "los_debug.h"
#include "los_arch_context.h"
#include "los_interrupt.h"
OsSecureContext *g_secureContext = NULL;
VOID HalSecureSVCHandler(UINT32 svcID, UINTPTR arg)
{
switch (svcID) {
case OS_SVC_START_SCHEDULE:
HalSecureContextInit();
HalStartFirstTask();
break;
case OS_SVC_ALLOCATE_SECURE_CONTEXT:
g_secureContext = HalSecureContextAlloc(arg);
LOS_ASSERT(g_secureContext != NULL);
HalSecureContextLoad(g_secureContext);
break;
case OS_SVC_FREE_SECURE_CONTEXT:
HalSecureContextFree(g_secureContext);
break;
default:
PRINT_ERR("Incorrect svc id = %u\n", svcID);
break;
}
}
VOID HalStartToRun(VOID)
{
HalSVCStartSchedule();
}
VOID LOS_SecureContextAlloc(UINT32 secureStackSize)
{
if (secureStackSize == 0) {
return;
}
LOS_ASSERT((__get_IPSR() == 0) && (__get_PRIMASK() == 0));
secureStackSize = LOS_Align(secureStackSize, sizeof(UINTPTR));
HalSVCSecureContextAlloc(secureStackSize);
}
VOID LOS_SecureContextFree(VOID)
{
HalSVCSecureContextFree();
}

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@@ -1,60 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_TRUSTZONE_H
#define _LOS_TRUSTZONE_H
#include "los_config.h"
#include "los_task.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
extern VOID LOS_SecureContextAlloc(UINT32 secureStackSize);
extern VOID LOS_SecureContextFree(VOID);
extern VOID HalStartFirstTask(VOID);
extern VOID HalSVCStartSchedule(VOID);
extern VOID HalSVCSecureContextAlloc(UINT32 secureStackSize);
extern VOID HalSVCSecureContextFree(VOID);
extern VOID HalSVCHandler(VOID);
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif

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@@ -1,98 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_secure_context.h"
#include "los_secure_macros.h"
#include "los_secure_heap.h"
OS_CMSE_NS_ENTRY VOID HalSecureContextInit(VOID)
{
UINT32 ipsr;
OS_IPSR_READ(ipsr);
if (!ipsr) {
return;
}
HalSecureContextInitAsm();
}
OS_CMSE_NS_ENTRY OsSecureContext *HalSecureContextAlloc(UINT32 size)
{
OsSecureContext *secureContext = NULL;
UINT32 ipsr;
OS_IPSR_READ(ipsr);
if (!ipsr) {
return NULL;
}
secureContext = HalSecureMalloc(sizeof(OsSecureContext));
if (secureContext == NULL) {
return NULL;
}
secureContext->stackLimit = HalSecureMalloc(size);
if (secureContext->stackLimit == NULL) {
HalSecureFree(secureContext);
return NULL;
}
secureContext->stackStart = secureContext->stackLimit + size;
secureContext->curStackPointer = secureContext->stackStart;
return secureContext;
}
OS_CMSE_NS_ENTRY VOID HalSecureContextFree(OsSecureContext *secureContext)
{
UINT32 ipsr;
OS_IPSR_READ(ipsr);
if (!ipsr) {
return;
}
HalSecureFree(secureContext->stackLimit);
secureContext->stackLimit = NULL;
HalSecureFree(secureContext);
}
OS_CMSE_NS_ENTRY VOID HalSecureContextLoad(OsSecureContext *secureContext)
{
HalSecureContextLoadAsm(secureContext);
}
OS_CMSE_NS_ENTRY VOID HalSecureContextSave(OsSecureContext *secureContext)
{
HalSecureContextSaveAsm(secureContext);
}

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@@ -1,53 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_SECURE_HEAP_H
#define _LOS_SECURE_HEAP_H
#include "los_config.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
VOID *HalSecureMalloc(UINT32 size);
VOID HalSecureFree(VOID *ptr);
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif

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@@ -1,58 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_SECURE_MACROS_H
#define _LOS_SECURE_MACROS_H
#include "los_config.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#define OS_CMSE_NS_ENTRY __attribute__((cmse_nonsecure_entry))
#define OS_CMSE_NS_CALL __attribute__((cmse_nonsecure_call))
#define OS_IPSR_READ(ipsr) __asm volatile("MRS %0, IPSR" : "=r" (ipsr))
#define OS_SVC_ALLOCATE_SECURE_CONTEXT 0
#define OS_SVC_FREE_SECURE_CONTEXT 1
#define OS_SVC_START_SCHEDULE 2
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif

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@@ -1,304 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_ATOMIC_H
#define _LOS_ARCH_ATOMIC_H
#include "los_compiler.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
{
INT32 val;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("ldrex %0, [%1]\n"
: "=&r"(val)
: "r"(v)
: "cc");
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
{
UINT32 status;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("1:ldrex %0, [%2]\n"
" strex %0, %3, [%2]\n"
" teq %0, #0\n"
" beq 1b"
: "=&r"(status), "+m"(*v)
: "r"(v), "r"(setVal)
: "cc");
LOS_IntRestore(intSave);
}
STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
{
INT32 val;
UINT32 status;
do {
__asm__ __volatile__("ldrex %1, [%2]\n"
"add %1, %1, %3\n"
"strex %0, %1, [%2]"
: "=&r"(status), "=&r"(val)
: "r"(v), "r"(addVal)
: "cc");
} while (__builtin_expect(status != 0, 0));
return val;
}
STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
{
INT32 val;
UINT32 status;
do {
__asm__ __volatile__("ldrex %1, [%2]\n"
"sub %1, %1, %3\n"
"strex %0, %1, [%2]"
: "=&r"(status), "=&r"(val)
: "r"(v), "r"(subVal)
: "cc");
} while (__builtin_expect(status != 0, 0));
return val;
}
STATIC INLINE VOID ArchAtomicInc(Atomic *v)
{
(VOID)ArchAtomicAdd(v, 1);
}
STATIC INLINE VOID ArchAtomicDec(Atomic *v)
{
(VOID)ArchAtomicSub(v, 1);
}
STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
{
return ArchAtomicAdd(v, 1);
}
STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
{
return ArchAtomicSub(v, 1);
}
/**
* @ingroup los_arch_atomic
* @brief Atomic exchange for 32-bit variable.
*
* @par Description:
* This API is used to implement the atomic exchange for 32-bit variable
* and return the previous value of the atomic variable.
* @attention
* <ul>The pointer v must not be NULL.</ul>
*
* @param v [IN] The variable pointer.
* @param val [IN] The exchange value.
*
* @retval #INT32 The previous value of the atomic variable
* @par Dependency:
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
* @see
*/
STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
{
INT32 prevVal = 0;
UINT32 status = 0;
do {
__asm__ __volatile__("ldrex %0, [%3]\n"
"strex %1, %4, [%3]"
: "=&r"(prevVal), "=&r"(status), "+m"(*v)
: "r"(v), "r"(val)
: "cc");
} while (__builtin_expect(status != 0, 0));
return prevVal;
}
/**
* @ingroup los_arch_atomic
* @brief Atomic exchange for 32-bit variable with compare.
*
* @par Description:
* This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
* @attention
* <ul>The pointer v must not be NULL.</ul>
*
* @param v [IN] The variable pointer.
* @param val [IN] The new value.
* @param oldVal [IN] The old value.
*
* @retval TRUE The previous value of the atomic variable is not equal to oldVal.
* @retval FALSE The previous value of the atomic variable is equal to oldVal.
* @par Dependency:
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
* @see
*/
STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
{
INT32 prevVal = 0;
UINT32 status = 0;
do {
__asm__ __volatile__("1: ldrex %0, %2\n"
" mov %1, #0\n"
" cmp %0, %3\n"
" bne 2f\n"
" strex %1, %4, %2\n"
"2:"
: "=&r"(prevVal), "=&r"(status), "+Q"(*v)
: "r"(oldVal), "r"(val)
: "cc");
} while (__builtin_expect(status != 0, 0));
return prevVal != oldVal;
}
STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
{
UINT32 intSave;
intSave = LOS_IntLock();
*v = setVal;
LOS_IntRestore(intSave);
}
STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v += addVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v -= subVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
{
(VOID)ArchAtomic64Add(v, 1);
}
STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
{
return ArchAtomic64Add(v, 1);
}
STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
{
(VOID)ArchAtomic64Sub(v, 1);
}
STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
{
return ArchAtomic64Sub(v, 1);
}
STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
{
INT64 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
*v = val;
LOS_IntRestore(intSave);
return prevVal;
}
STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
{
INT64 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
if (prevVal == oldVal) {
*v = val;
}
LOS_IntRestore(intSave);
return prevVal != oldVal;
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_ATOMIC_H */

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@@ -1,51 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_TIMER_H
#define _LOS_ARCH_TIMER_H
#include "los_config.h"
#include "los_compiler.h"
#include "los_timer.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_TIMER_H */

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@@ -1,304 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_ATOMIC_H
#define _LOS_ARCH_ATOMIC_H
#include "los_compiler.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
{
INT32 val;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("ldrex %0, [%1]\n"
: "=&r"(val)
: "r"(v)
: "cc");
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
{
UINT32 status;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("1:ldrex %0, [%2]\n"
" strex %0, %3, [%2]\n"
" teq %0, #0\n"
" beq 1b"
: "=&r"(status), "+m"(*v)
: "r"(v), "r"(setVal)
: "cc");
LOS_IntRestore(intSave);
}
STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
{
INT32 val;
UINT32 status;
do {
__asm__ __volatile__("ldrex %1, [%2]\n"
"add %1, %1, %3\n"
"strex %0, %1, [%2]"
: "=&r"(status), "=&r"(val)
: "r"(v), "r"(addVal)
: "cc");
} while (__builtin_expect(status != 0, 0));
return val;
}
STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
{
INT32 val;
UINT32 status;
do {
__asm__ __volatile__("ldrex %1, [%2]\n"
"sub %1, %1, %3\n"
"strex %0, %1, [%2]"
: "=&r"(status), "=&r"(val)
: "r"(v), "r"(subVal)
: "cc");
} while (__builtin_expect(status != 0, 0));
return val;
}
STATIC INLINE VOID ArchAtomicInc(Atomic *v)
{
(VOID)ArchAtomicAdd(v, 1);
}
STATIC INLINE VOID ArchAtomicDec(Atomic *v)
{
(VOID)ArchAtomicSub(v, 1);
}
STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
{
return ArchAtomicAdd(v, 1);
}
STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
{
return ArchAtomicSub(v, 1);
}
/**
* @ingroup los_arch_atomic
* @brief Atomic exchange for 32-bit variable.
*
* @par Description:
* This API is used to implement the atomic exchange for 32-bit variable
* and return the previous value of the atomic variable.
* @attention
* <ul>The pointer v must not be NULL.</ul>
*
* @param v [IN] The variable pointer.
* @param val [IN] The exchange value.
*
* @retval #INT32 The previous value of the atomic variable
* @par Dependency:
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
* @see
*/
STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
{
INT32 prevVal = 0;
UINT32 status = 0;
do {
__asm__ __volatile__("ldrex %0, [%3]\n"
"strex %1, %4, [%3]"
: "=&r"(prevVal), "=&r"(status), "+m"(*v)
: "r"(v), "r"(val)
: "cc");
} while (__builtin_expect(status != 0, 0));
return prevVal;
}
/**
* @ingroup los_arch_atomic
* @brief Atomic exchange for 32-bit variable with compare.
*
* @par Description:
* This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
* @attention
* <ul>The pointer v must not be NULL.</ul>
*
* @param v [IN] The variable pointer.
* @param val [IN] The new value.
* @param oldVal [IN] The old value.
*
* @retval TRUE The previous value of the atomic variable is not equal to oldVal.
* @retval FALSE The previous value of the atomic variable is equal to oldVal.
* @par Dependency:
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
* @see
*/
STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
{
INT32 prevVal = 0;
UINT32 status = 0;
do {
__asm__ __volatile__("1: ldrex %0, %2\n"
" mov %1, #0\n"
" cmp %0, %3\n"
" bne 2f\n"
" strex %1, %4, %2\n"
"2:"
: "=&r"(prevVal), "=&r"(status), "+Q"(*v)
: "r"(oldVal), "r"(val)
: "cc");
} while (__builtin_expect(status != 0, 0));
return prevVal != oldVal;
}
STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
{
UINT32 intSave;
intSave = LOS_IntLock();
*v = setVal;
LOS_IntRestore(intSave);
}
STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v += addVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v -= subVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
{
(VOID)ArchAtomic64Add(v, 1);
}
STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
{
return ArchAtomic64Add(v, 1);
}
STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
{
(VOID)ArchAtomic64Sub(v, 1);
}
STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
{
return ArchAtomic64Sub(v, 1);
}
STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
{
INT64 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
*v = val;
LOS_IntRestore(intSave);
return prevVal;
}
STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
{
INT64 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
if (prevVal == oldVal) {
*v = val;
}
LOS_IntRestore(intSave);
return prevVal != oldVal;
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_ATOMIC_H */

View File

@@ -1,51 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_TIMER_H
#define _LOS_ARCH_TIMER_H
#include "los_config.h"
#include "los_compiler.h"
#include "los_timer.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_TIMER_H */

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@@ -1,535 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_interrupt.h"
#include "securec.h"
#include <stdarg.h>
#include "los_arch_interrupt.h"
#include "los_context.h"
#include "los_debug.h"
#include "los_hook.h"
#include "los_task.h"
#include "los_sched.h"
#include "los_memory.h"
#include "los_membox.h"
/*lint -save -e40 -e522 -e533*/
UINT32 g_intCount = 0;
/*lint -restore*/
#ifdef __ICCARM__
#pragma location = ".data.vector"
#pragma data_alignment=LOSCFG_ARCH_HWI_VECTOR_ALIGN
#elif defined(__CC_ARM) || defined(__GNUC__)
LITE_OS_SEC_VEC
#endif
/* *
* @ingroup los_hwi
* Hardware interrupt form mapping handling function array.
*/
STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
typedef struct {
HWI_PROC_FUNC pfnHandler;
VOID *pParm;
} HWI_HANDLER_FUNC;
/* *
* @ingroup los_hwi
* Hardware interrupt handler form mapping handling function array.
*/
STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
/* *
* @ingroup los_hwi
* Set interrupt vector table.
*/
VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg)
{
if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalInterrupt;
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector;
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg;
}
}
#else
/* *
* @ingroup los_hwi
* hardware interrupt handler form mapping handling function array.
*/
STATIC HWI_PROC_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {0};
/* *
* @ingroup los_hwi
* Set interrupt vector table.
*/
VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
{
if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
g_hwiForm[num + OS_SYS_VECTOR_CNT] = HalInterrupt;
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector;
}
}
#endif
WEAK VOID SysTick_Handler(VOID)
{
return;
}
/* ****************************************************************************
Function : HalIntNumGet
Description : Get an interrupt number
Input : None
Output : None
Return : Interrupt Indexes number
**************************************************************************** */
LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
{
return __get_IPSR();
}
inline UINT32 ArchIsIntActive(VOID)
{
return (g_intCount > 0);
}
/* ****************************************************************************
Function : HalHwiDefaultHandler
Description : default handler of the hardware interrupt
Input : None
Output : None
Return : None
**************************************************************************** */
/*lint -e529*/
LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
{
UINT32 irqNum = HalIntNumGet();
PRINT_ERR("%s irqnum:%d\n", __FUNCTION__, irqNum);
while (1) {}
}
WEAK VOID HalPreInterruptHandler(UINT32 arg)
{
return;
}
WEAK VOID HalAftInterruptHandler(UINT32 arg)
{
return;
}
/* ****************************************************************************
Function : HalInterrupt
Description : Hardware interrupt entry function
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
{
UINT32 hwiIndex;
UINT32 intSave;
#if (LOSCFG_KERNEL_RUNSTOP == 1)
SCB->SCR &= (UINT32) ~((UINT32)SCB_SCR_SLEEPDEEP_Msk);
#endif
intSave = LOS_IntLock();
g_intCount++;
LOS_IntRestore(intSave);
hwiIndex = HalIntNumGet();
OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
HalPreInterruptHandler(hwiIndex);
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
}
#else
if (g_hwiHandlerForm[hwiIndex] != 0) {
g_hwiHandlerForm[hwiIndex]();
}
#endif
HalAftInterruptHandler(hwiIndex);
OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
intSave = LOS_IntLock();
g_intCount--;
LOS_IntRestore(intSave);
}
/* ****************************************************************************
Function : ArchHwiCreate
Description : create hardware interrupt
Input : hwiNum --- hwi num to create
hwiPrio --- priority of the hwi
mode --- unused
handler --- hwi handler
arg --- param of the hwi handler
Output : None
Return : LOS_OK on success or error code on failure
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
HWI_PRIOR_T hwiPrio,
HWI_MODE_T mode,
HWI_PROC_FUNC handler,
HWI_ARG_T arg)
{
UINT32 intSave;
if (handler == NULL) {
return OS_ERRNO_HWI_PROC_FUNC_NULL;
}
if (hwiNum >= OS_HWI_MAX_NUM) {
return OS_ERRNO_HWI_NUM_INVALID;
}
if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
return OS_ERRNO_HWI_ALREADY_CREATED;
}
if (hwiPrio > OS_HWI_PRIO_LOWEST) {
return OS_ERRNO_HWI_PRIO_INVALID;
}
intSave = LOS_IntLock();
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
OsSetVector(hwiNum, handler, arg);
#else
OsSetVector(hwiNum, handler);
#endif
NVIC_EnableIRQ((IRQn_Type)hwiNum);
NVIC_SetPriority((IRQn_Type)hwiNum, hwiPrio);
LOS_IntRestore(intSave);
return LOS_OK;
}
/* ****************************************************************************
Function : ArchHwiDelete
Description : Delete hardware interrupt
Input : hwiNum --- hwi num to delete
Output : None
Return : LOS_OK on success or error code on failure
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
{
UINT32 intSave;
if (hwiNum >= OS_HWI_MAX_NUM) {
return OS_ERRNO_HWI_NUM_INVALID;
}
NVIC_DisableIRQ((IRQn_Type)hwiNum);
intSave = LOS_IntLock();
g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
LOS_IntRestore(intSave);
return LOS_OK;
}
#define FAULT_STATUS_REG_BIT 32
#define USGFAULT (1 << 18)
#define BUSFAULT (1 << 17)
#define MEMFAULT (1 << 16)
#define DIV0FAULT (1 << 4)
#define UNALIGNFAULT (1 << 3)
#define HARDFAULT_IRQN (-13)
ExcInfo g_excInfo = {0};
UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = {
0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED,
0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR,
0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR,
0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL
};
#if (LOSCFG_KERNEL_PRINTF != 0)
STATIC VOID OsExcNvicDump(VOID)
{
#define OS_NR_NVIC_EXC_DUMP_TYPES 7
UINT32 *base = NULL;
UINT32 len, i, j;
UINT32 rgNvicBases[OS_NR_NVIC_EXC_DUMP_TYPES] = {
OS_NVIC_SETENA_BASE, OS_NVIC_SETPEND_BASE, OS_NVIC_INT_ACT_BASE,
OS_NVIC_PRI_BASE, OS_NVIC_EXCPRI_BASE, OS_NVIC_SHCSR, OS_NVIC_INT_CTRL
};
UINT32 rgNvicLens[OS_NR_NVIC_EXC_DUMP_TYPES] = {
OS_NVIC_INT_ENABLE_SIZE, OS_NVIC_INT_PEND_SIZE, OS_NVIC_INT_ACT_SIZE,
OS_NVIC_INT_PRI_SIZE, OS_NVIC_EXCPRI_SIZE, OS_NVIC_SHCSR_SIZE,
OS_NVIC_INT_CTRL_SIZE
};
CHAR strRgEnable[] = "enable";
CHAR strRgPending[] = "pending";
CHAR strRgActive[] = "active";
CHAR strRgPriority[] = "priority";
CHAR strRgException[] = "exception";
CHAR strRgShcsr[] = "shcsr";
CHAR strRgIntCtrl[] = "control";
CHAR *strRgs[] = {
strRgEnable, strRgPending, strRgActive, strRgPriority,
strRgException, strRgShcsr, strRgIntCtrl
};
PRINTK("\r\nOS exception NVIC dump:\n");
for (i = 0; i < OS_NR_NVIC_EXC_DUMP_TYPES; i++) {
base = (UINT32 *)rgNvicBases[i];
len = rgNvicLens[i];
PRINTK("interrupt %s register, base address: %p, size: 0x%x\n", strRgs[i], base, len);
len = (len >> 2); /* 2: Gets the next register offset */
for (j = 0; j < len; j++) {
PRINTK("0x%x ", *(base + j));
if ((j != 0) && ((j % 16) == 0)) { /* 16: print wrap line */
PRINTK("\n");
}
}
PRINTK("\n");
}
}
STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
{
CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
PRINTK("Type = %d\n", excInfo->type);
PRINTK("ThrdPid = %d\n", excInfo->thrdPid);
PRINTK("Phase = %s\n", phaseStr[excInfo->phase]);
PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
}
STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
{
PRINTK("Current task info:\n");
if (excInfo->phase == OS_EXC_IN_TASK) {
LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
PRINTK("Task name = %s\n", taskCB->taskName);
PRINTK("Task ID = %d\n", taskCB->taskID);
PRINTK("Task SP = %p\n", taskCB->stackPointer);
PRINTK("Task ST = 0x%x\n", taskCB->topOfStack);
PRINTK("Task SS = 0x%x\n", taskCB->stackSize);
} else if (excInfo->phase == OS_EXC_IN_HWI) {
PRINTK("Exception occur in interrupt phase!\n");
} else {
PRINTK("Exception occur in system init phase!\n");
}
}
STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
{
PRINTK("Exception reg dump:\n");
PRINTK("PC = 0x%x\n", excInfo->context->uwPC);
PRINTK("LR = 0x%x\n", excInfo->context->uwLR);
PRINTK("SP = 0x%x\n", excInfo->context->uwSP);
PRINTK("R0 = 0x%x\n", excInfo->context->uwR0);
PRINTK("R1 = 0x%x\n", excInfo->context->uwR1);
PRINTK("R2 = 0x%x\n", excInfo->context->uwR2);
PRINTK("R3 = 0x%x\n", excInfo->context->uwR3);
PRINTK("R4 = 0x%x\n", excInfo->context->uwR4);
PRINTK("R5 = 0x%x\n", excInfo->context->uwR5);
PRINTK("R6 = 0x%x\n", excInfo->context->uwR6);
PRINTK("R7 = 0x%x\n", excInfo->context->uwR7);
PRINTK("R8 = 0x%x\n", excInfo->context->uwR8);
PRINTK("R9 = 0x%x\n", excInfo->context->uwR9);
PRINTK("R10 = 0x%x\n", excInfo->context->uwR10);
PRINTK("R11 = 0x%x\n", excInfo->context->uwR11);
PRINTK("R12 = 0x%x\n", excInfo->context->uwR12);
PRINTK("PriMask = 0x%x\n", excInfo->context->uwPriMask);
PRINTK("xPSR = 0x%x\n", excInfo->context->uwxPSR);
}
STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
{
UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
UINT32 index;
OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->uwSP);
PRINTK("----- backtrace start -----\n");
for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
if (LR[index] == 0) {
break;
}
PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]);
}
PRINTK("----- backtrace end -----\n");
}
STATIC VOID OsExcMemPoolCheckInfo(VOID)
{
PRINTK("\r\nmemory pools check:\n");
#if (LOSCFG_PLATFORM_EXC == 1)
MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
UINT32 errCnt;
UINT32 i;
(VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
if (errCnt < OS_SYS_MEM_NUM) {
errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
}
if (errCnt == 0) {
PRINTK("all memory pool check passed!\n");
return;
}
for (i = 0; i < errCnt; i++) {
PRINTK("pool num = %d\n", i);
PRINTK("pool type = %d\n", memExcInfo[i].type);
PRINTK("pool addr = 0x%x\n", memExcInfo[i].startAddr);
PRINTK("pool size = 0x%x\n", memExcInfo[i].size);
PRINTK("pool free = 0x%x\n", memExcInfo[i].free);
PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize);
PRINTK("pool error node addr = 0x%x\n", memExcInfo[i].errorAddr);
PRINTK("pool error node len = 0x%x\n", memExcInfo[i].errorLen);
PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner);
}
#endif
UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
if (ret == LOS_OK) {
PRINTK("system heap memcheck over, all passed!\n");
}
PRINTK("memory pool check end!\n");
}
#endif
STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
{
#if (LOSCFG_KERNEL_PRINTF != 0)
PRINTK("*************Exception Information**************\n");
OsExcTypeInfo(excInfo);
OsExcCurTaskInfo(excInfo);
OsExcRegInfo(excInfo);
OsExcBackTraceInfo(excInfo);
OsGetAllTskInfo();
OsExcNvicDump();
OsExcMemPoolCheckInfo();
#endif
}
LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr)
{
UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT; /* 16: Get Exception Type */
g_intCount++;
g_excInfo.nestCnt++;
g_excInfo.type = excType & OS_NULL_SHORT;
if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) {
g_excInfo.faultAddr = faultAddr;
} else {
g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
}
if (g_losTask.runTask != NULL) {
if (tmpFlag & OS_EXC_FLAG_IN_HWI) {
g_excInfo.phase = OS_EXC_IN_HWI;
g_excInfo.thrdPid = pid;
} else {
g_excInfo.phase = OS_EXC_IN_TASK;
g_excInfo.thrdPid = g_losTask.runTask->taskID;
}
} else {
g_excInfo.phase = OS_EXC_IN_INIT;
g_excInfo.thrdPid = OS_NULL_INT;
}
if (excType & OS_EXC_FLAG_NO_FLOAT) {
g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4));
} else {
g_excInfo.context = excBufAddr;
}
OsDoExcHook(EXC_INTERRUPT);
OsExcInfoDisplay(&g_excInfo);
ArchSysExit();
}
/* ****************************************************************************
Function : HalHwiInit
Description : initialization of the hardware interrupt
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
{
#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
UINT32 index;
g_hwiForm[0] = 0; /* [0] Top of Stack */
g_hwiForm[1] = Reset_Handler; /* [1] reset */
for (index = 2; index < OS_VECTOR_CNT; index++) { /* 2: The starting position of the interrupt */
g_hwiForm[index] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
}
/* Exception handler register */
g_hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT] = HalExcNMI;
g_hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT] = HalExcHardFault;
g_hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = HalExcMemFault;
g_hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT] = HalExcBusFault;
g_hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT] = HalExcUsageFault;
g_hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT] = HalExcSvcCall;
g_hwiForm[PendSV_IRQn + OS_SYS_VECTOR_CNT] = HalPendSV;
g_hwiForm[SysTick_IRQn + OS_SYS_VECTOR_CNT] = SysTick_Handler;
/* Interrupt vector table location */
SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm;
#endif
#if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */
NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP);
#endif
/* Enable USGFAULT, BUSFAULT, MEMFAULT */
*(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT);
/* Enable DIV 0 and unaligned exception */
#ifdef LOSCFG_ARCH_UNALIGNED_EXC
*(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT);
#else
*(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT);
#endif
return;
}

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/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_mpu.h"
#include "los_config.h"
#include "los_context.h"
#if (LOSCFG_MPU_ENABLE == 1)
#define SIZE_4G_BYTE 0x100000000
#define MPU_MAX_REGION_NUM 8
STATIC UINT8 g_regionNumBeUsed[MPU_MAX_REGION_NUM] = {0};
typedef enum {
MPU_AP_FORBID_USER_FORBID = 0x0, /* Privileged:No access Unprivileged:No access */
MPU_AP_RW_USER_FORBID = 0x1, /* Privileged:Read/Write Unprivileged:No access */
MPU_AP_RW_USER_RO = 0x2, /* Privileged:Read/Write Unprivileged:Read-only */
MPU_AP_RW_USER_RW = 0x3, /* Privileged:Read/Write Unprivileged:Read/Write */
MPU_AP_NA_USER_NA = 0x4, /* Privileged:UNPREDICTABLE Unprivileged:UNPREDICTABLE */
MPU_AP_RO_USER_FORBID = 0x5, /* Privileged:Read-only Unprivileged:No access */
MPU_AP_RO_USER_RO = 0x6, /* Privileged:Read-only Unprivileged:Read-only */
} MpuApConfig;
VOID ArchMpuEnable(UINT32 defaultRegionEnable)
{
UINT32 intSave = ArchIntLock();
MPU->CTRL = (MPU_CTRL_ENABLE_Msk | ((defaultRegionEnable << MPU_CTRL_PRIVDEFENA_Pos) & MPU_CTRL_PRIVDEFENA_Msk));
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
__DSB();
__ISB();
ArchIntRestore(intSave);
}
VOID ArchMpuDisable(VOID)
{
UINT32 intSave = ArchIntLock();
MPU->CTRL = 0;
__DSB();
__ISB();
ArchIntRestore(intSave);
}
STATIC VOID HalMpuRASRAddMemAttr(MPU_CFG_PARA *para, UINT32 *RASR)
{
BOOL cachable = 0;
BOOL buffable = 0;
switch (para->memType) {
case MPU_MEM_ON_CHIP_ROM:
case MPU_MEM_ON_CHIP_RAM:
cachable = 1;
buffable = 0;
break;
case MPU_MEM_XIP_PSRAM:
cachable = 1;
buffable = 1;
break;
case MPU_MEM_XIP_NOR_FLASH:
cachable = 0;
buffable = 1;
break;
default:
break;
}
(*RASR) |= ((cachable << MPU_RASR_C_Pos) | (buffable << MPU_RASR_B_Pos));
}
STATIC UINT32 HalMpuEncodeSize(UINT64 size)
{
UINT32 encodeSize = 0;
if (size > SIZE_4G_BYTE) {
return 0;
}
if ((size & 0x1F) != 0) { /* size should aligned to 32 byte at least. */
return 0;
}
size = (size >> 2);
while (size != 0) {
if (((size & 1) != 0) && ((size & 0xFFFFFFFE) != 0)) { /* size != 2^x (5 <= x <= 32) 128B - 4GB */
return 0;
}
size = (size >> 1);
encodeSize++;
}
return encodeSize;
}
STATIC UINT32 HalMpuEncodeAP(MpuAccessPermission permission)
{
UINT32 ap;
switch (permission) {
case MPU_RW_BY_PRIVILEGED_ONLY:
ap = MPU_AP_RW_USER_FORBID;
break;
case MPU_RW_ANY:
ap = MPU_AP_RW_USER_RW;
break;
case MPU_RO_BY_PRIVILEGED_ONLY:
ap = MPU_AP_RO_USER_FORBID;
break;
case MPU_RO_ANY:
ap = MPU_AP_RO_USER_RO;
break;
default:
ap = MPU_AP_RW_USER_RW;
break;
}
return ap;
}
STATIC UINT32 HalMpuGetRASR(UINT32 encodeSize, MPU_CFG_PARA *para)
{
UINT32 RASR;
UINT32 ap;
ap = HalMpuEncodeAP(para->permission);
RASR = MPU_RASR_ENABLE_Msk;
RASR |= ((encodeSize << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk);
RASR |= ((ap << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | ((para->executable << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) |
((para->shareability << MPU_RASR_S_Pos) & MPU_RASR_S_Msk);
HalMpuRASRAddMemAttr(para, &RASR);
return RASR;
}
UINT32 ArchMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para)
{
UINT32 RASR;
UINT32 RBAR;
UINT32 RNR;
UINT32 encodeSize;
UINT32 intSave;
UINT64 size;
if ((regionId >= MPU_MAX_REGION_NUM) || (para == NULL)) {
return LOS_NOK;
}
if ((MPU_TYPE_DREGION_Msk & MPU->TYPE) == 0) {
return LOS_NOK;
}
RNR = regionId;
encodeSize = HalMpuEncodeSize(para->size);
if (encodeSize == 0) {
return LOS_NOK;
}
size = para->size - 1; /* size aligned after encode check */
if ((para->baseAddr & size) != 0) { /* base addr should aligned to region size */
return LOS_NOK;
}
RBAR = para->baseAddr & MPU_RBAR_ADDR_Msk;
RASR = HalMpuGetRASR(encodeSize, para);
intSave = ArchIntLock();
if (g_regionNumBeUsed[regionId]) {
ArchIntRestore(intSave);
return LOS_NOK;
}
MPU->RNR = RNR;
MPU->RBAR = RBAR;
MPU->RASR = RASR;
__DSB();
__ISB();
g_regionNumBeUsed[regionId] = 1; /* Set mpu region used flag */
ArchIntRestore(intSave);
return LOS_OK;
}
UINT32 ArchMpuDisableRegion(UINT32 regionId)
{
volatile UINT32 type;
UINT32 intSave;
if (regionId >= MPU_MAX_REGION_NUM) {
return LOS_NOK;
}
intSave = ArchIntLock();
if (!g_regionNumBeUsed[regionId]) {
ArchIntRestore(intSave);
return LOS_NOK;
}
type = MPU->TYPE;
if ((MPU_TYPE_DREGION_Msk & type) != 0) {
MPU->RNR = regionId;
MPU->RASR = 0;
__DSB();
__ISB();
}
g_regionNumBeUsed[regionId] = 0; /* clear mpu region used flag */
ArchIntRestore(intSave);
return LOS_OK;
}
INT32 ArchMpuUnusedRegionGet(VOID)
{
INT32 id;
UINT32 intSave = ArchIntLock();
for (id = 0; id < MPU_MAX_REGION_NUM; id++) {
if (!g_regionNumBeUsed[id]) {
break;
}
}
ArchIntRestore(intSave);
if (id == MPU_MAX_REGION_NUM) {
return -1;
} else {
return id;
}
}
#endif

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@@ -1,122 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_timer.h"
#include "los_config.h"
#include "los_tick.h"
#include "los_arch_interrupt.h"
#include "los_debug.h"
STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
STATIC VOID SysTickReload(UINT64 nextResponseTime);
STATIC UINT64 SysTickCycleGet(UINT32 *period);
STATIC VOID SysTickLock(VOID);
STATIC VOID SysTickUnlock(VOID);
STATIC ArchTickTimer g_archTickTimer = {
.freq = 0,
.irqNum = SysTick_IRQn,
.init = SysTickStart,
.getCycle = SysTickCycleGet,
.reload = SysTickReload,
.lock = SysTickLock,
.unlock = SysTickUnlock,
.tickHandler = NULL,
};
STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
{
UINT32 ret;
ArchTickTimer *tick = &g_archTickTimer;
tick->freq = OS_SYS_CLOCK;
#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
OsSetVector(tick->irqNum, handler, NULL);
#else
OsSetVector(tick->irqNum, handler);
#endif
#endif
ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
if (ret == 1) {
return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
}
return LOS_OK;
}
STATIC VOID SysTickReload(UINT64 nextResponseTime)
{
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
NVIC_ClearPendingIRQ(SysTick_IRQn);
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
}
STATIC UINT64 SysTickCycleGet(UINT32 *period)
{
UINT32 hwCycle = 0;
UINT32 intSave = LOS_IntLock();
UINT32 val = SysTick->VAL;
*period = SysTick->LOAD;
if (val != 0) {
hwCycle = *period - val;
}
LOS_IntRestore(intSave);
return (UINT64)hwCycle;
}
STATIC VOID SysTickLock(VOID)
{
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
}
STATIC VOID SysTickUnlock(VOID)
{
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
}
ArchTickTimer *ArchSysTickTimerGet(VOID)
{
return &g_archTickTimer;
}
UINT32 ArchEnterSleep(VOID)
{
__DSB();
__WFI();
__ISB();
return LOS_OK;
}

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@@ -1,304 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_ATOMIC_H
#define _LOS_ARCH_ATOMIC_H
#include "los_compiler.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
{
INT32 val;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("ldrex %0, [%1]\n"
: "=&r"(val)
: "r"(v)
: "cc");
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
{
UINT32 status;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("1:ldrex %0, [%2]\n"
" strex %0, %3, [%2]\n"
" teq %0, #0\n"
" beq 1b"
: "=&r"(status), "+m"(*v)
: "r"(v), "r"(setVal)
: "cc");
LOS_IntRestore(intSave);
}
STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
{
INT32 val;
UINT32 status;
do {
__asm__ __volatile__("ldrex %1, [%2]\n"
"add %1, %1, %3\n"
"strex %0, %1, [%2]"
: "=&r"(status), "=&r"(val)
: "r"(v), "r"(addVal)
: "cc");
} while (__builtin_expect(status != 0, 0));
return val;
}
STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
{
INT32 val;
UINT32 status;
do {
__asm__ __volatile__("ldrex %1, [%2]\n"
"sub %1, %1, %3\n"
"strex %0, %1, [%2]"
: "=&r"(status), "=&r"(val)
: "r"(v), "r"(subVal)
: "cc");
} while (__builtin_expect(status != 0, 0));
return val;
}
STATIC INLINE VOID ArchAtomicInc(Atomic *v)
{
(VOID)ArchAtomicAdd(v, 1);
}
STATIC INLINE VOID ArchAtomicDec(Atomic *v)
{
(VOID)ArchAtomicSub(v, 1);
}
STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
{
return ArchAtomicAdd(v, 1);
}
STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
{
return ArchAtomicSub(v, 1);
}
/**
* @ingroup los_arch_atomic
* @brief Atomic exchange for 32-bit variable.
*
* @par Description:
* This API is used to implement the atomic exchange for 32-bit variable
* and return the previous value of the atomic variable.
* @attention
* <ul>The pointer v must not be NULL.</ul>
*
* @param v [IN] The variable pointer.
* @param val [IN] The exchange value.
*
* @retval #INT32 The previous value of the atomic variable
* @par Dependency:
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
* @see
*/
STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
{
INT32 prevVal = 0;
UINT32 status = 0;
do {
__asm__ __volatile__("ldrex %0, [%3]\n"
"strex %1, %4, [%3]"
: "=&r"(prevVal), "=&r"(status), "+m"(*v)
: "r"(v), "r"(val)
: "cc");
} while (__builtin_expect(status != 0, 0));
return prevVal;
}
/**
* @ingroup los_arch_atomic
* @brief Atomic exchange for 32-bit variable with compare.
*
* @par Description:
* This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
* @attention
* <ul>The pointer v must not be NULL.</ul>
*
* @param v [IN] The variable pointer.
* @param val [IN] The new value.
* @param oldVal [IN] The old value.
*
* @retval TRUE The previous value of the atomic variable is not equal to oldVal.
* @retval FALSE The previous value of the atomic variable is equal to oldVal.
* @par Dependency:
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
* @see
*/
STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
{
INT32 prevVal = 0;
UINT32 status = 0;
do {
__asm__ __volatile__("1: ldrex %0, %2\n"
" mov %1, #0\n"
" cmp %0, %3\n"
" bne 2f\n"
" strex %1, %4, %2\n"
"2:"
: "=&r"(prevVal), "=&r"(status), "+Q"(*v)
: "r"(oldVal), "r"(val)
: "cc");
} while (__builtin_expect(status != 0, 0));
return prevVal != oldVal;
}
STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
{
UINT32 intSave;
intSave = LOS_IntLock();
*v = setVal;
LOS_IntRestore(intSave);
}
STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v += addVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v -= subVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
{
(VOID)ArchAtomic64Add(v, 1);
}
STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
{
return ArchAtomic64Add(v, 1);
}
STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
{
(VOID)ArchAtomic64Sub(v, 1);
}
STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
{
return ArchAtomic64Sub(v, 1);
}
STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
{
INT64 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
*v = val;
LOS_IntRestore(intSave);
return prevVal;
}
STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
{
INT64 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
if (prevVal == oldVal) {
*v = val;
}
LOS_IntRestore(intSave);
return prevVal != oldVal;
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_ATOMIC_H */

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@@ -1,51 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_TIMER_H
#define _LOS_ARCH_TIMER_H
#include "los_config.h"
#include "los_compiler.h"
#include "los_timer.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_TIMER_H */

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@@ -1,155 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_context.h"
#include "securec.h"
#include "los_arch_context.h"
#include "los_arch_interrupt.h"
#include "los_task.h"
#include "los_sched.h"
#include "los_interrupt.h"
#include "los_debug.h"
/* ****************************************************************************
Function : ArchInit
Description : arch init function
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
{
HalHwiInit();
}
/* ****************************************************************************
Function : ArchSysExit
Description : Task exit function
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
{
LOS_IntLock();
while (1) {
}
}
/* ****************************************************************************
Function : ArchTskStackInit
Description : Task stack initialization function
Input : taskID --- TaskID
stackSize --- Total size of the stack
topStack --- Top of task's stack
Output : None
Return : Context pointer
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
{
TaskContext *context = NULL;
errno_t result;
/* initialize the task stack, write magic num to stack top */
result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize);
if (result != EOK) {
printf("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__);
}
*((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD;
context = (TaskContext *)(((UINTPTR)topStack + stackSize) - sizeof(TaskContext));
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined(__FPU_USED) && (__FPU_USED == 1U)))
context->S16 = 0xAA000010;
context->S17 = 0xAA000011;
context->S18 = 0xAA000012;
context->S19 = 0xAA000013;
context->S20 = 0xAA000014;
context->S21 = 0xAA000015;
context->S22 = 0xAA000016;
context->S23 = 0xAA000017;
context->S24 = 0xAA000018;
context->S25 = 0xAA000019;
context->S26 = 0xAA00001A;
context->S27 = 0xAA00001B;
context->S28 = 0xAA00001C;
context->S29 = 0xAA00001D;
context->S30 = 0xAA00001E;
context->S31 = 0xAA00001F;
context->S0 = 0xAA000000;
context->S1 = 0xAA000001;
context->S2 = 0xAA000002;
context->S3 = 0xAA000003;
context->S4 = 0xAA000004;
context->S5 = 0xAA000005;
context->S6 = 0xAA000006;
context->S7 = 0xAA000007;
context->S8 = 0xAA000008;
context->S9 = 0xAA000009;
context->S10 = 0xAA00000A;
context->S11 = 0xAA00000B;
context->S12 = 0xAA00000C;
context->S13 = 0xAA00000D;
context->S14 = 0xAA00000E;
context->S15 = 0xAA00000F;
context->FPSCR = 0x00000000;
context->NO_NAME = 0xAA000011;
#endif
context->uwR4 = 0x04040404L;
context->uwR5 = 0x05050505L;
context->uwR6 = 0x06060606L;
context->uwR7 = 0x07070707L;
context->uwR8 = 0x08080808L;
context->uwR9 = 0x09090909L;
context->uwR10 = 0x10101010L;
context->uwR11 = 0x11111111L;
context->uwPriMask = 0;
context->uwR0 = taskID;
context->uwR1 = 0x01010101L;
context->uwR2 = 0x02020202L;
context->uwR3 = 0x03030303L;
context->uwR12 = 0x12121212L;
context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
context->uwxPSR = 0x01000000L;
return (VOID *)context;
}
LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
{
(VOID)LOS_IntLock();
OsSchedStart();
HalStartToRun();
return LOS_OK; /* never return */
}

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@@ -1,122 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_timer.h"
#include "los_config.h"
#include "los_tick.h"
#include "los_arch_interrupt.h"
#include "los_debug.h"
STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
STATIC VOID SysTickReload(UINT64 nextResponseTime);
STATIC UINT64 SysTickCycleGet(UINT32 *period);
STATIC VOID SysTickLock(VOID);
STATIC VOID SysTickUnlock(VOID);
STATIC ArchTickTimer g_archTickTimer = {
.freq = 0,
.irqNum = SysTick_IRQn,
.init = SysTickStart,
.getCycle = SysTickCycleGet,
.reload = SysTickReload,
.lock = SysTickLock,
.unlock = SysTickUnlock,
.tickHandler = NULL,
};
STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
{
UINT32 ret;
ArchTickTimer *tick = &g_archTickTimer;
tick->freq = OS_SYS_CLOCK;
#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
OsSetVector(tick->irqNum, handler, NULL);
#else
OsSetVector(tick->irqNum, handler);
#endif
#endif
ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
if (ret == 1) {
return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
}
return LOS_OK;
}
STATIC VOID SysTickReload(UINT64 nextResponseTime)
{
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
NVIC_ClearPendingIRQ(SysTick_IRQn);
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
}
STATIC UINT64 SysTickCycleGet(UINT32 *period)
{
UINT32 hwCycle = 0;
UINT32 intSave = LOS_IntLock();
UINT32 val = SysTick->VAL;
*period = SysTick->LOAD;
if (val != 0) {
hwCycle = *period - val;
}
LOS_IntRestore(intSave);
return (UINT64)hwCycle;
}
STATIC VOID SysTickLock(VOID)
{
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
}
STATIC VOID SysTickUnlock(VOID)
{
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
}
ArchTickTimer *ArchSysTickTimerGet(VOID)
{
return &g_archTickTimer;
}
UINT32 ArchEnterSleep(VOID)
{
__DSB();
__WFI();
__ISB();
return LOS_OK;
}

View File

@@ -1,304 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_ATOMIC_H
#define _LOS_ARCH_ATOMIC_H
#include "los_compiler.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
{
INT32 val;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("ldrex %0, [%1]\n"
: "=&r"(val)
: "r"(v)
: "cc");
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
{
UINT32 status;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("1:ldrex %0, [%2]\n"
" strex %0, %3, [%2]\n"
" teq %0, #0\n"
" beq 1b"
: "=&r"(status), "+m"(*v)
: "r"(v), "r"(setVal)
: "cc");
LOS_IntRestore(intSave);
}
STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
{
INT32 val;
UINT32 status;
do {
__asm__ __volatile__("ldrex %1, [%2]\n"
"add %1, %1, %3\n"
"strex %0, %1, [%2]"
: "=&r"(status), "=&r"(val)
: "r"(v), "r"(addVal)
: "cc");
} while (__builtin_expect(status != 0, 0));
return val;
}
STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
{
INT32 val;
UINT32 status;
do {
__asm__ __volatile__("ldrex %1, [%2]\n"
"sub %1, %1, %3\n"
"strex %0, %1, [%2]"
: "=&r"(status), "=&r"(val)
: "r"(v), "r"(subVal)
: "cc");
} while (__builtin_expect(status != 0, 0));
return val;
}
STATIC INLINE VOID ArchAtomicInc(Atomic *v)
{
(VOID)ArchAtomicAdd(v, 1);
}
STATIC INLINE VOID ArchAtomicDec(Atomic *v)
{
(VOID)ArchAtomicSub(v, 1);
}
STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
{
return ArchAtomicAdd(v, 1);
}
STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
{
return ArchAtomicSub(v, 1);
}
/**
* @ingroup los_arch_atomic
* @brief Atomic exchange for 32-bit variable.
*
* @par Description:
* This API is used to implement the atomic exchange for 32-bit variable
* and return the previous value of the atomic variable.
* @attention
* <ul>The pointer v must not be NULL.</ul>
*
* @param v [IN] The variable pointer.
* @param val [IN] The exchange value.
*
* @retval #INT32 The previous value of the atomic variable
* @par Dependency:
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
* @see
*/
STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
{
INT32 prevVal = 0;
UINT32 status = 0;
do {
__asm__ __volatile__("ldrex %0, [%3]\n"
"strex %1, %4, [%3]"
: "=&r"(prevVal), "=&r"(status), "+m"(*v)
: "r"(v), "r"(val)
: "cc");
} while (__builtin_expect(status != 0, 0));
return prevVal;
}
/**
* @ingroup los_arch_atomic
* @brief Atomic exchange for 32-bit variable with compare.
*
* @par Description:
* This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
* @attention
* <ul>The pointer v must not be NULL.</ul>
*
* @param v [IN] The variable pointer.
* @param val [IN] The new value.
* @param oldVal [IN] The old value.
*
* @retval TRUE The previous value of the atomic variable is not equal to oldVal.
* @retval FALSE The previous value of the atomic variable is equal to oldVal.
* @par Dependency:
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
* @see
*/
STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
{
INT32 prevVal = 0;
UINT32 status = 0;
do {
__asm__ __volatile__("1: ldrex %0, %2\n"
" mov %1, #0\n"
" cmp %0, %3\n"
" bne 2f\n"
" strex %1, %4, %2\n"
"2:"
: "=&r"(prevVal), "=&r"(status), "+Q"(*v)
: "r"(oldVal), "r"(val)
: "cc");
} while (__builtin_expect(status != 0, 0));
return prevVal != oldVal;
}
STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
{
UINT32 intSave;
intSave = LOS_IntLock();
*v = setVal;
LOS_IntRestore(intSave);
}
STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v += addVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v -= subVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
{
(VOID)ArchAtomic64Add(v, 1);
}
STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
{
return ArchAtomic64Add(v, 1);
}
STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
{
(VOID)ArchAtomic64Sub(v, 1);
}
STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
{
return ArchAtomic64Sub(v, 1);
}
STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
{
INT64 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
*v = val;
LOS_IntRestore(intSave);
return prevVal;
}
STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
{
INT64 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
if (prevVal == oldVal) {
*v = val;
}
LOS_IntRestore(intSave);
return prevVal != oldVal;
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_ATOMIC_H */

View File

@@ -1,699 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_INTERRUPT_H
#define _LOS_ARCH_INTERRUPT_H
#include "los_config.h"
#include "los_compiler.h"
#include "los_interrupt.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
/* *
* @ingroup los_arch_interrupt
* Maximum number of used hardware interrupts.
*/
#ifndef OS_HWI_MAX_NUM
#define OS_HWI_MAX_NUM LOSCFG_PLATFORM_HWI_LIMIT
#endif
/* *
* @ingroup los_arch_interrupt
* Highest priority of a hardware interrupt.
*/
#ifndef OS_HWI_PRIO_HIGHEST
#define OS_HWI_PRIO_HIGHEST 0
#endif
/* *
* @ingroup los_arch_interrupt
* Lowest priority of a hardware interrupt.
*/
#ifndef OS_HWI_PRIO_LOWEST
#define OS_HWI_PRIO_LOWEST 7
#endif
/* *
* @ingroup los_arch_interrupt
* Define the type of a hardware interrupt vector table function.
*/
typedef VOID (**HWI_VECTOR_FUNC)(void);
/* *
* @ingroup los_arch_interrupt
* Count of interrupts.
*/
extern UINT32 g_intCount;
/* *
* @ingroup los_arch_interrupt
* Count of M-Core system interrupt vector.
*/
#define OS_SYS_VECTOR_CNT 16
/* *
* @ingroup los_arch_interrupt
* Count of M-Core interrupt vector.
*/
#define OS_VECTOR_CNT (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
/* *
* @ingroup los_arch_interrupt
* AIRCR register priority group parameter .
*/
#define OS_NVIC_AIRCR_PRIGROUP 7
/* *
* @ingroup los_arch_interrupt
* Boot interrupt vector table.
*/
extern UINT32 _BootVectors[];
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Invalid interrupt number.
*
* Value: 0x02000900
*
* Solution: Ensure that the interrupt number is valid. The value range of the interrupt number applicable for a Cortex-A7 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
*/
#define OS_ERRNO_HWI_NUM_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Null hardware interrupt handling function.
*
* Value: 0x02000901
*
* Solution: Pass in a valid non-null hardware interrupt handling function.
*/
#define OS_ERRNO_HWI_PROC_FUNC_NULL LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
*
* Value: 0x02000902
*
* Solution: Increase the configured maximum number of supported hardware interrupts.
*/
#define OS_ERRNO_HWI_CB_UNAVAILABLE LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
*
* Value: 0x02000903
*
* Solution: Expand the configured memory.
*/
#define OS_ERRNO_HWI_NO_MEMORY LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: The interrupt has already been created.
*
* Value: 0x02000904
*
* Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
*/
#define OS_ERRNO_HWI_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Invalid interrupt priority.
*
* Value: 0x02000905
*
* Solution: Ensure that the interrupt priority is valid. The value range of the interrupt priority applicable for a Cortex-A7 platform is [0,15].
*/
#define OS_ERRNO_HWI_PRIO_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Incorrect interrupt creation mode.
*
* Value: 0x02000906
*
* Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or OS_HWI_MODE_FAST of which the value can be 0 or 1.
*/
#define OS_ERRNO_HWI_MODE_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
*
* Value: 0x02000907
*
* Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
*/
#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
/* *
* @ingroup los_arch_interrupt
* SysTick control and status register.
*/
#define OS_SYSTICK_CONTROL_REG 0xE000E010
/* *
* @ingroup los_hw
* SysTick current value register.
*/
#define OS_SYSTICK_CURRENT_REG 0xE000E018
/* *
* @ingroup los_arch_interrupt
* Interrupt Priority-Level Registers.
*/
#define OS_NVIC_PRI_BASE 0xE000E400
/* *
* @ingroup los_arch_interrupt
* Interrupt enable register for 0-31.
*/
#define OS_NVIC_SETENA_BASE 0xE000E100
/* *
* @ingroup los_arch_interrupt
* interrupt pending register.
*/
#define OS_NVIC_SETPEND_BASE 0xE000E200
/* *
* @ingroup los_arch_interrupt
* Interrupt active register.
*/
#define OS_NVIC_INT_ACT_BASE 0xE000E300
/* *
* @ingroup los_arch_interrupt
* Interrupt disable register for 0-31.
*/
#define OS_NVIC_CLRENA_BASE 0xE000E180
/* *
* @ingroup los_arch_interrupt
* Interrupt control and status register.
*/
#define OS_NVIC_INT_CTRL 0xE000ED04
/* *
* @ingroup los_arch_interrupt
* Vector table offset register.
*/
#define OS_NVIC_VTOR 0xE000ED08
/* *
* @ingroup los_arch_interrupt
* Application interrupt and reset control register
*/
#define OS_NVIC_AIRCR 0xE000ED0C
/* *
* @ingroup los_arch_interrupt
* System exception priority register.
*/
#define OS_NVIC_EXCPRI_BASE 0xE000ED18
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 1 :reset.
*/
#define OS_EXC_RESET 1
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 2 :Non-Maskable Interrupt.
*/
#define OS_EXC_NMI 2
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 3 :(hard)fault.
*/
#define OS_EXC_HARD_FAULT 3
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 4 :MemManage fault.
*/
#define OS_EXC_MPU_FAULT 4
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 5 :Bus fault.
*/
#define OS_EXC_BUS_FAULT 5
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 6 :Usage fault.
*/
#define OS_EXC_USAGE_FAULT 6
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 11 :SVCall.
*/
#define OS_EXC_SVC_CALL 11
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 12 :Debug monitor.
*/
#define OS_EXC_DBG_MONITOR 12
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 14 :PendSV.
*/
#define OS_EXC_PEND_SV 14
/* *
* @ingroup los_arch_interrupt
* Interrupt No. 15 :SysTick.
*/
#define OS_EXC_SYS_TICK 15
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
/* *
* @ingroup los_arch_interrupt
* Set interrupt vector table.
*/
extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg);
#else
/* *
* @ingroup los_arch_interrupt
* Set interrupt vector table.
*/
extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
#endif
/* *
* @ingroup los_arch_interrupt
* @brief: Hardware interrupt entry function.
*
* @par Description:
* This API is used as all hardware interrupt handling function entry.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param:None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID HalInterrupt(VOID);
/* *
* @ingroup los_arch_interrupt
* @brief: Get an interrupt number.
*
* @par Description:
* This API is used to get the current interrupt number.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param: None.
*
* @retval: Interrupt Indexes number.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern UINT32 HalIntNumGet(VOID);
/* *
* @ingroup los_arch_interrupt
* @brief: Default vector handling function.
*
* @par Description:
* This API is used to configure interrupt for null function.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param:None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID HalHwiDefaultHandler(VOID);
/* *
* @ingroup los_arch_interrupt
* @brief: Reset the vector table.
*
* @par Description:
* This API is used to reset the vector table.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param:None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID Reset_Handler(VOID);
/* *
* @ingroup los_arch_interrupt
* @brief: Pended System Call.
*
* @par Description:
* PendSV can be pended and is useful for an OS to pend an exception
* so that an action can be performed after other important tasks are completed.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param:None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID HalPendSV(VOID);
#define OS_EXC_IN_INIT 0
#define OS_EXC_IN_TASK 1
#define OS_EXC_IN_HWI 2
#define OS_EXC_MAX_BUF_LEN 25
#define OS_EXC_MAX_NEST_DEPTH 1
#define OS_NVIC_SHCSR 0xE000ED24
#define OS_NVIC_CCR 0xE000ED14
#define OS_NVIC_INT_ENABLE_SIZE 0x20
#define OS_NVIC_INT_PRI_SIZE 0xF0
#define OS_NVIC_EXCPRI_SIZE 0xC
#define OS_NVIC_INT_CTRL_SIZE 4
#define OS_NVIC_SHCSR_SIZE 4
#define OS_NVIC_INT_PEND_SIZE OS_NVIC_INT_ACT_SIZE
#define OS_NVIC_INT_ACT_SIZE OS_NVIC_INT_ENABLE_SIZE
#define OS_EXC_FLAG_NO_FLOAT 0x10000000
#define OS_EXC_FLAG_FAULTADDR_VALID 0x01
#define OS_EXC_FLAG_IN_HWI 0x02
#define OS_EXC_IMPRECISE_ACCESS_ADDR 0xABABABAB
#define OS_EXC_EVENT 0x00000001
/**
* @ingroup los_exc
* the struct of register files
*
* description: the register files that saved when exception triggered
*
* notes:the following register with prefix 'uw' correspond to the registers in the cpu data sheet.
*/
typedef struct TagExcContext {
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
UINT32 S16;
UINT32 S17;
UINT32 S18;
UINT32 S19;
UINT32 S20;
UINT32 S21;
UINT32 S22;
UINT32 S23;
UINT32 S24;
UINT32 S25;
UINT32 S26;
UINT32 S27;
UINT32 S28;
UINT32 S29;
UINT32 S30;
UINT32 S31;
#endif
UINT32 uwR4;
UINT32 uwR5;
UINT32 uwR6;
UINT32 uwR7;
UINT32 uwR8;
UINT32 uwR9;
UINT32 uwR10;
UINT32 uwR11;
UINT32 uwPriMask;
/* auto save */
UINT32 uwSP;
UINT32 uwR0;
UINT32 uwR1;
UINT32 uwR2;
UINT32 uwR3;
UINT32 uwR12;
UINT32 uwLR;
UINT32 uwPC;
UINT32 uwxPSR;
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED) && (__FPU_USED== 1U)))
UINT32 S0;
UINT32 S1;
UINT32 S2;
UINT32 S3;
UINT32 S4;
UINT32 S5;
UINT32 S6;
UINT32 S7;
UINT32 S8;
UINT32 S9;
UINT32 S10;
UINT32 S11;
UINT32 S12;
UINT32 S13;
UINT32 S14;
UINT32 S15;
UINT32 FPSCR;
UINT32 NO_NAME;
#endif
} EXC_CONTEXT_S;
typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
VOID HalExcNMI(VOID);
VOID HalExcHardFault(VOID);
VOID HalExcMemFault(VOID);
VOID HalExcBusFault(VOID);
VOID HalExcUsageFault(VOID);
VOID HalExcSvcCall(VOID);
VOID HalHwiInit(VOID);
/**
* @ingroup los_exc
* Cortex-M exception types: An error occurred while the bus status register was being pushed.
*/
#define OS_EXC_BF_STKERR 1
/**
* @ingroup los_exc
* Cortex-M exception types: An error occurred while the bus status register was out of the stack.
*/
#define OS_EXC_BF_UNSTKERR 2
/**
* @ingroup los_exc
* Cortex-M exception types: Bus status register imprecise data access violation.
*/
#define OS_EXC_BF_IMPRECISERR 3
/**
* @ingroup los_exc
* Cortex-M exception types: Bus status register exact data access violation.
*/
#define OS_EXC_BF_PRECISERR 4
/**
* @ingroup los_exc
* Cortex-M exception types: Bus status register access violation while pointing.
*/
#define OS_EXC_BF_IBUSERR 5
/**
* @ingroup los_exc
* Cortex-M exception types: An error occurred while the memory management status register was being pushed.
*/
#define OS_EXC_MF_MSTKERR 6
/**
* @ingroup los_exc
* Cortex-M exception types: An error occurred while the memory management status register was out of the stack.
*/
#define OS_EXC_MF_MUNSTKERR 7
/**
* @ingroup los_exc
* Cortex-M exception types: Memory management status register data access violation.
*/
#define OS_EXC_MF_DACCVIOL 8
/**
* @ingroup los_exc
* Cortex-M exception types: Memory management status register access violation.
*/
#define OS_EXC_MF_IACCVIOL 9
/**
* @ingroup los_exc
* Cortex-M exception types: Incorrect usage indicating that the divisor is zero during the division operation.
*/
#define OS_EXC_UF_DIVBYZERO 10
/**
* @ingroup los_exc
* Cortex-M exception types: Usage error, error caused by unaligned access.
*/
#define OS_EXC_UF_UNALIGNED 11
/**
* @ingroup los_exc
* Cortex-M exception types: Incorrect usage attempting to execute coprocessor related instruction.
*/
#define OS_EXC_UF_NOCP 12
/**
* @ingroup los_exc
* Cortex-M exception types: Usage error attempting to load EXC_RETURN to PC illegally on exception return.
*/
#define OS_EXC_UF_INVPC 13
/**
* @ingroup los_exc
* Cortex-M exception types: Incorrect usage, attempting to cut to ARM state.
*/
#define OS_EXC_UF_INVSTATE 14
/**
* @ingroup los_exc
* Cortex-M exception types: Incorrect usage. Executed instruction whose code is undefined.
*/
#define OS_EXC_UF_UNDEFINSTR 15
/**
* @ingroup los_exc
* Cortex-M exception types: NMI
*/
#define OS_EXC_CAUSE_NMI 16
/**
* @ingroup los_exc
* Cortex-M exception types: hard fault
*/
#define OS_EXC_CAUSE_HARDFAULT 17
/**
* @ingroup los_exc
* Cortex-M exception types: The task handler exits.
*/
#define OS_EXC_CAUSE_TASK_EXIT 18
/**
* @ingroup los_exc
* Cortex-M exception types: A fatal error.
*/
#define OS_EXC_CAUSE_FATAL_ERR 19
/**
* @ingroup los_exc
* Cortex-M exception types: Hard Fault caused by a debug event.
*/
#define OS_EXC_CAUSE_DEBUGEVT 20
/**
* @ingroup los_exc
* Cortex-M exception types: A hard fault that occurs when a quantity is oriented.
*/
#define OS_EXC_CAUSE_VECTBL 21
/**
* @ingroup los_exc
* Exception information structure
*
* Description: Exception information saved when an exception is triggered on the Cortex-M7 platform.
*
*/
typedef struct TagExcInfo {
/**< Exception occurrence phase: 0 means that an exception occurs in initialization,
* 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
UINT16 phase;
/**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */
UINT16 type;
/**< If the exact address access error indicates the wrong access address when the exception occurred */
UINT32 faultAddr;
/**< An exception occurs in an interrupt, indicating the interrupt number.
* An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
UINT32 thrdPid;
/**< Number of nested exceptions. Currently only registered hook functions are supported
* when an exception is entered for the first time */
UINT16 nestCnt;
/**< reserve */
UINT16 reserved;
/**< Hardware context at the time an exception to the automatic stack floating-point register occurs */
EXC_CONTEXT_S *context;
} ExcInfo;
extern UINT32 g_curNestCount;
extern UINT32 g_intCount;
extern UINT8 g_uwExcTbl[32];
extern ExcInfo g_excInfo;
#define MAX_INT_INFO_SIZE (8 + 0x164)
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_INTERRUPT_H */

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/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_TIMER_H
#define _LOS_ARCH_TIMER_H
#include "los_config.h"
#include "los_compiler.h"
#include "los_timer.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_TIMER_H */

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@@ -1,155 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_context.h"
#include "securec.h"
#include "los_arch_context.h"
#include "los_arch_interrupt.h"
#include "los_task.h"
#include "los_sched.h"
#include "los_interrupt.h"
#include "los_debug.h"
/* ****************************************************************************
Function : ArchInit
Description : arch init function
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
{
HalHwiInit();
}
/* ****************************************************************************
Function : ArchSysExit
Description : Task exit function
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
{
LOS_IntLock();
while (1) {
}
}
/* ****************************************************************************
Function : ArchTskStackInit
Description : Task stack initialization function
Input : taskID --- TaskID
stackSize --- Total size of the stack
topStack --- Top of task's stack
Output : None
Return : Context pointer
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
{
TaskContext *context = NULL;
errno_t result;
/* initialize the task stack, write magic num to stack top */
result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize);
if (result != EOK) {
printf("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__);
}
*((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD;
context = (TaskContext *)(((UINTPTR)topStack + stackSize) - sizeof(TaskContext));
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined(__FPU_USED) && (__FPU_USED == 1U)))
context->S16 = 0xAA000010;
context->S17 = 0xAA000011;
context->S18 = 0xAA000012;
context->S19 = 0xAA000013;
context->S20 = 0xAA000014;
context->S21 = 0xAA000015;
context->S22 = 0xAA000016;
context->S23 = 0xAA000017;
context->S24 = 0xAA000018;
context->S25 = 0xAA000019;
context->S26 = 0xAA00001A;
context->S27 = 0xAA00001B;
context->S28 = 0xAA00001C;
context->S29 = 0xAA00001D;
context->S30 = 0xAA00001E;
context->S31 = 0xAA00001F;
context->S0 = 0xAA000000;
context->S1 = 0xAA000001;
context->S2 = 0xAA000002;
context->S3 = 0xAA000003;
context->S4 = 0xAA000004;
context->S5 = 0xAA000005;
context->S6 = 0xAA000006;
context->S7 = 0xAA000007;
context->S8 = 0xAA000008;
context->S9 = 0xAA000009;
context->S10 = 0xAA00000A;
context->S11 = 0xAA00000B;
context->S12 = 0xAA00000C;
context->S13 = 0xAA00000D;
context->S14 = 0xAA00000E;
context->S15 = 0xAA00000F;
context->FPSCR = 0x00000000;
context->NO_NAME = 0xAA000011;
#endif
context->uwR4 = 0x04040404L;
context->uwR5 = 0x05050505L;
context->uwR6 = 0x06060606L;
context->uwR7 = 0x07070707L;
context->uwR8 = 0x08080808L;
context->uwR9 = 0x09090909L;
context->uwR10 = 0x10101010L;
context->uwR11 = 0x11111111L;
context->uwPriMask = 0;
context->uwR0 = taskID;
context->uwR1 = 0x01010101L;
context->uwR2 = 0x02020202L;
context->uwR3 = 0x03030303L;
context->uwR12 = 0x12121212L;
context->uwLR = (UINT32)(UINTPTR)ArchSysExit;
context->uwPC = (UINT32)(UINTPTR)OsTaskEntry;
context->uwxPSR = 0x01000000L;
return (VOID *)context;
}
LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
{
(VOID)LOS_IntLock();
OsSchedStart();
HalStartToRun();
return LOS_OK; /* never return */
}

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@@ -1,122 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_timer.h"
#include "los_config.h"
#include "los_tick.h"
#include "los_arch_interrupt.h"
#include "los_debug.h"
STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
STATIC VOID SysTickReload(UINT64 nextResponseTime);
STATIC UINT64 SysTickCycleGet(UINT32 *period);
STATIC VOID SysTickLock(VOID);
STATIC VOID SysTickUnlock(VOID);
STATIC ArchTickTimer g_archTickTimer = {
.freq = 0,
.irqNum = SysTick_IRQn,
.init = SysTickStart,
.getCycle = SysTickCycleGet,
.reload = SysTickReload,
.lock = SysTickLock,
.unlock = SysTickUnlock,
.tickHandler = NULL,
};
STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
{
UINT32 ret;
ArchTickTimer *tick = &g_archTickTimer;
tick->freq = OS_SYS_CLOCK;
#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
OsSetVector(tick->irqNum, handler, NULL);
#else
OsSetVector(tick->irqNum, handler);
#endif
#endif
ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
if (ret == 1) {
return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL;
}
return LOS_OK;
}
STATIC VOID SysTickReload(UINT64 nextResponseTime)
{
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
NVIC_ClearPendingIRQ(SysTick_IRQn);
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
}
STATIC UINT64 SysTickCycleGet(UINT32 *period)
{
UINT32 hwCycle = 0;
UINT32 intSave = LOS_IntLock();
UINT32 val = SysTick->VAL;
*period = SysTick->LOAD;
if (val != 0) {
hwCycle = *period - val;
}
LOS_IntRestore(intSave);
return (UINT64)hwCycle;
}
STATIC VOID SysTickLock(VOID)
{
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
}
STATIC VOID SysTickUnlock(VOID)
{
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
}
ArchTickTimer *ArchSysTickTimerGet(VOID)
{
return &g_archTickTimer;
}
UINT32 ArchEnterSleep(VOID)
{
__DSB();
__WFI();
__ISB();
return LOS_OK;
}

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@@ -1,56 +0,0 @@
/*
* Copyright (c) 2021-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARCH_ELF_H
#define _ARCH_ELF_H
#include "elf.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#define check_arch(ehdr) ((ehdr)->e_machine == EM_ARM)
#define R_ARCH_NONE R_ARM_NONE
#define R_ARCH_GLOB_DAT R_ARM_GLOB_DAT
#define R_ARCH_JUMP_SLOT R_ARM_JUMP_SLOT
#define R_ARCH_ABS32 R_ARM_ABS32
#define R_ARCH_RELATIVE R_ARM_RELATIVE
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _ARCH_ELF_H */

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@@ -1,34 +0,0 @@
# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
# of conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import("//kernel/liteos_m/liteos.gni")
module_group("csky") {
modules = [ "v2/gcc" ]
}

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@@ -1,45 +0,0 @@
# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
# of conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import("//kernel/liteos_m/liteos.gni")
module_name = "arch"
kernel_module(module_name) {
sources = [
"los_context.c",
"los_dispatch.S",
"los_exc.S",
"los_interrupt.c",
"los_timer.c",
]
}
config("public") {
include_dirs = [ "." ]
}

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@@ -1,300 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_ATOMIC_H
#define _LOS_ARCH_ATOMIC_H
#include "los_compiler.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
{
INT32 val;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("ldw %0, (%1)\n"
: "=&r"(val)
: "r"(v)
: "cc");
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
{
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("stw %0, (%1, 0)"
: "=&r"(setVal)
: "r"(v)
: "cc");
LOS_IntRestore(intSave);
}
STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
{
INT32 val;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("ldw %0, (%1)\n"
"add %0, %0, %2\n"
"stw %0, (%1, 0)"
: "=&r"(val)
: "r"(v), "r"(addVal)
: "cc");
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
{
INT32 val;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("ldw %0, (%1)\n"
"sub %0, %2\n"
"stw %0, (%1, 0)"
: "=&r"(val)
: "r"(v), "r"(subVal)
: "cc");
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomicInc(Atomic *v)
{
(VOID)ArchAtomicAdd(v, 1);
}
STATIC INLINE VOID ArchAtomicDec(Atomic *v)
{
(VOID)ArchAtomicSub(v, 1);
}
STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
{
return ArchAtomicAdd(v, 1);
}
STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
{
return ArchAtomicSub(v, 1);
}
/**
* @ingroup los_arch_atomic
* @brief Atomic exchange for 32-bit variable.
*
* @par Description:
* This API is used to implement the atomic exchange for 32-bit variable
* and return the previous value of the atomic variable.
* @attention
* <ul>The pointer v must not be NULL.</ul>
*
* @param v [IN] The variable pointer.
* @param val [IN] The exchange value.
*
* @retval #INT32 The previous value of the atomic variable
* @par Dependency:
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
* @see
*/
STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
{
INT32 prevVal = 0;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("ldw %0, (%1)\n"
"stw %2, (%1)"
: "=&r"(prevVal)
: "r"(v), "r"(val)
: "cc");
LOS_IntRestore(intSave);
return prevVal;
}
/**
* @ingroup los_arch_atomic
* @brief Atomic exchange for 32-bit variable with compare.
*
* @par Description:
* This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
* @attention
* <ul>The pointer v must not be NULL.</ul>
*
* @param v [IN] The variable pointer.
* @param val [IN] The new value.
* @param oldVal [IN] The old value.
*
* @retval TRUE The previous value of the atomic variable is not equal to oldVal.
* @retval FALSE The previous value of the atomic variable is equal to oldVal.
* @par Dependency:
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
* @see
*/
STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
{
INT32 prevVal = 0;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("1: ldw %0, (%1)\n"
" cmpne %0, %2\n"
" bt 2f\n"
" stw %3, (%1)\n"
"2:"
: "=&r"(prevVal)
: "r"(v), "r"(oldVal), "r"(val)
: "cc");
LOS_IntRestore(intSave);
return prevVal != oldVal;
}
STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
{
UINT32 intSave;
intSave = LOS_IntLock();
*v = setVal;
LOS_IntRestore(intSave);
}
STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v += addVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v -= subVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
{
(VOID)ArchAtomic64Add(v, 1);
}
STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
{
return ArchAtomic64Add(v, 1);
}
STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
{
(VOID)ArchAtomic64Sub(v, 1);
}
STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
{
return ArchAtomic64Sub(v, 1);
}
STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
{
INT64 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
*v = val;
LOS_IntRestore(intSave);
return prevVal;
}
STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
{
INT64 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
if (prevVal == oldVal) {
*v = val;
}
LOS_IntRestore(intSave);
return prevVal != oldVal;
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_ATOMIC_H */

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@@ -1,76 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_CONTEXT_H
#define _LOS_ARCH_CONTEXT_H
#include "los_config.h"
#include "los_compiler.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#define OS_TRAP_STACK_SIZE 500
typedef struct TagTskContext {
UINT32 R0;
UINT32 R1;
UINT32 R2;
UINT32 R3;
UINT32 R4;
UINT32 R5;
UINT32 R6;
UINT32 R7;
UINT32 R8;
UINT32 R9;
UINT32 R10;
UINT32 R11;
UINT32 R12;
UINT32 R13;
UINT32 R15;
UINT32 EPSR;
UINT32 EPC;
} TaskContext;
VOID HalStartToRun(VOID);
VOID HalTaskContextSwitch(VOID);
VOID HalIrqEndCheckNeedSched(VOID);
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_CONTEXT_H */

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@@ -1,391 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_INTERRUPT_H
#define _LOS_ARCH_INTERRUPT_H
#include "los_config.h"
#include "los_compiler.h"
#include "los_interrupt.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
/* *
* @ingroup los_arch_interrupt
* Maximum number of used hardware interrupts.
*/
#ifndef OS_HWI_MAX_NUM
#define OS_HWI_MAX_NUM LOSCFG_PLATFORM_HWI_LIMIT
#endif
/* *
* @ingroup los_arch_interrupt
* Highest priority of a hardware interrupt.
*/
#ifndef OS_HWI_PRIO_HIGHEST
#define OS_HWI_PRIO_HIGHEST 0
#endif
/* *
* @ingroup los_arch_interrupt
* Lowest priority of a hardware interrupt.
*/
#ifndef OS_HWI_PRIO_LOWEST
#define OS_HWI_PRIO_LOWEST 3
#endif
/* *
* @ingroup los_arch_interrupt
* Check the interrupt priority.
*/
#define HWI_PRI_VALID(pri) (((pri) >= OS_HWI_PRIO_HIGHEST) && ((pri) <= OS_HWI_PRIO_LOWEST))
/* *
* @ingroup los_arch_interrupt
* Define the type of a hardware interrupt vector table function.
*/
typedef VOID (**HWI_VECTOR_FUNC)(VOID);
/* *
* @ingroup los_arch_interrupt
* Count of interrupts.
*/
extern UINT32 g_intCount;
/* *
* @ingroup los_arch_interrupt
* Count of C-sky system interrupt vector.
*/
#define OS_SYS_VECTOR_CNT 32
/* *
* @ingroup los_arch_interrupt
* Count of C-sky interrupt vector.
*/
#define OS_VECTOR_CNT (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
#define PSR_VEC_OFFSET 16U
#define VIC_REG_BASE 0xE000E100UL
typedef struct {
UINT32 ISER[4U];
UINT32 RESERVED0[12U];
UINT32 IWER[4U];
UINT32 RESERVED1[12U];
UINT32 ICER[4U];
UINT32 RESERVED2[12U];
UINT32 IWDR[4U];
UINT32 RESERVED3[12U];
UINT32 ISPR[4U];
UINT32 RESERVED4[12U];
UINT32 ISSR[4U];
UINT32 RESERVED5[12U];
UINT32 ICPR[4U];
UINT32 RESERVED6[12U];
UINT32 ICSR[4U];
UINT32 RESERVED7[12U];
UINT32 IABR[4U];
UINT32 RESERVED8[60U];
UINT32 IPR[32U];
UINT32 RESERVED9[480U];
UINT32 ISR;
UINT32 IPTR;
UINT32 TSPEND;
UINT32 TSABR;
UINT32 TSPR;
} VIC_TYPE;
extern VIC_TYPE *VIC_REG;
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Invalid interrupt number.
*
* Value: 0x02000900
*
* Solution: Ensure that the interrupt number is valid.
*/
#define OS_ERRNO_HWI_NUM_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Null hardware interrupt handling function.
*
* Value: 0x02000901
*
* Solution: Pass in a valid non-null hardware interrupt handling function.
*/
#define OS_ERRNO_HWI_PROC_FUNC_NULL LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
*
* Value: 0x02000902
*
* Solution: Increase the configured maximum number of supported hardware interrupts.
*/
#define OS_ERRNO_HWI_CB_UNAVAILABLE LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
*
* Value: 0x02000903
*
* Solution: Expand the configured memory.
*/
#define OS_ERRNO_HWI_NO_MEMORY LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: The interrupt has already been created.
*
* Value: 0x02000904
*
* Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
*/
#define OS_ERRNO_HWI_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Invalid interrupt priority.
*
* Value: 0x02000905
*
* Solution: Ensure that the interrupt priority is valid.
*/
#define OS_ERRNO_HWI_PRIO_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Incorrect interrupt creation mode.
*
* Value: 0x02000906
*
* Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or OS_HWI_MODE_FAST.
*/
#define OS_ERRNO_HWI_MODE_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
*
* Value: 0x02000907
*
* Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
*/
#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Invalid interrupt number.
*
* Value: 0x02000900
*
* Solution: Ensure that the interrupt number is valid.
*/
#define LOS_ERRNO_HWI_NUM_INVALID OS_ERRNO_HWI_NUM_INVALID
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
/* *
* @ingroup los_arch_interrupt
* Set interrupt vector table.
*/
extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg);
#else
/* *
* @ingroup los_arch_interrupt
* Set interrupt vector table.
*/
extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
#endif
/* *
* @ingroup los_arch_interrupt
* @brief: Hardware interrupt entry function.
*
* @par Description:
* This API is used as all hardware interrupt handling function entry.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param:None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID HalInterrupt(VOID);
/* *
* @ingroup los_arch_interrupt
* @brief: Get an interrupt number.
*
* @par Description:
* This API is used to get the current interrupt number.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param: None.
*
* @retval: Interrupt Indexes number.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern UINT32 HalIntNumGet(VOID);
/* *
* @ingroup los_arch_interrupt
* @brief: Default vector handling function.
*
* @par Description:
* This API is used to configure interrupt for null function.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param:None.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
extern VOID HalHwiDefaultHandler(VOID);
#define OS_EXC_IN_INIT 0
#define OS_EXC_IN_TASK 1
#define OS_EXC_IN_HWI 2
#define OS_VIC_INT_ENABLE_SIZE 0x4
#define OS_VIC_INT_WAKER_SIZE 0x4
#define OS_VIC_INT_ICER_SIZE 0x4
#define OS_VIC_INT_ISPR_SIZE 0x4
#define OS_VIC_INT_IABR_SIZE 0x4
#define OS_VIC_INT_IPR_SIZE 0x4
#define OS_VIC_INT_ISR_SIZE 0x4
#define OS_VIC_INT_IPTR_SIZE 0x4
#define OS_EXC_FLAG_FAULTADDR_VALID 0x01
#define OS_EXC_IMPRECISE_ACCESS_ADDR 0xABABABAB
/**
* @ingroup los_exc
* the struct of register files
*
* description: the register files that saved when exception triggered
*
* notes:the following register with prefix 'uw' correspond to the registers in the cpu data sheet.
*/
typedef struct TagExcContext {
UINT32 R0;
UINT32 R1;
UINT32 R2;
UINT32 R3;
UINT32 R4;
UINT32 R5;
UINT32 R6;
UINT32 R7;
UINT32 R8;
UINT32 R9;
UINT32 R10;
UINT32 R11;
UINT32 R12;
UINT32 R13;
UINT32 R14;
UINT32 R15;
UINT32 EPSR;
UINT32 EPC;
} EXC_CONTEXT_S;
/* *
* @ingroup los_arch_interrupt
* @brief: Exception handler function.
*
* @par Description:
* This API is used to handle Exception.
*
* @attention:
* <ul><li>None.</li></ul>
*
* @param excBufAddr [IN] The address of stack pointer at which the error occurred.
* @param faultAddr [IN] The address at which the error occurred.
*
* @retval:None.
* @par Dependency:
* <ul><li>los_arch_interrupt.h: the header file that contains the API declaration.</li></ul>
* @see None.
*/
LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(EXC_CONTEXT_S *excBufAddr, UINT32 faultAddr);
VOID IrqEntry(VOID);
VOID HandleEntry(VOID);
VOID HalHwiInit(VOID);
/**
* @ingroup los_exc
* Exception information structure
*
* Description: Exception information saved when an exception is triggered on the Csky platform.
*
*/
typedef struct TagExcInfo {
UINT16 phase;
UINT16 type;
UINT32 faultAddr;
UINT32 thrdPid;
UINT16 nestCnt;
UINT16 reserved;
EXC_CONTEXT_S *context;
} ExcInfo;
extern ExcInfo g_excInfo;
#define MAX_INT_INFO_SIZE (8 + 0x164)
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_INTERRUPT_H */

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@@ -1,51 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_TIMER_H
#define _LOS_ARCH_TIMER_H
#include "los_config.h"
#include "los_compiler.h"
#include "los_timer.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_TIMER_H */

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@@ -1,144 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_context.h"
#include "securec.h"
#include "los_arch_context.h"
#include "los_arch_interrupt.h"
#include "los_task.h"
#include "los_sched.h"
#include "los_interrupt.h"
#include "los_debug.h"
STATIC UINT32 g_sysNeedSched = FALSE;
/* ****************************************************************************
Function : ArchInit
Description : arch init function
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
{
HalHwiInit();
}
/* ****************************************************************************
Function : ArchSysExit
Description : Task exit function
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
{
LOS_IntLock();
while (1) {
}
}
/* ****************************************************************************
Function : ArchTskStackInit
Description : Task stack initialization function
Input : taskID --- TaskID
stackSize --- Total size of the stack
topStack --- Top of task's stack
Output : None
Return : Context pointer
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
{
TaskContext *context = NULL;
errno_t result;
/* initialize the task stack, write magic num to stack top */
result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize);
if (result != EOK) {
printf("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__);
}
*((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD;
context = (TaskContext *)(((UINTPTR)topStack + stackSize) - sizeof(TaskContext));
context->R0 = taskID;
context->R1 = 0x01010101L;
context->R2 = 0x02020202L;
context->R3 = 0x03030303L;
context->R4 = 0x04040404L;
context->R5 = 0x05050505L;
context->R6 = 0x06060606L;
context->R7 = 0x07070707L;
context->R8 = 0x08080808L;
context->R9 = 0x09090909L;
context->R10 = 0x10101010L;
context->R11 = 0x11111111L;
context->R12 = 0x12121212L;
context->R13 = 0x13131313L;
context->R15 = (UINT32)ArchSysExit;
context->EPSR = 0xe0000144L;
context->EPC = (UINT32)OsTaskEntry;
return (VOID *)context;
}
LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
{
(VOID)LOS_IntLock();
OsSchedStart();
HalStartToRun();
return LOS_OK; /* never return */
}
VOID HalIrqEndCheckNeedSched(VOID)
{
if (g_sysNeedSched && g_taskScheduled && LOS_CHECK_SCHEDULE) {
ArchTaskSchedule();
}
}
VOID ArchTaskSchedule(VOID)
{
UINT32 intSave;
if (OS_INT_ACTIVE) {
g_sysNeedSched = TRUE;
return;
}
intSave = LOS_IntLock();
g_sysNeedSched = FALSE;
BOOL isSwitch = OsSchedTaskSwitch();
if (isSwitch) {
HalTaskContextSwitch();
}
LOS_IntRestore(intSave);
return;
}

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@@ -1,89 +0,0 @@
/*
* Copyright (c) 2013-2020, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#define OS_TASK_STATUS_RUNNING 0x0010
#define VIC_TSPDR 0XE000EC08
.section .text
.align 2
.type HalStartToRun, %function
.global HalStartToRun
HalStartToRun:
lrw r1, g_losTask
lrw r2, g_losTask + 4
ldw r0, (r2)
st.w r0, (r1)
st.w r0, (r2)
ldw sp, (r0)
ldw r0, (sp, 64)
mtcr r0, epc
ldw r0, (sp, 60)
mtcr r0, epsr
ldw r15, (sp, 56)
ldm r0-r13, (sp)
rte
.align 2
.type HalTaskContextSwitch, %function
.global HalTaskContextSwitch
HalTaskContextSwitch:
subi sp, 68
stm r0-r13, (sp)
stw r15, (sp, 56)
mfcr r1, psr
stw r1, (sp, 60)
stw r15, (sp, 64)
lrw r2, g_losTask
ldw r0, (r2)
stw sp, (r0)
lrw r3, g_losTask + 4
ldw r0, (r3)
stw r0, (r2)
ldw sp, (r0)
ldw r0, (sp, 64)
mtcr r0, epc
ldw r0, (sp, 60)
mtcr r0, epsr
ldw r15, (sp, 56)
ldm r0-r13, (sp)
addi sp, 68
rte

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@@ -1,77 +0,0 @@
/*
* Copyright (c) 2013-2020, Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.import HalExcHandleEntry
.extern g_trapStackBase
.section .text
.align 2
.global HandleEntry
HandleEntry:
mov r10, sp
lrw r14, g_trapStackBase
stm r0-r15, (sp)
stw r10, (sp, 56)
mfcr r0, epsr
stw r0, (sp, 64)
mfcr r0, epc
stw r0, (sp, 68)
mov r0, sp
mfcr r1, epc
mov sp, r10
lrw r2, HalExcHandleEntry
jmp r2
.section .text
.align 2
.global IrqEntry
IrqEntry:
psrset ee
subi sp, 72
stm r0-r15, (sp)
mfcr r0, epsr
stw r0, (sp, 64)
mfcr r0, epc
stw r0, (sp, 68)
jbsr HalInterrupt
ldw r0, (sp, 68)
mtcr r0, epc
ldw r0, (sp, 64)
bseti r0, r0, 6
mtcr r0, epsr
ldm r0-r15, (sp)
addi sp, 72
rte

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@@ -1,580 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_interrupt.h"
#include <stdarg.h>
#include "securec.h"
#include "los_context.h"
#include "los_arch_context.h"
#include "los_arch_interrupt.h"
#include "los_debug.h"
#include "los_hook.h"
#include "los_task.h"
#include "los_sched.h"
#include "los_memory.h"
#include "los_membox.h"
#define INT_OFFSET 6
#define PRI_OFF_PER_INT 8
#define PRI_PER_REG 4
#define PRI_OFF_IN_REG 6
#define PRI_BITS 2
#define PRI_HI 0
#define PRI_LOW 7
#define MASK_8_BITS 0xFF
#define MASK_32_BITS 0xFFFFFFFF
#define BYTES_OF_128_INT 4
#define TIM_INT_NUM 1
#define OS_USER_HWI_MIN 0
#define OS_USER_HWI_MAX (LOSCFG_PLATFORM_HWI_LIMIT - 1)
#define HWI_ALIGNSIZE 0x400
UINT32 g_intCount = 0;
CHAR g_trapStackBase[OS_TRAP_STACK_SIZE];
VIC_TYPE *VIC_REG = (VIC_TYPE *)VIC_REG_BASE;
UINT32 HwiNumValid(UINT32 num)
{
return ((num) >= OS_USER_HWI_MIN) && ((num) <= OS_USER_HWI_MAX);
}
UINT32 HalGetPsr(VOID)
{
UINT32 intSave;
__asm__ volatile("mfcr %0, psr" : "=r" (intSave) : : "memory");
return intSave;
}
UINT32 HalSetVbr(UINT32 intSave)
{
__asm__ volatile("mtcr %0, vbr" : : "r"(intSave) : "memory");
return intSave;
}
UINT32 ArchIntLock(VOID)
{
UINT32 intSave;
__asm__ __volatile__(
"mfcr %0, psr \n"
"psrclr ie"
: "=r"(intSave)
:
: "memory");
return intSave;
}
UINT32 ArchIntUnLock(VOID)
{
UINT32 intSave;
__asm__ __volatile__(
"mfcr %0, psr \n"
"psrset ie"
: "=r"(intSave)
:
: "memory");
return intSave;
}
VOID ArchIntRestore(UINT32 intSave)
{
__asm__ __volatile__("mtcr %0, psr" : : "r"(intSave));
}
UINT32 ArchIntLocked(VOID)
{
UINT32 intSave;
__asm__ volatile("mfcr %0, psr" : "=r" (intSave) : : "memory");
return !(intSave & (1 << INT_OFFSET));
}
UINT32 HalIrqUnmask(UINT32 hwiNum)
{
UINT32 intSave;
if (!HwiNumValid(hwiNum)) {
return LOS_ERRNO_HWI_NUM_INVALID;
}
intSave = LOS_IntLock();
VIC_REG->ISER[hwiNum / OS_SYS_VECTOR_CNT] = (UINT32)(1UL << (hwiNum % OS_SYS_VECTOR_CNT));
VIC_REG->ISSR[hwiNum / OS_SYS_VECTOR_CNT] = (UINT32)(1UL << (hwiNum % OS_SYS_VECTOR_CNT));
LOS_IntRestore(intSave);
return LOS_OK;
}
UINT32 HalIrqSetPriority(UINT32 hwiNum, UINT8 priority)
{
UINT32 intSave;
if (!HwiNumValid(hwiNum)) {
return LOS_ERRNO_HWI_NUM_INVALID;
}
if (!HWI_PRI_VALID(priority)) {
return OS_ERRNO_HWI_PRIO_INVALID;
}
intSave = LOS_IntLock();
VIC_REG->IPR[hwiNum / PRI_PER_REG] |= (((priority << PRI_OFF_IN_REG) << (hwiNum % PRI_PER_REG)) * PRI_OFF_PER_INT);
LOS_IntRestore(intSave);
return LOS_OK;
}
UINT32 HalIrqMask(HWI_HANDLE_T hwiNum)
{
UINT32 intSave;
if (!HwiNumValid(hwiNum)) {
return LOS_ERRNO_HWI_NUM_INVALID;
}
intSave = LOS_IntLock();
VIC_REG->ICER[hwiNum / OS_SYS_VECTOR_CNT] = (UINT32)(1UL << (hwiNum % OS_SYS_VECTOR_CNT));
LOS_IntRestore(intSave);
return LOS_OK;
}
UINT32 HalIrqPending(UINT32 hwiNum)
{
UINT32 intSave;
if (!HwiNumValid(hwiNum)) {
return LOS_ERRNO_HWI_NUM_INVALID;
}
intSave = LOS_IntLock();
VIC_REG->ISPR[hwiNum / OS_SYS_VECTOR_CNT] = (UINT32)(1UL << (hwiNum % OS_SYS_VECTOR_CNT));
LOS_IntRestore(intSave);
return LOS_OK;
}
UINT32 HalIrqClear(UINT32 hwiNum)
{
if (!HwiNumValid(hwiNum)) {
return LOS_ERRNO_HWI_NUM_INVALID;
}
VIC_REG->ICPR[hwiNum / OS_SYS_VECTOR_CNT] = (UINT32)(1UL << (hwiNum % OS_SYS_VECTOR_CNT));
return LOS_OK;
}
/* *
* @ingroup los_hwi
* Hardware interrupt form mapping handling function array.
*/
STATIC HWI_PROC_FUNC __attribute__((aligned(HWI_ALIGNSIZE))) g_hwiForm[OS_VECTOR_CNT] = {0};
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
typedef struct {
HWI_PROC_FUNC pfnHandler;
VOID *pParm;
} HWI_HANDLER_FUNC;
/* *
* @ingroup los_hwi
* Hardware interrupt handler form mapping handling function array.
*/
STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
/* *
* @ingroup los_hwi
* Set interrupt vector table.
*/
VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg)
{
if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)IrqEntry;
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector;
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg;
HalIrqUnmask(num);
}
}
#else
/* *
* @ingroup los_hwi
* Hardware interrupt handler form mapping handling function array.
*/
STATIC HWI_PROC_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {0};
/* *
* @ingroup los_hwi
* Set interrupt vector table.
*/
VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
{
if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
g_hwiForm[num + OS_SYS_VECTOR_CNT] = IrqEntry;
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector;
HalIrqUnmask(num);
}
}
#endif
/* ****************************************************************************
Function : HalIntNumGet
Description : Get an interrupt number
Input : None
Output : None
Return : Interrupt Indexes number
**************************************************************************** */
LITE_OS_SEC_TEXT_MINOR UINT32 HalIntNumGet(VOID)
{
return HalGetPsr();
}
inline UINT32 ArchIsIntActive(VOID)
{
return (g_intCount > 0);
}
/* ****************************************************************************
Function : HalHwiDefaultHandler
Description : default handler of the hardware interrupt
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
{
UINT32 irqNum = HalIntNumGet();
irqNum = (irqNum >> PSR_VEC_OFFSET) & MASK_8_BITS;
PRINT_ERR("%s irqnum:%x\n", __FUNCTION__, irqNum);
while (1) {}
}
WEAK VOID HalPreInterruptHandler(UINT32 arg)
{
return;
}
WEAK VOID HalAftInterruptHandler(UINT32 arg)
{
return;
}
/* ****************************************************************************
Function : HalInterrupt
Description : Hardware interrupt entry function
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
{
UINT32 hwiIndex;
UINT32 intSave;
intSave = LOS_IntLock();
g_intCount++;
LOS_IntRestore(intSave);
hwiIndex = HalIntNumGet();
hwiIndex = (hwiIndex >> PSR_VEC_OFFSET) & MASK_8_BITS;
OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
HalPreInterruptHandler(hwiIndex);
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
}
#else
if (g_hwiHandlerForm[hwiIndex] != 0) {
g_hwiHandlerForm[hwiIndex]();
}
#endif
HalAftInterruptHandler(hwiIndex);
OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
intSave = LOS_IntLock();
g_intCount--;
HalIrqEndCheckNeedSched();
LOS_IntRestore(intSave);
}
/* ****************************************************************************
Function : ArchHwiCreate
Description : create hardware interrupt
Input : hwiNum --- hwi num to create
hwiPrio --- priority of the hwi
mode --- unused
handler --- hwi handler
arg --- param of the hwi handler
Output : None
Return : LOS_OK on success or error code on failure
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
HWI_PRIOR_T hwiPrio,
HWI_MODE_T mode,
HWI_PROC_FUNC handler,
HWI_ARG_T arg)
{
UINT32 intSave;
if (handler == NULL) {
return OS_ERRNO_HWI_PROC_FUNC_NULL;
}
if (hwiNum >= OS_HWI_MAX_NUM) {
return OS_ERRNO_HWI_NUM_INVALID;
}
if (g_hwiHandlerForm[hwiNum + OS_SYS_VECTOR_CNT] != 0) {
return OS_ERRNO_HWI_ALREADY_CREATED;
}
if (g_hwiHandlerForm[hwiNum + OS_SYS_VECTOR_CNT] != 0) {
return OS_ERRNO_HWI_ALREADY_CREATED;
}
if (hwiPrio > OS_HWI_PRIO_LOWEST) {
return OS_ERRNO_HWI_PRIO_INVALID;
}
intSave = LOS_IntLock();
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
OsSetVector(hwiNum, handler, arg);
#else
OsSetVector(hwiNum, handler);
#endif
HalIrqUnmask(hwiNum);
(VOID)HalIrqSetPriority(hwiNum, (UINT8)hwiPrio);
LOS_IntRestore(intSave);
return LOS_OK;
}
/* ****************************************************************************
Function : ArchHwiDelete
Description : Delete hardware interrupt
Input : hwiNum --- hwi num to delete
Output : None
Return : LOS_OK on success or error code on failure
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
{
UINT32 intSave;
if (hwiNum >= OS_HWI_MAX_NUM) {
return OS_ERRNO_HWI_NUM_INVALID;
}
HalIrqMask(hwiNum);
intSave = LOS_IntLock();
g_hwiHandlerForm[hwiNum + OS_SYS_VECTOR_CNT] = 0;
LOS_IntRestore(intSave);
return LOS_OK;
}
ExcInfo g_excInfo = {0};
#if (LOSCFG_KERNEL_PRINTF != 0)
STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
{
CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
PRINTK("Type = %d\n", excInfo->type);
PRINTK("ThrdPid = %d\n", excInfo->thrdPid);
PRINTK("Phase = %s\n", phaseStr[excInfo->phase]);
PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
}
STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
{
PRINTK("Current task info:\n");
if (excInfo->phase == OS_EXC_IN_TASK) {
LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
PRINTK("Task name = %s\n", taskCB->taskName);
PRINTK("Task ID = %d\n", taskCB->taskID);
PRINTK("Task SP = 0x%x\n", (UINTPTR)taskCB->stackPointer);
PRINTK("Task ST = 0x%x\n", taskCB->topOfStack);
PRINTK("Task SS = 0x%x\n", taskCB->stackSize);
} else if (excInfo->phase == OS_EXC_IN_HWI) {
PRINTK("Exception occur in interrupt phase!\n");
} else {
PRINTK("Exception occur in system init phase!\n");
}
}
STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
{
EXC_CONTEXT_S *excContext = excInfo->context;
PRINTK("Exception reg dump:\n");
PRINTK("R0 = 0x%x\n"
"R1 = 0x%x\n"
"R2 = 0x%x\n"
"R3 = 0x%x\n"
"R4 = 0x%x\n"
"R5 = 0x%x\n"
"R6 = 0x%x\n"
"R7 = 0x%x\n"
"R8 = 0x%x\n"
"R9 = 0x%x\n"
"R10 = 0x%x\n"
"R11 = 0x%x\n"
"R12 = 0x%x\n"
"R13 = 0x%x\n"
"R14 = 0x%x\n"
"R15 = 0x%x\n"
"EPSR = 0x%x\n"
"EPC = 0x%x\n",
excContext->R0, excContext->R1, excContext->R2, excContext->R3, excContext->R4, excContext->R5,
excContext->R6, excContext->R7, excContext->R8, excContext->R9, excContext->R10, excContext->R11,
excContext->R12, excContext->R13, excContext->R14, excContext->R15, excContext->EPSR,
excContext->EPC);
}
STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
{
UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
UINT32 index;
OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->R14);
PRINTK("----- backtrace start -----\n");
for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
if (LR[index] == 0) {
break;
}
PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]);
}
PRINTK("----- backtrace end -----\n");
}
STATIC VOID OsExcMemPoolCheckInfo(VOID)
{
PRINTK("\r\nmemory pools check:\n");
#if (LOSCFG_PLATFORM_EXC == 1)
MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
UINT32 errCnt;
UINT32 i;
(VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
if (errCnt < OS_SYS_MEM_NUM) {
errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
}
if (errCnt == 0) {
PRINTK("all memory pool check passed!\n");
return;
}
for (i = 0; i < errCnt; i++) {
PRINTK("pool num = %d\n", i);
PRINTK("pool type = %d\n", memExcInfo[i].type);
PRINTK("pool addr = 0x%x\n", memExcInfo[i].startAddr);
PRINTK("pool size = 0x%x\n", memExcInfo[i].size);
PRINTK("pool free = 0x%x\n", memExcInfo[i].free);
PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize);
PRINTK("pool error node addr = 0x%x\n", memExcInfo[i].errorAddr);
PRINTK("pool error node len = 0x%x\n", memExcInfo[i].errorLen);
PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner);
}
#endif
UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
if (ret == LOS_OK) {
PRINTK("system heap memcheck over, all passed!\n");
}
PRINTK("memory pool check end!\n");
}
#endif
STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
{
#if (LOSCFG_KERNEL_PRINTF != 0)
PRINTK("*************Exception Information**************\n");
OsExcTypeInfo(excInfo);
OsExcCurTaskInfo(excInfo);
OsExcRegInfo(excInfo);
OsExcBackTraceInfo(excInfo);
OsGetAllTskInfo();
OsExcMemPoolCheckInfo();
#endif
}
LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(EXC_CONTEXT_S *excBufAddr, UINT32 faultAddr)
{
UINT16 tmpFlag = ((excBufAddr->EPSR >> PSR_VEC_OFFSET) & MASK_8_BITS);
g_excInfo.nestCnt++;
UINT32 excType = (HalGetPsr() >> PSR_VEC_OFFSET) & MASK_8_BITS;
g_excInfo.type = excType;
g_excInfo.faultAddr = faultAddr;
if (g_losTask.runTask != NULL) {
if (tmpFlag > 0) {
g_excInfo.phase = OS_EXC_IN_HWI;
g_excInfo.thrdPid = tmpFlag;
} else {
g_excInfo.phase = OS_EXC_IN_TASK;
g_excInfo.thrdPid = g_losTask.runTask->taskID;
}
} else {
g_excInfo.phase = OS_EXC_IN_INIT;
g_excInfo.thrdPid = OS_NULL_INT;
}
g_excInfo.context = excBufAddr;
OsDoExcHook(EXC_INTERRUPT);
OsExcInfoDisplay(&g_excInfo);
ArchSysExit();
}
/* stack protector */
WEAK UINT32 __stack_chk_guard = 0xd00a0dff;
WEAK VOID __stack_chk_fail(VOID)
{
/* __builtin_return_address is a builtin function, building in gcc */
LOS_Panic("stack-protector: Kernel stack is corrupted in: %x\n",
__builtin_return_address(0));
}
/* ****************************************************************************
Function : HalHwiInit
Description : initialization of the hardware interrupt
Input : None
Output : None
Return : None
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
{
UINT32 i;
for (i = 1; i < OS_SYS_VECTOR_CNT; i++) {
g_hwiForm[i] = (HWI_PROC_FUNC)HandleEntry;
}
for (i = OS_SYS_VECTOR_CNT; i < (LOSCFG_PLATFORM_HWI_LIMIT + OS_SYS_VECTOR_CNT); i++) {
g_hwiForm[i] = (HWI_PROC_FUNC)IrqEntry;
}
HalSetVbr((UINT32)&g_hwiForm);
for (int i = 0; i < BYTES_OF_128_INT; i++) {
VIC_REG->IABR[i] = 0x0;
VIC_REG->ICPR[i] = MASK_32_BITS;
}
return;
}

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@@ -1,151 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_timer.h"
#include "los_config.h"
#include "los_tick.h"
#include "los_arch_interrupt.h"
#include "los_debug.h"
typedef struct {
UINT32 CTRL;
UINT32 LOAD;
UINT32 VAL;
UINT32 CALIB;
} CORE_TIM_TYPE;
#define OS_CYCLE_PER_TICK (OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND)
#define CORE_TIM_BASE (0xE000E010UL)
#define SysTick ((CORE_TIM_TYPE *)CORE_TIM_BASE)
#define CORETIM_ENABLE (1UL << 0)
#define CORETIM_INTMASK (1UL << 1)
#define CORETIM_SOURCE (1UL << 2)
#define CORETIM_MODE (1UL << 16)
#define TIM_INT_NUM 1
STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
STATIC VOID SysTickReload(UINT64 nextResponseTime);
STATIC UINT64 SysTickCycleGet(UINT32 *period);
STATIC VOID SysTickLock(VOID);
STATIC VOID SysTickUnlock(VOID);
STATIC ArchTickTimer g_archTickTimer = {
.freq = 0,
.irqNum = TIM_INT_NUM,
.init = SysTickStart,
.getCycle = SysTickCycleGet,
.reload = SysTickReload,
.lock = SysTickLock,
.unlock = SysTickUnlock,
.tickHandler = NULL,
};
/* ****************************************************************************
Function : HalTickStart
Description : Configure Tick Interrupt Start
Input : none
output : none
return : LOS_OK - Success , or LOS_ERRNO_TICK_CFG_INVALID - failed
**************************************************************************** */
STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
{
ArchTickTimer *tick = &g_archTickTimer;
tick->freq = OS_SYS_CLOCK;
SysTick->LOAD = (OS_CYCLE_PER_TICK - 1);
SysTick->VAL = 0;
SysTick->CTRL |= (CORETIM_SOURCE | CORETIM_ENABLE | CORETIM_INTMASK);
VIC_REG->IWER[0] = 0x1 << TIM_INT_NUM;
#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
OsSetVector(tick->irqNum, handler, NULL);
#else
OsSetVector(tick->irqNum, handler);
#endif
#endif
return LOS_OK;
}
STATIC VOID SysTickReload(UINT64 nextResponseTime)
{
SysTick->CTRL &= ~CORETIM_ENABLE;
SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL |= CORETIM_ENABLE;
}
STATIC UINT64 SysTickCycleGet(UINT32 *period)
{
UINT32 hwCycle;
UINT32 intSave = LOS_IntLock();
*period = SysTick->LOAD;
hwCycle = *period - SysTick->VAL;
LOS_IntRestore(intSave);
return (UINT64)hwCycle;
}
STATIC VOID SysTickLock(VOID)
{
SysTick->CTRL &= ~CORETIM_ENABLE;
}
STATIC VOID SysTickUnlock(VOID)
{
SysTick->CTRL |= CORETIM_ENABLE;
}
ArchTickTimer *ArchSysTickTimerGet(VOID)
{
return &g_archTickTimer;
}
VOID Wfi(VOID)
{
__asm__ volatile("wait");
}
VOID Dsb(VOID)
{
__asm__ volatile("sync" : : : "memory");
}
UINT32 ArchEnterSleep(VOID)
{
Dsb();
Wfi();
return LOS_OK;
}

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@@ -1,71 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ATOMIC_H
#define _LOS_ATOMIC_H
#include "los_compiler.h"
#include "los_arch_atomic.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#define LOS_AtomicRead ArchAtomicRead
#define LOS_AtomicSet ArchAtomicSet
#define LOS_AtomicAdd ArchAtomicAdd
#define LOS_AtomicSub ArchAtomicSub
#define LOS_AtomicInc ArchAtomicInc
#define LOS_AtomicIncRet ArchAtomicIncRet
#define LOS_AtomicDec ArchAtomicDec
#define LOS_AtomicDecRet ArchAtomicDecRet
#define LOS_Atomic64Read ArchAtomic64Read
#define LOS_Atomic64Set ArchAtomic64Set
#define LOS_Atomic64Add ArchAtomic64Add
#define LOS_Atomic64Sub ArchAtomic64Sub
#define LOS_Atomic64Inc ArchAtomic64Inc
#define LOS_Atomic64IncRet ArchAtomic64IncRet
#define LOS_Atomic64Dec ArchAtomic64Dec
#define LOS_Atomic64DecRet ArchAtomic64DecRet
#define LOS_AtomicXchg32bits ArchAtomicXchg32bits
#define LOS_AtomicXchg64bits ArchAtomicXchg64bits
#define LOS_AtomicCmpXchg32bits ArchAtomicCmpXchg32bits
#define LOS_AtomicCmpXchg64bits ArchAtomicCmpXchg64bits
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ATOMIC_H */

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@@ -1,34 +0,0 @@
# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
# of conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import("//kernel/liteos_m/liteos.gni")
module_group("risc-v") {
modules = [ "riscv32/gcc" ]
}

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@@ -1,303 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_ATOMIC_H
#define _LOS_ARCH_ATOMIC_H
#include "los_compiler.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
{
INT32 val;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("lr.w %0, (%1)\n"
"fence rw, rw\n"
: "=&r"(val)
: "r"(v)
: "memory");
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
{
UINT32 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("amoswap.w %0, %2, (%1)\n"
: "=r"(prevVal)
: "r"(v), "r"(setVal)
: "memory");
LOS_IntRestore(intSave);
}
STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
{
INT32 val;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("amoadd.w %0, %2, (%1)\n"
"lw %0, (%1)\n"
"fence rw, rw\n"
: "=&r"(val)
: "r"(v), "r"(addVal)
: "memory");
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
{
INT32 val;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("amoadd.w %0, %2, (%1)\n"
"lw %0, (%1)\n"
"fence rw, rw\n"
: "=&r"(val)
: "r"(v), "r"(-subVal)
: "memory");
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomicInc(Atomic *v)
{
(VOID)ArchAtomicAdd(v, 1);
}
STATIC INLINE VOID ArchAtomicDec(Atomic *v)
{
(VOID)ArchAtomicSub(v, 1);
}
STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
{
return ArchAtomicAdd(v, 1);
}
STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
{
return ArchAtomicSub(v, 1);
}
/**
* @ingroup los_arch_atomic
* @brief Atomic exchange for 32-bit variable.
*
* @par Description:
* This API is used to implement the atomic exchange for 32-bit variable
* and return the previous value of the atomic variable.
* @attention
* <ul>The pointer v must not be NULL.</ul>
*
* @param v [IN] The variable pointer.
* @param val [IN] The exchange value.
*
* @retval #INT32 The previous value of the atomic variable
* @par Dependency:
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
* @see
*/
STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
{
INT32 prevVal = 0;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("lw %0, 0(%1)\n"
"amoswap.w %0, %2, (%1)\n"
: "=&r"(prevVal)
: "r"(v), "r"(val)
: "memory");
LOS_IntRestore(intSave);
return prevVal;
}
/**
* @ingroup los_arch_atomic
* @brief Atomic exchange for 32-bit variable with compare.
*
* @par Description:
* This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
* @attention
* <ul>The pointer v must not be NULL.</ul>
*
* @param v [IN] The variable pointer.
* @param val [IN] The new value.
* @param oldVal [IN] The old value.
*
* @retval TRUE The previous value of the atomic variable is not equal to oldVal.
* @retval FALSE The previous value of the atomic variable is equal to oldVal.
* @par Dependency:
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
* @see
*/
STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
{
INT32 prevVal = 0;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("1: lw %0, 0(%1)\n"
" bne %0, %2, 2f\n"
" amoswap.w %0, %3, (%1)\n"
"2:"
: "=&r"(prevVal)
: "r"(v), "r"(oldVal), "r"(val)
: "memory");
LOS_IntRestore(intSave);
return prevVal != oldVal;
}
STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
{
UINT32 intSave;
intSave = LOS_IntLock();
*v = setVal;
LOS_IntRestore(intSave);
}
STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v += addVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v -= subVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
{
(VOID)ArchAtomic64Add(v, 1);
}
STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
{
return ArchAtomic64Add(v, 1);
}
STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
{
(VOID)ArchAtomic64Sub(v, 1);
}
STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
{
return ArchAtomic64Sub(v, 1);
}
STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
{
INT64 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
*v = val;
LOS_IntRestore(intSave);
return prevVal;
}
STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
{
INT64 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
if (prevVal == oldVal) {
*v = val;
}
LOS_IntRestore(intSave);
return prevVal != oldVal;
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_ATOMIC_H */

View File

@@ -1,303 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_ATOMIC_H
#define _LOS_ARCH_ATOMIC_H
#include "los_compiler.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
{
INT32 val;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("lr.w %0, (%1)\n"
"fence rw, rw\n"
: "=&r"(val)
: "r"(v)
: "memory");
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
{
UINT32 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("amoswap.w %0, %2, (%1)\n"
: "=r"(prevVal)
: "r"(v), "r"(setVal)
: "memory");
LOS_IntRestore(intSave);
}
STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
{
INT32 val;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("amoadd.w %0, %2, (%1)\n"
"lw %0, (%1)\n"
"fence rw, rw\n"
: "=&r"(val)
: "r"(v), "r"(addVal)
: "memory");
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
{
INT32 val;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("amoadd.w %0, %2, (%1)\n"
"lw %0, (%1)\n"
"fence rw, rw\n"
: "=&r"(val)
: "r"(v), "r"(-subVal)
: "memory");
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomicInc(Atomic *v)
{
(VOID)ArchAtomicAdd(v, 1);
}
STATIC INLINE VOID ArchAtomicDec(Atomic *v)
{
(VOID)ArchAtomicSub(v, 1);
}
STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
{
return ArchAtomicAdd(v, 1);
}
STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
{
return ArchAtomicSub(v, 1);
}
/**
* @ingroup los_arch_atomic
* @brief Atomic exchange for 32-bit variable.
*
* @par Description:
* This API is used to implement the atomic exchange for 32-bit variable
* and return the previous value of the atomic variable.
* @attention
* <ul>The pointer v must not be NULL.</ul>
*
* @param v [IN] The variable pointer.
* @param val [IN] The exchange value.
*
* @retval #INT32 The previous value of the atomic variable
* @par Dependency:
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
* @see
*/
STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
{
INT32 prevVal = 0;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("lw %0, 0(%1)\n"
"amoswap.w %0, %2, (%1)\n"
: "=&r"(prevVal)
: "r"(v), "r"(val)
: "memory");
LOS_IntRestore(intSave);
return prevVal;
}
/**
* @ingroup los_arch_atomic
* @brief Atomic exchange for 32-bit variable with compare.
*
* @par Description:
* This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
* @attention
* <ul>The pointer v must not be NULL.</ul>
*
* @param v [IN] The variable pointer.
* @param val [IN] The new value.
* @param oldVal [IN] The old value.
*
* @retval TRUE The previous value of the atomic variable is not equal to oldVal.
* @retval FALSE The previous value of the atomic variable is equal to oldVal.
* @par Dependency:
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
* @see
*/
STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
{
INT32 prevVal = 0;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("1: lw %0, 0(%1)\n"
" bne %0, %2, 2f\n"
" amoswap.w %0, %3, (%1)\n"
"2:"
: "=&r"(prevVal)
: "r"(v), "r"(oldVal), "r"(val)
: "memory");
LOS_IntRestore(intSave);
return prevVal != oldVal;
}
STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
{
UINT32 intSave;
intSave = LOS_IntLock();
*v = setVal;
LOS_IntRestore(intSave);
}
STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v += addVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v -= subVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
{
(VOID)ArchAtomic64Add(v, 1);
}
STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
{
return ArchAtomic64Add(v, 1);
}
STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
{
(VOID)ArchAtomic64Sub(v, 1);
}
STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
{
return ArchAtomic64Sub(v, 1);
}
STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
{
INT64 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
*v = val;
LOS_IntRestore(intSave);
return prevVal;
}
STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
{
INT64 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
if (prevVal == oldVal) {
*v = val;
}
LOS_IntRestore(intSave);
return prevVal != oldVal;
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_ATOMIC_H */

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@@ -1,34 +0,0 @@
# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
# of conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import("//kernel/liteos_m/liteos.gni")
module_group("xtensa") {
modules = [ "lx6/gcc" ]
}

View File

@@ -1,46 +0,0 @@
# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
# of conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import("//kernel/liteos_m/liteos.gni")
module_name = "arch"
kernel_module(module_name) {
sources = [
"los_context.c",
"los_dispatch.S",
"los_exc.S",
"los_interrupt.c",
"los_timer.c",
"los_window.S",
]
}
config("public") {
include_dirs = [ "." ]
}

View File

@@ -1,308 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_ATOMIC_H
#define _LOS_ARCH_ATOMIC_H
#include "los_compiler.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
{
INT32 val;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("l32ai %0, %1, 0\n"
: "=&a"(val)
: "a"(v)
: "memory");
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
{
INT32 val;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("l32ai %0, %2, 0\n"
"wsr %0, SCOMPARE1\n"
"s32c1i %3, %1"
: "=&a"(val), "+m"(*v)
: "a"(v), "a"(setVal)
: "memory");
LOS_IntRestore(intSave);
}
STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
{
INT32 val;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("l32ai %0, %2, 0\n"
"wsr %0, SCOMPARE1\n"
"add %0, %0, %3\n"
"s32c1i %0, %1\n"
: "=&a"(val), "+m"(*v)
: "a"(v), "a"(addVal)
: "memory");
LOS_IntRestore(intSave);
return *v;
}
STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
{
INT32 val;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("l32ai %0, %2, 0\n"
"wsr %0, SCOMPARE1\n"
"sub %0, %0, %3\n"
"s32c1i %0, %1\n"
: "=&a"(val), "+m"(*v)
: "a"(v), "a"(subVal)
: "memory");
LOS_IntRestore(intSave);
return *v;
}
STATIC INLINE VOID ArchAtomicInc(Atomic *v)
{
(VOID)ArchAtomicAdd(v, 1);
}
STATIC INLINE VOID ArchAtomicDec(Atomic *v)
{
(VOID)ArchAtomicSub(v, 1);
}
STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
{
return ArchAtomicAdd(v, 1);
}
STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
{
return ArchAtomicSub(v, 1);
}
/**
* @ingroup los_arch_atomic
* @brief Atomic exchange for 32-bit variable.
*
* @par Description:
* This API is used to implement the atomic exchange for 32-bit variable
* and return the previous value of the atomic variable.
* @attention
* <ul>The pointer v must not be NULL.</ul>
*
* @param v [IN] The variable pointer.
* @param val [IN] The exchange value.
*
* @retval #INT32 The previous value of the atomic variable
* @par Dependency:
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
* @see
*/
STATIC INLINE INT32 ArchAtomicXchg32bits(volatile INT32 *v, INT32 val)
{
INT32 prevVal = 0;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("l32ai %0, %2, 0\n"
"wsr %0, SCOMPARE1\n"
"s32c1i %3, %1\n"
: "=&a"(prevVal), "+m"(*v)
: "a"(v), "a"(val)
: "memory");
LOS_IntRestore(intSave);
return prevVal;
}
/**
* @ingroup los_arch_atomic
* @brief Atomic exchange for 32-bit variable with compare.
*
* @par Description:
* This API is used to implement the atomic exchange for 32-bit variable, if the value of variable is equal to oldVal.
* @attention
* <ul>The pointer v must not be NULL.</ul>
*
* @param v [IN] The variable pointer.
* @param val [IN] The new value.
* @param oldVal [IN] The old value.
*
* @retval TRUE The previous value of the atomic variable is not equal to oldVal.
* @retval FALSE The previous value of the atomic variable is equal to oldVal.
* @par Dependency:
* <ul><li>los_arch_atomic.h: the header file that contains the API declaration.</li></ul>
* @see
*/
STATIC INLINE BOOL ArchAtomicCmpXchg32bits(volatile INT32 *v, INT32 val, INT32 oldVal)
{
INT32 prevVal = 0;
UINT32 intSave;
intSave = LOS_IntLock();
__asm__ __volatile__("l32ai %0, %2, 0\n"
"wsr %0, SCOMPARE1\n"
"bne %0, %3, 2f\n"
"s32c1i %4, %1\n"
"2:\n"
: "=&a"(prevVal), "+m"(*v)
: "a"(v), "a"(oldVal), "a"(val)
: "cc");
LOS_IntRestore(intSave);
return prevVal != oldVal;
}
STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
{
UINT32 intSave;
intSave = LOS_IntLock();
*v = setVal;
LOS_IntRestore(intSave);
}
STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v += addVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
{
INT64 val;
UINT32 intSave;
intSave = LOS_IntLock();
*v -= subVal;
val = *v;
LOS_IntRestore(intSave);
return val;
}
STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
{
(VOID)ArchAtomic64Add(v, 1);
}
STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
{
return ArchAtomic64Add(v, 1);
}
STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
{
(VOID)ArchAtomic64Sub(v, 1);
}
STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
{
return ArchAtomic64Sub(v, 1);
}
STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
{
INT64 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
*v = val;
LOS_IntRestore(intSave);
return prevVal;
}
STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
{
INT64 prevVal;
UINT32 intSave;
intSave = LOS_IntLock();
prevVal = *v;
if (prevVal == oldVal) {
*v = val;
}
LOS_IntRestore(intSave);
return prevVal != oldVal;
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_ATOMIC_H */

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@@ -1,71 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_CONTEXT_H
#define _LOS_ARCH_CONTEXT_H
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#define SAVED_REG_NUM 8
#define SPILL_WINDOW_SIZE 8
typedef struct {
UINT32 pc;
UINT32 ps;
UINT32 regA[16];
UINT32 sar;
UINT32 excCause;
UINT32 excVaddr;
UINT32 lbeg;
UINT32 lend;
UINT32 lcount;
#if (defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))
UINT32 temp;
UINT16 cpenable;
UINT16 cpstored;
UINT32 fcr;
UINT32 fsr;
UINT32 regF[16];
#endif
UINT32 res[4];
} TaskContext;
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_CONTEXT_H */

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@@ -1,250 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_INTERRUPT_H
#define _LOS_ARCH_INTERRUPT_H
#include "los_config.h"
#include "los_compiler.h"
#include "los_interrupt.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
typedef struct {
UINT32 pc;
UINT32 ps;
UINT32 regA[16];
UINT32 sar;
UINT32 excCause;
UINT32 excVaddr;
UINT32 lbeg;
UINT32 lend;
UINT32 lcount;
#if (defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))
UINT32 temp;
UINT16 cpenable;
UINT16 cpstored;
UINT32 fcr;
UINT32 fsr;
UINT32 regF[16];
#endif
UINT32 res[4];
} EXC_CONTEXT_S;
#define VECTOR_START _init_start
extern CHAR *VECTOR_START;
#define INIT_VECTOR_START ((UINTPTR)&VECTOR_START)
/* *
* @ingroup los_arch_interrupt
* Maximum number of used hardware interrupts.
*/
#ifndef OS_HWI_MAX_NUM
#define OS_HWI_MAX_NUM LOSCFG_PLATFORM_HWI_LIMIT
#endif
/* *
* @ingroup los_arch_interrupt
* Highest priority of a hardware interrupt.
*/
#ifndef OS_HWI_PRIO_HIGHEST
#define OS_HWI_PRIO_HIGHEST 0
#endif
/* *
* @ingroup los_arch_interrupt
* Lowest priority of a hardware interrupt.
*/
#ifndef OS_HWI_PRIO_LOWEST
#define OS_HWI_PRIO_LOWEST 7
#endif
#define OS_EXC_IN_INIT 0
#define OS_EXC_IN_TASK 1
#define OS_EXC_IN_HWI 2
/* *
* @ingroup los_arch_interrupt
* Define the type of a hardware interrupt vector table function.
*/
typedef VOID (**HWI_VECTOR_FUNC)(VOID);
/* *
* @ingroup los_arch_interrupt
* Count of interrupts.
*/
extern UINT32 g_intCount;
/* *
* @ingroup los_arch_interrupt
* Count of Xtensa system interrupt vector.
*/
#define OS_SYS_VECTOR_CNT 0
/* *
* @ingroup los_arch_interrupt
* Count of Xtensa interrupt vector.
*/
#define OS_VECTOR_CNT (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Invalid interrupt number.
*
* Value: 0x02000900
*
* Solution: Ensure that the interrupt number is valid.
*/
#define OS_ERRNO_HWI_NUM_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Null hardware interrupt handling function.
*
* Value: 0x02000901
*
* Solution: Pass in a valid non-null hardware interrupt handling function.
*/
#define OS_ERRNO_HWI_PROC_FUNC_NULL LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
*
* Value: 0x02000902
*
* Solution: Increase the configured maximum number of supported hardware interrupts.
*/
#define OS_ERRNO_HWI_CB_UNAVAILABLE LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
*
* Value: 0x02000903
*
* Solution: Expand the configured memory.
*/
#define OS_ERRNO_HWI_NO_MEMORY LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: The interrupt has already been created.
*
* Value: 0x02000904
*
* Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
*/
#define OS_ERRNO_HWI_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Invalid interrupt priority.
*
* Value: 0x02000905
*
* Solution: Ensure that the interrupt priority is valid.
*/
#define OS_ERRNO_HWI_PRIO_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: Incorrect interrupt creation mode.
*
* Value: 0x02000906
*
* Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or OS_HWI_MODE_FAST.
*/
#define OS_ERRNO_HWI_MODE_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
/* *
* @ingroup los_arch_interrupt
* Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
*
* Value: 0x02000907
*
* Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
*/
#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
/* *
* @ingroup los_arch_interrupt
* Set interrupt vector table.
*/
extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg);
#else
/* *
* @ingroup los_arch_interrupt
* Set interrupt vector table.
*/
extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
#endif
VOID HalInterrupt(VOID);
UINT32 HalIntNumGet(VOID);
VOID HalHwiDefaultHandler(VOID);
VOID HalExcHandleEntry(UINTPTR faultAddr, EXC_CONTEXT_S *excBufAddr, UINT32 type);
VOID HalHwiInit(VOID);
/**
* @ingroup los_exc
* Exception information structure
*
* Description: Exception information saved when an exception is triggered on the Xtensa platform.
*
*/
typedef struct TagExcInfo {
UINT16 phase;
UINT16 type;
UINT32 faultAddr;
UINT32 thrdPid;
UINT16 nestCnt;
UINT16 reserved;
EXC_CONTEXT_S *context;
} ExcInfo;
extern UINT32 g_curNestCount;
extern ExcInfo g_excInfo;
#define MAX_INT_INFO_SIZE (8 + 0x164)
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_INTERRUPT_H */

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@@ -1,171 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_MACRO_H
#define _LOS_ARCH_MACRO_H
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
.macro POP_ALL_REG SP PC PState
#if (defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))
l16ui a3, \SP, CONTEXT_OFF_CPENABLE
wsr a3, CPENABLE
rsync
l16ui a3, \SP, CONTEXT_OFF_CPSTORED
bbci.l a3, 0, 2f
l32i a3, \SP, CONTEXT_OFF_FCR
wur.FCR a3
l32i a3, \SP, CONTEXT_OFF_FSR
wur.FSR a3
lsi f0, \SP, CONTEXT_OFF_F0
lsi f1, \SP, CONTEXT_OFF_F1
lsi f2, \SP, CONTEXT_OFF_F2
lsi f3, \SP, CONTEXT_OFF_F3
lsi f4, \SP, CONTEXT_OFF_F4
lsi f5, \SP, CONTEXT_OFF_F5
lsi f6, \SP, CONTEXT_OFF_F6
lsi f7, \SP, CONTEXT_OFF_F7
lsi f8, \SP, CONTEXT_OFF_F8
lsi f9, \SP, CONTEXT_OFF_F9
lsi f10, \SP, CONTEXT_OFF_F10
lsi f11, \SP, CONTEXT_OFF_F11
lsi f12, \SP, CONTEXT_OFF_F12
lsi f13, \SP, CONTEXT_OFF_F13
lsi f14, \SP, CONTEXT_OFF_F14
lsi f15, \SP, CONTEXT_OFF_F15
2:
movi a4, 0
s16i a4, \SP, CONTEXT_OFF_CPSTORED
#endif
l32i a3, \SP, CONTEXT_OFF_LBEG
l32i a4, \SP, CONTEXT_OFF_LEND
wsr a3, LBEG
l32i a3, \SP, CONTEXT_OFF_LCOUNT
wsr a4, LEND
wsr a3, LCOUNT
l32i a3, \SP, CONTEXT_OFF_SAR
l32i a1, \SP, CONTEXT_OFF_A1
wsr a3, SAR
l32i a3, \SP, CONTEXT_OFF_A3
l32i a4, \SP, CONTEXT_OFF_A4
l32i a5, \SP, CONTEXT_OFF_A5
l32i a6, \SP, CONTEXT_OFF_A6
l32i a7, \SP, CONTEXT_OFF_A7
l32i a8, \SP, CONTEXT_OFF_A8
l32i a9, \SP, CONTEXT_OFF_A9
l32i a10, \SP, CONTEXT_OFF_A10
l32i a11, \SP, CONTEXT_OFF_A11
l32i a12, \SP, CONTEXT_OFF_A12
l32i a13, \SP, CONTEXT_OFF_A13
l32i a14, \SP, CONTEXT_OFF_A14
l32i a15, \SP, CONTEXT_OFF_A15
l32i a0, \SP, CONTEXT_OFF_PS
wsr a0, \PState
l32i a0, \SP, CONTEXT_OFF_PC
wsr a0, \PC
l32i a0, \SP, CONTEXT_OFF_A0
l32i a2, \SP, CONTEXT_OFF_A2
.endm
.macro PUSH_ALL_REG SP
s32i a0, \SP, CONTEXT_OFF_A0
s32i a1, \SP, CONTEXT_OFF_A1
s32i a2, \SP, CONTEXT_OFF_A2
s32i a3, \SP, CONTEXT_OFF_A3
s32i a4, \SP, CONTEXT_OFF_A4
s32i a5, \SP, CONTEXT_OFF_A5
s32i a6, \SP, CONTEXT_OFF_A6
s32i a7, \SP, CONTEXT_OFF_A7
s32i a8, \SP, CONTEXT_OFF_A8
s32i a9, \SP, CONTEXT_OFF_A9
s32i a10, \SP, CONTEXT_OFF_A10
s32i a11, \SP, CONTEXT_OFF_A11
s32i a12, \SP, CONTEXT_OFF_A12
s32i a13, \SP, CONTEXT_OFF_A13
s32i a14, \SP, CONTEXT_OFF_A14
s32i a15, \SP, CONTEXT_OFF_A15
rsr a3, SAR
s32i a3, \SP, CONTEXT_OFF_SAR
rsr a3, LBEG
s32i a3, \SP, CONTEXT_OFF_LBEG
rsr a3, LEND
s32i a3, \SP, CONTEXT_OFF_LEND
rsr a3, LCOUNT
s32i a3, \SP, CONTEXT_OFF_LCOUNT
rsr a3, PS
s32i a3, \SP, CONTEXT_OFF_PS
#if (defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))
rsr a3, CPENABLE
beqz a3, 1f
s16i a3, \SP, CONTEXT_OFF_CPSTORED
s16i a3, \SP, CONTEXT_OFF_CPENABLE
bbci.l a3, 0, 1f
rur.FCR a3
s32i a3, \SP, CONTEXT_OFF_FCR
rur.FSR a3
s32i a3, \SP, CONTEXT_OFF_FSR
ssi f0, \SP, CONTEXT_OFF_F0
ssi f1, \SP, CONTEXT_OFF_F1
ssi f2, \SP, CONTEXT_OFF_F2
ssi f3, \SP, CONTEXT_OFF_F3
ssi f4, \SP, CONTEXT_OFF_F4
ssi f5, \SP, CONTEXT_OFF_F5
ssi f6, \SP, CONTEXT_OFF_F6
ssi f7, \SP, CONTEXT_OFF_F7
ssi f8, \SP, CONTEXT_OFF_F8
ssi f9, \SP, CONTEXT_OFF_F9
ssi f10, \SP, CONTEXT_OFF_F10
ssi f11, \SP, CONTEXT_OFF_F11
ssi f12, \SP, CONTEXT_OFF_F12
ssi f13, \SP, CONTEXT_OFF_F13
ssi f14, \SP, CONTEXT_OFF_F14
ssi f15, \SP, CONTEXT_OFF_F15
1:
#endif
.endm
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_MACRO_H */

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@@ -1,172 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @defgroup Special Register Fields and Values
* @ingroup kernel
*/
#ifndef _ARCH_REGS_H
#define _ARCH_REGS_H
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
/* PS register -- imprecise exception */
#define SPREG_PS_DEPC_SHIFT 4
#define SPREG_PS_DEPC_MASK 0x00000004
#define SPREG_PS_DEPC SPREG_PS_DEPC_MASK
/* PS register -- interrupt part */
#define SPREG_PS_DI_SHIFT 3
#define SPREG_PS_DI_MASK 0x0000000F
#define SPREG_PS_DI SPREG_PS_DI_MASK
#define SPREG_PS_DI_DEPC 0x0000000C
/* PS register -- stack part */
#define SPREG_PS_STACK_SHIFT 5
#define SPREG_PS_STACK_MASK 0x000000E0
#define SPREG_PS_STACK_INTERRUPT 0x00000000
#define SPREG_PS_STACK_CROSS 0x00000020
#define SPREG_PS_STACK_IDLE 0x00000040
#define SPREG_PS_STACK_KERNEL 0x00000060
#define SPREG_PS_STACK_PAGE 0x000000E0
#define SPREG_PS_STACK_FIRSTINT 0x00000080
#define SPREG_PS_STACK_FIRSTKER 0x000000A0
/* PS register -- entry no rotate */
#define SPREG_PS_ENTRYNR_SHIFT 22
#define SPREG_PS_ENTRYNR_MASK 0x00400000
#define SPREG_PS_ENTRYNR SPREG_PS_ENTRYNR_MASK
/* Exccause Register -- cause */
#define SPREG_EXCCAUSE_CAUSE_SHIFT 0
#define SPREG_EXCCAUSE_CAUSE_BITS 4
#define SPREG_EXCCAUSE_CAUSE_MASK 0x0000000F
/**
* @ingroup Execute level of core
*/
#define EXEC_LEVEL_APPLICATION_CODE 2
#define EXEC_LEVEL_EXCEPTION_HANDLER 3
#define EXEC_LEVEL_INTERRUPT_HANDLER 4
#define EXEC_LEVEL_NON_INTERRUPTIBLE 5
/**
* @ingroup Schedule Flag stored on Task Context
*/
#define OS_SCHED_FLAG_TASKPREEMT 4 /* Task Preemted through LOS_Schedule */
/**
* @ingroup Context Fields Define
*/
#define CONTEXT_OFF_EPC 0
#define CONTEXT_OFF_PC 0 /* reuse with EPC */
#define CONTEXT_OFF_PS 4
#define CONTEXT_OFF_A0 8
#define CONTEXT_OFF_A1 12
#define CONTEXT_OFF_A2 16
#define CONTEXT_OFF_A3 20
#define CONTEXT_OFF_A4 24
#define CONTEXT_OFF_A5 28
#define CONTEXT_OFF_A6 32
#define CONTEXT_OFF_A7 36
#define CONTEXT_OFF_A8 40
#define CONTEXT_OFF_A9 44
#define CONTEXT_OFF_A10 48
#define CONTEXT_OFF_A11 52
#define CONTEXT_OFF_A12 56
#define CONTEXT_OFF_A13 60
#define CONTEXT_OFF_A14 64
#define CONTEXT_OFF_A15 68
#define CONTEXT_OFF_RESERVED 72
#define CONTEXT_OFF_SAR 72
#define CONTEXT_OFF_SCHED_FLAG 76 /* reuse with exccause */
#define CONTEXT_OFF_EXCCAUSE 76
#define CONTEXT_OFF_EXCVADDR 80
#define CONTEXT_OFF_LBEG 84
#define CONTEXT_OFF_LEND 88
#define CONTEXT_OFF_LCOUNT 92
#if (defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))
#define CONTEXT_OFF_TMP0 96
#define CONTEXT_OFF_CPENABLE 100
#define CONTEXT_OFF_CPSTORED 102
#define CONTEXT_OFF_FCR 104
#define CONTEXT_OFF_FSR 108
#define CONTEXT_OFF_F0 112
#define CONTEXT_OFF_F1 116
#define CONTEXT_OFF_F2 120
#define CONTEXT_OFF_F3 124
#define CONTEXT_OFF_F4 128
#define CONTEXT_OFF_F5 132
#define CONTEXT_OFF_F6 136
#define CONTEXT_OFF_F7 140
#define CONTEXT_OFF_F8 144
#define CONTEXT_OFF_F9 148
#define CONTEXT_OFF_F10 152
#define CONTEXT_OFF_F11 156
#define CONTEXT_OFF_F12 160
#define CONTEXT_OFF_F13 164
#define CONTEXT_OFF_F14 168
#define CONTEXT_OFF_F15 172
#define CONTEXT_SIZE 192
#else
#define CONTEXT_SIZE 112
#endif
#define EXCCAUSE_LEVEL1INTERRUPT 4
#define XTENSA_LOGREG_NUM 16
#define INDEX_OF_SP 1
#define INDEX_OF_ARGS0 6
#define WINDOWSTARTBITS 16
#define WINDOWBASEBITS 4
#define WINDOWSTARTMASK ((1 << WINDOWSTARTBITS) - 1)
#define WOE_ENABLE 0x40000
#define BIT_CALLINC 16
#define LEVEL_MASK 0xf
#define INT_MASK 5
#define LEVEL1_INT_MASK 1
#define USER_VECTOR_MODE 0x20
#define LEVEL1 1
#define LEVEL2 2
#define LEVEL3 3
#define LEVEL4 4
#define LEVEL5 5
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _ARCH_REGS_H */

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@@ -1,96 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_ARCH_TIMER_H
#define _LOS_ARCH_TIMER_H
#include "los_config.h"
#include "los_compiler.h"
#include "los_timer.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
VOID SysTick_Handler(VOID);
#define TIM0_GROUP0 0x3FF5F000
#define TIM0_GROUP1 0x3FF60000
#define TIM1_GROUP0 0x3FF5F024
#define TIM1_GROUP1 0x3FF60024
#define TIM0_INT_ENABLE_GROUP0 0x3FF5F098
#define TIM0_INT_ENABLE_GROUP1 0x3FF60098
#define TIM0_INT_CLEAR_GROUP0 0x3FF5F0A4
#define TIM0_INT_CLEAR_GROUP1 0x3FF600A4
typedef struct {
UINT32 CTRL;
UINT64 VAL;
UINT32 UPDATE;
UINT64 ALARM;
UINT64 LOAD;
UINT32 LOAD_TRI;
} Systick_t;
STATIC INLINE UINT32 GetCcount(VOID)
{
UINT32 intSave;
__asm__ __volatile__("rsr %0, ccount" : "=a"(intSave) :);
return intSave;
}
STATIC INLINE VOID ResetCcount(VOID)
{
__asm__ __volatile__("wsr %0, ccount; rsync" : :"a"(0));
}
STATIC INLINE UINT32 GetCcompare(VOID)
{
UINT32 intSave;
__asm__ __volatile__("rsr %0, ccompare0" : "=a"(intSave) :);
return intSave;
}
STATIC INLINE VOID SetCcompare(UINT32 newCompareVal)
{
__asm__ __volatile__("wsr %0, ccompare0; rsync" : : "a"(newCompareVal));
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_ARCH_TIMER_H */

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@@ -1,177 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_context.h"
#include "securec.h"
#include "los_arch_regs.h"
#include "los_arch_context.h"
#include "los_arch_interrupt.h"
#include "los_task.h"
#include "los_sched.h"
#include "los_interrupt.h"
#include "los_arch_timer.h"
#include "los_timer.h"
#include "los_debug.h"
STATIC UINT32 g_sysNeedSched = FALSE;
UINT32 g_stackDefault[] = {
0x00000000, /* REG_OFF_PC */
0x00000000, /* REG_OFF_PS */
0x00000A00, /* REG_OFF_AR00 */
0x00000A01, /* REG_OFF_AR01 */
0x00000A02, /* REG_OFF_AR02 */
0x00000A03, /* REG_OFF_AR03 */
0x00000A04, /* REG_OFF_AR04 */
0x00000A05, /* REG_OFF_AR05 */
0x00000A06, /* REG_OFF_AR06 */
0x00000A07, /* REG_OFF_AR07 */
0x00000A08, /* REG_OFF_AR08 */
0x00000A09, /* REG_OFF_AR09 */
0x00000A10, /* REG_OFF_AR10 */
0x00000A11, /* REG_OFF_AR11 */
0x00000A12, /* REG_OFF_AR12 */
0x00000A13, /* REG_OFF_AR13 */
0x00000A14, /* REG_OFF_AR14 */
0x00000A15, /* REG_OFF_AR15 */
0x00000000, /* REG_OFF_RESERVED */
0x00000000, /* REG_OFF_EXCCAUSE */
0x00000000, /* REG_OFF_EXCVASSR */
0x00000000, /* REG_OFF_LCOUNT */
0x00000000, /* REG_OFF_LEND */
0x00000000, /* REG_OFF_LBEG */
#if (defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U))
0x00000000, /* REG_OFF_TMP0 */
0x00000001, /* REG_OFF_CPENABLE | CONTEXT_OFF_CPSTORED */
0x00000000, /* REG_OFF_FCR */
0x00000000, /* REG_OFF_FSR */
0x00000000, /* REG_OFF_F0 */
0x00000000, /* REG_OFF_F1 */
0x00000000, /* REG_OFF_F2 */
0x00000000, /* REG_OFF_F3 */
0x00000000, /* REG_OFF_F4 */
0x00000000, /* REG_OFF_F5 */
0x00000000, /* REG_OFF_F6 */
0x00000000, /* REG_OFF_F7 */
0x00000000, /* REG_OFF_F8 */
0x00000000, /* REG_OFF_F9 */
0x00000000, /* REG_OFF_F10 */
0x00000000, /* REG_OFF_F11 */
0x00000000, /* REG_OFF_F12 */
0x00000000, /* REG_OFF_F13 */
0x00000000, /* REG_OFF_F14 */
0x00000000, /* REG_OFF_F15 */
#endif
0x00000000, /* REG_OFF_SPILL_RESERVED */
0x00000000, /* REG_OFF_SPILL_RESERVED */
0x00000000, /* REG_OFF_SPILL_RESERVED */
0x00000000, /* REG_OFF_SPILL_RESERVED */
};
LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
{
HalHwiInit();
}
LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
{
LOS_IntLock();
while (1) {
}
}
LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
{
TaskContext *context = NULL;
errno_t result;
/* initialize the task stack, write magic num to stack top */
result = memset_s(topStack, stackSize, (INT32)(OS_TASK_STACK_INIT & 0xFF), stackSize);
if (result != EOK) {
printf("memset_s is failed:%s[%d]\r\n", __FUNCTION__, __LINE__);
}
*((UINT32 *)(topStack)) = OS_TASK_MAGIC_WORD;
context = (TaskContext *)((((UINTPTR)topStack + stackSize) - sizeof(TaskContext)));
/* initialize the task context */
result = memcpy_s(context, sizeof(TaskContext), g_stackDefault, sizeof(TaskContext));
if (result != EOK) {
PRINT_ERR("[%s] memcpy_s failed!\n", __func__);
}
context->pc = (UINT32)(UINTPTR)OsTaskEntry;
context->regA[INDEX_OF_SP] = (UINTPTR)topStack + stackSize; /* endStack */
context->regA[INDEX_OF_ARGS0] = taskID; /* argument1 */
context->ps = SPREG_PS_STACK_CROSS | WOE_ENABLE | 1 << BIT_CALLINC; /* set to kernel stack */
return (VOID *)context;
}
VOID HalStartToRun(VOID)
{
__asm__ volatile ("call0 OsStartToRun");
}
LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
{
(VOID)LOS_IntLock();
OsSchedStart();
HalStartToRun();
return LOS_OK;
}
VOID ArchTaskSchedule(VOID)
{
UINT32 intSave;
if (OS_INT_ACTIVE) {
g_sysNeedSched = TRUE;
return;
}
intSave = LOS_IntLock();
g_sysNeedSched = FALSE;
BOOL isSwitch = OsSchedTaskSwitch();
if (isSwitch) {
HalTaskContextSwitch();
}
LOS_IntRestore(intSave);
return;
}
VOID HalIrqEndCheckNeedSched(VOID)
{
if (g_sysNeedSched && g_taskScheduled && LOS_CHECK_SCHEDULE) {
ArchTaskSchedule();
}
}

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@@ -1,128 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_arch_regs.h"
#include "los_arch_macro.h"
.section .text
.literal_position
.align 4
.type HalTaskContextSwitch, %function
.global HalTaskContextSwitch
HalTaskContextSwitch:
entry sp, 16
addi a2, sp, -CONTEXT_SIZE
PUSH_ALL_REG a2
call0 SaveRetAddr
beqi a3, 1, .switchdone
movi a4, g_losTask
l32i a5, a4, 0 /* get run task */
s32i a2, a5, 0 /* store sp */
l32i a5, a4, 4 /* get new task */
s32i a5, a4, 0 /* run task = new task */
l32i a4, a5, 0 /* get new sp */
rsr a5, PS
movi a3, ~(WOE_ENABLE | LEVEL_MASK)
and a2, a5, a3
addi a2, a2, 3
wsr a2, PS
rsync
call0 SpillWindow
mov a2, a4
POP_ALL_REG a2 EPC5 EPS5
rfi 5
.switchdone:
retw
.type HakSpillWindow, %function
.global HakSpillWindow
HakSpillWindow:
entry sp, 32
addi a2, sp, -CONTEXT_SIZE
PUSH_ALL_REG a2
rsr a5, PS
movi a3, ~(WOE_ENABLE | LEVEL_MASK) /* disable woe and int */
and a3, a5, a3
addi a3, a3, LEVEL3
wsr a3, PS
rsync
mov a4, a2
call0 SpillWindow
l32i a5, a4, CONTEXT_OFF_PS /* restroe PS */
wsr a5, PS
rsync
l32i a0, a4, CONTEXT_OFF_A0
l32i a1, a4, CONTEXT_OFF_A1
retw
.type OsStartToRun, %function
.global OsStartToRun
OsStartToRun:
movi a2, g_losTask
l32i a3, a2, 4 /* get new task */
l32i sp, a3, 0 /* get sp */
rsr a4, PS
movi a3, ~(WOE_ENABLE | LEVEL_MASK)
and a2, a4, a3
addi a2, a2, LEVEL3
wsr a2, PS
rsync
mov a5, a1
l32i a1, a1, CONTEXT_OFF_A1
call0 SpillWindow
mov a2, a5
POP_ALL_REG a2 EPC5 EPS5
rfi 5
.global SaveRetAddr
.type SaveRetAddr, @function
.literal_position
.align 4
SaveRetAddr:
movi a3, 1
s32i a3, a2, CONTEXT_OFF_A3
s32i a0, a2, CONTEXT_OFF_PC /* save pc */
movi a3, 0
ret

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@@ -1,370 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_arch_regs.h"
#include "los_arch_macro.h"
.extern HalInterrupt
.extern UserException
.section .iram,"ax"
.literal_position
.type HandleEntry,@function
.align 4
HandleEntry:
mov a0, sp
addi sp, sp, -CONTEXT_SIZE
PUSH_ALL_REG a1
s32i a0, sp, CONTEXT_OFF_A1
rsr a0, EPC1
s32i a0, sp, CONTEXT_OFF_PC
rsr a0, EXCSAVE1
s32i a0, sp, CONTEXT_OFF_A0
wsr a1, EXCSAVE1
l32i a1, a1, CONTEXT_OFF_A1
call0 SpillWindow
rsr a1, EXCSAVE1
rsr a0, EXCCAUSE
s32i a0, sp, CONTEXT_OFF_EXCCAUSE
rsr a0, EXCVADDR
s32i a0, sp, CONTEXT_OFF_EXCVADDR
movi a0, INT_MASK | USER_VECTOR_MODE | WOE_ENABLE
wsr a0, PS
rsr a6, EPC1
mov a7, sp
rsr a8, EXCCAUSE
call4 HalExcHandleEntry
1:
j 1b
.begin literal_prefix .DebugExceptionHandler
.section .DebugExceptionHandler.text, "ax"
.global DebugExceptionHandler
.align 4
.literal_position
DebugExceptionHandler:
call0 UserException
.end literal_prefix
.begin literal_prefix .NMIExceptionHandler
.section .NMIExceptionHandler.text, "ax"
.global NMIExceptionHandler
.align 4
.literal_position
NMIExceptionHandler:
call0 UserException
.end literal_prefix
.begin literal_prefix .DoubleExceptionHandler
.section .DoubleExceptionHandler.text, "ax"
.global DoubleExceptionHandler
.align 4
.literal_position
DoubleExceptionHandler:
movi a0, INT_MASK | USER_VECTOR_MODE | WOE_ENABLE
wsr a0, PS
rsr a2, EXCCAUSE
call0 UserException
.end literal_prefix
.begin literal_prefix .KernelExceptionHandler
.section .KernelExceptionHandler.text, "ax"
.global KernelExceptionHandler
.align 4
.literal_position
KernelExceptionHandler:
wsr a0, EXCSAVE1
call0 KernelException
.end literal_prefix
.section .iram,"ax"
.align 4
KernelException:
movi a0,5
wsr a0,EXCCAUSE
call0 UserException
rfe
.begin literal_prefix .UserExceptionHandler
.section .UserExceptionHandler.text, "ax"
.global UserExceptionHandler
.type UserExceptionHandler,@function
.align 4
.literal_position
UserExceptionHandler:
wsr a0, EXCSAVE1
call0 UserException
.end literal_prefix
.section .iram,"ax"
.type UserException,@function
.align 4
UserException:
rsr a0, EXCCAUSE
beqi a0, 4, InterruptEntry1
call0 HandleEntry
1:
j 1b
.section .iram,"ax"
.type InterruptEntry1,@function
.align 4
InterruptEntry1:
mov a0, sp
addi sp, sp, -CONTEXT_SIZE
PUSH_ALL_REG a1
s32i a0, sp, CONTEXT_OFF_A1
rsr a0, EPC1
s32i a0, sp, CONTEXT_OFF_PC
rsr a0, EXCSAVE1
s32i a0, sp, CONTEXT_OFF_A0
wsr a1, EXCSAVE1
l32i a1, a1, CONTEXT_OFF_A1
call0 SpillWindow
rsr a1, EXCSAVE1
movi a0, LEVEL1_INT_MASK | USER_VECTOR_MODE | WOE_ENABLE
wsr a0, PS
rsync
call4 HalInterrupt
mov a2, a1
POP_ALL_REG a2 EPC1 PS
rfe
.begin literal_prefix .InterruptEntry2
.section .InterruptEntry2.text, "ax"
.global InterruptEntry2
.type InterruptEntry2,@function
.align 4
.literal_position
InterruptEntry2:
wsr a0, EXCSAVE2
movi a4, LEVEL2
call0 HandleEntry
.end literal_prefix
.begin literal_prefix .InterruptEntry3
.section .InterruptEntry3.text, "ax"
.global InterruptEntry3
.type InterruptEntry3,@function
.align 4
.literal_position
InterruptEntry3:
wsr a0, EXCSAVE3
movi a4, LEVEL3
call0 HandleEntry
.end literal_prefix
.begin literal_prefix .InterruptEntry4
.section .InterruptEntry4.text, "ax"
.global InterruptEntry4
.type InterruptEntry4,@function
.align 4
.literal_position
InterruptEntry4:
wsr a0, EXCSAVE4
movi a4, LEVEL4
call0 HandleEntry
.end literal_prefix
.begin literal_prefix .InterruptEntry5
.section .InterruptEntry5.text, "ax"
.global InterruptEntry5
.type InterruptEntry5,@function
.align 4
.literal_position
InterruptEntry5:
wsr a0, EXCSAVE5
movi a4, LEVEL5
call0 HandleEntry
.end literal_prefix
.section .WindowVectors.text, "ax"
.org 0x0
.global OverFlowGroup1
OverFlowGroup1:
addi a5, a5, -16
s32i a3, a5, 12
s32i a2, a5, 8
s32i a1, a5, 4
s32i a0, a5, 0
addi a5, a5, 16
rfwo
.org 0x40
.global UnderFlowGroup1
UnderFlowGroup1:
addi a5, a5, -16
l32i a3, a5, 12
l32i a2, a5, 8
l32i a1, a5, 4
l32i a0, a5, 0
addi a5, a5, 16
rfwu
.org 0x80
.global OverFlowGroup2
OverFlowGroup2:
addi a9, a9, -16
s32i a3, a9, 12
s32i a2, a9, 8
s32i a1, a9, 4
s32i a0, a9, 0
addi a9, a9, 16
addi a1, a1, -12
l32i a0, a1, 0
addi a1, a1, 12
addi a0, a0, -32
s32i a7, a0, 12
s32i a6, a0, 8
s32i a5, a0, 4
s32i a4, a0, 0
rfwo
.org 0xC0
.global UnderFlowGroup2
UnderFlowGroup2:
addi a9, a9, -16
l32i a3, a9, 12
l32i a2, a9, 8
l32i a1, a9, 4
l32i a0, a9, 0
addi a9, a9, 16
addi a1, a1, -12
l32i a4, a1, 0
addi a1, a1, 12
addi a4, a4, -32
l32i a7, a4, 12
l32i a6, a4, 8
l32i a5, a4, 4
l32i a4, a4, 0
rfwu
.org 0x100
.global OverFlowGroup3
OverFlowGroup3:
addi a13, a13, -16
s32i a3, a13, 12
s32i a2, a13, 8
s32i a1, a13, 4
s32i a0, a13, 0
addi a13, a13, 16
addi a1, a1, -12
l32i a0, a1, 0
addi a1, a1, 12
addi a0, a0, -48
s32i a11, a0, 28
s32i a10, a0, 24
s32i a9, a0, 20
s32i a8, a0, 16
s32i a7, a0, 12
s32i a6, a0, 8
s32i a5, a0, 4
s32i a4, a0, 0
rfwo
.org 0x140
.global UnderFlowGroup3
UnderFlowGroup3:
addi a13, a13, -16
l32i a3, a13, 12
l32i a2, a13, 8
l32i a1, a13, 4
l32i a0, a13, 0
addi a13, a13, 16
addi a1, a1, -12
l32i a4, a1, 0
addi a1, a1, 12
addi a4, a4, -48
l32i a11, a0, 28
l32i a10, a0, 24
l32i a9, a0, 20
l32i a8, a0, 16
l32i a7, a4, 12
l32i a6, a4, 8
l32i a5, a4, 4
l32i a4, a4, 0
rfwu
.global EnableExceptionInterface
.section .iram,"ax"
.type EnableExceptionInterface,@function
.align 4
EnableExceptionInterface:
entry a1,16
retw

View File

@@ -1,554 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_interrupt.h"
#include <stdarg.h>
#include "securec.h"
#include "los_context.h"
#include "los_arch_interrupt.h"
#include "los_debug.h"
#include "los_hook.h"
#include "los_task.h"
#include "los_sched.h"
#include "los_memory.h"
#include "los_membox.h"
#include "los_arch_regs.h"
UINT32 g_intCount = 0;
/* *
* @ingroup los_hwi
* Hardware interrupt form mapping handling function array.
*/
STATIC HWI_PROC_FUNC __attribute__((aligned(LOSCFG_ARCH_HWI_VECTOR_ALIGN))) g_hwiForm[OS_VECTOR_CNT] = {0};
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
typedef struct {
HWI_PROC_FUNC pfnHandler;
VOID *pParm;
} HWI_HANDLER_FUNC;
/* *
* @ingroup los_hwi
* Hardware interrupt handler form mapping handling function array.
*/
STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
/* *
* @ingroup los_hwi
* Set interrupt vector table.
*/
VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg)
{
if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalInterrupt;
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector;
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg;
}
}
#else
/* *
* @ingroup los_hwi
* Hardware interrupt handler form mapping handling function array.
*/
STATIC HWI_PROC_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {0};
/* *
* @ingroup los_hwi
* Set interrupt vector table.
*/
VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
{
if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
g_hwiForm[num + OS_SYS_VECTOR_CNT] = HalInterrupt;
g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector;
}
}
#endif
UINT32 HwiNumValid(UINT32 num)
{
return (num >= OS_SYS_VECTOR_CNT) && (num <= OS_VECTOR_CNT);
}
/* *
* @ingroup los_hwi
* Lock all interrupt.
*/
UINT32 ArchIntLock(VOID)
{
UINT32 ret;
__asm__ volatile("rsil %0, %1" : "=r"(ret) : "i"(INT_MASK) : "memory");
return ret;
}
/* *
* @ingroup los_hwi
* Restore interrupt status.
*/
VOID ArchIntRestore(UINT32 intSave)
{
__asm__ volatile("wsr.ps %0; rsync" : : "r"(intSave) : "memory");
}
/* *
* @ingroup los_hwi
* Unlock interrupt.
*/
UINT32 ArchIntUnLock(VOID)
{
UINT32 intSave;
__asm__ volatile("rsil %0, %1" : "=r"(intSave) : "i"(0) : "memory");
return intSave;
}
/* *
* @ingroup los_hwi
* Determine if the interrupt is locked
*/
STATIC INLINE UINT32 ArchIntLocked(VOID)
{
UINT32 intSave;
__asm__ volatile("rsr %0, ps " : "=r"(intSave) : : "memory");
return (intSave & SPREG_PS_DI_MASK);
}
/* *
* @ingroup los_hwi
* Trigger the interrupt
*/
UINT32 HalIrqPending(HWI_HANDLE_T hwiNum)
{
if (!HwiNumValid(hwiNum)) {
return OS_ERRNO_HWI_NUM_INVALID;
}
__asm__ __volatile__("wsr %0, intset; rsync" : : "a"(0x1U << hwiNum));
return LOS_OK;
}
/* *
* @ingroup los_hwi
* Unmask the interrupt
*/
UINT32 HalIrqUnmask(HWI_HANDLE_T hwiNum)
{
UINT32 ier;
if (!HwiNumValid(hwiNum)) {
return OS_ERRNO_HWI_NUM_INVALID;
}
__asm__ __volatile__("rsr %0, intenable" : "=a"(ier) : : "memory");
__asm__ __volatile__("wsr %0, intenable; rsync" : : "a"(ier | ((UINT32)0x1U << hwiNum)));
return LOS_OK;
}
/* *
* @ingroup los_hwi
* Mask the interrupt
*/
UINT32 HalIrqMask(HWI_HANDLE_T hwiNum)
{
UINT32 ier;
if (!HwiNumValid(hwiNum)) {
return OS_ERRNO_HWI_NUM_INVALID;
}
__asm__ __volatile__("rsr %0, intenable" : "=a"(ier) : : "memory");
__asm__ __volatile__("wsr %0, intenable; rsync" : : "a"(ier & ~((UINT32)0x1U << hwiNum)));
return LOS_OK;
}
/* ****************************************************************************
Function : HalIntNumGet
Description : Get an interrupt number
Input : None
Output : None
Return : Interrupt Indexes number
**************************************************************************** */
UINT32 HalIntNumGet(VOID)
{
UINT32 ier;
UINT32 intenable;
UINT32 intSave;
__asm__ __volatile__("rsr %0, interrupt" : "=a"(ier) : : "memory");
__asm__ __volatile__("rsr %0, intenable" : "=a"(intenable) : : "memory");
intSave = ier & intenable;
return __builtin_ffs(intSave) - 1;
}
/* *
* @ingroup los_hwi
* Clear the interrupt
*/
UINT32 HalIrqClear(HWI_HANDLE_T vector)
{
if (!HwiNumValid(vector)) {
return OS_ERRNO_HWI_NUM_INVALID;
}
__asm__ __volatile__("wsr %0, intclear; rsync" : : "a"(0x1U << vector));
return LOS_OK;
}
INLINE UINT32 ArchIsIntActive(VOID)
{
return (g_intCount > 0);
}
/* ****************************************************************************
Function : HalHwiDefaultHandler
Description : default handler of the hardware interrupt
Input : None
Output : None
Return : None
**************************************************************************** */
VOID HalHwiDefaultHandler(VOID)
{
UINT32 irqNum = HalIntNumGet();
PRINT_ERR("%s irqnum:%d\n", __FUNCTION__, irqNum);
while (1) {}
}
WEAK VOID HalPreInterruptHandler(UINT32 arg)
{
return;
}
WEAK VOID HalAftInterruptHandler(UINT32 arg)
{
return;
}
/* ****************************************************************************
Function : HalInterrupt
Description : Hardware interrupt entry function
Input : None
Output : None
Return : None
**************************************************************************** */
VOID HalInterrupt(VOID)
{
UINT32 hwiIndex;
UINT32 intSave;
intSave = LOS_IntLock();
g_intCount++;
LOS_IntRestore(intSave);
hwiIndex = HalIntNumGet();
HalIrqClear(hwiIndex);
OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
HalPreInterruptHandler(hwiIndex);
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
}
#else
if (g_hwiHandlerForm[hwiIndex] != 0) {
g_hwiHandlerForm[hwiIndex]();
}
#endif
HalAftInterruptHandler(hwiIndex);
OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
intSave = LOS_IntLock();
g_intCount--;
LOS_IntRestore(intSave);
HalIrqEndCheckNeedSched();
}
/* ****************************************************************************
Function : ArchHwiCreate
Description : create hardware interrupt
Input : hwiNum --- hwi num to create
hwiPrio --- priority of the hwi
mode --- unused
handler --- hwi handler
arg --- param of the hwi handler
Output : None
Return : LOS_OK on success or error code on failure
**************************************************************************** */
UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
HWI_PRIOR_T hwiPrio,
HWI_MODE_T mode,
HWI_PROC_FUNC handler,
HWI_ARG_T arg)
{
UINT32 intSave;
if (handler == NULL) {
return OS_ERRNO_HWI_PROC_FUNC_NULL;
}
if (hwiNum >= OS_HWI_MAX_NUM) {
return OS_ERRNO_HWI_NUM_INVALID;
}
if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
return OS_ERRNO_HWI_ALREADY_CREATED;
}
if (hwiPrio > OS_HWI_PRIO_LOWEST) {
return OS_ERRNO_HWI_PRIO_INVALID;
}
intSave = LOS_IntLock();
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
OsSetVector(hwiNum, handler, arg);
#else
OsSetVector(hwiNum, handler);
#endif
HalIrqUnmask(hwiNum);
LOS_IntRestore(intSave);
return LOS_OK;
}
/* ****************************************************************************
Function : ArchHwiDelete
Description : Delete hardware interrupt
Input : hwiNum --- hwi num to delete
Output : None
Return : LOS_OK on success or error code on failure
**************************************************************************** */
LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum)
{
UINT32 intSave;
if (hwiNum >= OS_HWI_MAX_NUM) {
return OS_ERRNO_HWI_NUM_INVALID;
}
HalIrqMask(hwiNum);
intSave = LOS_IntLock();
g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
LOS_IntRestore(intSave);
return LOS_OK;
}
ExcInfo g_excInfo = {0};
#if (LOSCFG_KERNEL_PRINTF != 0)
STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
{
CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
PRINTK("Type = %d\n", excInfo->type);
PRINTK("ThrdPid = %d\n", excInfo->thrdPid);
PRINTK("Phase = %s\n", phaseStr[excInfo->phase]);
PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
}
STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
{
PRINTK("Current task info:\n");
if (excInfo->phase == OS_EXC_IN_TASK) {
LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
PRINTK("Task name = %s\n", taskCB->taskName);
PRINTK("Task ID = %d\n", taskCB->taskID);
PRINTK("Task SP = 0x%x\n", (UINTPTR)taskCB->stackPointer);
PRINTK("Task ST = 0x%x\n", taskCB->topOfStack);
PRINTK("Task SS = 0x%x\n", taskCB->stackSize);
} else if (excInfo->phase == OS_EXC_IN_HWI) {
PRINTK("Exception occur in interrupt phase!\n");
} else {
PRINTK("Exception occur in system init phase!\n");
}
}
STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
{
INT32 index;
PRINTK("Exception reg dump:\n");
PRINTK("sar = 0x%x\n", excInfo->context->sar);
PRINTK("excCause = 0x%x\n", excInfo->context->excCause);
PRINTK("excVaddr = 0x%x\n", excInfo->context->excVaddr);
PRINTK("lbeg = 0x%x\n", excInfo->context->lbeg);
PRINTK("lend = 0x%x\n", excInfo->context->lend);
PRINTK("lcount = 0x%x\n", excInfo->context->lcount);
PRINTK("pc = 0x%x\n", excInfo->context->pc);
PRINTK("ps = 0x%x\n", excInfo->context->ps);
for (index = 0; index < XTENSA_LOGREG_NUM; index++) {
PRINTK("regA%d = 0x%x\n", index, excInfo->context->regA[index]);
}
}
STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
{
UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
UINT32 index;
OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->regA[1]);
PRINTK("----- backtrace start -----\n");
for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
if (LR[index] == 0) {
break;
}
PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]);
}
PRINTK("----- backtrace end -----\n");
}
STATIC VOID OsExcMemPoolCheckInfo(VOID)
{
PRINTK("\r\nmemory pools check:\n");
#if (LOSCFG_PLATFORM_EXC == 1)
MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
UINT32 errCnt;
UINT32 i;
(VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
if (errCnt < OS_SYS_MEM_NUM) {
errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
}
if (errCnt == 0) {
PRINTK("all memory pool check passed!\n");
return;
}
for (i = 0; i < errCnt; i++) {
PRINTK("pool num = %d\n", i);
PRINTK("pool type = %d\n", memExcInfo[i].type);
PRINTK("pool addr = 0x%x\n", memExcInfo[i].startAddr);
PRINTK("pool size = 0x%x\n", memExcInfo[i].size);
PRINTK("pool free = 0x%x\n", memExcInfo[i].free);
PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize);
PRINTK("pool error node addr = 0x%x\n", memExcInfo[i].errorAddr);
PRINTK("pool error node len = 0x%x\n", memExcInfo[i].errorLen);
PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner);
}
#endif
UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
if (ret == LOS_OK) {
PRINTK("system heap memcheck over, all passed!\n");
}
PRINTK("memory pool check end!\n");
}
#endif
STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
{
#if (LOSCFG_KERNEL_PRINTF != 0)
PRINTK("*************Exception Information**************\n");
OsExcTypeInfo(excInfo);
OsExcCurTaskInfo(excInfo);
OsExcRegInfo(excInfo);
OsExcBackTraceInfo(excInfo);
OsGetAllTskInfo();
OsExcMemPoolCheckInfo();
#endif
}
VOID HalExcHandleEntry(UINTPTR faultAddr, EXC_CONTEXT_S *excBufAddr, UINT32 type)
{
g_excInfo.nestCnt++;
g_excInfo.faultAddr = faultAddr;
g_excInfo.type = type;
LosTaskCB *taskCB = g_losTask.runTask;
if ((taskCB == NULL) || (taskCB == OS_TCB_FROM_TID(g_taskMaxNum))) {
g_excInfo.phase = OS_EXC_IN_INIT;
g_excInfo.thrdPid = OS_NULL_INT;
} else if (HalIntNumGet() != OS_NULL_INT) {
g_excInfo.phase = OS_EXC_IN_HWI;
g_excInfo.thrdPid = HalIntNumGet();
} else {
g_excInfo.phase = OS_EXC_IN_TASK;
g_excInfo.thrdPid = g_losTask.runTask->taskID;
}
g_excInfo.context = excBufAddr;
OsDoExcHook(EXC_INTERRUPT);
OsExcInfoDisplay(&g_excInfo);
ArchSysExit();
}
/* Stack protector */
WEAK UINT32 __stack_chk_guard = 0xd00a0dff;
WEAK VOID __stack_chk_fail(VOID)
{
/* __builtin_return_address is a builtin function, building in gcc */
LOS_Panic("stack-protector: Kernel stack is corrupted in: 0x%x\n",
__builtin_return_address(0));
}
/* ****************************************************************************
Function : HalHwiInit
Description : initialization of the hardware interrupt
Input : None
Output : None
Return : None
**************************************************************************** */
VOID HalHwiInit(VOID)
{
EnableExceptionInterface();
for (UINT32 i = 0; i < OS_HWI_MAX_NUM; i++) {
g_hwiForm[i + OS_SYS_VECTOR_CNT] = HalHwiDefaultHandler;
HalIrqMask(i);
}
asm volatile ("wsr %0, vecbase" : : "r"(INIT_VECTOR_START));
return;
}

View File

@@ -1,141 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_timer.h"
#include "los_config.h"
#include "los_tick.h"
#include "los_arch_interrupt.h"
#include "los_arch_timer.h"
#include "los_debug.h"
STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
STATIC VOID SysTickReload(UINT64 nextResponseTime);
STATIC UINT64 SysTickCycleGet(UINT32 *period);
STATIC VOID SysTickLock(VOID);
STATIC VOID SysTickUnlock(VOID);
STATIC ArchTickTimer g_archTickTimer = {
.freq = 0,
.irqNum = OS_TICK_INT_NUM,
.init = SysTickStart,
.getCycle = SysTickCycleGet,
.reload = SysTickReload,
.lock = SysTickLock,
.unlock = SysTickUnlock,
.tickHandler = NULL,
};
STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
{
ArchTickTimer *tick = &g_archTickTimer;
tick->freq = OS_SYS_CLOCK;
#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
OsSetVector(tick->irqNum, handler, NULL);
#else
OsSetVector(tick->irqNum, handler);
#endif
#endif
ResetCcount();
SetCcompare(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX);
__asm__ __volatile__("wsr %0, ccompare1; rsync" : : "a"(0));
__asm__ __volatile__("wsr %0, ccompare2; rsync" : : "a"(0));
HalIrqUnmask(tick->irqNum);
return LOS_OK;
}
STATIC VOID SysTickReload(UINT64 nextResponseTime)
{
UINT32 timerL;
timerL = GetCcount();
timerL += nextResponseTime;
SetCcompare(timerL);
}
STATIC UINT64 SysTickCycleGet(UINT32 *period)
{
UINT32 tickCycleH;
UINT32 tickCycleL;
UINT32 temp;
static UINT64 tickCycle = 0;
(VOID)period;
UINT32 intSave = LOS_IntLock();
temp = tickCycle & 0xFFFFFFFF;
tickCycleH = tickCycle >> SHIFT_32_BIT;
tickCycleL = GetCcount();
if (tickCycleL < temp) {
tickCycleH++;
}
tickCycle = (((UINT64)tickCycleH) << SHIFT_32_BIT) | tickCycleL;
LOS_IntRestore(intSave);
return tickCycle;
}
STATIC VOID SysTickLock(VOID)
{
HalIrqMask(OS_TICK_INT_NUM);
}
STATIC VOID SysTickUnlock(VOID)
{
HalIrqUnmask(OS_TICK_INT_NUM);
}
ArchTickTimer *ArchSysTickTimerGet(VOID)
{
return &g_archTickTimer;
}
VOID Wfi(VOID)
{
__asm__ volatile("waiti 0" : : : "memory");
}
VOID Dsb(VOID)
{
__asm__ volatile("dsync" : : : "memory");
}
UINT32 ArchEnterSleep(VOID)
{
Dsb();
Wfi();
return LOS_OK;
}

View File

@@ -1,187 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_arch_regs.h"
.text
.align 4
.literal_position
.global SpillWindow
SpillWindow:
rsr a2, WINDOWBASE /* read windowbase reg */
movi a3, WINDOWSTARTBITS
sub a3, a3, a2 /* get the num of high bits */
addi a3, a3, -1
ssl a3 /* set left shift bit */
rsr a3, WINDOWSTART /* read windowstart reg */
sll a3, a3
movi a2, WINDOWSTARTMASK
and a3, a3, a2
beqi a3, 0, .Linvalidwindowstart /* if a3 == 0 goto Linvalidwindowstart */
rsr a2, WINDOWBASE /* read windowbase reg */
addi a2, a2, 1
ssr a2
rsr a2, WINDOWSTART
srl a2, a2
or a2, a2, a3
movi a3, 0
.bitclear0:
bbsi.l a2, 0, .bitcleardone
srli a2, a2, 1
addi a3, a3, 1
j .bitclear0
.bitcleardone:
srli a2, a2, 1 /* drop the first bit */
wsr a2, WINDOWSTART
rsr a2, WINDOWBASE
add a2, a2, a3
wsr a2, WINDOWBASE
rsync
rsr a2, WINDOWSTART
.Lspillstart:
beqi a2, 0, .Ldone
bbsi.l a2, 0, .Lspill4
bbsi.l a2, 1, .Lspill8
bbsi.l a2, 2, .Lspill12
j .Linvalidwindow
.Lspill4:
s32e a4, a9, -16
s32e a5, a9, -12
s32e a6, a9, -8
s32e a7, a9, -4
srli a6, a2, 1
rotw 1
j .Lspillstart
.Lspill8:
s32e a4, a13, -16
s32e a5, a13, -12
s32e a6, a13, -8
s32e a7, a13, -4
l32i a3, a5, -12 /* call[i - 1]'s sp */
addi a3, a3, -16 /* base area */
s32e a8, a3, -16
s32e a9, a3, -12
s32e a10, a3, -8
s32e a11, a3, -4
srli a10, a2, 2
rotw 2
j .Lspillstart
.Lspill12:
rotw 1
s32e a0, a13, -16
s32e a1, a13, -12
s32e a2, a13, -8
s32e a3, a13, -4
l32i a3, a1, -12 /* call[i - 1]'s sp */
addi a3, a3, -16 /* base area */
s32e a4, a3, -32
s32e a5, a3, -28
s32e a6, a3, -24
s32e a7, a3, -20
s32e a8, a3, -16
s32e a9, a3, -12
s32e a10, a3, -8
s32e a11, a3, -4
rotw -1
srli a14, a2, 3
rotw 3
j .Lspillstart
.Ldone:
rotw 1
rsr a2, WINDOWBASE
ssl a2
movi a2, 1
sll a2, a2
wsr a2, WINDOWSTART
rsync
movi a2, 0
ret
.Linvalidwindowstart:
movi a2, 1
ret
.Linvalidwindow:
movi a3, 1
slli a2, a2, 1
or a2, a2, a3
rsr a3, WINDOWBASE
.RestoreWindowBase:
bbsi.l a2, WINDOWSTARTBITS - 1, .RestoreWindow
slli a2, a2, 1
addi a3, a3, -1
j .RestoreWindowBase
.RestoreWindow:
extui a3, a3, 0, WINDOWSTARTBITS /* the original bit */
addi a3, a3, 1
ssl a3
sll a3, a2
slli a2, a2, 32 - WINDOWSTARTBITS
srl a2, a2
or a2, a2, a3
extui a2, a2, 0, WINDOWSTARTBITS
wsr a2, WINDOWSTART
movi a3, 31
rsr a2, SAR
sub a2, a3, a2
wsr a2, WINDOWBASE
rsync
movi a2, 2
ret

View File

@@ -1,61 +1,41 @@
```
.
├── arch --- Code of the kernel instruction architecture layer
│   ├── arm --- ARM32 architecture
│   │   ├── arm9 --- ARM9 architecture
│   │   │ └── gcc --- Implementation of the GCC toolchain
│   │   ├── cortex-m3 --- Cortex-m3 architecture
│   │   │ └── keil --- Implementation of the keil toolchain
│   │   ├── cortex-m33 --- Cortex-m33 architecture
│   │   │ │── gcc --- Implementation of the GCC toolchain
│   │   │ │ │── NTZ --- Cortex-m33 Non-TrustZone architecture
│   │   │ │ └── TZ --- Cortex-m33 TrustZone architecture
│   │   │ └── iar --- Implementation of the IAR toolchain
│   │   │ │── NTZ --- Cortex-m33 Non-TrustZone architecture
│   │   │ └── TZ --- Cortex-m33 TrustZone architecture
│   │   └── cortex-m4 --- Cortex-m4 architecture
│   │   │ │── gcc --- Implementation of the GCC toolchain
│   │   │ └── iar --- Implementation of the IAR toolchain
│   │   └── cortex-m7 --- Cortex-m7 architecture
│   │   │── gcc --- Implementation of the GCC toolchain
│   │   └── iar --- Implementation of the IAR toolchain
│   ├── csky --- csky architecture
│   │ └── v2 --- csky v2 architecture
│   │   └── gcc --- Implementation of the GCC toolchain
│   ├── xtensa --- xtensa architecture
│   │ └── lx6 --- xtensa lx6 architecture
│   │   └── gcc --- Implementation of the GCC toolchain
│   ├── risc-v --- Risc-v architecture
│   │ ├── nuclei --- Nuclei architecture
│   │   │ └── gcc --- Implementation of the GCC toolchain
│   │ └── riscv32 --- Riscv32 architecture
│   │   └── gcc --- Implementation of the GCC toolchain
│   └── include
│   ├── los_arch.h --- Arch initialization
│   ├── los_atomic.h --- Atomic operations
│   ├── los_context.h --- Context switch
│   ├── los_interrupt.h --- Interrupts
│   ├── los_mpu.h --- Memory protection unit operations
│   └── los_timer.h --- Timer operations
├── components --- Components available for porting and header files exposed externally
├── backtrace --- Backtrace support
├── cppsupport --- C++ support
├── cpup --- CPU percent (CPUP)
├── dynlink --- Dynamic loading and linking
├── exchook --- Exception hooks
├── fs --- File systems
│ ├── lmk --- Low memory killer functions
│ ├── lms --- Lite memory sanitizer functions
│ ├── net --- Networking functions
│ ├── power --- Power management
│ ├── shell --- Shell function
│ ├── fs --- File systems
│ └── trace --- Trace tool
├── drivers --- driver Kconfig
   ├── backtrace --- Backtrace
   ├── cppsupport --- C++
   ├── cpup --- CPUP
   ├── exchook --- Exception hook
   ├── fs --- File System
   └── net --- Network
├── kal --- Kernel Abstraction Layer, APIs exposed externally, including CMSIS APIs and part of POSIX APIs
│   ├── cmsis --- CMSIS
│   └── posix --- POSIX
├── kernel --- Code for defining the minimum kernel function set
│   ├── arch --- Code of the kernel instruction architecture layer
│   │   ├── arm --- ARM32 architecture
│   │   │   ├── cortex-m3 --- Cortex-m3 architecture
│   │   │   │ └── keil --- Implementation of the Keil toolchain
│   │   │   ├── cortex-m33 --- Cortex-m33 architecture
│   │   │   │ │── gcc --- Implementation of the GCC toolchain
│   │   │   │ └── iar --- Implementation of the IAR toolchain
│   │   │   └── cortex-m4 --- Cortex-m4 architecture
│   │   │   │ │── gcc --- Implementation of the GCC toolchain
│   │   │   │ └── iar --- Implementation of the IAR toolchain
│   │   │   └── cortex-m7 --- Cortex-m7 architecture
│   │   │   │ │── gcc --- Implementation of the GCC toolchain
│   │   │   │ └── iar --- Implementation of the IAR toolchain
│   │   ├── risc-v --- Risc-v architecture
│   │   │ ├── nuclei --- Nuclei architecture
│   │   │   │ └── gcc --- Implementation of the GCC toolchain
│   │   │ └── riscv32 --- Riscv32 architecture
│   │   │   │ └── gcc --- Implementation of the GCC toolchain
│   │   └── include
│   │   ├── los_arch.h --- Arch initialization
│   │   ├── los_atomic.h --- Atomic operations
│   │   ├── los_context.h --- Context switch
│   │   ├── los_interrupt.h --- Interrupts
│   │   ├── los_mpu.h --- Memory protection unit operations
│   │   └── los_timer.h --- Timer operations
│   ├── include
│   │   ├── los_config.h --- Configuration parameters
│   │   ├── los_event.h --- Events management
@@ -79,8 +59,6 @@
│ │ └── Src --- Application codes
│   └── riscv_nuclei_gd32vf103_soc_gcc
│   └── riscv_sifive_fe310_gcc
├── testsuites --- Kernel testsuites
├── tools --- Kernel tools
└── utils
├── internal
├── BUILD.gn --- Gn build config file

View File

@@ -1,60 +1,41 @@
```
.
├── arch --- 内核指令架构层代码
│   ├── arm --- ARM32架构
│   │   ├── arm9 --- arm9架构
│   │   │ └── gcc --- gcc 编译工具链实现
│   │   ├── cortex-m3 --- Cortex-m3架构
│   │   │ └── keil --- Keil编译工具链实现
│   │   ├── cortex-m33 --- Cortex-m33架构
│   │   │ │── gcc --- GCC编译工具链实现
│   │   │ │ │── NTZ --- Cortex-m33非TrustZone架构实现
│   │   │ │ └── TZ --- Cortex-m33 TrustZone架构实现
│   │   │ └── iar --- IAR编译工具链实现
│   │   │ │── NTZ --- Cortex-m33非TrustZone架构实现
│   │   │ └── TZ --- Cortex-m33 TrustZone架构实现
│   │   └── cortex-m4 --- Cortex-m4架构
│   │   │ │── gcc --- GCC编译工具链实现
│   │   │ └── iar --- IAR编译工具链实现
│   │   └── cortex-m7 --- Cortex-m7架构
│   │   │── gcc --- GCC编译工具链实现
│   │   └── iar --- IAR编译工具链实现
│   ├── csky --- csky架构
│   │ └── v2 --- csky v2架构
│   │   └── gcc --- GCC编译工具链实现
│   ├── xtensa --- xtensa架构
│   │ └── lx6 --- xtensa lx6架构
│   │   └── gcc --- GCC编译工具链实现
│   ├── risc-v --- Risc-v架构
│   │ ├── nuclei --- Nuclei架构
│   │   │ └── gcc --- GCC编译工具链实现
│   │ └── riscv32 --- Riscv32架构
│   │   └── gcc --- GCC编译工具链实现
│   └── include
│   ├── los_arch.h --- 定义arch初始化
│   ├── los_atomic.h --- 定义通用arch原子操作
│   ├── los_context.h --- 定义通用arch上下文切换
│   ├── los_interrupt.h --- 定义通用arch中断
│   ├── los_mpu.h --- 定义通用arch内存保护
│   └── los_timer.h --- 定义通用arch定时器
├── components --- 移植可选组件,依赖内核,单独对外提供头文件
├── backtrace --- 回溯功能
├── cppsupport --- C++支持
├── cpup --- CPUP功能
├── dynlink --- 动态加载与链接
├── exchook --- 异常钩子
├── fs --- 文件系统
│ ├── lmk --- Low memory killer 机制
│ ├── lms --- Lite memory sanitizer 机制
│ ├── net --- Network功能
│ ├── power --- 低功耗管理
│ ├── shell --- shell功能
│ └── trace --- trace 工具
├── drivers --- 驱动框架Kconfig
   ├── backtrace --- 回溯栈支持
   ├── cppsupport --- C++支持
   ├── cpup --- CPUP功能
   ├── exchook --- 异常钩子
   ├── fs --- 文件系统
   └── net --- 网络功能
├── kal --- 内核抽象层提供内核对外接口当前支持CMSIS接口和部分POSIX接口
│   ├── cmsis --- CMSIS标准支持
│   └── posix --- POSIX标准支持
├── kernel --- 内核最小功能集代码
│   ├── arch --- 内核指令架构层代码
│   │   ├── arm --- ARM32架构
│   │   │   ├── cortex-m3 --- Cortex-m3架构
│   │   │   │ └── keil --- Keil编译工具链实现
│   │   │   ├── cortex-m33 --- Cortex-m33架构
│   │   │   │ │── gcc --- GCC编译工具链实现
│   │   │   │ └── iar --- IAR编译工具链实现
│   │   │   └── cortex-m4 --- Cortex-m4架构
│   │   │   │ │── gcc --- GCC编译工具链实现
│   │   │   │ └── iar --- IAR编译工具链实现
│   │   │   └── cortex-m7 --- Cortex-m7架构
│   │   │   │ │── gcc --- GCC编译工具链实现
│   │   │   │ └── iar --- IAR编译工具链实现
│   │   ├── risc-v --- Risc-v架构
│   │   │ ├── nuclei --- Nuclei架构
│   │   │   │ └── gcc --- GCC编译工具链实现
│   │   │ └── riscv32 --- Riscv32架构
│   │   │   │ └── gcc --- GCC编译工具链实现
│   │   └── include
│   │   ├── los_arch.h --- 定义arch初始化
│   │   ├── los_atomic.h --- 定义通用arch原子操作
│   │   ├── los_context.h --- 定义通用arch上下文切换
│   │   ├── los_interrupt.h --- 定义通用arch中断
│   │   ├── los_mpu.h --- 定义通用arch内存保护
│   │   └── los_timer.h --- 定义通用arch定时器
│   ├── include
│   │   ├── los_config.h --- 功能开关和配置参数
│   │   ├── los_event.h --- 事件
@@ -78,8 +59,6 @@
│ │ └── Src --- Application相关代码
│   └── riscv_nuclei_gd32vf103_soc_gcc
│   └── riscv_sifive_fe310_gcc
├── testsuites --- 内核测试用例
├── tools --- 内核工具
└── utils
├── internal
├── BUILD.gn --- Gn构建文件

View File

@@ -1,64 +0,0 @@
# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
# of conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import("//kernel/liteos_m/liteos.gni")
group("components") {
deps = [
"backtrace",
"cppsupport",
"cpup",
"dynlink",
"exchook",
"fs",
"lmk",
"lms",
"net",
"power",
"shell",
"trace",
]
}
config("public") {
configs = [
"backtrace:public",
"cppsupport:public",
"cpup:public",
"dynlink:public",
"exchook:public",
"fs:public",
"net:public",
"power:public",
"shell:public",
"trace:public",
"lmk:public",
"lms:public",
]
}

View File

@@ -27,14 +27,13 @@
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import("//kernel/liteos_m/liteos.gni")
module_switch = defined(LOSCFG_KERNEL_BACKTRACE)
module_name = get_path_info(rebase_path("."), "name")
kernel_module(module_name) {
static_library("backtrace") {
sources = [ "los_backtrace.c" ]
}
config("public") {
include_dirs = [ "." ]
include_dirs = [
"../../kernel/include",
"../../kernel/arch/include",
"../../utils",
"//third_party/bounds_checking_function/include",
]
}

View File

@@ -32,22 +32,9 @@
#include "los_backtrace.h"
#include "los_task.h"
#include "los_debug.h"
#if (LOSCFG_BACKTRACE_TYPE == 4)
#include "los_arch_regs.h"
#endif
#if (LOSCFG_BACKTRACE_TYPE != 0)
/* This function is used to judge whether the data in the stack is a code section address.
The default code section is only one, but there may be more than one. Modify the
judgment condition to support multiple code sections. */
WEAK BOOL OsStackDataIsCodeAddr(UINTPTR value)
{
if ((value >= CODE_START_ADDR) && (value < CODE_END_ADDR)) {
return TRUE;
}
return FALSE;
}
#if (LOSCFG_BACKTRACE_TYPE == 1)
#define OS_BACKTRACE_START 2
/* Thumb instruction, so the pc must be an odd number */
@@ -193,10 +180,12 @@ STATIC INLINE UINTPTR OsAddrIsValid(UINTPTR sp)
return pc;
}
#elif (LOSCFG_BACKTRACE_TYPE == 2)
STATIC INLINE BOOL OsBackTraceFpCheck(UINT32 value);
#define OS_BACKTRACE_START 1
#define OS_RA_OFFSET 4
#define OS_FP_OFFSET 8
#define OS_FP_ALIGN(value) (((UINT32)(value) & (UINT32)(LOSCFG_STACK_POINT_ALIGN_SIZE - 1)) == 0)
#define OS_FP_CHECK(value) (((UINT32)(value) != FP_INIT_VALUE) && OS_FP_ALIGN(value))
STATIC INLINE UINTPTR OsFpGet(VOID)
{
@@ -206,41 +195,12 @@ STATIC INLINE UINTPTR OsFpGet(VOID)
return fp;
}
WEAK BOOL IsValidFP(UINTPTR fp)
{
LosTaskCB *taskCB = NULL;
UINTPTR stackTop, stackBottom;
UINTPTR irqStackTop, irqStackBottom;
if ((fp == FP_INIT_VALUE) || !OS_FP_ALIGN(fp)) {
return FALSE;
}
if (LOS_TaskIsRunning()) {
taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
stackTop = taskCB->topOfStack;
stackBottom = taskCB->topOfStack + taskCB->stackSize;
irqStackTop = (UINTPTR)CSTACK_START_ADDR;
irqStackBottom = (UINTPTR)CSTACK_SECTION_END;
} else {
stackTop = 0;
stackBottom = 0;
irqStackTop = (UINTPTR)CSTACK_START_ADDR;
irqStackBottom = (UINTPTR)CSTACK_SECTION_END;
}
if (((fp > stackTop) && (fp <= stackBottom)) || ((fp > irqStackTop) && (fp <= irqStackBottom))) {
return TRUE;
}
return FALSE;
}
VOID LOS_RecordLR(UINTPTR *LR, UINT32 LRSize, UINT32 jumpCount, UINTPTR SP)
{
UINTPTR backFp;
UINTPTR tmpFp;
UINTPTR backRa;
UNUSED(SP);
UINT32 backFp = OsFpGet();
UINT32 tmpFp;
UINT32 backRa;
UINT32 count = 0;
UINT32 index = 0;
@@ -248,31 +208,21 @@ VOID LOS_RecordLR(UINTPTR *LR, UINT32 LRSize, UINT32 jumpCount, UINTPTR SP)
return;
}
if (SP != 0) {
backFp = SP;
} else {
backFp = OsFpGet();
}
if (!IsValidFP(backFp)) {
PRINT_ERR("BackTrace failed! Invalid fp 0x%x\n", backFp);
return;
}
do {
while (OS_FP_CHECK(backFp)) {
tmpFp = backFp;
backRa = *((UINTPTR *)(UINTPTR)(tmpFp - OS_RA_OFFSET));
backFp = *((UINTPTR *)(UINTPTR)(tmpFp - OS_FP_OFFSET));
backRa = *((UINT32 *)(UINTPTR)(tmpFp - OS_RA_OFFSET));
backFp = *((UINT32 *)(UINTPTR)(tmpFp - OS_FP_OFFSET));
if (index++ < jumpCount) {
continue;
}
LR[count] = backRa;
count++;
if ((count == LRSize) || (backFp == tmpFp)) {
if ((count == LRSize) || (backFp == tmpFp) ||
(!OsStackDataIsCodeAddr(backRa))) {
break;
}
} while (IsValidFP(backFp));
}
if (count < LRSize) {
LR[count] = 0;
@@ -291,7 +241,7 @@ VOID LOS_RecordLR(UINTPTR *LR, UINT32 LRSize, UINT32 jumpCount, UINTPTR SP)
STATIC INLINE BOOL OsInsIsJump(UINTPTR addr)
{
UINT16 ins1 = *((UINT16 *)addr);
UINT16 ins2 = *((UINT16 *)(addr + 2)); // 2, for the mask
UINT16 ins2 = *((UINT16 *)(addr + 2));
/* Jal ins */
if (((ins1 & OS_JALX_INS_MASK) == OS_JAL_INS_LOW) ||
@@ -390,323 +340,6 @@ STATIC INLINE UINTPTR OsAddrIsValid(UINTPTR sp)
return pc;
}
#elif (LOSCFG_BACKTRACE_TYPE == 4)
#define OS_BACKTRACE_START 0
#define ALIGN_MASK (4 - 1)
#define OS_REG_LR_OFFSET (CONTEXT_SIZE - 8)
UINT32 IsSpAligned(UINT32 value)
{
return (value & (UINT32)(ALIGN_MASK)) == 0;
}
STATIC INLINE UINTPTR HalGetLr(VOID)
{
UINTPTR regLr;
__asm__ __volatile__("mov %0, a0" : "=r"(regLr));
return regLr;
}
/* This function is used to check sp address. */
BOOL IsValidSP(UINTPTR regSP, UINTPTR start, UINTPTR end)
{
return (regSP >= start) && (regSP <= end) && IsSpAligned(regSP);
}
/* This function is used to check return address. */
BOOL IsValidRa(UINTPTR regRA)
{
regRA &= ~VIR_TEXT_ADDR_MASK;
regRA |= TEXT_ADDR_MASK;
return OsStackDataIsCodeAddr(regRA);
}
BOOL FindSuitableStack(UINTPTR regSP, UINTPTR *start, UINTPTR *end)
{
UINT32 stackStart;
UINT32 stackEnd;
BOOL found = FALSE;
if (LOS_TaskIsRunning()) {
UINT32 taskID = LOS_CurTaskIDGet();
LosTaskCB *taskCB = OS_TCB_FROM_TID(taskID);
stackStart = taskCB->topOfStack;
stackEnd = taskCB->topOfStack + taskCB->stackSize;
if (IsValidSP(regSP, stackStart, stackEnd)) {
found = TRUE;
goto FOUND;
}
}
if (IsValidSP(regSP, CSTACK_START_ADDR, CSTACK_END_ADDR)) {
stackStart = CSTACK_START_ADDR;
stackEnd = CSTACK_END_ADDR;
found = TRUE;
goto FOUND;
}
FOUND:
if (found == TRUE) {
*start = stackStart;
*end = stackEnd;
}
return found;
}
UINT32 HalBackTraceGet(UINTPTR sp, UINT32 retAddr, UINTPTR *callChain, UINT32 maxDepth, UINT32 jumpCount)
{
UINTPTR tmpSp;
UINT32 tmpRa;
UINTPTR backRa = retAddr;
UINTPTR backSp = sp;
UINTPTR stackStart;
UINT32 stackEnd;
UINT32 count = 0;
UINT32 index = 0;
if (FindSuitableStack(sp, &stackStart, &stackEnd) == FALSE) {
PRINTK("sp:0x%x error, backtrace failed!\n", sp);
return 0;
}
while (IsValidSP(backSp, stackStart, stackEnd)) {
if (callChain == NULL) {
PRINTK("trace%u ra:0x%x sp:0x%x\n", count, (backRa << WINDOW_INCREMENT_SHIFT) >>
WINDOW_INCREMENT_SHIFT, backSp);
} else {
if (index++ < jumpCount) {
continue;
}
backRa &= ~VIR_TEXT_ADDR_MASK;
backRa |= TEXT_ADDR_MASK;
callChain[count++] = backRa;
}
tmpRa = backRa;
tmpSp = backSp;
backRa = *((UINT32 *)(UINTPTR)(tmpSp - RA_OFFSET));
backSp = *((UINT32 *)(UINTPTR)(tmpSp - SP_OFFSET));
if ((tmpRa == backRa) || (backSp == tmpSp) || (count == maxDepth) || !IsValidRa(backRa)) {
break;
}
}
return count;
}
VOID LOS_RecordLR(UINTPTR *LR, UINT32 LRSize, UINT32 jumpCount, UINTPTR SP)
{
UINTPTR reglr;
if (LR == NULL) {
return;
}
if (SP == 0) {
__asm__ __volatile__("mov %0, sp" : "=a"(SP) : :);
__asm__ __volatile__("mov %0, a0" : "=a"(reglr) : :);
} else {
reglr = *(UINT32 *)(SP - OS_REG_LR_OFFSET);
}
HakSpillWindow();
HalBackTraceGet(SP, reglr, LR, LRSize, jumpCount);
}
#elif (LOSCFG_BACKTRACE_TYPE == 5)
#define OS_BACKTRACE_START 0
UINT32 IsAligned(UINT32 val, UINT32 align)
{
return ((val & (align - 1)) == 0);
}
STATIC INLINE UINTPTR OsSpGet(VOID)
{
UINTPTR regSp;
__asm__ __volatile__("mov %0, sp" : "=r"(regSp));
return regSp;
}
/* This function is used to check sp. */
BOOL IsValidSP(UINTPTR regSP, UINTPTR start, UINTPTR end)
{
return (regSP >= start) && (regSP <= end);
}
BOOL FindSuitableStack(UINTPTR regSP, UINTPTR *start, UINTPTR *end)
{
UINT32 stackStart;
UINT32 stackEnd;
BOOL found = FALSE;
if (LOS_TaskIsRunning()) {
UINT32 taskID = LOS_CurTaskIDGet();
LosTaskCB *taskCB = OS_TCB_FROM_TID(taskID);
stackStart = taskCB->topOfStack;
stackEnd = taskCB->topOfStack + taskCB->stackSize;
if (IsValidSP(regSP, stackStart, stackEnd)) {
found = TRUE;
goto FOUND;
}
}
if (IsValidSP(regSP, CSTACK_START_ADDR, CSTACK_END_ADDR)) {
stackStart = CSTACK_START_ADDR;
stackEnd = CSTACK_END_ADDR;
found = TRUE;
goto FOUND;
}
FOUND:
if (found == TRUE) {
*start = stackStart;
*end = stackEnd;
}
return found;
}
VOID LOS_RecordLR(UINTPTR *LR, UINT32 LRSize, UINT32 jumpCount, UINTPTR SP)
{
UINTPTR stackPointer;
UINTPTR topOfStack;
UINTPTR tmpStack = 0;
UINTPTR stackBottom;
UINTPTR checkBL;
UINT32 count = 0;
UINT32 index = 0;
if (LR == NULL) {
return;
}
if (SP == 0) {
SP = OsSpGet();
}
stackPointer = SP;
if (FindSuitableStack(stackPointer, &topOfStack, &stackBottom) == FALSE) {
return;
}
while ((stackPointer < stackBottom) && (count < LRSize)) {
if (IsValidSP(*(UINT32 *)stackPointer, topOfStack, stackBottom)
&& OsStackDataIsCodeAddr(*(UINT32 *)(stackPointer + STACK_OFFSET))
&& IsAligned(*(UINT32 *)stackPointer, ALGIN_CODE)) {
if (tmpStack == *(UINT32 *)stackPointer) {
break;
}
tmpStack = *(UINT32 *)stackPointer;
checkBL = *(UINT32 *)(stackPointer + STACK_OFFSET);
if (count++ < jumpCount) {
continue;
}
stackPointer = tmpStack;
LR[index++] = checkBL;
continue;
}
stackPointer += STACK_OFFSET;
}
if (index < LRSize) {
LR[index] = 0;
}
}
#elif (LOSCFG_BACKTRACE_TYPE == 6)
#define OS_BACKTRACE_START 1
#define STACK_OFFSET 4
#define THUMB_OFFSET 2
#define THUMB_BIT 16
#define ARM_ALIGN_CODE 4
#define THUMB_ALIGN_CODE 2
#define BL_CMD_OFFSET 4
#define ARM_BL_MASK 0xEB000000
#define THUMB_BL_MASK 0xF000F000
#define CLEAR_LOW_BIT_MASK 0xFFFFFFFE
STATIC INLINE BOOL IsAligned(UINT32 val, UINT32 align)
{
return ((val & (align - 1)) == 0);
}
STATIC INLINE UINTPTR OsSpGet(VOID)
{
UINTPTR SP;
__asm volatile("mov %0, sp" : "=r"(SP));
return SP;
}
STATIC INLINE BOOL IsArmValidLr(UINTPTR lr)
{
return ((*(UINT32 *)(lr - BL_CMD_OFFSET) & ARM_BL_MASK) == ARM_BL_MASK);
}
STATIC INLINE BOOL IsThumbValidLr(UINTPTR lr)
{
lr = (*(UINT16 *)(lr - BL_CMD_OFFSET) << THUMB_BIT) + *(UINT16 *)(lr - THUMB_OFFSET);
return ((lr & THUMB_BL_MASK) == THUMB_BL_MASK);
}
VOID LOS_RecordLR(UINTPTR *LR, UINT32 LRSize, UINT32 jumpCount, UINTPTR SP)
{
UINT32 count = 0;
UINT32 index = 0;
LosTaskCB *taskCB = NULL;
UINT32 taskID;
UINT32 stackStart, stackEnd;
UINTPTR framePtr, tmpFramePtr, linkReg;
if (LR == NULL) {
return;
}
if (SP == 0) {
SP = OsSpGet();
}
if (LOS_TaskIsRunning()) {
taskID = LOS_CurTaskIDGet();
taskCB = OS_TCB_FROM_TID(taskID);
stackStart = taskCB->topOfStack;
stackEnd = stackStart + taskCB->stackSize;
} else {
stackStart = CSTACK_START_ADDR;
stackEnd = CSTACK_END_ADDR;
}
while ((SP > stackStart) && (SP < stackEnd)) {
linkReg = *(UINTPTR *)SP;
if (!OsStackDataIsCodeAddr(linkReg)) {
SP += STACK_OFFSET;
continue;
}
if (((!IsAligned(linkReg, ARM_ALIGN_CODE)) || !IsArmValidLr(linkReg)) &&
((!IsAligned(linkReg - 1, THUMB_ALIGN_CODE)) || !IsThumbValidLr(linkReg - 1))) {
SP += STACK_OFFSET;
continue;
}
if (index >= jumpCount) {
LR[count++] = linkReg & CLEAR_LOW_BIT_MASK;
if (count == LRSize) {
break;
}
}
++index;
SP += STACK_OFFSET;
}
/* if linkReg is not enough,clean up the last of the effective LR as the end. */
if (count < LRSize) {
LR[count] = 0;
}
}
#else
#error Unknown backtrace type.
#endif
@@ -774,9 +407,10 @@ VOID LOS_BackTrace(VOID)
PRINTK("----- traceback end -----\r\n");
}
VOID OsBackTraceInit(VOID)
VOID OSBackTraceInit(VOID)
{
OsBackTraceHookSet(LOS_RecordLR);
}
#endif

View File

@@ -56,7 +56,7 @@ extern "C" {
#pragma section=CSTACK_SECTION_NAME
/* Default only one code section. In fact, there may be more than one.
You can define more than one and redefine the OsStackDataIsCodeAddr function
You can define more than one and modify the OsStackDataIsCodeAddr function
to support searching in multiple code sections */
#define CODE_START_ADDR ((UINTPTR)__section_begin(CODE_SECTION_NAME))
#define CODE_END_ADDR ((UINTPTR)__section_end(CODE_SECTION_NAME))
@@ -84,7 +84,7 @@ extern CHAR *CODE_SECTION_START(CODE_SECTION_NAME);
extern CHAR *CODE_SECTION_END(CODE_SECTION_NAME);
/* Default only one code section. In fact, there may be more than one.
You can define more than one and redefine the OsStackDataIsCodeAddr function
You can define more than one and modify the OsStackDataIsCodeAddr function
to support searching in multiple code sections */
#define CODE_START_ADDR ((UINTPTR)&CODE_SECTION_START(CODE_SECTION_NAME))
#define CODE_END_ADDR ((UINTPTR)&CODE_SECTION_END(CODE_SECTION_NAME))
@@ -106,7 +106,7 @@ extern CHAR *CSTACK_SECTION_START;
extern CHAR *CSTACK_SECTION_END;
/* Default only one code section. In fact, there may be more than one.
You can define more than one and redefine the OsStackDataIsCodeAddr function
You can define more than one and modify the OsStackDataIsCodeAddr function
to support searching in multiple code sections */
#define CODE_START_ADDR ((UINTPTR)&CODE_SECTION_START)
#define CODE_END_ADDR ((UINTPTR)&CODE_SECTION_END)
@@ -138,85 +138,22 @@ extern CHAR *CSTACK_SECTION_END;
#else
#error Unknown compiler.
#endif
#elif (LOSCFG_BACKTRACE_TYPE == 4)
/* The default code section start address */
#define CODE_SECTION_START __text_start
/* The default code section end address */
#define CODE_SECTION_END __text_end
/* The default C stack section start address */
#define CSTACK_SECTION_START __init_stack_s
/* The default C stack section end address */
#define CSTACK_SECTION_END __init_stack_e
extern CHAR *CODE_SECTION_START;
extern CHAR *CODE_SECTION_END;
extern CHAR *CSTACK_SECTION_START;
extern CHAR *CSTACK_SECTION_END;
#define CODE_START_ADDR ((UINTPTR)&CODE_SECTION_START)
#define CODE_END_ADDR ((UINTPTR)&CODE_SECTION_END)
#define CSTACK_START_ADDR ((UINTPTR)&CSTACK_SECTION_START)
#define CSTACK_END_ADDR ((UINTPTR)&CSTACK_SECTION_END)
#define VIR_TEXT_ADDR_MASK 0x80000000
#define TEXT_ADDR_MASK 0x40000000
#define RA_OFFSET 16
#define SP_OFFSET 12
#define WINDOW_INCREMENT_SHIFT 2
UINT32 HalBackTraceGet(UINTPTR sp, UINT32 retAddr, UINTPTR *callChain, UINT32 maxDepth, UINT32 jumpCount);
#elif (LOSCFG_BACKTRACE_TYPE == 5)
/* The default code section start address */
#define CODE_SECTION_START __text_start
/* The default code section end address */
#define CODE_SECTION_END __text_end
/* The default C stack section start address */
#define CSTACK_SECTION_START __init_stack_s
/* The default C stack section end address */
#define CSTACK_SECTION_END __ram_end
extern CHAR *CODE_SECTION_START;
extern CHAR *CODE_SECTION_END;
extern CHAR *CSTACK_SECTION_START;
extern CHAR *CSTACK_SECTION_END;
#define CODE_START_ADDR ((UINTPTR)&CODE_SECTION_START)
#define CODE_END_ADDR ((UINTPTR)&CODE_SECTION_END)
#define CSTACK_START_ADDR ((UINTPTR)&CSTACK_SECTION_START)
#define CSTACK_END_ADDR ((UINTPTR)&CSTACK_SECTION_END)
#define ALGIN_CODE 2
#define STACK_OFFSET 4
#elif (LOSCFG_BACKTRACE_TYPE == 6)
extern CHAR *__svc_stack;
extern CHAR *__svc_stack_top;
/* The default code section start address */
#define CODE_SECTION_START __text_start
/* The default code section end address */
#define CODE_SECTION_END __text_end
/* The default C stack section start address */
#define CSTACK_SECTION_START __svc_stack
/* The default C stack section end address */
#define CSTACK_SECTION_END __svc_stack_top
extern CHAR *CODE_SECTION_START;
extern CHAR *CODE_SECTION_END;
extern CHAR *CSTACK_SECTION_START;
extern CHAR *CSTACK_SECTION_END;
/* Default only one code section. In fact, there may be more than one.
You can define more than one and redefine the OsStackDataIsCodeAddr function
to support searching in multiple code sections */
#define CODE_START_ADDR ((UINTPTR)&CODE_SECTION_START)
#define CODE_END_ADDR ((UINTPTR)&CODE_SECTION_END)
#define CSTACK_START_ADDR ((UINTPTR)&CSTACK_SECTION_START)
#define CSTACK_END_ADDR ((UINTPTR)&CSTACK_SECTION_END)
#endif
/* This function is used to judge whether the data in the stack is a code section address.
The default code section is only one, but there may be more than one. Modify the
judgment condition to support multiple code sections. */
STATIC INLINE BOOL OsStackDataIsCodeAddr(UINTPTR value)
{
if ((value >= CODE_START_ADDR) && (value < CODE_END_ADDR)) {
return TRUE;
}
return FALSE;
}
/* This function is currently used to register the memory leak check hook,
other uses do not need to be called temporarily. */
VOID OsBackTraceInit(VOID);
VOID OSBackTraceInit(VOID);
/* This function is used to print the function call stack. */
VOID LOS_BackTrace(VOID);
@@ -230,5 +167,4 @@ VOID LOS_RecordLR(UINTPTR *LR, UINT32 LRSize, UINT32 jumpCount, UINTPTR SP);
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif
#endif

View File

@@ -27,14 +27,8 @@
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import("//kernel/liteos_m/liteos.gni")
module_switch = defined(LOSCFG_KERNEL_CPPSUPPORT)
module_name = get_path_info(rebase_path("."), "name")
kernel_module(module_name) {
static_library("cppsupport") {
sources = [ "los_cppsupport.c" ]
}
config("public") {
include_dirs = [ "." ]
include_dirs = [ "../../utils" ]
}

View File

@@ -31,6 +31,7 @@
#include "los_cppsupport.h"
typedef VOID (*InitFunc)(VOID);
INT32 LOS_CppSystemInit(UINTPTR initArrayStart, UINTPTR initArrayEnd)
@@ -38,10 +39,12 @@ INT32 LOS_CppSystemInit(UINTPTR initArrayStart, UINTPTR initArrayEnd)
UINTPTR *start;
InitFunc initFunc = NULL;
for (start = (UINTPTR *)initArrayStart; start < (UINTPTR *)initArrayEnd; start++) {
for (start = (UINTPTR *)initArrayStart; start < (UINTPTR *)initArrayEnd; start++){
initFunc = (InitFunc)(*start);
initFunc();
}
return 0;
}

View File

@@ -27,14 +27,13 @@
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import("//kernel/liteos_m/liteos.gni")
module_switch = defined(LOSCFG_BASE_CORE_CPUP)
module_name = get_path_info(rebase_path("."), "name")
kernel_module(module_name) {
static_library("cpup") {
sources = [ "los_cpup.c" ]
}
config("public") {
include_dirs = [ "." ]
include_dirs = [
"../../kernel/include",
"../../kernel/arch/include",
"../../utils",
"//third_party/bounds_checking_function/include",
]
}

View File

@@ -1,39 +0,0 @@
# Copyright (c) 2021-2021 Huawei Device Co., Ltd. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
# of conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import("//kernel/liteos_m/liteos.gni")
module_switch = defined(LOSCFG_KERNEL_DYNLINK)
module_name = get_path_info(rebase_path("."), "name")
kernel_module(module_name) {
sources = [ "los_dynlink.c" ]
}
config("public") {
include_dirs = [ "." ]
}

View File

@@ -1,935 +0,0 @@
/*
* Copyright (c) 2021-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_dynlink.h"
#include "stdlib.h"
#include "string.h"
#include "unistd.h"
#include "fcntl.h"
#include "errno.h"
#include "limits.h"
#include "sys/stat.h"
#include "securec.h"
#include "arch_elf.h"
#include "los_task.h"
#include "los_debug.h"
#include "los_mux.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#if (LOSCFG_DYNLINK == 1)
#if defined(__ICCARM__) || defined(__CC_ARM)
/**
* Place instructions below in .icf linker file:
*
* keep {section .TABLE.START};
* keep {section .sym.*};
* keep {section .table.end};
* define block SYMBOL_TABLE with fixed order
* {
* section .TABLE.START,
* section .sym.*,
* section .table.end
* };
* place in ROM_region {readonly, block SYMBOL_TABLE};
*/
const SymInfo symTableStart __attribute__((section(".TABLE.START"))) = {
.name = "start",
.addr = 0
};
const SymInfo symTableEnd __attribute__((section(".table.end"))) = {
.name = "end",
.addr = 0
};
#pragma section=".TABLE.START"
#pragma section=".table.end"
#elif defined(__CLANG_ARM) || defined(__GNUC__)
/**
* Place instructions below in rodata segment of .ld linker file:
*
* __sym_table_start = .;
* KEEP(*( SORT (.sym.*)));
* __sym_table_end = .;
*/
extern char __sym_table_start[];
extern char __sym_table_end[];
#else
#error Unknown compiler.
#endif
STATIC LOS_DL_LIST g_dynSharedObjLink;
STATIC UINT32 g_dynlinkMux;
STATIC DynSharedObj *OsIsPreLoaded(const CHAR *fileName)
{
DynSharedObj *dso = NULL;
LOS_DL_LIST_FOR_EACH_ENTRY(dso, &g_dynSharedObjLink, DynSharedObj, dsoNode) {
if (!strcmp(fileName, dso->fileName)) {
++dso->ref;
return dso;
}
}
return NULL;
}
STATIC INT32 OsVerifyEhdr(const LD_ELF_EHDR *ehdr, UINT32 fileLen)
{
if (memcmp(ehdr->e_ident, LD_ELFMAG, LD_SELFMAG) != LOS_OK) {
PRINT_ERR("The file is not elf format\n");
return LOS_NOK;
}
if (ehdr->e_type != ET_DYN) {
PRINT_ERR("The file is not shared library\n");
return LOS_NOK;
}
if (!check_arch(ehdr)) {
PRINT_ERR("The file can not load in current platform\n");
return LOS_NOK;
}
if (ehdr->e_phnum > PHDR_NUM_MAX) {
PRINT_ERR("The num of program header is out of limit\n");
return LOS_NOK;
}
if (ehdr->e_phoff > fileLen) {
PRINT_ERR("The offset of program header is invalid, elf file is bad\n");
return LOS_NOK;
}
return LOS_OK;
}
STATIC INT32 OsReadELFInfo(INT32 fd, UINT8 *buffer, size_t readSize, off_t offset)
{
ssize_t byteNum;
off_t returnPos;
if (readSize > 0) {
returnPos = lseek(fd, offset, SEEK_SET);
if (returnPos != offset) {
PRINT_ERR("Failed to seek the position!, offset: %#x\n", offset);
return LOS_NOK;
}
byteNum = read(fd, buffer, readSize);
if (byteNum <= 0) {
PRINT_ERR("Failed to read from offset: %#x!\n", offset);
return LOS_NOK;
}
}
return LOS_OK;
}
STATIC INT32 OsGetFileLength(UINT32 *fileLen, const CHAR *fileName)
{
struct stat buf;
INT32 ret;
ret = stat(fileName, &buf);
if (ret < 0) {
PRINT_ERR("Failed to stat file: %s, errno: %d\n", fileName, errno);
return LOS_NOK;
}
if (buf.st_size > FILE_LENGTH_MAX) {
PRINT_ERR("The file: %s length is out of limit!\n", fileName);
return LOS_NOK;
}
*fileLen = (UINT32)buf.st_size;
return LOS_OK;
}
STATIC INT32 OsReadEhdr(INT32 fd, UINT32 fileLen, DynLinkInfo *dlInfo)
{
INT32 ret;
ret = OsReadELFInfo(fd, (UINT8 *)&dlInfo->elfEhdr, sizeof(LD_ELF_EHDR), 0);
if (ret != LOS_OK) {
return -EIO;
}
ret = OsVerifyEhdr(&dlInfo->elfEhdr, fileLen);
if (ret != LOS_OK) {
return -ELIBBAD;
}
return LOS_OK;
}
STATIC INT32 OsReadPhdrs(INT32 fd, UINT32 fileLen, DynLinkInfo *dlInfo)
{
INT32 ret;
UINT32 size;
LD_ELF_EHDR *ehdr = &dlInfo->elfEhdr;
if ((ehdr->e_phnum == 0) || (ehdr->e_phentsize != sizeof(LD_ELF_PHDR))) {
goto ERR;
}
size = sizeof(LD_ELF_PHDR) * ehdr->e_phnum;
if ((ehdr->e_phoff + size) > fileLen) {
goto ERR;
}
dlInfo->elfPhdr = (LD_ELF_PHDR *)LOS_MemAlloc(OS_SYS_MEM_ADDR, size);
if (dlInfo->elfPhdr == NULL) {
return -ENOMEM;
}
ret = OsReadELFInfo(fd, (UINT8 *)dlInfo->elfPhdr, size, ehdr->e_phoff);
if (ret != LOS_OK) {
LOS_MemFree(OS_SYS_MEM_ADDR, dlInfo->elfPhdr);
return -EIO;
}
return LOS_OK;
ERR:
PRINT_ERR("the file is bad\n");
return -ELIBBAD;
}
STATIC DynSharedObj *OsLoadInit(const CHAR *fileName, VOID *pool)
{
DynSharedObj *dso = NULL;
UINT32 allocSize, nameLen;
UINT32 fileLen = 0;
INT32 ret;
nameLen = strlen(fileName);
if (nameLen > PATH_MAX) {
PRINT_ERR("file name length is too long\n");
errno = ENAMETOOLONG;
return NULL;
}
allocSize = sizeof(DynSharedObj) + nameLen + 1;
dso = (DynSharedObj *)LOS_MemAlloc(OS_SYS_MEM_ADDR, allocSize);
if (dso == NULL) {
PRINT_ERR("failed to alloc for dso\n");
errno = ENOMEM;
return NULL;
}
(VOID)memset_s(dso, allocSize, 0, allocSize);
dso->dlInfo = (DynLinkInfo *)LOS_MemAlloc(OS_SYS_MEM_ADDR, sizeof(DynLinkInfo));
if (dso->dlInfo == NULL) {
LOS_MemFree(OS_SYS_MEM_ADDR, dso);
PRINT_ERR("failed to alloc for loadInfo\n");
errno = ENOMEM;
return NULL;
}
(VOID)memset_s(dso->dlInfo, sizeof(DynLinkInfo), 0, sizeof(DynLinkInfo));
ret = OsGetFileLength(&fileLen, fileName);
if (ret != LOS_OK) {
errno = ENOENT;
goto ERR1;
}
dso->fd = open(fileName, O_RDONLY);
if (dso->fd < 0) {
PRINT_ERR("Failed to open ELF file: %s!\n", fileName);
goto ERR1;
}
ret = OsReadEhdr(dso->fd, fileLen, dso->dlInfo);
if (ret != LOS_OK) {
errno = -ret;
goto ERR2;
}
ret = OsReadPhdrs(dso->fd, fileLen, dso->dlInfo);
if (ret != LOS_OK) {
errno = -ret;
goto ERR2;
}
strcpy(dso->buf, fileName);
dso->fileName = dso->buf;
dso->ref = 1;
dso->pool = (pool ? pool : OS_SYS_MEM_ADDR);
LOS_ListInit(&dso->dsoNode);
return dso;
ERR2:
close(dso->fd);
ERR1:
LOS_MemFree(OS_SYS_MEM_ADDR, dso->dlInfo);
LOS_MemFree(OS_SYS_MEM_ADDR, dso);
return NULL;
}
STATIC INT32 OsReserveSpace(const DynLinkInfo *dlInfo, UINT32 *boundary)
{
const LD_ELF_PHDR *elfPhdrTemp = dlInfo->elfPhdr;
INT32 phdrNum = dlInfo->elfEhdr.e_phnum;
UINTPTR addrMin = SIZE_MAX;
UINTPTR addrMax = 0;
UINT32 offStart = 0;
UINT64 size;
INT32 i;
for (i = 0; i < phdrNum; ++i, ++elfPhdrTemp) {
if (elfPhdrTemp->p_type == PT_TLS) {
PRINT_ERR("unsupport tls\n");
return 0;
}
if (elfPhdrTemp->p_type != PT_LOAD) {
continue;
}
if (*boundary == 0) {
*boundary = elfPhdrTemp->p_align;
}
if (elfPhdrTemp->p_vaddr < addrMin) {
addrMin = elfPhdrTemp->p_vaddr;
offStart = elfPhdrTemp->p_offset;
}
if ((elfPhdrTemp->p_vaddr + elfPhdrTemp->p_memsz) > addrMax) {
addrMax = elfPhdrTemp->p_vaddr + elfPhdrTemp->p_memsz;
}
}
if ((addrMin == addrMax) || (addrMax < addrMin)) {
return 0;
}
size = ELF_ALIGN_UP(addrMax, *boundary) - ELF_ALIGN_DOWN(addrMin, *boundary) + ELF_ALIGN_DOWN(offStart, *boundary);
return (size > UINT_MAX) ? 0 : (UINT32)size;
}
STATIC UINTPTR OsDoLoadFile(INT32 fd, UINTPTR addr, const LD_ELF_PHDR *elfPhdr, UINT32 boundary)
{
INT32 ret;
UINT32 offset = elfPhdr->p_offset - ELF_ALIGN_OFFSET(elfPhdr->p_vaddr, boundary);
UINT32 size = elfPhdr->p_filesz + ELF_ALIGN_OFFSET(elfPhdr->p_vaddr, boundary);
if (size == 0) {
return 0;
}
addr = ELF_ALIGN_DOWN(addr, boundary);
ret = OsReadELFInfo(fd, (UINT8 *)addr, size, offset);
if (ret != LOS_OK) {
return 0;
}
return addr;
}
STATIC INT32 OsLoadELFFile(DynSharedObj *dso, UINT32 boundary)
{
DynLinkInfo *dlInfo = dso->dlInfo;
const LD_ELF_PHDR *elfPhdrTemp = dlInfo->elfPhdr;
const LD_ELF_EHDR *elfEhdr = &dlInfo->elfEhdr;
UINTPTR loadBase = dso->loadBase;
UINTPTR vAddr, loadAddr, bssStart, bssEnd;
INT32 i;
for (i = 0; i < elfEhdr->e_phnum; ++i, ++elfPhdrTemp) {
if (elfPhdrTemp->p_type != PT_LOAD) {
continue;
}
if ((elfPhdrTemp->p_flags & PF_R) == 0) {
return -ENOEXEC;
}
vAddr = elfPhdrTemp->p_vaddr;
loadAddr = OsDoLoadFile(dso->fd, (vAddr + loadBase), elfPhdrTemp, boundary);
if (loadAddr == 0) {
return -EFAULT;
}
if ((elfPhdrTemp->p_memsz > elfPhdrTemp->p_filesz) && (elfPhdrTemp->p_flags & PF_W)) {
bssStart = loadAddr + ELF_ALIGN_OFFSET(vAddr, boundary) + elfPhdrTemp->p_filesz;
bssEnd = loadAddr + ELF_ALIGN_OFFSET(vAddr, boundary) + elfPhdrTemp->p_memsz;
(VOID)memset_s((VOID *)bssStart, bssEnd - bssStart, 0, bssEnd - bssStart);
}
}
return LOS_OK;
}
STATIC INT32 OsLoadLibrary(DynSharedObj *dso)
{
UINT32 loadSize;
UINT32 boundary = 0;
INT32 ret;
loadSize = OsReserveSpace(dso->dlInfo, &boundary);
if (loadSize == 0) {
PRINT_ERR("failed to reserve space!\n");
return -EINVAL;
}
dso->loadBase = (UINTPTR)LOS_MemAllocAlign(dso->pool, loadSize, boundary);
if (dso->loadBase == 0) {
PRINT_ERR("failed to alloc memory for loading shared library\n");
return -ENOMEM;
}
ret = OsLoadELFFile(dso, boundary);
if (ret != LOS_OK) {
LOS_MemFree(dso->pool, (VOID *)dso->loadBase);
PRINT_ERR("failed to load shared library\n");
return ret;
}
return LOS_OK;
}
STATIC INT32 OsGetDynBase(DynSharedObj *dso)
{
DynLinkInfo *dlInfo = dso->dlInfo;
const LD_ELF_PHDR *elfPhdrTemp = dlInfo->elfPhdr;
INT32 phdrNum = dlInfo->elfEhdr.e_phnum;
INT32 i;
for (i = 0; i < phdrNum; ++i, ++elfPhdrTemp) {
if (elfPhdrTemp->p_type != PT_DYNAMIC) {
continue;
}
dlInfo->dynBase = dso->loadBase + elfPhdrTemp->p_vaddr;
return LOS_OK;
}
return LOS_NOK;
}
STATIC INT32 OsParseDynamic(DynSharedObj *dso)
{
LD_ELF_DYN *dyn = NULL;
DynLinkInfo *dlInfo = dso->dlInfo;
RelocInfoTab *relInfoTab = &dlInfo->relInfoTab;
for (dyn = (LD_ELF_DYN *)dlInfo->dynBase; dyn->d_tag != DT_NULL; ++dyn) {
switch (dyn->d_tag) {
case DT_NEEDED:
PRINT_ERR("shared library should not depend on others\n");
return -ENOTSUP;
case DT_TEXTREL:
PRINT_ERR("you should recompile shared library with -fPIC\n");
return -EFAULT;
case DT_HASH:
dlInfo->hashTab = (UINT32 *)(dso->loadBase + dyn->d_un.d_ptr);
break;
case DT_SYMTAB:
dlInfo->symTab = (LD_ELF_SYM *)(dso->loadBase + dyn->d_un.d_ptr);
break;
case DT_STRTAB:
dlInfo->symStrings = (CHAR *)(dso->loadBase + dyn->d_un.d_ptr);
break;
case DT_REL:
relInfoTab->rel.relTab = dso->loadBase + dyn->d_un.d_ptr;
relInfoTab->rel.relEntSize = sizeof(LD_ELF_REL);
break;
case DT_RELSZ:
relInfoTab->rel.relTabSize = dyn->d_un.d_val;
break;
case DT_RELA:
relInfoTab->rela.relTab = dso->loadBase + dyn->d_un.d_ptr;
relInfoTab->rela.relEntSize = sizeof(LD_ELF_RELA);
break;
case DT_RELASZ:
relInfoTab->rela.relTabSize = dyn->d_un.d_val;
break;
case DT_JMPREL:
relInfoTab->jmpRel.relTab = dso->loadBase + dyn->d_un.d_ptr;
break;
case DT_PLTRELSZ:
relInfoTab->jmpRel.relTabSize = dyn->d_un.d_val;
break;
case DT_PLTREL:
relInfoTab->jmpRel.relEntSize = (dyn->d_un.d_val == DT_REL) ? sizeof(LD_ELF_REL) : sizeof(LD_ELF_RELA);
default:
break;
}
}
return LOS_OK;
}
STATIC UINT32 OsGetHashVal(const CHAR *name)
{
UINT32 hashVal = 0;
UINT32 tmp;
const UINT8 *str = (const UINT8 *)name;
while (*str) {
hashVal = (*str) + (hashVal << WORD_SHIFT);
tmp = hashVal & HASH_MASK;
if (tmp != 0) {
hashVal ^= tmp >> HASH_SHIFT;
}
hashVal &= ~tmp;
++str;
}
return hashVal;
}
STATIC LD_ELF_SYM *OsFindSymInDso(const DynLinkInfo *dlInfo, const CHAR *name)
{
LD_ELF_SYM *symTab = dlInfo->symTab;
LD_ELF_SYM *sym = NULL;
CHAR *symStr = dlInfo->symStrings;
UINT32 *hashTab = dlInfo->hashTab;
UINT32 bucketNum = hashTab[0];
UINT32 *bucket = &hashTab[BUCKET_IDX];
UINT32 *chain = &bucket[bucketNum];
UINT32 hashVal = OsGetHashVal(name);
UINT32 symIdx;
for (symIdx = bucket[hashVal % bucketNum]; symIdx; symIdx = chain[symIdx]) {
if (strcmp(name, symStr + symTab[symIdx].st_name) != 0) {
continue;
}
sym = symTab + symIdx;
if ((sym->st_value == 0) || (sym->st_shndx == 0)) {
return NULL;
}
return symTab + symIdx;
}
return NULL;
}
STATIC SymInfo *OsFindSymInTable(const CHAR *name)
{
#if defined(__ICCARM__) || defined(__CC_ARM)
SymInfo *symTab = (SymInfo *)__section_end(".TABLE.START");
UINT32 symTableSize = ((UINTPTR)__section_begin(".table.end") -
(UINTPTR)__section_end(".TABLE.START")) / sizeof(SymInfo);
#elif defined(__CLANG_ARM) || defined(__GNUC__)
SymInfo *symTab = (SymInfo *)__sym_table_start;
UINT32 symTableSize = (__sym_table_end - __sym_table_start) / sizeof(SymInfo);
#endif
INT32 startIdx = 0;
INT32 endIdx = symTableSize - 1;
INT32 ret, midIdx;
while (startIdx <= endIdx) {
midIdx = startIdx + ((UINT32)(endIdx - startIdx) >> 1);
ret = strcmp(symTab[midIdx].name, name);
if (ret > 0) {
endIdx = midIdx - 1;
} else if (ret < 0) {
startIdx = midIdx + 1;
} else {
return symTab + midIdx;
}
}
return NULL;
}
STATIC UINTPTR OsFindSym(const DynSharedObj *dso, INT32 symIdx)
{
DynLinkInfo *dlInfo = dso->dlInfo;
CHAR *symStrings = dlInfo->symStrings;
CHAR *symStr = NULL;
LD_ELF_SYM *symTab = dlInfo->symTab;
LD_ELF_SYM *sym = NULL;
LD_ELF_SYM *symInDso = NULL;
SymInfo *symInTab = NULL;
sym = symTab + symIdx;
symStr = symStrings + sym->st_name;
if ((symInDso = OsFindSymInDso(dlInfo, symStr)) != NULL) {
return dso->loadBase + symInDso->st_value;
} else if ((symInTab = OsFindSymInTable(symStr)) != NULL) {
return symInTab->addr;
} else {
PRINT_ERR("failed to relocate %s, symbol: %s not found\n", dso->fileName, symStr);
return 0;
}
}
STATIC INT32 OsDoReloc(const DynSharedObj *dso, INT32 type, UINTPTR relocAddr, UINT32 addend, UINTPTR symAddr)
{
switch (type) {
case R_ARCH_NONE:
break;
case R_ARCH_GLOB_DAT:
case R_ARCH_JUMP_SLOT:
*(UINTPTR *)relocAddr = symAddr + addend;
break;
case R_ARCH_ABS32:
*(UINTPTR *)relocAddr = symAddr + ((addend != 0) ? addend : *(UINTPTR *)relocAddr);
break;
case R_ARCH_RELATIVE:
*(UINTPTR *)relocAddr = dso->loadBase + ((addend != 0) ? addend : *(UINTPTR *)relocAddr);
break;
default:
PRINT_ERR("failed to relocate %s, unsupported reloc type: %d\n", dso->fileName, type);
return -ENOTSUP;
}
return LOS_OK;
}
STATIC INT32 OsDoRelocSyms(DynSharedObj *dso, RelocInfo *relInfo)
{
UINT32 relStride = relInfo->relEntSize / sizeof(UINT32);
UINT32 *relTab = (UINT32 *)relInfo->relTab;
UINT32 addend;
UINTPTR relocAddr, symAddr;
INT32 i, symIdx, ret, type;
for (i = 0; i < relInfo->relTabSize; i += relInfo->relEntSize, relTab += relStride) {
type = REL_TYPE(relTab[1]);
if (type == R_ARCH_NONE) {
continue;
}
symIdx = REL_SYM(relTab[1]);
if (symIdx == 0) {
symAddr = 0;
} else {
symAddr = OsFindSym(dso, symIdx);
if (symAddr == 0) {
return -EFAULT;
}
}
relocAddr = dso->loadBase + relTab[0];
addend = (relInfo->relEntSize == sizeof(LD_ELF_REL)) ? 0 : relTab[relStride - 1];
ret = OsDoReloc(dso, type, relocAddr, addend, symAddr);
if (ret != LOS_OK) {
return ret;
}
}
return LOS_OK;
}
STATIC INT32 OsRelocSyms(DynSharedObj *dso)
{
DynLinkInfo *dlInfo = dso->dlInfo;
RelocInfo *relInfo = (RelocInfo *)&dlInfo->relInfoTab;
INT32 relTypes = sizeof(RelocInfoTab) / sizeof(RelocInfo);
INT32 i, ret;
for (i = 0; i < relTypes; ++i, ++relInfo) {
if (relInfo->relTab == 0) {
continue;
}
ret = OsDoRelocSyms(dso, relInfo);
if (ret != LOS_OK) {
return ret;
}
}
return LOS_OK;
}
STATIC INT32 OsDoDynLink(DynSharedObj *dso)
{
INT32 ret;
ret = OsGetDynBase(dso);
if (ret != LOS_OK) {
PRINT_ERR("there are no dynamic segments in elf file\n");
return -ELIBBAD;
}
ret = OsParseDynamic(dso);
if (ret != LOS_OK) {
return ret;
}
ret = OsRelocSyms(dso);
if (ret != LOS_OK) {
return ret;
}
return LOS_OK;
}
STATIC VOID OsDeLoadInit(DynSharedObj *dso)
{
LOS_MemFree(OS_SYS_MEM_ADDR, dso->dlInfo->elfPhdr);
dso->dlInfo->elfPhdr = NULL;
close(dso->fd);
}
STATIC VOID OsGetInitFini(DynSharedObj *dso)
{
LD_ELF_DYN *dyn = NULL;
DynLinkInfo *dlInfo = dso->dlInfo;
InitFiniTab *initFiniTab = &dso->initFiniTab;
for (dyn = (LD_ELF_DYN *)dlInfo->dynBase; dyn->d_tag != DT_NULL; ++dyn) {
switch (dyn->d_tag) {
case DT_INIT:
initFiniTab->init.func = dyn->d_un.d_ptr;
break;
case DT_INIT_ARRAY:
initFiniTab->init.array = dyn->d_un.d_ptr;
break;
case DT_INIT_ARRAYSZ:
initFiniTab->init.arraySz = dyn->d_un.d_val;
break;
case DT_FINI:
initFiniTab->fini.func = dyn->d_un.d_ptr;
break;
case DT_FINI_ARRAY:
initFiniTab->fini.array = dyn->d_un.d_ptr;
break;
case DT_FINI_ARRAYSZ:
initFiniTab->fini.arraySz = dyn->d_un.d_val;
break;
default:
break;
}
}
}
STATIC VOID OsDoInit(DynSharedObj *dso)
{
InitFiniTab *initFiniTab = &dso->initFiniTab;
INIT_FINI_FUNC initFunc = NULL;
UINTPTR *func = NULL;
UINT32 funcNum;
OsGetInitFini(dso);
if (initFiniTab->init.func != 0) {
initFunc = (INIT_FINI_FUNC)(dso->loadBase + initFiniTab->init.func);
initFunc();
}
if (initFiniTab->init.array == 0) {
return;
}
funcNum = initFiniTab->init.arraySz / sizeof(UINTPTR);
func = (UINTPTR *)(dso->loadBase + initFiniTab->init.array);
while (funcNum--) {
initFunc = (INIT_FINI_FUNC)(*func);
initFunc();
++func;
}
}
VOID *LOS_SoLoad(const CHAR *fileName, VOID *pool)
{
INT32 ret;
DynSharedObj *dso = NULL;
if (fileName == NULL) {
PRINT_ERR("invalid file name\n");
errno = EINVAL;
return NULL;
}
(VOID)LOS_MuxPend(g_dynlinkMux, LOS_WAIT_FOREVER);
dso = OsIsPreLoaded(fileName);
if (dso != NULL) {
(VOID)LOS_MuxPost(g_dynlinkMux);
return dso;
}
dso = OsLoadInit(fileName, pool);
if (dso == NULL) {
(VOID)LOS_MuxPost(g_dynlinkMux);
return NULL;
}
ret = OsLoadLibrary(dso);
if (ret != LOS_OK) {
errno = -ret;
goto ERR1;
}
ret = OsDoDynLink(dso);
if (ret != LOS_OK) {
errno = -ret;
goto ERR2;
}
OsDoInit(dso);
LOS_ListAdd(&g_dynSharedObjLink, &dso->dsoNode);
(VOID)LOS_MuxPost(g_dynlinkMux);
OsDeLoadInit(dso);
return dso;
ERR2:
LOS_MemFree(dso->pool, (VOID *)dso->loadBase);
ERR1:
close(dso->fd);
(VOID)LOS_MuxPost(g_dynlinkMux);
LOS_MemFree(OS_SYS_MEM_ADDR, dso->dlInfo->elfPhdr);
LOS_MemFree(OS_SYS_MEM_ADDR, dso->dlInfo);
LOS_MemFree(OS_SYS_MEM_ADDR, dso);
return NULL;
}
STATIC DynSharedObj *OsCheckHandle(VOID *handle)
{
DynSharedObj *dso = NULL;
LOS_DL_LIST_FOR_EACH_ENTRY(dso, &g_dynSharedObjLink, DynSharedObj, dsoNode) {
if (handle == dso) {
return dso;
}
}
return NULL;
}
VOID *LOS_FindSym(VOID *handle, const CHAR *name)
{
LD_ELF_SYM *sym = NULL;
DynSharedObj *dso = NULL;
VOID *symAddr = NULL;
if ((handle == NULL) || (name == NULL)) {
goto ERR;
}
(VOID)LOS_MuxPend(g_dynlinkMux, LOS_WAIT_FOREVER);
dso = OsCheckHandle(handle);
if (dso == NULL) {
(VOID)LOS_MuxPost(g_dynlinkMux);
goto ERR;
}
sym = OsFindSymInDso(dso->dlInfo, name);
if (sym == NULL) {
(VOID)LOS_MuxPost(g_dynlinkMux);
PRINT_ERR("failed to find symbol: %s\n", name);
errno = EFAULT;
return NULL;
}
symAddr = (VOID *)(dso->loadBase + sym->st_value);
(VOID)LOS_MuxPost(g_dynlinkMux);
return symAddr;
ERR:
PRINT_ERR("invalid input param\n");
errno = EINVAL;
return NULL;
}
STATIC VOID OsDoFini(DynSharedObj *dso)
{
InitFiniTab *initFiniTab = &dso->initFiniTab;
INIT_FINI_FUNC finiFunc = NULL;
UINTPTR *func = NULL;
UINT32 funcNum;
if (initFiniTab->fini.array != 0) {
funcNum = initFiniTab->fini.arraySz / sizeof(UINTPTR);
func = (UINTPTR *)(dso->loadBase + initFiniTab->fini.array) + funcNum;
while (funcNum--) {
--func;
finiFunc = (INIT_FINI_FUNC)(*func);
finiFunc();
}
}
if (initFiniTab->fini.func != 0) {
finiFunc = (INIT_FINI_FUNC)(dso->loadBase + initFiniTab->fini.func);
finiFunc();
}
}
INT32 LOS_SoUnload(VOID *handle)
{
DynSharedObj *dso = NULL;
if (handle == NULL) {
goto ERR;
}
(VOID)LOS_MuxPend(g_dynlinkMux, LOS_WAIT_FOREVER);
dso = OsCheckHandle(handle);
if (dso == NULL) {
(VOID)LOS_MuxPost(g_dynlinkMux);
goto ERR;
}
if (dso->ref > 1) {
--dso->ref;
(VOID)LOS_MuxPost(g_dynlinkMux);
return LOS_OK;
}
OsDoFini(dso);
LOS_ListDelete(&dso->dsoNode);
(VOID)LOS_MuxPost(g_dynlinkMux);
LOS_MemFree(dso->pool, (VOID *)dso->loadBase);
LOS_MemFree(OS_SYS_MEM_ADDR, dso->dlInfo);
LOS_MemFree(OS_SYS_MEM_ADDR, dso);
return LOS_OK;
ERR:
PRINT_ERR("invalid handle\n");
errno = EINVAL;
return LOS_NOK;
}
INT32 LOS_DynlinkInit(VOID)
{
UINT32 ret;
LOS_ListInit(&g_dynSharedObjLink);
ret = LOS_MuxCreate(&g_dynlinkMux);
if (ret != LOS_OK) {
return LOS_NOK;
}
return LOS_OK;
}
#endif /* LOSCFG_DYNLINK */
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */

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@@ -1,201 +0,0 @@
/*
* Copyright (c) 2021-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LOS_DYNLINK_H
#define _LOS_DYNLINK_H
#include "elf.h"
#include "los_compiler.h"
#include "los_list.h"
#include "los_memory.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#ifdef LOSCFG_AARCH64
typedef Elf64_Ehdr LD_ELF_EHDR;
typedef Elf64_Phdr LD_ELF_PHDR;
typedef Elf64_Sym LD_ELF_SYM;
typedef Elf64_Dyn LD_ELF_DYN;
typedef Elf64_Rel LD_ELF_REL;
typedef Elf64_Rela LD_ELF_RELA;
#define REL_TYPE(x) ELF64_R_TYPE(x)
#define REL_SYM(x) ELF64_R_SYM(x)
#define REL_INFO ELF64_R_INFO
#else
typedef Elf32_Ehdr LD_ELF_EHDR;
typedef Elf32_Phdr LD_ELF_PHDR;
typedef Elf32_Sym LD_ELF_SYM;
typedef Elf32_Dyn LD_ELF_DYN;
typedef Elf32_Rel LD_ELF_REL;
typedef Elf32_Rela LD_ELF_RELA;
#define REL_TYPE(x) ELF32_R_TYPE(x)
#define REL_SYM(x) ELF32_R_SYM(x)
#define REL_INFO ELF32_R_INFO
#endif
#define LD_ELFMAG "\177ELF"
#define LD_SELFMAG 4
#define PHDR_NUM_MAX 128
#define DYNAMIC_CNT 32
#define HASH_MASK 0xf0000000
#define WORD_SHIFT 4
#define HASH_SHIFT 24
#define BUCKET_IDX 2
#define ELF_ALIGN_UP(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
#define ELF_ALIGN_DOWN(a, b) ((a) & ~((b) - 1))
#define ELF_ALIGN_OFFSET(a, b) ((a) & ((b) - 1))
#ifndef PATH_MAX
#define PATH_MAX 256
#endif
#ifndef FILE_LENGTH_MAX
#define FILE_LENGTH_MAX 0x40000
#endif
typedef VOID (*INIT_FINI_FUNC)(VOID);
typedef struct {
UINTPTR relTab;
UINT32 relTabSize;
UINT32 relEntSize;
} RelocInfo;
typedef struct {
RelocInfo rel;
RelocInfo rela;
RelocInfo jmpRel;
} RelocInfoTab;
typedef struct {
UINTPTR func;
UINTPTR array;
UINT32 arraySz;
} InitFiniInfo;
typedef struct {
InitFiniInfo init;
InitFiniInfo fini;
} InitFiniTab;
typedef struct {
LD_ELF_EHDR elfEhdr;
LD_ELF_PHDR *elfPhdr;
UINTPTR dynBase;
UINT32 *hashTab;
LD_ELF_SYM *symTab;
CHAR *symStrings;
RelocInfoTab relInfoTab;
} DynLinkInfo;
typedef struct {
CHAR *fileName;
INT32 fd;
DynLinkInfo *dlInfo;
UINTPTR loadBase;
InitFiniTab initFiniTab;
LOS_DL_LIST dsoNode;
UINT32 ref;
VOID *pool;
CHAR buf[];
} DynSharedObj;
typedef struct {
CHAR *name;
UINTPTR addr;
} SymInfo;
#define SYM_EXPORT(func) \
const SymInfo sym_##func __attribute__((section(".sym."#func))) = { \
.name = #func, \
.addr = (UINTPTR)func \
};
/*
* @brief Load the shared library file named by the NULL-terminated string filename and
* return a valid handle for the loaded library.
*
* @param fileName The name pointer of shared library.
* @param pool The heap for shared library to load. If the parameter, pool, is NULL, then
* the dynamic loader & linker module will use the default heap and the pool is not NULL,
* then the shared library will be loaded to the heap by pool.
*
* @note When the heap, pool, is not NULL, you should call LOS_MemInit() to initialize the
* pool before calling LOS_SoLoad(). By the way, the system will comsume a certain amount
* of memory to initialize the pool. LOS_SoLoad must not be called in interrupt callback.
*
* @return Return NULL if error. Return non-NULL if success.
*/
VOID *LOS_SoLoad(const CHAR *fileName, VOID *pool);
/*
* @brief Get the address of symbol named by the parameter, name, from the parameter, handle.
*
* @param handle The handle for the loaded shared library.
* @param name The name of symbol to search.
*
* @note LOS_FindSym must not be called in interrupt callback.
*
* @return Return NULL if error. Return non-NULL if success.
*/
VOID *LOS_FindSym(VOID *handle, const CHAR *name);
/*
* @brief Decrement the reference count on the loaded shared library refered to by handle.
* If the reference count drops to zero, then the library is unloaded.
*
* This function validates that the handle is valid.
*
* @param handle The handle for the loaded shared library by LOS_SoLoad() interface.
*
* @note LOS_SoUnload must not be called in interrupt callback.
*
* @return Return 1 if error. Return 0 if success.
*/
INT32 LOS_SoUnload(VOID *handle);
/*
* @brief Initialization for dynamic loader & linker module.
*
* @param VOID.
*
* @return Return LOS_NOK if error. Return LOS_OK if success.
*/
INT32 LOS_DynlinkInit(VOID);
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _LOS_DYNLINK_H */

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@@ -1,65 +0,0 @@
#!/bin/bash
# Copyright (c) 2021-2021 Huawei Device Co., Ltd. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
# of conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
# Description: The script is used to calculate the memory size that the specified shared library
# will occupy when loading to the RAM.
READELF=readelf
RM=rm
SIZE=0x0
SIZE_ALL=0x0
SIZE_MAX=0
TMP_FILE=tmp.txt
if [ $# -lt 1 ]; then
echo "Usage: ./so_parse lib.so"
exit 1
fi
parse_line()
{
MEM_SIZE=$(echo $1 | awk '{print $6}')
echo ${MEM_SIZE}
}
${READELF} -l $1 | while read line; do
HEAD_STRING=$(echo ${line} | awk '{print $1}')
if [[ "${HEAD_STRING}" == *"LOAD"* ]]; then
SIZE=`parse_line "${line}"`
SIZE=`echo ${SIZE}`
SIZE_ALL=$((SIZE_ALL+SIZE))
fi
echo ${SIZE_ALL} >> ${TMP_FILE}
done
NEED_SIZE=`tail -n 1 ${TMP_FILE}`
echo "${NEED_SIZE} kb memory to reserve for $1!"
${RM} -f ${TMP_FILE}

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@@ -27,17 +27,15 @@
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
import("//kernel/liteos_m/liteos.gni")
module_switch = defined(LOSCFG_PLATFORM_EXC)
module_name = get_path_info(rebase_path("."), "name")
kernel_module(module_name) {
static_library("exchook") {
sources = [
"los_exc_info.c",
"los_exchook.c",
]
}
config("public") {
include_dirs = [ "." ]
include_dirs = [
"../../kernel/arch/include",
"../../kernel/include",
"../../utils",
"//third_party/bounds_checking_function/include",
]
}

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