!350 删除不合规的targets文件

Merge pull request !350 from lixilun/OpenHarmony_1.0.1_release

.gitee/ISSUE_TEMPLATE.zh-CN.md

@@ -0,0 +1,11 @@
+### 该问题是怎么引起的？
+
+
+
+### 重现步骤
+
+
+
+### 报错信息
+    
+    

.gitee/PULL_REQUEST_TEMPLATE.zh-CN.md

@@ -0,0 +1,12 @@
+### 相关的Issue
+    
+    
+### 原因（目的、解决的问题等）
+
+
+### 描述（做了什么，变更了什么）
+
+
+### 测试用例（新增、改动、可能影响的功能）
+    
+    

README.md

@@ -3,7 +3,6 @@
 -   [Introduction](#section11660541593)
 -   [Directory Structure](#section161941989596)
 -   [Constraints](#section119744591305)
--   [Usage](#section3732185231214)
 -   [Repositories Involved](#section1371113476307)
 
 ## Introduction<a name="section11660541593"></a>
@@ -39,29 +38,6 @@ Programming languages: C and C++
 
 Currently applicable architectures: Cortex-M3, Cortex-M4, Cortex-M7, and RISC-V
 
-## Usage<a name="section3732185231214"></a>
-
-LiteOS Cortex-M provides projects for three chip architectures, which are located in the  **targets**  directory. The methods of compiling and using these projects are as follows:
-
--   Cortex-M3:
-
-The  **kernel/liteos\_m/targets/cortex-m3\_stm32f103\_simulator\_keil**  directory is the Keil project directory created based on the STM32F103 chip architecture. You can download and install Keil development tools from the Internet. To compile the Cortex-M3 project, go to the  **cortex-m3\_stm32f103\_simulator\_keil/project**  directory and double-click the  **los\_demo.uvproj**  file to open the desired project. After the compilation is successful, burn the file to the corresponding board using JLINK or STM32 ST-LINK Utility.
-
--   Cortex-M4:
-
-The  **kernel/liteos\_m/targets/cortex-m4\_stm32f429ig\_fire-challenger\_iar**  directory is the IAR project directory created based on the STM32F429IG chip architecture. You can download and install IAR development tools from the Internet. To compile the Cortex-M4 project, go to the  **cortex-m4\_stm32f429ig\_fire-challenger\_iar/project**  directory and double-click the  **los\_demo.eww**  file to open the desired project. After the compilation is successful, burn the file to the corresponding board using JLINK or STM32 ST-LINK Utility.
-
--   Cortex-M7:
-
-The  **kernel/liteos\_m/targets/cortex-m7\_nucleo\_f767zi\_gcc**  directory is the Makefile project directory created based on the STM32F767ZI chip architecture. The compilation commands are as follows:
-
-```
-cd kernel/liteos_m/targets/cortex-m7_nucleo_f767zi_gcc
-make clean; make
-```
-
-After the compilation is successful, the executable file  **NUCLEO-F767.hex**  is generated in the  **cortex-m7\_nucleo\_f767zi\_gcc/build**  directory. Burn the file to the corresponding board using STM32 ST-LINK Utility.
-
 ## Change Log
 
 v1.0.1

README_zh.md

@@ -3,7 +3,6 @@
 -   [简介](#section11660541593)
 -   [目录](#section161941989596)
 -   [约束](#section119744591305)
--   [使用说明](#section3732185231214)
 -   [相关仓](#section1371113476307)
 
 ## 简介<a name="section11660541593"></a>
@@ -39,29 +38,6 @@ OpenHarmony LiteOS-M内核是面向IoT领域构建的轻量级物联网操作系
 
 适用架构：当前只适用于cortex-m3、cortex-m4、cortex-m7、risc-v芯片架构。
 
-## 使用说明<a name="section3732185231214"></a>
-
-LiteOS-M内核提供了三种芯片架构的工程位于targets目录。三种架构的工程编译及使用方式如下：
-
--   cortex-m3：
-
-kernel/liteos\_m/targets/cortex-m3\_stm32f103\_simulator\_keil目录是基于STM32F103芯片架构构建的keil工程目录，keil开发工具可通过网络下载并安装。进入cortex-m3\_stm32f103\_simulator\_keil/project目录，双击los\_demo.uvproj文件即可打开相应工程，编译成功后即可通过JLINK或者STM32 ST-LINK Utility烧录至对应单板。
-
--   cortex-m4：
-
-kernel/liteos\_m/targets/cortex-m4\_stm32f429ig\_fire-challenger\_iar目录是基于STM32F429IG芯片架构构建的IAR工程目录，IAR开发工具可通过网络下载并安装。进入cortex-m4\_stm32f429ig\_fire-challenger\_iar/project目录，双击los\_demo.eww文件即可打开相应工程，编译成功后即可通过JLINK或者STM32 ST-LINK Utility烧录至对应单板。
-
--   cortex-m7：
-
-kernel/liteos\_m/targets/cortex-m7\_nucleo\_f767zi\_gcc目录是基于STM32F767ZI芯片架构构建的Makefile工程目录。编译方式如下：
-
-```
-cd kernel/liteos_m/targets/cortex-m7_nucleo_f767zi_gcc
-make clean; make
-```
-
-编译成功后在cortex-m7\_nucleo\_f767zi\_gcc/build目录下生成NUCLEO-F767.hex可执行文件，通过烧录工具STM32 ST-LINK Utility烧录到对应的单板。
-
 ## 修改日志
 
 v1.0.1

components/backtrace/los_backtrace.c

@@ -125,7 +125,7 @@ STATIC INLINE UINT32 OsStackAddrGet(UINTPTR *stackStart, UINTPTR *stackEnd, UINT
             *stackEnd = (UINTPTR)taskCB->topOfStack + taskCB->stackSize;
             if ((SP < (UINTPTR)taskCB->topOfStack) || (SP >= *stackEnd)) {
                 PRINT_ERR("msp statck [0x%x, 0x%x], cur task stack [0x%x, 0x%x], cur sp(0x%x) is overflow!\n",
-                           CODE_START_ADDR, CSTACK_END_ADDR, (UINTPTR)taskCB->topOfStack, *stackEnd, SP);
+                          CODE_START_ADDR, CSTACK_END_ADDR, (UINTPTR)taskCB->topOfStack, *stackEnd, SP);
                 return LOS_NOK;
             }
         }
@@ -135,7 +135,7 @@ STATIC INLINE UINT32 OsStackAddrGet(UINTPTR *stackStart, UINTPTR *stackEnd, UINT
             *stackEnd = CSTACK_END_ADDR;
             if ((*stackStart < CODE_START_ADDR) || (*stackStart >= CSTACK_END_ADDR)) {
                 PRINT_ERR("msp stack [0x%x, 0x%x], cur sp(0x%x) is overflow!\n",
-                           CODE_START_ADDR, CSTACK_END_ADDR, *stackStart);
+                          CODE_START_ADDR, CSTACK_END_ADDR, *stackStart);
                 return LOS_NOK;
             }
             PRINTK("msp, start = %x, end = %x\n", *stackStart, *stackEnd);
@@ -146,7 +146,7 @@ STATIC INLINE UINT32 OsStackAddrGet(UINTPTR *stackStart, UINTPTR *stackEnd, UINT
             *stackEnd = (UINTPTR)taskCB->topOfStack + taskCB->stackSize;
             if ((*stackStart < (UINTPTR)taskCB->topOfStack) || (*stackStart >= *stackEnd)) {
                 PRINT_ERR("psp stack [0x%x, 0x%x], cur sp(0x%x) is overflow, cur task id is %d!\n",
-                           taskCB->topOfStack, *stackEnd, *stackStart, taskID);
+                          taskCB->topOfStack, *stackEnd, *stackStart, taskID);
                 return LOS_NOK;
             }
             PRINTK("psp, start = %x, end = %x\n", *stackStart, *stackEnd);

components/fs/fatfs/fs.c

@@ -44,6 +44,7 @@
 
 #ifdef LOSCFG_NET_LWIP_SACK
 #include "lwip/lwipopts.h"
+#include "lwip/sockets.h"
 #define CONFIG_NSOCKET_DESCRIPTORS  LWIP_CONFIG_NUM_SOCKETS
 #else
 #define CONFIG_NSOCKET_DESCRIPTORS  0

components/net/lwip-2.1/porting/include/arch/cc.h

@@ -32,19 +32,42 @@
 #ifndef _LWIP_PORTING_CC_H_
 #define _LWIP_PORTING_CC_H_
 
+#ifdef LITTLE_ENDIAN
+#undef LITTLE_ENDIAN
+#endif
+
+#ifdef BIG_ENDIAN
+#undef BIG_ENDIAN
+#endif
+
+#include <endian.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include "securec.h"
-#include "log.h"
+#include "memory_pool.h"
 
 #ifdef htons
 #define LWIP_DONT_PROVIDE_BYTEORDER_FUNCTIONS
 #endif
 
-#define LWIP_PROVIDE_ERRNO 1
-#define __SIZEOF_POINTER__ 4   // 32位系统
+#define SOCKLEN_T_DEFINED
+#define SA_FAMILY_T_DEFINED
+#define IN_PORT_T_DEFINED
 
-#define LOS_TASK_STATUS_DETACHED   0x0100  // 预留字段
+#define LWIP_TIMEVAL_PRIVATE    0
+#define LWIP_ERRNO_STDINCLUDE
+#define LWIP_SOCKET_STDINCLUDE
+
+#define LWIP_DNS_API_DEFINE_ERRORS    0
+#define LWIP_DNS_API_DEFINE_FLAGS     0
+#define LWIP_DNS_API_DECLARE_STRUCTS  0
+#define LWIP_DNS_API_DECLARE_H_ERRNO  0
+
+#ifndef __SIZEOF_POINTER__
+#define __SIZEOF_POINTER__ 4   // 32 bit system
+#endif
+
+#define LOS_TASK_STATUS_DETACHED   0x0100  // reserved
 
 #if defined(__arm__) && defined(__ARMCC_VERSION)
     /* Keil uVision4 tools */
@@ -96,7 +119,6 @@ extern void HilogPrintf(const char *fmt, ...);
 #define init_waitqueue_head(...)
 #define poll_check_waiters(...)
 #define IOCTL_CMD_CASE_HANDLER()
-#define DF_NADDR(addr)
 
 #define DNS_SERVER_ADDRESS(ipaddr)        (ip4_addr_set_u32(ipaddr, ipaddr_addr("114.114.114.114")))
 #define DNS_SERVER_ADDRESS_SECONDARY(ipaddr)        (ip4_addr_set_u32(ipaddr, ipaddr_addr("114.114.115.115")))

components/net/lwip-2.1/porting/include/arch/sys_arch.h

@@ -33,8 +33,6 @@
 #define _LWIP_PORTING_SYS_ARCH_H_
 
 #include <stdint.h>
-#include "memory_pool.h"
-#include "los_mux.h"
 
 #ifdef __cplusplus
 extern "C" {

components/net/lwip-2.1/porting/include/lwip/inet.h

@@ -1,71 +1,65 @@
-/*
- * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this list of
- *    conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice, this list
- *    of conditions and the following disclaimer in the documentation and/or other materials
- *    provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors may be used
- *    to endorse or promote products derived from this software without specific prior written
- *    permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "los_tick.h"
-#include "los_arch_interrupt.h"
-#include "stm324x9i_eval.h"
-
-/**
-  * @brief  Configures the USART Peripheral.
-  * @param  None
-  * @retval None
-  */
-void USART_Config(void)
-{
-  USART_InitTypeDef USART_InitStructure;
-
-  /* USARTx configured as follows:
-        - BaudRate = 115200 baud
-        - Word Length = 8 Bits
-        - One Stop Bit
-        - No parity
-        - Hardware flow control disabled (RTS and CTS signals)
-        - Receive and transmit enabled
-  */
-  USART_InitStructure.USART_BaudRate = 115200;
-  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-  USART_InitStructure.USART_StopBits = USART_StopBits_1;
-  USART_InitStructure.USART_Parity = USART_Parity_No;
-  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-  USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-
-  STM_EVAL_COMInit(COM1, &USART_InitStructure);
-}
-
-void SysTick_Handler(void)
-{
-    OsTickHandler();
-}
-
-void PendSV_Handler(void)
-{
-    HalPendSV();
-}
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LWIP_PORTING_INET_H_
+#define _LWIP_PORTING_INET_H_
+
+#include <arpa/inet.h>
+#include <netinet/in.h>
+#include_next <lwip/inet.h>
+
+#if LWIP_IPV4
+#define inet_addr_from_ip4addr(target_inaddr, source_ipaddr) \
+            ((target_inaddr)->s_addr = ip4_addr_get_u32(source_ipaddr))
+#define inet_addr_to_ip4addr(target_ipaddr, source_inaddr) \
+            (ip4_addr_set_u32(target_ipaddr, (source_inaddr)->s_addr))
+
+/* directly map this to the lwip internal functions */
+#define inet_addr(cp)                   ipaddr_addr(cp)
+#define inet_aton(cp, addr)             ip4addr_aton(cp, (ip4_addr_t*)addr)
+#define inet_ntoa(addr)                 ip4addr_ntoa((const ip4_addr_t*)&(addr))
+#define inet_ntoa_r(addr, buf, buflen)  ip4addr_ntoa_r((const ip4_addr_t*)&(addr), buf, buflen)
+#endif /* LWIP_IPV4 */
+#if LWIP_IPV6
+#define inet6_addr_from_ip6addr(target_in6addr, source_ip6addr) \
+            {(target_in6addr)->s6_addr32[0] = (source_ip6addr)->addr[0]; \
+            (target_in6addr)->s6_addr32[1] = (source_ip6addr)->addr[1]; \
+            (target_in6addr)->s6_addr32[2] = (source_ip6addr)->addr[2]; \
+            (target_in6addr)->s6_addr32[3] = (source_ip6addr)->addr[3];}
+#define inet6_addr_to_ip6addr(target_ip6addr, source_in6addr) \
+            {(target_ip6addr)->addr[0] = (source_in6addr)->s6_addr32[0]; \
+            (target_ip6addr)->addr[1] = (source_in6addr)->s6_addr32[1]; \
+            (target_ip6addr)->addr[2] = (source_in6addr)->s6_addr32[2]; \
+            (target_ip6addr)->addr[3] = (source_in6addr)->s6_addr32[3]; \
+            ip6_addr_clear_zone(target_ip6addr);}
+#endif /* LWIP_IPV6 */
+
+#endif /* _LWIP_PORTING_INET_H_ */

components/net/lwip-2.1/porting/include/lwip/lwipopts.h

@@ -134,8 +134,7 @@
 #define LWIP_NETIF_LOOPBACK             1
 #define LWIP_POSIX_SOCKETS_IO_NAMES     0
 #define LWIP_RAW                        1
-#define CONFIG_NFILE_DESCRIPTORS        1
-#define LWIP_SOCKET_OFFSET              CONFIG_NFILE_DESCRIPTORS
+#define LWIP_SOCKET_OFFSET              FAT_MAX_OPEN_FILES
 #define LWIP_SO_RCVBUF                  1
 #define LWIP_SO_RCVTIMEO                1
 #define LWIP_SO_SNDTIMEO                1

components/net/lwip-2.1/porting/include/lwip/netdb.h

@@ -1,39 +1,38 @@
-/*
- * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this list of
- *    conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice, this list
- *    of conditions and the following disclaimer in the documentation and/or other materials
- *    provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors may be used
- *    to endorse or promote products derived from this software without specific prior written
- *    permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __LITEOS_NETDB_PORTING_H__
-#define __LITEOS_NETDB_PORTING_H__
-
-#include "lwip/netdb.h"
-
-struct hostent *gethostbyname(const char *name);
-
-#endif // __LITEOS_NETDB_PORTING_H__
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LWIP_PORTING_NETDB_H_
+#define _LWIP_PORTING_NETDB_H_
+
+#include <netdb.h>
+#include_next <lwip/netdb.h>
+
+#endif /* _LWIP_PORTING_NETDB_H_ */

components/net/lwip-2.1/porting/include/lwip/netif.h

@@ -32,6 +32,9 @@
 #ifndef _LWIP_PORTING_NETIF_H_
 #define _LWIP_PORTING_NETIF_H_
 
+#include <net/if.h>
+#include <netinet/ip.h>
+
 #define netif_find netifapi_netif_find_by_name
 
 #if LWIP_DHCPS
@@ -39,12 +42,11 @@
                                             LWIP_NETIF_CLIENT_DATA_INDEX_DHCPS
 #endif
 
-#define LWIP_NETIF_FULLNAME 16
 #define linkoutput      linkoutput; \
                         void (*drv_send)(struct netif *netif, struct pbuf *p); \
                         u8_t (*drv_set_hwaddr)(struct netif *netif, u8_t *addr, u8_t len); \
                         void (*drv_config)(struct netif *netif, u32_t config_flags, u8_t setBit); \
-                        char full_name[LWIP_NETIF_FULLNAME]; \
+                        char full_name[IFNAMSIZ]; \
                         u16_t link_layer_type
 #include_next <lwip/netif.h>
 #undef linkoutput
@@ -52,7 +54,7 @@
 #undef LWIP_NETIF_CLIENT_DATA_INDEX_DHCP
 #endif
 
-#include <lwip/etharp.h> // For ETHARP_HWADDR_LEN, by `hieth-sf src/interface.c' and `wal/wal_net.c'
+#include <lwip/etharp.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -60,9 +62,9 @@ extern "C" {
 
 // redefine NETIF_NAMESIZE which was defined in netif.h
 #undef NETIF_NAMESIZE
-#define NETIF_NAMESIZE LWIP_NETIF_FULLNAME
+#define NETIF_NAMESIZE IFNAMSIZ
 
-#define LOOPBACK_IF         0 // 772
+#define LOOPBACK_IF         0
 #define ETHERNET_DRIVER_IF  1
 #define WIFI_DRIVER_IF      801
 #define BT_PROXY_IF         802

components/net/lwip-2.1/porting/include/lwip/sockets.h

@@ -1,79 +1,83 @@
-/*
- * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this list of
- *    conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice, this list
- *    of conditions and the following disclaimer in the documentation and/or other materials
- *    provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors may be used
- *    to endorse or promote products derived from this software without specific prior written
- *    permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef	_SYS_SOCKET_PORTING_H
-#define	_SYS_SOCKET_PORTING_H
-
-#include "lwip/sockets.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-int socket (int, int, int);
-
-int bind (int, const struct sockaddr *, socklen_t);
-int connect (int, const struct sockaddr *, socklen_t);
-int listen (int, int);
-int accept (int, struct sockaddr *__restrict, socklen_t *__restrict);
-
-int getsockname (int, struct sockaddr *__restrict, socklen_t *__restrict);
-int getpeername (int, struct sockaddr *__restrict, socklen_t *__restrict);
-
-ssize_t send (int, const void *, size_t, int);
-ssize_t recv (int, void *, size_t, int);
-ssize_t sendto (int, const void *, size_t, int, const struct sockaddr *, socklen_t);
-ssize_t recvfrom (int, void *__restrict, size_t, int, struct sockaddr *__restrict, socklen_t *__restrict);
-ssize_t sendmsg (int, const struct msghdr *, int);
-ssize_t recvmsg (int, struct msghdr *, int);
-
-int getsockopt (int, int, int, void *__restrict, socklen_t *__restrict);
-int setsockopt (int, int, int, const void *, socklen_t);
-
-const char *inet_ntop(int af, const void *src, char *dst, socklen_t size);
-int inet_pton(int af, const char *src, void *dst);
-
-int shutdown (int, int);
-int closesocket(int sockfd);
-
-int ioctlsocket(int s, long cmd, void *argp);
-
-#if LWIP_SOCKET_SELECT
-int select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, struct timeval *timeout);
-#endif
-#if LWIP_SOCKET_POLL
-int poll(struct pollfd *fds, nfds_t nfds, int timeout);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif
+/*
+ * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
+ * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ *    conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ *    of conditions and the following disclaimer in the documentation and/or other materials
+ *    provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without specific prior written
+ *    permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LWIP_PORTING_SOCKETS_H_
+#define _LWIP_PORTING_SOCKETS_H_
+
+#include <sys/socket.h>
+#include <poll.h>
+#include <netinet/tcp.h>
+#include <netinet/in.h>
+#include <sys/ioctl.h>
+#include <sys/select.h>
+#include <limits.h>
+#include <fcntl.h>
+#include_next <lwip/sockets.h>
+#include <fatfs.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if FD_SETSIZE < (LWIP_SOCKET_OFFSET + MEMP_NUM_NETCONN)
+#error "external FD_SETSIZE too small for number of sockets"
+#else
+#define LWIP_SELECT_MAXNFDS FD_SETSIZE
+#endif
+
+#if IOV_MAX > 0xFFFF
+#error "IOV_MAX larger than supported by LwIP"
+#endif
+
+#if LWIP_UDP && LWIP_UDPLITE
+#define UDPLITE_SEND_CSCOV 0x01 /* sender checksum coverage */
+#define UDPLITE_RECV_CSCOV 0x02 /* minimal receiver checksum coverage */
+#endif
+
+// For BSD 4.4 socket sa_len compatibility
+#define DF_NADDR(addr)
+#define SA_LEN(addr, _)  (IP_IS_V4_VAL(addr) ? sizeof(struct sockaddr_in) : sizeof(struct sockaddr_in6))
+#define sa_len sa_data[0] * 0 + SA_LEN(naddr, _)
+#define sin_len sin_zero[0]
+#define sin6_len sin6_addr.s6_addr[0]
+
+// for sockets.c, TCP_KEEPALIVE is not supported currently
+#define TCP_KEEPALIVE   0xFF
+#define SIN_ZERO_LEN    8
+
+int closesocket(int sockfd);
+int ioctlsocket(int s, long cmd, void *argp);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _LWIP_PORTING_SOCKETS_H_ */

components/net/lwip-2.1/porting/src/netdb_porting.c

@@ -29,7 +29,7 @@
  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "netdb.h"
+#include "lwip/netdb.h"
 
 struct hostent *gethostbyname(const char *name)
 {

components/net/lwip-2.1/porting/src/sys_arch.c

@@ -41,15 +41,15 @@
 #include <los_timer.h>
 #include <los_config.h>
 
-#define YES 1
-#define NO 0
-#define LOSCFG_KERNEL_SMP NO
+#ifndef LOSCFG_KERNEL_SMP
+#define LOSCFG_KERNEL_SMP 0
+#endif
 
-#if (LOSCFG_KERNEL_SMP == YES)
+#if (LOSCFG_KERNEL_SMP)
 SPIN_LOCK_INIT(arch_protect_spin);
 static u32_t lwprot_thread = LOS_ERRNO_TSK_ID_INVALID;
 static int lwprot_count = 0;
-#endif /* LOSCFG_KERNEL_SMP == YES */
+#endif /* LOSCFG_KERNEL_SMP */
 
 #define ROUND_UP_DIV(val, div) (((val) + (div) - 1) / (div))
 #define LWIP_LOG_BUF_SIZE 64
@@ -98,7 +98,7 @@ u32_t sys_now(void)
  */
 sys_prot_t sys_arch_protect(void)
 {
-#if (LOSCFG_KERNEL_SMP == YES)
+#if (LOSCFG_KERNEL_SMP)
     /* Note that we are using spinlock instead of mutex for LiteOS-SMP here:
      * 1. spinlock is more effective for short critical region protection.
      * 2. this function is called only in task context, not in interrupt handler.
@@ -116,14 +116,14 @@ sys_prot_t sys_arch_protect(void)
     }
 #else
     LOS_TaskLock();
-#endif /* LOSCFG_KERNEL_SMP == YES */
+#endif /* LOSCFG_KERNEL_SMP */
     return 0; /* return value is unused */
 }
 
 void sys_arch_unprotect(sys_prot_t pval)
 {
     LWIP_UNUSED_ARG(pval);
-#if (LOSCFG_KERNEL_SMP == YES)
+#if (LOSCFG_KERNEL_SMP)
     if (lwprot_thread == LOS_CurTaskIDGet()) {
         lwprot_count--;
         if (lwprot_count == 0) {
@@ -133,7 +133,7 @@ void sys_arch_unprotect(sys_prot_t pval)
     }
 #else
     LOS_TaskUnlock();
-#endif /* LOSCFG_KERNEL_SMP == YES */
+#endif /* LOSCFG_KERNEL_SMP */
 }
 
 /**

components/net/test/lwip_test.h

@@ -32,8 +32,10 @@
 #ifndef LWIP_TEST_H
 #define LWIP_TEST_H
 
+#include "lwip/arch.h"
+#include "lwip/sockets.h"
 #include <sys/socket.h>
-#include "log.h"
+#include <arpa/inet.h>
 #include "securec.h"
 
 #ifdef __cplusplus

components/net/test/net_socket_test_002.c

@@ -30,14 +30,18 @@
  */
 
 #include "lwip_test.h"
+#include "lwipopts.h"
+#include <arch/sys_arch.h>
+#include <lwip/sys.h>
 
 #define MSG "Hi, I am UDP"
 #define TEST_CASE 120
 
 static char g_buf[BUF_SIZE + 1] = { 0 };
 
-int UdpTest(void)
+void UdpTestTask(void *p)
 {
+    (void)p;
     LogPrintln("net_socket_test_002.c enter");
     g_testCase = TEST_CASE;
     int sfd;
@@ -111,6 +115,13 @@ int UdpTest(void)
     /* close socket */
     ret = closesocket(sfd);
     LWIP_ASSERT("socket invalid param.", ret != -1);
-    return LWIP_TEST_RET_OK;
+    return;
 }
 
+int UdpTest()
+{
+    int ret = sys_thread_new("udp_test", UdpTestTask, NULL,
+        STACK_TEST_SIZE, TCPIP_THREAD_PRIO);
+    ICUNIT_ASSERT_NOT_EQUAL(ret, -1, 23);
+    return ret;
+}

components/net/test/net_socket_test_003.c

@@ -39,7 +39,6 @@
 #define TEST_CASE 130
 
 static char g_buf[BUF_SIZE + 1] = { 0 };
-extern sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread, void *arg, int stackSize, int prio);
 
 static int SampleTcpServer()
 {

components/net/test/net_socket_test_007.c

@@ -40,7 +40,6 @@ static char g_buf_temp[BUF_SIZE + 1] = { 0 };
 #define SEND_UDP_COUNT 10000  // send count
 #define TEST_CASE 170
 
-extern sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread, void *arg, int stackSize, int prio);
 static void UdpTestMoreTask(void *p)
 {
     (void)p;

components/net/test/net_socket_test_008.c

@@ -41,8 +41,6 @@
 static char g_serverSendBuf[BUF_SIZE + 1] = { 0 };
 static char g_clientRecvBuf[BUF_SIZE + 1] = { 0 };
 
-extern sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread, void *arg, int stackSize, int prio);
-
 static void InitMsgBuf()
 {
     int i;

components/net/test/net_socket_test_009.c

@@ -43,8 +43,6 @@
 
 static char g_buf[BUF_SIZE + 1] = { 0 };
 
-extern sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread, void *arg, int stackSize, int prio);
-
 static int SampleTcpServer()
 {
 #if LWIP_SOCKET_SELECT

components/net/test/net_socket_test_010.c

@@ -43,8 +43,6 @@
 #define TIME_OUT (1000 * 10) // timeout 10s
 static char g_buf[BUF_SIZE + 1] = { 0 };
 
-extern sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread, void *arg, int stackSize, int prio);
-
 static int SampleTcpServer()
 {
 #if LWIP_SOCKET_POLL

components/net/test/net_socket_test_011.c

@@ -310,8 +310,9 @@ static struct netif *CreateBtNetIf()
     return btNetif;
 }
 
-int UdpTestNetif(void)
+static void UdpTestNetifTask(void *p)
 {
+    (void)p;
     LogPrintln("net_socket_test_011.c enter");
     g_testCase = TEST_CASE;
     int sfd;
@@ -363,7 +364,15 @@ int UdpTestNetif(void)
     /* close socket */
     ret = closesocket(sfd);
     LWIP_ASSERT("socket invalid param.", ret != -1);
-    return LWIP_TEST_RET_OK;
+    return;
+}
+
+int UdpTestNetif()
+{
+    int ret = sys_thread_new("udp_test_netif", UdpTestNetifTask, NULL,
+        STACK_TEST_SIZE, TCPIP_THREAD_PRIO);
+    ICUNIT_ASSERT_NOT_EQUAL(ret, -1, 23);
+    return ret;
 }
 
 static void ArpPackageProc(struct netif *netif, struct pbuf *p)

components/net/test/net_socket_test_012.c

@@ -45,7 +45,6 @@ static int g_portClient = STACK_PORT_TCP_DUP_START;
 
 static char g_bufServer[BUF_SIZE + 1] = { 0 };
 static char g_bufClient[BUF_SIZE + 1] = { 0 };
-extern sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread, void *arg, int stackSize, int prio);
 
 static int SampleTcpServer()
 {

components/net/test/net_socket_test_013.c

@@ -38,8 +38,6 @@
 #define STACK_PORT_TCP_LONG 2231
 #define TCP_LONG_BUF_SIZE (2 * 1024)
 
-extern sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread, void *arg, int stackSize, int prio);
-
 static int SampleTcpServer()
 {
     int sfd, lsfd;

components/net/test/test_main.c

@@ -119,7 +119,7 @@ static void LwipTestTimeoutCallback(void const *argument)
 
 osTimerId_t g_lwipTestTimerId = NULL;
 
-void LwipTestStartTimer(uint32 timeout)
+void LwipTestStartTimer(uint32_t timeout)
 {
     osStatus_t status;
     if (g_lwipTestTimerId != NULL) {

kal/cmsis/cmsis_liteos2.c

@@ -58,7 +58,12 @@ static osKernelState_t g_kernelState;
 
 extern BOOL g_taskScheduled;
 
-#define LOS_PRIORITY_WIN 8
+/* LOSCFG_BASE_CORE_TSK_DEFAULT_PRIO <---> osPriorityNormal */
+#define LOS_PRIORITY(cmsisPriority) (LOSCFG_BASE_CORE_TSK_DEFAULT_PRIO - ((cmsisPriority) - osPriorityNormal))
+#define CMSIS_PRIORITY(losPriority) (osPriorityNormal + (LOSCFG_BASE_CORE_TSK_DEFAULT_PRIO - (losPriority)))
+
+/* OS_TASK_PRIORITY_HIGHEST and OS_TASK_PRIORITY_LOWEST is reserved for internal TIMER and IDLE task use only. */
+#define ISVALID_LOS_PRIORITY(losPrio) ((losPrio) > OS_TASK_PRIORITY_HIGHEST && (losPrio) < OS_TASK_PRIORITY_LOWEST)
 
 const osVersion_t g_stLosVersion = { 001, 001 };
 
@@ -74,8 +79,6 @@ const osVersion_t g_stLosVersion = { 001, 001 };
 #define KERNEL_ID "HUAWEI-LiteOS"
 
 //  ==== Kernel Management Functions ====
-uint32_t osTaskStackWaterMarkGet(UINT32 taskID);
-
 
 osStatus_t osKernelInitialize(void)
 {
@@ -303,27 +306,28 @@ osThreadId_t osThreadNew(osThreadFunc_t func, void *argument, const osThreadAttr
     UINT32 uwTid;
     UINT32 uwRet;
     LosTaskCB *pstTaskCB = NULL;
-    TSK_INIT_PARAM_S stTskInitParam;
+    TSK_INIT_PARAM_S stTskInitParam = {NULL};
+    UINT16 usPriority;
 
-    if (OS_INT_ACTIVE) {
-        return NULL;
-    }
-
-    if ((attr == NULL) || (func == NULL) || (attr->priority < osPriorityLow1) ||
-        (attr->priority > osPriorityAboveNormal6)) {
+    if (OS_INT_ACTIVE || (func == NULL)) {
+        return (osThreadId_t)NULL;
+    }
+
+    usPriority = attr ? LOS_PRIORITY(attr->priority) : LOSCFG_BASE_CORE_TSK_DEFAULT_PRIO;
+    if (!ISVALID_LOS_PRIORITY(usPriority)) {
+        /* unsupported priority */
         return (osThreadId_t)NULL;
     }
 
-    (void)memset_s(&stTskInitParam, sizeof(TSK_INIT_PARAM_S), 0, sizeof(TSK_INIT_PARAM_S));
     stTskInitParam.pfnTaskEntry = (TSK_ENTRY_FUNC)func;
 #ifndef LITEOS_WIFI_IOT_VERSION
     stTskInitParam.uwArg = (UINT32)argument;
 #else
     stTskInitParam.auwArgs[0] = (UINT32)argument;
 #endif
-    stTskInitParam.uwStackSize = attr->stack_size;
-    stTskInitParam.pcName = (CHAR *)attr->name;
-    stTskInitParam.usTaskPrio = OS_TASK_PRIORITY_LOWEST - ((UINT16)(attr->priority) - LOS_PRIORITY_WIN); /* 0~31 */
+    stTskInitParam.uwStackSize = attr ? attr->stack_size : LOSCFG_BASE_CORE_TSK_DEFAULT_STACK_SIZE;
+    stTskInitParam.pcName = (CHAR *)(attr ? attr->name : "[NULL]");
+    stTskInitParam.usTaskPrio = usPriority;
 
     uwRet = LOS_TaskCreate(&uwTid, &stTskInitParam);
 
@@ -483,12 +487,12 @@ osStatus_t osThreadSetPriority(osThreadId_t thread_id, osPriority_t priority)
         return osErrorParameter;
     }
 
-    if (priority < osPriorityLow1 || priority > osPriorityAboveNormal6) {
+    usPriority = LOS_PRIORITY(priority);
+    if (!ISVALID_LOS_PRIORITY(usPriority)) {
         return osErrorParameter;
     }
 
     pstTaskCB = (LosTaskCB *)thread_id;
-    usPriority = OS_TASK_PRIORITY_LOWEST - ((UINT16)priority - LOS_PRIORITY_WIN);
     uwRet = LOS_TaskPriSet(pstTaskCB->taskID, usPriority);
     switch (uwRet) {
         case LOS_ERRNO_TSK_PRIOR_ERROR:
@@ -521,7 +525,7 @@ osPriority_t osThreadGetPriority(osThreadId_t thread_id)
         return osPriorityError;
     }
 
-    return (osPriority_t)(OS_TASK_PRIORITY_LOWEST - (usRet - LOS_PRIORITY_WIN));
+    return (osPriority_t)CMSIS_PRIORITY(usRet);
 }
 
 
@@ -891,7 +895,7 @@ uint32_t osEventFlagsGet(osEventFlagsId_t ef_id)
     uint32_t rflags;
 
     if (pstEventCB == NULL) {
-        return (uint32_t)osFlagsErrorParameter;
+        return 0;
     }
 
     uwIntSave = LOS_IntLock();

kal/posix/include/limits.h

@@ -5,6 +5,8 @@
 #define PATH_MAX 256
 #define MQ_PRIO_MAX 1
 #define PTHREAD_STACK_MIN LOSCFG_BASE_CORE_TSK_MIN_STACK_SIZE
+#define IOV_MAX 1024
+#define SSIZE_MAX LONG_MAX
 #include_next <limits.h>
 #else
 

kal/posix/musl_src/network/h_errno.c

@@ -0,0 +1,9 @@
+#include <netdb.h>
+
+#undef h_errno
+int h_errno;
+
+int *__h_errno_location(void)
+{
+    return &h_errno;
+}

kal/posix/src/pthread.c

@@ -97,7 +97,7 @@ int pthread_create(pthread_t *thread, const pthread_attr_t *attr,
     taskInitParam.pfnTaskEntry = PthreadEntry;
     taskInitParam.uwArg   = (UINT32)(UINTPTR)pthreadData;
 
-    if (LOS_TaskCreate(&taskID, &taskInitParam) != LOS_OK) {
+    if (LOS_TaskCreateOnly(&taskID, &taskInitParam) != LOS_OK) {
         free(pthreadData);
         return EINVAL;
     }
@@ -105,6 +105,8 @@ int pthread_create(pthread_t *thread, const pthread_attr_t *attr,
     /* set pthread default name */
     (void)sprintf_s(taskInitParam.pcName, PTHREAD_NAMELEN, "pthread%u", taskID);
 
+    (void)LOS_TaskResume(taskID);
+
     *thread = (pthread_t)taskID;
     return 0;
 }

kal/posix/src/time.c

@@ -55,16 +55,15 @@ STATIC const UINT16 g_daysInMonth[2][13] = {
 
 STATIC const UINT8 g_montbl[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
 
-static UINT64 g_rtcTimeBase = 0;
-static UINT64 g_systickBase = 0;
-
 /*
- * Time zone information, stored in minutes,
+ * Time zone information, stored in seconds,
  * negative values indicate the east of UTC,
  * positive values indicate the west of UTC.
  */
-static INT32 g_rtcTimeZone = -480;
-static struct tm g_tm = {0};
+long timezone = -8 * 60 * 60; // defaults to CST: 8 hours east of the Prime Meridian
+
+/* internal shared struct tm object for localtime and gmtime */
+static struct tm g_tm;
 
 int nanosleep(const struct timespec *rqtp, struct timespec *rmtp)
 {
@@ -405,33 +404,28 @@ int clock_nanosleep(clockid_t clk, int flags, const struct timespec *req, struct
 
 clock_t clock(void)
 {
-    return HalGetExpandTick();
+    clock_t clk;
+    struct timespec hwTime;
+    OsGetHwTime(&hwTime);
+
+    clk = hwTime.tv_sec * CLOCKS_PER_SEC;
+    clk += hwTime.tv_nsec  / (OS_SYS_NS_PER_SECOND / CLOCKS_PER_SEC);
+
+    return clk;
 }
 
 time_t time(time_t *timer)
 {
-    UINT64 usec = 0;
-    time_t sec;
-    INT32 rtcRet;
+    struct timespec ts;
 
-    rtcRet = HalGetRtcTime(&usec);
-    if (rtcRet != 0) {
-        UINT64 currentTime;
-        UINT64 tickDelta;
-        UINT64 currentTick = HalGetExpandTick();
-        if ((g_systickBase != 0) && (currentTick > g_systickBase)) {
-            tickDelta = currentTick - g_systickBase;
-        }
-        currentTime = g_rtcTimeBase + tickDelta;
-        sec = currentTime / OS_SYS_MS_PER_SECOND;
-    } else {
-        sec = usec / OS_SYS_US_PER_SECOND;
+    if (-1 == clock_gettime(CLOCK_REALTIME, &ts)) {
+        return (time_t)-1;
     }
 
     if (timer != NULL) {
-        *timer = sec;
+        *timer = ts.tv_sec;
     }
-    return sec;
+    return ts.tv_sec;
 }
 
 /*
@@ -494,23 +488,23 @@ static INT32 ConvertSecs2Utc(time_t t, INT32 offset, struct tm *tp)
     days -= daysInMonth[month];
     tp->tm_mon = month;
     tp->tm_mday = days + 1;
+    tp->__tm_gmtoff = offset;
+    tp->__tm_zone = NULL;
+    tp->tm_isdst = 0;
     return 1;
 }
 
-struct tm *gmtime_r(const time_t *timer, struct tm *tp)
+struct tm *gmtime_r(const time_t *timep, struct tm *result)
 {
-    time_t t64;
-    UINT32 intSave;
-    if ((timer == NULL) || (tp == NULL)) {
+    if ((timep == NULL) || (result == NULL)) {
+        errno = EFAULT;
         return NULL;
     }
-    intSave = LOS_IntLock();
-    t64 = *timer;
-    if (!ConvertSecs2Utc(t64, 0, tp)) {
-        tp = NULL;
+    if (!ConvertSecs2Utc(*timep, 0, result)) {
+        errno = EINVAL;
+        return NULL;
     }
-    (void)LOS_IntRestore(intSave);
-    return tp;
+    return result;
 }
 
 struct tm *gmtime(const time_t *timer)
@@ -518,22 +512,17 @@ struct tm *gmtime(const time_t *timer)
     return gmtime_r(timer, &g_tm);
 }
 
-struct tm *localtime_r(const time_t *timer, struct tm *tp)
+struct tm *localtime_r(const time_t *timep, struct tm *result)
 {
-    UINT32 intSave;
-    time_t t64;
-    INT32 offset;
-    if ((timer == NULL) || (tp == NULL)) {
+    if ((timep == NULL) || (result == NULL)) {
+        errno = EFAULT;
         return NULL;
     }
-    intSave = LOS_IntLock();
-    t64 = *timer;
-    offset = -(g_rtcTimeZone * SECS_PER_MIN);
-    if (!ConvertSecs2Utc(t64, offset, tp)) {
-        tp = NULL;
+    if (!ConvertSecs2Utc(*timep, -timezone, result)) {
+        errno = EINVAL;
+        return NULL;
     }
-    (void)LOS_IntRestore(intSave);
-    return tp;
+    return result;
 }
 
 struct tm *localtime(const time_t *timer)
@@ -569,78 +558,90 @@ static time_t ConvertUtc2Secs(struct tm *tm)
     }
 
     seconds += (tm->tm_mday - 1) * SECS_PER_DAY;
-
     seconds += tm->tm_hour * SECS_PER_HOUR + tm->tm_min * SECS_PER_MIN + tm->tm_sec;
 
+    seconds -= tm->__tm_gmtoff; // sub time zone to get UTC time
     return seconds;
 }
 
 time_t mktime(struct tm *tmptr)
 {
-    struct tm tempTime;
     time_t timeInSeconds;
     if (tmptr == NULL) {
-        return 0;
+        errno = EFAULT;
+        return (time_t)-1;
     }
-    if (tmptr->tm_year < (EPOCH_YEAR - TM_YEAR_BASE)) {
-        return 0;
+
+    /* tm_isdst is not supported and is ignored */
+    if (tmptr->tm_year < (EPOCH_YEAR - TM_YEAR_BASE) ||
+            tmptr->__tm_gmtoff > (-TIME_ZONE_MIN * SECS_PER_MIN) ||
+            tmptr->__tm_gmtoff < (-TIME_ZONE_MAX * SECS_PER_MIN) ||
+            tmptr->tm_sec > 60 || tmptr->tm_sec < 0 ||      /* Seconds [0-60] */
+            tmptr->tm_min > 59 || tmptr->tm_min < 0 ||      /* Minutes [0-59] */
+            tmptr->tm_hour > 23 || tmptr->tm_hour < 0 ||    /* Hours [0-23] */
+            tmptr->tm_mday > 31 || tmptr->tm_mday < 1 ||    /* Day of the month [1-31] */
+            tmptr->tm_mon > 11 || tmptr->tm_mon < 0) {      /* Month [0-11] */
+        errno = EOVERFLOW;
+        return (time_t)-1;
     }
-    tempTime = *tmptr;
-    timeInSeconds = ConvertUtc2Secs(&tempTime);
-    timeInSeconds += g_rtcTimeZone * SECS_PER_MIN;
+    timeInSeconds = ConvertUtc2Secs(tmptr);
+    /* normalize tm_wday and tm_yday */
+    ConvertSecs2Utc(timeInSeconds, tmptr->__tm_gmtoff, tmptr);
     return timeInSeconds;
 }
 
 int gettimeofday(struct timeval *tv, void *ptz)
 {
-    INT32 rtcRet;
-    INT32 timeZone = 0;
-    UINT64 usec = 0;
-    UINT64 currentTime;
-    UINT64 tickDelta = 0;
-    UINT64 currentTick;
-
+    struct timespec ts;
     struct timezone *tz = (struct timezone *)ptz;
-    if ((tv == NULL) && (tz == NULL)) {
-        return -1;
-    }
+
     if (tv != NULL) {
-        rtcRet = HalGetRtcTime(&usec);
-        if (rtcRet != 0) {
-            currentTick = HalGetExpandTick();
-            if ((g_systickBase != 0) && (currentTick > g_systickBase)) {
-                tickDelta = currentTick - g_systickBase;
-            }
-            currentTime = g_rtcTimeBase + tickDelta;
-            tv->tv_sec = currentTime / OS_SYS_MS_PER_SECOND;
-            tv->tv_usec = (currentTime % OS_SYS_MS_PER_SECOND) * OS_SYS_MS_PER_SECOND;
-        } else {
-            tv->tv_sec = usec / OS_SYS_US_PER_SECOND;
-            tv->tv_usec = usec % OS_SYS_US_PER_SECOND;
+        if (-1 == clock_gettime(CLOCK_REALTIME, &ts)) {
+            return -1;
         }
+        tv->tv_sec = ts.tv_sec;
+        tv->tv_usec = ts.tv_nsec / OS_SYS_NS_PER_US;
     }
-    HalGetRtcTimeZone(&timeZone);
     if (tz != NULL) {
-        tz->tz_minuteswest = timeZone;
+        tz->tz_minuteswest = timezone / SECS_PER_MIN;
+        tz->tz_dsttime = 0;
     }
     return 0;
 }
 
 int settimeofday(const struct timeval *tv, const struct timezone *tz)
 {
-    UINT64 usec;
-    if ((tv == NULL) || (tz == NULL)) {
+    struct timespec ts;
+    INT32 rtcTimeZone = timezone;
+
+    if (tv == NULL) {
+        errno = EFAULT;
         return -1;
     }
-    g_rtcTimeBase = tv->tv_sec * OS_SYS_MS_PER_SECOND + tv->tv_usec / OS_SYS_MS_PER_SECOND;
-    g_systickBase = HalGetExpandTick();
-    if ((tz->tz_minuteswest > TIME_ZONE_MIN) &&
-        (tz->tz_minuteswest < TIME_ZONE_MAX)) {
-        g_rtcTimeZone = tz->tz_minuteswest;
+
+    if (tz != NULL) {
+        if ((tz->tz_minuteswest >= TIME_ZONE_MIN) &&
+            (tz->tz_minuteswest <= TIME_ZONE_MAX)) {
+            rtcTimeZone = tz->tz_minuteswest * SECS_PER_MIN;
+        } else {
+            errno = EINVAL;
+            return -1;
+        }
     }
-    usec = tv->tv_sec * OS_SYS_US_PER_SECOND + tv->tv_usec;
-    HalSetRtcTime(g_rtcTimeBase, &usec);
-    HalSetRtcTimeZone(g_rtcTimeZone);
+
+    if (tv->tv_usec >= OS_SYS_US_PER_SECOND) {
+        errno = EINVAL;
+        return -1;
+    }
+
+    ts.tv_sec = tv->tv_sec;
+    ts.tv_nsec = tv->tv_usec * OS_SYS_NS_PER_US;
+    if (-1 == clock_settime(CLOCK_REALTIME, &ts)) {
+        return -1;
+    }
+
+    timezone = rtcTimeZone;
+
     return 0;
 }
 
@@ -652,4 +653,4 @@ int usleep(unsigned useconds)
     specTime.tv_sec = (time_t)(nanoseconds / OS_SYS_NS_PER_SECOND);
     specTime.tv_nsec = (long)(nanoseconds % OS_SYS_NS_PER_SECOND);
     return nanosleep(&specTime, NULL);
-}
+}

kal/posix/src/time_internal.h

@@ -61,8 +61,8 @@
 #define DAYS_PER_NORMAL_YEAR 365
 #define DAYS_PER_LEAP_YEAR   366
 #define BEGIN_WEEKDAY        4
-#define TIME_ZONE_MAX        720 /* 12 * 60 */
-#define TIME_ZONE_MIN        (-840) /* -14 * 60 */
+#define TIME_ZONE_MAX        720 /* UTC-12:00 , the last time zone */
+#define TIME_ZONE_MIN        (-840) /* UTC+14:00 , the first time zone */
 
 /*
  * Nonzero if YEAR is a leap year (every 4 years,
@@ -72,14 +72,6 @@
 #define IS_LEAP_YEAR(year) \
     (((year) % 4 == 0) && (((year) % 100 != 0) || ((year) % 400 == 0)))
 #endif
-/* The lowest two bytes indicate minutes of the time zone */
-#ifndef OFFSET_TO_MINUTE
-#define OFFSET_TO_MINUTE(time) (((time) < 0) ? (-(time)) : (time))
-#endif
-/* The highest 31 bytes, 1 indicates eastern time zone<6E><65>? indicates western time zone */
-#ifndef TIME_ZONE_SIGN
-#define TIME_ZONE_SIGN(time) ((time) >> 31)
-#endif
 
 #define DIV(a, b) (((a) / (b)) - ((a) % (b) < 0))
 #define LEAPS_THRU_END_OF(y) (DIV (y, 4) - DIV (y, 100) + DIV (y, 400))

kernel/arch/arm/cortex-m3/keil/cmsis/core_cmFunc.h

@@ -52,9 +52,6 @@
   #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
 #endif
 
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
 /** \brief  Get Control Register
 
     This function returns the content of the Control Register.

kernel/arch/arm/cortex-m3/keil/los_timer.c

@@ -223,36 +223,6 @@ VOID HalEnterSleep(LOS_SysSleepEnum sleep)
 	__ISB();
 }
 
-WEAK VOID HalDelay(UINT32 ticks)
-{
-
-}
-
-WEAK UINT64 HalGetExpandTick(VOID)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalGetRtcTime(UINT64 *usec)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalGetRtcTimeZone(INT32 *timeZone)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalSetRtcTime(UINT64 utcTime, UINT64 *usec)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalSetRtcTimeZone(INT32 timeZone)
-{
-    return LOS_OK;
-}
-
 #ifdef __cplusplus
 #if __cplusplus
 }

kernel/arch/arm/cortex-m33/gcc/los_timer.c

@@ -213,11 +213,6 @@ VOID HalEnterSleep(LOS_SysSleepEnum sleep)
 	__ISB();
 }
 
-WEAK VOID HalDelay(UINT32 ticks)
-{
-
-}
-
 #ifdef __cplusplus
 #if __cplusplus
 }

kernel/arch/arm/cortex-m4/gcc/los_timer.c

@@ -222,36 +222,6 @@ VOID HalEnterSleep(LOS_SysSleepEnum sleep)
     __ISB();
 }
 
-WEAK VOID HalDelay(UINT32 ticks)
-{
-    return;
-}
-
-WEAK UINT64 HalGetExpandTick(VOID)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalGetRtcTime(UINT64 *usec)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalGetRtcTimeZone(INT32 *timeZone)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalSetRtcTime(UINT64 utcTime, UINT64 *usec)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalSetRtcTimeZone(INT32 timeZone)
-{
-    return LOS_OK;
-}
-
 #ifdef __cplusplus
 #if __cplusplus
 }

kernel/arch/arm/cortex-m4/iar/los_timer.c

@@ -222,36 +222,6 @@ VOID HalEnterSleep(LOS_SysSleepEnum sleep)
     __ISB();
 }
 
-WEAK VOID HalDelay(UINT32 ticks)
-{
-    return;
-}
-
-WEAK UINT64 HalGetExpandTick(VOID)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalGetRtcTime(UINT64 *usec)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalGetRtcTimeZone(INT32 *timeZone)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalSetRtcTime(UINT64 utcTime, UINT64 *usec)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalSetRtcTimeZone(INT32 timeZone)
-{
-    return LOS_OK;
-}
-
 #ifdef __cplusplus
 #if __cplusplus
 }

kernel/arch/arm/cortex-m7/gcc/los_timer.c

@@ -222,36 +222,6 @@ VOID HalEnterSleep(LOS_SysSleepEnum sleep)
 	__ISB();
 }
 
-WEAK VOID HalDelay(UINT32 ticks)
-{
-
-}
-
-WEAK UINT64 HalGetExpandTick(VOID)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalGetRtcTime(UINT64 *usec)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalGetRtcTimeZone(INT32 *timeZone)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalSetRtcTime(UINT64 utcTime, UINT64 *usec)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalSetRtcTimeZone(INT32 timeZone)
-{
-    return LOS_OK;
-}
-
 #ifdef __cplusplus
 #if __cplusplus
 }

kernel/arch/arm/cortex-m7/iar/los_timer.c

@@ -222,36 +222,6 @@ VOID HalEnterSleep(LOS_SysSleepEnum sleep)
 	__ISB();
 }
 
-WEAK VOID HalDelay(UINT32 ticks)
-{
-
-}
-
-WEAK UINT64 HalGetExpandTick(VOID)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalGetRtcTime(UINT64 *usec)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalGetRtcTimeZone(INT32 *timeZone)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalSetRtcTime(UINT64 utcTime, UINT64 *usec)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalSetRtcTimeZone(INT32 timeZone)
-{
-    return LOS_OK;
-}
-
 #ifdef __cplusplus
 #if __cplusplus
 }

kernel/arch/include/los_timer.h

@@ -69,38 +69,6 @@ VOID HalEnterSleep(LOS_SysSleepEnum sleep);
 
 VOID HalDelay(UINT32 ticks);
 
-UINT64 HalGetExpandTick(VOID);
-
-INT32 HalGetRtcTime(UINT64 *usec);
-
-INT32 HalGetRtcTimeZone(INT32 *timeZone);
-
-INT32 HalSetRtcTime(UINT64 utcTime, UINT64 *usec);
-
-INT32 HalSetRtcTimeZone(INT32 timeZone);
-
- /**
- * @ingroup los_timer
- * @brief Configure Tick Interrupt Start.
- *
- * @par Description:
- * This API is used to configure Tick Interrupt Start while macro LOSCFG_BASE_CORE_TICK_HW_TIME is No.
- *
- * @attention
- * <ul>
- * <li>None.</li>
- * </ul>
- *
- * @param: None.
- *
- * @retval #LOS_OK                               0:configure Tick Interrupt success.
- * @retval #LOS_ERRNO_TICK_CFG_INVALID           0x02000400:configure Tick Interrupt failed.
- *
- * @par Dependency:
- * <ul><li>los_config.h: the header file that contains the API declaration.</li></ul>
- * @see
- */
-
 /**
  * @ingroup los_hwi
  * @brief reconfig systick, and clear SysTick_IRQn.
@@ -218,4 +186,4 @@ extern VOID HalTicklessDisable(VOID);
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-#endif
+#endif

kernel/arch/risc-v/riscv32/gcc/los_timer.c

@@ -41,7 +41,6 @@ extern "C" {
 #endif /* __cplusplus */
 #endif /* __cplusplus */
 
-#define NS_PER_SECOND  1000000000.0
 
 WEAK UINT32 HalTickStart(OS_TICK_HANDLER handler)
 {
@@ -67,36 +66,6 @@ LITE_OS_SEC_TEXT_MINOR VOID HalGetCpuCycle(UINT32 *cntHi, UINT32 *cntLo)
     return;
 }
 
-WEAK VOID HalDelay(UINT32 ticks)
-{
-
-}
-
-WEAK UINT64 HalGetExpandTick(VOID)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalGetRtcTime(UINT64 *usec)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalGetRtcTimeZone(INT32 *timeZone)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalSetRtcTime(UINT64 utcTime, UINT64 *usec)
-{
-    return LOS_OK;
-}
-
-WEAK INT32 HalSetRtcTimeZone(INT32 timeZone)
-{
-    return LOS_OK;
-}
-
 #ifdef __cplusplus
 #if __cplusplus
 }

kernel/include/los_config.h

@@ -502,6 +502,14 @@ extern UINT8 *m_aucSysMem0;
 #define OS_SYS_NOCACHEMEM_ADDR                              (&g_sysNoCacheMem0[0])
 #endif
 
+/**
+ * @ingroup los_config
+ * Configuration of multiple non-continuous memory regions as one memory pool
+ */
+#ifndef LOSCFG_MEM_MUL_REGIONS
+#define LOSCFG_MEM_MUL_REGIONS                              0
+#endif
+
 /* =============================================================================
                                         Exception module configuration
 ============================================================================= */

kernel/include/los_memory.h

@@ -120,6 +120,47 @@ extern UINT32 LOS_MemDeInit(VOID *pool);
 extern UINT32 LOS_MemPoolList(VOID);
 #endif
 
+#if (LOSCFG_MEM_MUL_REGIONS == 1)
+typedef struct {
+    VOID *startAddress;
+    UINT32 length;
+} LosMemRegion;
+
+/**
+ * @ingroup los_memory
+ * @brief Initialize multiple non-continuous memory regions.
+ *
+ * @par Description:
+ * <ul>
+ * <li>This API is used to initialize multiple non-continuous memory regions. If the starting address of a pool is specified,
+ *  the memory regions will be linked to the pool as free nodes. Otherwise, the first memory region will be initialized as a 
+ *  new pool, and the rest regions will be linked as free nodes to the new pool.</li>
+ * </ul>
+ *
+ * @attention
+ * <ul>
+ * <li>If the starting address of a memory pool is specified, the start address of the non-continuous memory regions should be
+ *  greater than the end address of the memory pool.</li>
+ * <li>The multiple non-continuous memory regions shouldn't conflict with each other.</li>
+ * </ul>
+ *
+ * @param pool           [IN] The memory pool address. If NULL is specified, the start address of first memory region will be 
+ *                            initialized as the memory pool address. If not NULL, it should be a valid address of a memory pool.
+ * @param memRegions     [IN] The LosMemRegion array that contains multiple non-continuous memory regions. The start address
+ *                           of the memory regions are placed in ascending order.
+ * @param memRegionCount [IN] The count of non-continuous memory regions, and it should be the length of the LosMemRegion array.
+ *
+ * @retval #LOS_NOK    The multiple non-continuous memory regions fails to be initialized.
+ * @retval #LOS_OK     The multiple non-continuous memory regions is initialized successfully.
+ * @par Dependency:
+ * <ul>
+ * <li>los_memory.h: the header file that contains the API declaration.</li>
+ * </ul>
+ * @see None.
+ */
+extern UINT32 LOS_MemRegionsAdd(VOID *pool, const LosMemRegion * const memRegions, UINT32 memRegionCount);
+#endif
+
 /**
  * @ingroup los_memory
  * Memory pool extern information structure

kernel/src/los_init.c

@@ -192,14 +192,6 @@ LITE_OS_SEC_TEXT_INIT UINT32 LOS_KernelInit(VOID)
     }
 #endif
 
-#ifdef LOSCFG_TEST
-    //ret = los_TestInit();
-    //if (ret != LOS_OK) {
-    //    PRINT_ERR("los_TestInit error\n");
-    //    return ret;
-    //}
-#endif
-
 #if (LOSCFG_PLATFORM_EXC == 1)
     OsExcMsgDumpInit();
 #endif

kernel/src/los_task.c

@@ -545,9 +545,9 @@ LITE_OS_SEC_TEXT_MINOR UINT32 OsGetAllTskInfo(VOID)
         }
 
         PRINTK("%d    %d    %s    0x%x    0x%x    0x%x    0x%x    0x%x    ",
-                  taskCB->taskID, taskCB->priority, OsConvertTskStatus(taskCB->taskStatus),
-                  taskCB->stackSize, OsGetTaskWaterLine(taskCB->taskID),
-                  (UINT32)(UINTPTR)taskCB->stackPointer, taskCB->topOfStack, taskCB->eventMask);
+               taskCB->taskID, taskCB->priority, OsConvertTskStatus(taskCB->taskStatus),
+               taskCB->stackSize, OsGetTaskWaterLine(taskCB->taskID),
+               (UINT32)(UINTPTR)taskCB->stackPointer, taskCB->topOfStack, taskCB->eventMask);
 
         semID = (taskCB->taskSem == NULL) ? OS_NULL_SHORT : (((LosSemCB *)taskCB->taskSem)->semID);
         PRINTK("0x%x    ", semID);

kernel/src/mm/los_memory.c

@@ -156,6 +156,9 @@ struct OsMemPoolInfo {
     UINT32 waterLine;   /* Maximum usage size in a memory pool */
     UINT32 curUsedSize; /* Current usage size in a memory pool */
 #endif
+#if (LOSCFG_MEM_MUL_REGIONS == 1)
+    UINT32 totalGapSize;
+#endif
 };
 
 struct OsMemPoolHead {
@@ -276,6 +279,20 @@ STATIC INLINE UINT32 OsMemAllocCheck(struct OsMemPoolHead *pool, UINT32 intSave)
 #define OS_MEM_MAGIC_VALID(node)    TRUE
 #endif
 
+#if (LOSCFG_MEM_MUL_REGIONS == 1)
+/**
+ *  When LOSCFG_MEM_MUL_REGIONS is enabled to support multiple non-continuous memory regions, the gap between two memory regions 
+ *  is marked as a used OsMemNodeHead node. The gap node couldn't be freed, and would also be skipped in some DFX functions. The 
+ *  'ptr.prev' pointer of this node is set to OS_MEM_GAP_NODE_MAGIC to identify that this is a gap node.
+*/
+#define OS_MEM_GAP_NODE_MAGIC       0xDCBAABCD
+#define OS_MEM_MARK_GAP_NODE(node)  (((struct OsMemNodeHead *)(node))->ptr.prev = (struct OsMemNodeHead *)OS_MEM_GAP_NODE_MAGIC)
+#define OS_MEM_IS_GAP_NODE(node)    (((struct OsMemNodeHead *)(node))->ptr.prev == (struct OsMemNodeHead *)OS_MEM_GAP_NODE_MAGIC)
+#else
+#define OS_MEM_MARK_GAP_NODE(node)
+#define OS_MEM_IS_GAP_NODE(node)    FALSE
+#endif
+
 STATIC INLINE VOID OsMemFreeNodeAdd(VOID *pool, struct OsMemFreeNodeHead *node);
 STATIC INLINE UINT32 OsMemFree(struct OsMemPoolHead *pool, struct OsMemNodeHead *node);
 STATIC VOID OsMemInfoPrint(VOID *pool);
@@ -514,8 +531,8 @@ STATIC INLINE VOID OsMemUsedNodePrint(struct OsMemNodeHead *node)
 {
     UINT32 count;
 
-    if (OS_MEM_NODE_GET_USED_FLAG(node->sizeAndFlag)) {
-        PRINTK("0x%x: 0x%x ", node, OS_MEM_NODE_GET_SIZE(node->sizeAndFlag));
+    if (OS_MEM_NODE_GET_USED_FLAG(node->sizeAndFlag) && !OS_MEM_IS_GAP_NODE(node)) {
+        PRINTK("0x%x: 0x%x ", (UINTPTR)node, OS_MEM_NODE_GET_SIZE(node->sizeAndFlag));
         for (count = 0; count < LOSCFG_MEM_RECORD_LR_CNT; count++) {
             PRINTK(" 0x%x ", node->linkReg[count]);
         }
@@ -751,7 +768,7 @@ STATIC INLINE VOID OsMemMergeNode(struct OsMemNodeHead *node)
 
     node->ptr.prev->sizeAndFlag += node->sizeAndFlag;
     nextNode = (struct OsMemNodeHead *)((UINTPTR)node + node->sizeAndFlag);
-    if (!OS_MEM_NODE_GET_LAST_FLAG(nextNode->sizeAndFlag)) {
+    if (!OS_MEM_NODE_GET_LAST_FLAG(nextNode->sizeAndFlag) && !OS_MEM_IS_GAP_NODE(nextNode)) {
         nextNode->ptr.prev = node->ptr.prev;
     }
 }
@@ -766,7 +783,7 @@ STATIC INLINE VOID OsMemSplitNode(VOID *pool, struct OsMemNodeHead *allocNode, U
     newFreeNode->header.sizeAndFlag = allocNode->sizeAndFlag - allocSize;
     allocNode->sizeAndFlag = allocSize;
     nextNode = OS_MEM_NEXT_NODE(&newFreeNode->header);
-    if (!OS_MEM_NODE_GET_LAST_FLAG(nextNode->sizeAndFlag)) {
+    if (!OS_MEM_NODE_GET_LAST_FLAG(nextNode->sizeAndFlag) && !OS_MEM_IS_GAP_NODE(nextNode)) {
         nextNode->ptr.prev = &newFreeNode->header;
         if (!OS_MEM_NODE_GET_USED_FLAG(nextNode->sizeAndFlag)) {
             OsMemFreeNodeDelete(pool, (struct OsMemFreeNodeHead *)nextNode);
@@ -1161,6 +1178,10 @@ STATIC UINT32 OsMemCheckUsedNode(const struct OsMemPoolHead *pool, const struct
 
     do {
         do {
+            if (OS_MEM_IS_GAP_NODE(node)) {
+                break;
+            }
+
             if (!OsMemIsNodeValid(node, startNode, endNode, pool)) {
                 break;
             }
@@ -1174,7 +1195,7 @@ STATIC UINT32 OsMemCheckUsedNode(const struct OsMemPoolHead *pool, const struct
                 break;
             }
 
-            if (!OS_MEM_NODE_GET_LAST_FLAG(nextNode->sizeAndFlag)) {
+            if (!OS_MEM_NODE_GET_LAST_FLAG(nextNode->sizeAndFlag) && !OS_MEM_IS_GAP_NODE(nextNode)) {
                 if (nextNode->ptr.prev != node) {
                     break;
                 }
@@ -1472,6 +1493,9 @@ UINT32 LOS_MemPoolSizeGet(const VOID *pool)
     }
 
     count += ((struct OsMemPoolHead *)pool)->info.totalSize;
+#if (LOSCFG_MEM_MUL_REGIONS == 1)
+    count -= ((struct OsMemPoolHead *)pool)->info.totalGapSize;
+#endif
 
 #if OS_MEM_EXPAND_ENABLE
     UINT32 size;
@@ -1524,7 +1548,9 @@ UINT32 LOS_MemTotalUsedGet(VOID *pool)
     }
 #else
     for (tmpNode = OS_MEM_FIRST_NODE(pool); tmpNode < endNode;) {
-        if (OS_MEM_NODE_GET_USED_FLAG(tmpNode->sizeAndFlag)) {
+        if (OS_MEM_IS_GAP_NODE(tmpNode)) {
+            memUsed += OS_MEM_NODE_HEAD_SIZE;
+        } else if (OS_MEM_NODE_GET_USED_FLAG(tmpNode->sizeAndFlag)) {
             memUsed += OS_MEM_NODE_GET_SIZE(tmpNode->sizeAndFlag);
         }
         tmpNode = OS_MEM_NEXT_NODE(tmpNode);
@@ -1656,6 +1682,9 @@ STATIC UINT32 OsMemIntegrityCheck(const struct OsMemPoolHead *pool, struct OsMem
     *preNode = OS_MEM_FIRST_NODE(pool);
     do {
         for (*tmpNode = *preNode; *tmpNode < endNode; *tmpNode = OS_MEM_NEXT_NODE(*tmpNode)) {
+            if (OS_MEM_IS_GAP_NODE(*tmpNode)) {
+                continue;
+            }
             if (OsMemIntegrityCheckSub(tmpNode, pool, endNode) == LOS_NOK) {
                 return LOS_NOK;
             }
@@ -1853,7 +1882,11 @@ STATIC INLINE VOID OsMemInfoGet(struct OsMemPoolHead *poolInfo, struct OsMemNode
             maxFreeSize = size;
         }
     } else {
-        size = OS_MEM_NODE_GET_SIZE(node->sizeAndFlag);
+        if (OS_MEM_IS_GAP_NODE(node)) {
+            size = OS_MEM_NODE_HEAD_SIZE;
+        } else {
+            size = OS_MEM_NODE_GET_SIZE(node->sizeAndFlag);
+        }
         ++usedNodeNum;
         totalUsedSize += size;
     }
@@ -1942,7 +1975,7 @@ STATIC VOID OsMemInfoPrint(VOID *pool)
     PRINTK("---------------    --------     -------       --------     "
            "--------------       -------------      ------------\n");
     PRINTK("0x%-16x   0x%-8x   0x%-8x    0x%-8x   0x%-16x   0x%-13x    0x%-13x\n",
-           (UINTPTR)poolInfo->info.pool, LOS_MemPoolSizeGet(pool), status.totalUsedSize,
+           poolInfo->info.pool, LOS_MemPoolSizeGet(pool), status.totalUsedSize,
            status.totalFreeSize, status.maxFreeNodeSize, status.usedNodeNum,
            status.freeNodeNum);
 #endif
@@ -2004,6 +2037,149 @@ VOID LOS_MemUnlockEnable(VOID *pool)
     ((struct OsMemPoolHead *)pool)->info.attr |= OS_MEM_POOL_UNLOCK_ENABLE;
 }
 
+#if (LOSCFG_MEM_MUL_REGIONS == 1)
+STATIC INLINE UINT32 OsMemMulRegionsParamCheck(VOID *pool, const LosMemRegion * const memRegions, UINT32 memRegionCount)
+{
+    const LosMemRegion *memRegion = NULL;
+    VOID *lastStartAddress = NULL;
+    VOID *curStartAddress = NULL;
+    UINT32 lastLength;
+    UINT32 curLength;
+    UINT32 regionCount;
+
+    if ((pool != NULL) && (((struct OsMemPoolHead *)pool)->info.pool != pool)) {
+        PRINT_ERR("wrong mem pool addr: %p, func: %s, line: %d\n", pool, __FUNCTION__, __LINE__);
+        return LOS_NOK;
+    }
+
+    if (pool != NULL) {
+        lastStartAddress = pool;
+        lastLength = ((struct OsMemPoolHead *)pool)->info.totalSize;
+    }
+
+    memRegion = memRegions;
+    regionCount = 0;
+    while (regionCount < memRegionCount) {
+        curStartAddress = memRegion->startAddress;
+        curLength = memRegion->length;
+        if ((curStartAddress == NULL) || (curLength == 0)) {
+            PRINT_ERR("Memory address or length configured wrongly:address:0x%x, the length:0x%x\n", (UINTPTR)curStartAddress, curLength);
+            return LOS_NOK;
+        }
+        if (((UINTPTR)curStartAddress & (OS_MEM_ALIGN_SIZE - 1)) || (curLength & (OS_MEM_ALIGN_SIZE - 1))) {
+            PRINT_ERR("Memory address or length configured not aligned:address:0x%x, the length:0x%x, alignsize:%d\n", \
+                     (UINTPTR)curStartAddress, curLength, OS_MEM_ALIGN_SIZE);
+            return LOS_NOK;
+        }
+        if ((lastStartAddress != NULL) && (((UINT8 *)lastStartAddress + lastLength) >= (UINT8 *)curStartAddress)) {
+            PRINT_ERR("Memory regions overlapped, the last start address:0x%x, the length:0x%x, the current start address:0x%x\n", \
+                     (UINTPTR)lastStartAddress, lastLength, (UINTPTR)curStartAddress);
+            return LOS_NOK;
+        }
+        memRegion++;
+        regionCount++;
+        lastStartAddress = curStartAddress;
+        lastLength = curLength;
+    }
+    return LOS_OK;
+}
+
+STATIC INLINE VOID OsMemMulRegionsLink(struct OsMemPoolHead *poolHead, VOID *lastStartAddress, UINT32 lastLength, struct OsMemNodeHead *lastEndNode, const LosMemRegion *memRegion)
+{
+    UINT32 curLength;
+    UINT32 gapSize;
+    struct OsMemNodeHead *curEndNode = NULL;
+    struct OsMemNodeHead *curFreeNode = NULL;
+    VOID *curStartAddress = NULL;
+
+    curStartAddress = memRegion->startAddress;
+    curLength = memRegion->length;
+
+    // mark the gap between two regions as one used node
+    gapSize = (UINT8 *)(curStartAddress) - ((UINT8 *)(lastStartAddress) + lastLength);
+    lastEndNode->sizeAndFlag = gapSize + OS_MEM_NODE_HEAD_SIZE;
+    OS_MEM_SET_MAGIC(lastEndNode);
+    OS_MEM_NODE_SET_USED_FLAG(lastEndNode->sizeAndFlag);
+
+    // mark the gap node with magic number
+    OS_MEM_MARK_GAP_NODE(lastEndNode);
+
+    poolHead->info.totalSize += (curLength + gapSize);
+    poolHead->info.totalGapSize += gapSize;
+
+    curFreeNode = (struct OsMemNodeHead *)curStartAddress;
+    curFreeNode->sizeAndFlag = curLength - OS_MEM_NODE_HEAD_SIZE;
+    curFreeNode->ptr.prev = lastEndNode;
+    OS_MEM_SET_MAGIC(curFreeNode);
+    OsMemFreeNodeAdd(poolHead, (struct OsMemFreeNodeHead *)curFreeNode);
+
+    curEndNode = OS_MEM_END_NODE(curStartAddress, curLength);
+    curEndNode->sizeAndFlag = 0;
+    curEndNode->ptr.prev = curFreeNode;
+    OS_MEM_SET_MAGIC(curEndNode);
+    OS_MEM_NODE_SET_USED_FLAG(curEndNode->sizeAndFlag);
+
+#if (LOSCFG_MEM_WATERLINE == 1)
+    poolHead->info.curUsedSize += OS_MEM_NODE_HEAD_SIZE;
+    poolHead->info.waterLine = poolHead->info.curUsedSize;
+#endif
+}
+
+UINT32 LOS_MemRegionsAdd(VOID *pool, const LosMemRegion *const memRegions, UINT32 memRegionCount)
+{
+    UINT32 ret;
+    UINT32 lastLength;
+    UINT32 curLength;
+    UINT32 regionCount;
+    struct OsMemPoolHead *poolHead = NULL;
+    struct OsMemNodeHead *lastEndNode = NULL;
+    struct OsMemNodeHead *firstFreeNode = NULL;
+    const LosMemRegion *memRegion = NULL;
+    VOID *lastStartAddress = NULL;
+    VOID *curStartAddress = NULL;
+
+    ret = OsMemMulRegionsParamCheck(pool, memRegions, memRegionCount);
+    if (ret != LOS_OK) {
+        return ret;
+    }
+
+    memRegion = memRegions;
+    regionCount = 0;
+    if (pool != NULL) { // add the memory regions to the specified memory pool
+        poolHead = (struct OsMemPoolHead *)pool;
+        lastStartAddress = pool;
+        lastLength = poolHead->info.totalSize;
+    } else { // initialize the memory pool with the first memory region
+        lastStartAddress = memRegion->startAddress;
+        lastLength = memRegion->length;
+        poolHead = (struct OsMemPoolHead *)lastStartAddress;
+        ret = LOS_MemInit(lastStartAddress, lastLength);
+        if (ret != LOS_OK) {
+            return ret;
+        }
+        memRegion++;
+        regionCount++;
+    }
+
+    firstFreeNode = OS_MEM_FIRST_NODE(lastStartAddress);
+    lastEndNode = OS_MEM_END_NODE(lastStartAddress, lastLength);
+    while (regionCount < memRegionCount) { // traverse the rest memory regions, and initialize them as free nodes and link together
+        curStartAddress = memRegion->startAddress;
+        curLength = memRegion->length;
+
+        OsMemMulRegionsLink(poolHead, lastStartAddress, lastLength, lastEndNode, memRegion);
+        lastStartAddress = curStartAddress;
+        lastLength = curLength;
+        lastEndNode = OS_MEM_END_NODE(curStartAddress, curLength);
+        memRegion++;
+        regionCount++;
+    }
+
+    firstFreeNode->ptr.prev = lastEndNode;
+    return ret;
+}
+#endif
+
 UINT32 OsMemSystemInit(VOID)
 {
     UINT32 ret;

targets/cortex-m3_stm32f103_simulator_keil/Driver/STM32F103/uart.c

@@ -1,440 +0,0 @@
-/*
- * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this list of
- *    conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice, this list
- *    of conditions and the following disclaimer in the documentation and/or other materials
- *    provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors may be used
- *    to endorse or promote products derived from this software without specific prior written
- *    permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <stdio.h>
-#include "los_compiler.h"
-
-#define OS_USART1  0x40013800
-#define OS_USART2  0x40004400
-#define OS_USART3  0x40004800
-#define OS_USART4  0x40004C00
-#define OS_USART5  0x40005000
-
-#define OS_USART_USR   OS_USART1
-
-
-#define GPIO_Pin_0                 ((UINT16)0x0001)  /* Pin 0 selected */
-#define GPIO_Pin_1                 ((UINT16)0x0002)  /* Pin 1 selected */
-#define GPIO_Pin_2                 ((UINT16)0x0004)  /* Pin 2 selected */
-#define GPIO_Pin_3                 ((UINT16)0x0008)  /* Pin 3 selected */
-#define GPIO_Pin_4                 ((UINT16)0x0010)  /* Pin 4 selected */
-#define GPIO_Pin_5                 ((UINT16)0x0020)  /* Pin 5 selected */
-#define GPIO_Pin_6                 ((UINT16)0x0040)  /* Pin 6 selected */
-#define GPIO_Pin_7                 ((UINT16)0x0080)  /* Pin 7 selected */
-#define GPIO_Pin_8                 ((UINT16)0x0100)  /* Pin 8 selected */
-#define GPIO_Pin_9                 ((UINT16)0x0200)  /* Pin 9 selected */
-#define GPIO_Pin_10                ((UINT16)0x0400)  /* Pin 10 selected */
-#define GPIO_Pin_11                ((UINT16)0x0800)  /* Pin 11 selected */
-#define GPIO_Pin_12                ((UINT16)0x1000)  /* Pin 12 selected */
-#define GPIO_Pin_13                ((UINT16)0x2000)  /* Pin 13 selected */
-#define GPIO_Pin_14                ((UINT16)0x4000)  /* Pin 14 selected */
-#define GPIO_Pin_15                ((UINT16)0x8000)  /* Pin 15 selected */
-#define GPIO_Pin_All               ((UINT16)0xFFFF)  /* All pins selected */
-
-#define   GPIOA                 0x40010800
-#define   GPIOB                 0x40010C00
-#define   GPIOC                 0x40011000
-#define   GPIOD                 0x40011400
-#define   GPIOE                 0x40011800
-#define   GPIOF                 0x40011C00
-#define   GPIOG                 0x40012000
-
-#define  RCC_REG_BASE           0x40021000
-#define  RCC_APB2ENR_OFFSET     0x18
-#define  RCC_APB1ENR_OFFSET     0x1C
-
-#if (OS_USART_USR == OS_USART1)
-#define RCC_APBENR_USART_EN  0x4004
-#define  GPIO_RxPin                 GPIO_Pin_10
-#define  GPIO_TxPin                 GPIO_Pin_9
-#define  GPIOx                      GPIOA
-
-#elif (OS_USART_USR == OS_USART2)
-#define RCC_APBENR_USART_EN  0x20000
-#define  GPIO_TxPin                 GPIO_Pin_5
-#define  GPIO_RxPin                 GPIO_Pin_6
-#define  GPIOx                      GPIOD
-
-#elif (OS_USART_USR == OS_USART3)
-#define RCC_APBENR_USART_EN  0x40000
-#define  GPIO_RxPin                 GPIO_Pin_11
-#define  GPIO_TxPin                 GPIO_Pin_10
-#define  GPIOx                      GPIOB
-
-#elif (OS_USART_USR == OS_USART4)
-#define RCC_APBENR_USART_EN  0x80000
-#define  GPIO_RxPin                 GPIO_Pin_11
-#define  GPIO_TxPin                 GPIO_Pin_10
-#define  GPIOx                      GPIOC
-
-#elif (OS_USART_USR == OS_USART5)
-#define RCC_APBENR_USART_EN  0x100000
-#define  GPIO_RxPin                 GPIO_Pin_2
-#define  GPIO_TxPin                 GPIO_Pin_12
-#define  GPIOx                      GPIOC
-
-#endif
-
-typedef struct tagUsartMap
-{
-    volatile UINT32 SR;
-    volatile UINT32 DR;
-    volatile UINT32 BRR;
-    volatile UINT32 CR1;
-    volatile UINT32 CR2;
-    volatile UINT32 CR3;
-    volatile UINT32 GTPR;
-}USART_MAP_S;
-
-typedef struct
-{
-  UINT32 USART_BaudRate;
-  UINT16 USART_WordLength;
-  UINT16 USART_StopBits;
-  UINT16 USART_Parity;
-  UINT16 USART_Mode;
-  UINT16 USART_HardwareFlowControl;
-  UINT16 USART_Clock;
-  UINT16 USART_CPOL;
-  UINT16 USART_CPHA;
-  UINT16 USART_LastBit;
-}USART_INIT_S;
-
-/* USART Word Length ---------------------------------------------------------*/
-#define USART_WordLength_8b                  ((UINT16)0x0000)
-#define USART_WordLength_9b                  ((UINT16)0x1000)
-
-/* USART Stop Bits -----------------------------------------------------------*/
-#define USART_StopBits_1                     ((UINT16)0x0000)
-#define USART_StopBits_0_5                   ((UINT16)0x1000)
-#define USART_StopBits_2                     ((UINT16)0x2000)
-#define USART_StopBits_1_5                   ((UINT16)0x3000)
-
-/* USART Parity --------------------------------------------------------------*/
-#define USART_Parity_No                      ((UINT16)0x0000)
-#define USART_Parity_Even                    ((UINT16)0x0400)
-#define USART_Parity_Odd                     ((UINT16)0x0600)
-
-/* USART Mode ----------------------------------------------------------------*/
-#define USART_Mode_Rx                        ((UINT16)0x0004)
-#define USART_Mode_Tx                        ((UINT16)0x0008)
-
-/* USART Hardware Flow Control -----------------------------------------------*/
-#define USART_HardwareFlowControl_None       ((UINT16)0x0000)
-#define USART_HardwareFlowControl_RTS        ((UINT16)0x0100)
-#define USART_HardwareFlowControl_CTS        ((UINT16)0x0200)
-#define USART_HardwareFlowControl_RTS_CTS    ((UINT16)0x0300)
-
-/* USART Clock ---------------------------------------------------------------*/
-#define USART_Clock_Disable                  ((UINT16)0x0000)
-#define USART_Clock_Enable                   ((UINT16)0x0800)
-
-/* USART Clock Polarity ------------------------------------------------------*/
-#define USART_CPOL_Low                       ((UINT16)0x0000)
-#define USART_CPOL_High                      ((UINT16)0x0400)
-
-/* USART Clock Phase ---------------------------------------------------------*/
-#define USART_CPHA_1Edge                     ((UINT16)0x0000)
-#define USART_CPHA_2Edge                     ((UINT16)0x0200)
-
-
-/* USART Last Bit ------------------------------------------------------------*/
-#define USART_LastBit_Disable                ((UINT16)0x0000)
-#define USART_LastBit_Enable                 ((UINT16)0x0100)
-
-enum GPIOSpeed_TypeDef
-{
-  GPIO_Speed_10MHz = 1,
-  GPIO_Speed_2MHz,
-  GPIO_Speed_50MHz
-};
-
-enum GPIOMode_TypeDef
-{ GPIO_Mode_AIN = 0x0,
-  GPIO_Mode_IN_FLOATING = 0x04,
-  GPIO_Mode_IPD = 0x28,
-  GPIO_Mode_IPU = 0x48,
-  GPIO_Mode_Out_OD = 0x14,
-  GPIO_Mode_Out_PP = 0x10,
-  GPIO_Mode_AF_OD = 0x1C,
-  GPIO_Mode_AF_PP = 0x18
-};
-
-typedef struct
-{
-  UINT16 GPIO_Pin;
-  enum GPIOSpeed_TypeDef GPIO_Speed;
-  enum GPIOMode_TypeDef GPIO_Mode;
-}GPIO_InitTypeDef;
-
-typedef struct
-{
-  volatile UINT32 CRL;
-  volatile UINT32 CRH;
-  volatile UINT32 IDR;
-  volatile UINT32 ODR;
-  volatile UINT32 BSRR;
-  volatile UINT32 BRR;
-  volatile UINT32 LCKR;
-}GPIO_TypeDef;
-
-VOID GPIO_Init(GPIO_TypeDef * pGPIO, GPIO_InitTypeDef * GPIO_InitStruct)
-{
-  UINT32 currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
-  UINT32 tmpreg = 0x00, pinmask = 0x00;
-
-/*---------------------------- GPIO Mode Configuration -----------------------*/
-  currentmode = ((UINT32)GPIO_InitStruct->GPIO_Mode) & ((UINT32)0x0F);
-
-  if ((((UINT32)GPIO_InitStruct->GPIO_Mode) & ((UINT32)0x10)) != 0x00)
-  {
-    /* Output mode */
-    currentmode |= (UINT32)GPIO_InitStruct->GPIO_Speed;
-  }
-
-/*---------------------------- GPIO CRL Configuration ------------------------*/
-  /* Configure the eight low port pins */
-  if (((UINT32)GPIO_InitStruct->GPIO_Pin & ((UINT32)0x00FF)) != 0x00)
-  {
-    tmpreg = pGPIO->CRL;
-
-    for (pinpos = 0x00; pinpos < 0x08; pinpos++)
-    {
-      pos = ((UINT32)0x01) << pinpos;
-      /* Get the port pins position */
-      currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
-
-      if (currentpin == pos)
-      {
-        pos = pinpos << 2;
-        /* Clear the corresponding low control register bits */
-        pinmask = ((UINT32)0x0F) << pos;
-        tmpreg &= ~pinmask;
-
-        /* Write the mode configuration in the corresponding bits */
-        tmpreg |= (currentmode << pos);
-
-        /* Reset the corresponding ODR bit */
-        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
-        {
-          pGPIO->BRR = (((UINT32)0x01) << pinpos);
-        }
-        /* Set the corresponding ODR bit */
-        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
-        {
-          pGPIO->BSRR = (((UINT32)0x01) << pinpos);
-        }
-      }
-    }
-    pGPIO->CRL = tmpreg;
-  }
-/*---------------------------- GPIO CRH Configuration ------------------------*/
-  /* Configure the eight high port pins */
-  if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
-  {
-    tmpreg = pGPIO->CRH;
-    for (pinpos = 0x00; pinpos < 0x08; pinpos++)
-    {
-      pos = (((UINT32)0x01) << (pinpos + 0x08));
-      /* Get the port pins position */
-      currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
-      if (currentpin == pos)
-      {
-        pos = pinpos << 2;
-        /* Clear the corresponding high control register bits */
-        pinmask = ((UINT32)0x0F) << pos;
-        tmpreg &= ~pinmask;
-
-        /* Write the mode configuration in the corresponding bits */
-        tmpreg |= (currentmode << pos);
-
-        /* Reset the corresponding ODR bit */
-        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
-        {
-          pGPIO->BRR = (((UINT32)0x01) << (pinpos + 0x08));
-        }
-        /* Set the corresponding ODR bit */
-        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
-        {
-          pGPIO->BSRR = (((UINT32)0x01) << (pinpos + 0x08));
-        }
-      }
-    }
-    pGPIO->CRH = tmpreg;
-  }
-}
-
-UINT32 USART_Init(USART_MAP_S * USARTx, USART_INIT_S * pstInitParam)
-{
-    UINT32  tmpreg;
-    UINT32  apbclock;
-    UINT32  integerdivider;
-    UINT32  fractionaldivider;
-
-    /*---------------------------- USART CR2 Configuration -----------------------*/
-    tmpreg = USARTx->CR2;
-    /* Clear STOP[13:12], CLKEN, CPOL, CPHA and LBCL bits */
-    tmpreg &= 0xC0FF;
-
-    /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
-    /* Set STOP[13:12] bits according to USART_Mode value */
-    /* Set CPOL bit according to USART_CPOL value */
-    /* Set CPHA bit according to USART_CPHA value */
-    /* Set LBCL bit according to USART_LastBit value */
-    tmpreg |= (UINT32)pstInitParam->USART_StopBits | pstInitParam->USART_Clock |
-    pstInitParam->USART_CPOL | pstInitParam->USART_CPHA |
-    pstInitParam->USART_LastBit;
-
-    /* Write to USART CR2 */
-    USARTx->CR2 = (UINT16)tmpreg;
-
-    /*---------------------------- USART CR1 Configuration -----------------------*/
-    tmpreg = 0x00;
-    tmpreg = USARTx->CR1;
-    /* Clear M, PCE, PS, TE and RE bits */
-    tmpreg &= 0xE9F3;
-
-    /* Configure the USART Word Length, Parity and mode ----------------------- */
-    /* Set the M bits according to USART_WordLength value */
-    /* Set PCE and PS bits according to USART_Parity value */
-    /* Set TE and RE bits according to USART_Mode value */
-    tmpreg |= (UINT32)pstInitParam->USART_WordLength | pstInitParam->USART_Parity |
-    pstInitParam->USART_Mode;
-
-    /* Write to USART CR1 */
-    USARTx->CR1 = (UINT16)tmpreg;
-
-    /*---------------------------- USART CR3 Configuration -----------------------*/
-    tmpreg = 0x00;
-    tmpreg = USARTx->CR3;
-    /* Clear CTSE and RTSE bits */
-    tmpreg &= 0xFCFF;
-
-    /* Configure the USART HFC -------------------------------------------------*/
-    /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
-    tmpreg |= pstInitParam->USART_HardwareFlowControl;
-
-    /* Write to USART CR3 */
-    USARTx->CR3 = (UINT16)tmpreg;
-
-    /*---------------------------- USART BRR Configuration -----------------------*/
-    tmpreg = 0x00;
-
-    /* Configure the USART Baud Rate -------------------------------------------*/
-    if ((*(UINT32*)&USARTx) == OS_USART1)
-    {
-        apbclock = 8000000;
-    }
-    else
-    {
-        apbclock = 36000000;
-    }
-
-    /* Determine the integer part */
-    integerdivider = ((0x19 * apbclock) / (0x04 * (pstInitParam->USART_BaudRate)));
-    tmpreg = (integerdivider / 0x64) << 0x04;
-
-    /* Determine the fractional part */
-    fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04));
-    tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((UINT8)0x0F);
-
-    /* Write to USART BRR */
-    USARTx->BRR = (UINT16)tmpreg;
-
-    /* UART enable */
-    USARTx->CR1 |= 0x2000;
-
-    return LOS_OK;
-}
-
-int fputc(int ch, FILE *f)
-{
-  USART_MAP_S * USARTx =  (USART_MAP_S *)OS_USART_USR;
-
-  USARTx->DR = (UINT8)ch;
-
-  while((USARTx->SR & 0x80) == 0);
-
-  return ch;
-}
-
-void uart_puts(char * s)
-{
-  USART_MAP_S * USARTx =  (USART_MAP_S *)OS_USART_USR;
-
-  while (*s)
-  {
-    USARTx->DR = *s++;
-    while((USARTx->SR & 0x80) == 0);
-  }
-}
-
-UINT32 LOS_UartBaseInit(void)
-{
-  GPIO_InitTypeDef GPIO_InitStructure;
-  USART_INIT_S   USART_InitStructure;
-  USART_MAP_S * USARTx =  (USART_MAP_S *)OS_USART_USR;
-
-    /* uart rcc enable */
-#if (OS_USART_USR == OS_USART1)
-    *(volatile UINT32 *)(RCC_REG_BASE + RCC_APB2ENR_OFFSET) |= RCC_APBENR_USART_EN;
-#else
-    *(volatile UINT32 *)(RCC_REG_BASE + RCC_APB1ENR_OFFSET) |= RCC_APBENR_USART_EN;
-#endif
-
-  /* Configure USARTx_Tx as alternate function push-pull */
-  GPIO_InitStructure.GPIO_Pin = GPIO_TxPin;
-  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-  GPIO_Init((GPIO_TypeDef*)GPIOx, &GPIO_InitStructure);
-
-  /* Configure USARTx_Rx as input floating */
-  GPIO_InitStructure.GPIO_Pin = GPIO_RxPin;
-  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-  GPIO_Init((GPIO_TypeDef*)GPIOx, &GPIO_InitStructure);
-
-  USART_InitStructure.USART_BaudRate = 115200;
-  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-  USART_InitStructure.USART_StopBits = USART_StopBits_1;
-  USART_InitStructure.USART_Parity = USART_Parity_No ;
-  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-  USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx;
-
-  USART_InitStructure.USART_Clock = USART_Clock_Disable;
-  USART_InitStructure.USART_CPOL = USART_CPOL_Low;
-  USART_InitStructure.USART_CPHA = USART_CPHA_2Edge;
-  USART_InitStructure.USART_LastBit = USART_LastBit_Disable;
-
-
-  USART_Init(USARTx, &USART_InitStructure);
-
-  return 0;
-}

targets/cortex-m3_stm32f103_simulator_keil/main.c

@@ -1,136 +0,0 @@
-/*
- * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this list of
- *    conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice, this list
- *    of conditions and the following disclaimer in the documentation and/or other materials
- *    provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors may be used
- *    to endorse or promote products derived from this software without specific prior written
- *    permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "los_tick.h"
-#include "los_task.h"
-#include "los_config.h"
-#include "los_interrupt.h"
-#include "los_debug.h"
-#include "los_compiler.h"
-
-#ifdef __cplusplus
-#if __cplusplus
-extern "C" {
-#endif /* __cpluscplus */
-#endif /* __cpluscplus */
-
-#pragma data_alignment=8
-UINT8 g_memStart[LOSCFG_SYS_HEAP_SIZE];
-
-VOID taskSampleEntry2(VOID)
-{
-    while(1) {
-      LOS_TaskDelay(10000);
-      printf("taskSampleEntry2 running...\n");
-    }
-}
-
-
-VOID taskSampleEntry1(VOID)
-{
-    while(1) {
-      LOS_TaskDelay(2000);
-      printf("taskSampleEntry1 running...\n");
-    }
-
-}
-
-UINT32 taskSample(VOID)
-{
-    UINT32  uwRet;
-    UINT32 taskID1,taskID2;
-    TSK_INIT_PARAM_S stTask1={0};
-    stTask1.pfnTaskEntry = (TSK_ENTRY_FUNC)taskSampleEntry1;
-    stTask1.uwStackSize  = 0X1000;
-    stTask1.pcName       = "taskSampleEntry1";
-    stTask1.usTaskPrio   = 6;
-    uwRet = LOS_TaskCreate(&taskID1, &stTask1);
-    if (uwRet != LOS_OK) {
-        printf("create task1 failed\n");
-    }
-
-    stTask1.pfnTaskEntry = (TSK_ENTRY_FUNC)taskSampleEntry2;
-    stTask1.uwStackSize  = 0X1000;
-    stTask1.pcName       = "taskSampleEntry2";
-    stTask1.usTaskPrio   = 7;
-    uwRet = LOS_TaskCreate(&taskID2, &stTask1);
-    if (uwRet != LOS_OK) {
-        printf("create task2 failed\n");
-    }
-    return LOS_OK;
-}
-
-
-void LOS_HardBootInit()
-{
-    UINT32 uwRet = LOS_OK;
-
-    uwRet = LOS_UartBaseInit();
-    if (uwRet != LOS_OK)
-    {
-        return ;
-    }
-
-    return ;
-}
-
-
-/*****************************************************************************
- Function    : main
- Description : Main function entry
- Input       : None
- Output      : None
- Return      : None
- *****************************************************************************/
-LITE_OS_SEC_TEXT_INIT int main(void)
-{
-    unsigned int ret;
-
-    //USART_Config();
-
-    printf("\n\rhello world!!\n\r");
-
-    ret = LOS_KernelInit();
-    taskSample();
-    if (ret == LOS_OK) {
-        LOS_Start();
-    }
-
-    while (1) {
-        __asm volatile("wfi");
-    }
-}
-
-#ifdef __cplusplus
-#if __cplusplus
-}
-#endif /* __cpluscplus */
-#endif /* __cpluscplus */

targets/cortex-m3_stm32f103_simulator_keil/project/los_demo.sct

@@ -1,24 +0,0 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x08000000 0x00200000  {    ; load region size_region
-  ER_IROM1 0x08000000 0x00200000  {  ; load address = execution address
-   	los_startup.o (RESET, +First)
-   *(InRoot$$Sections)
-   * (+RO)
-  }
-  RW_IRAM1 0x20000000 0x00200000  {  ; RW data
-      * (.data, .bss, .data.init)
-  }
-    VECTOR 0x20200000 0x400         ; Vector
-  {
-	* (.vector)
-  }
-  
-  ARM_LIB_STACKHEAP 0x08100000 EMPTY 0x1000 
-  {
-	
-  }	
-}
-

targets/cortex-m3_stm32f103_simulator_keil/project/los_demo.uvopt

@@ -1,665 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
-
-  <SchemaVersion>1.0</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Extensions>
-    <cExt>*.c</cExt>
-    <aExt>*.s*; *.src; *.a*</aExt>
-    <oExt>*.obj; *.o</oExt>
-    <lExt>*.lib</lExt>
-    <tExt>*.txt; *.h; *.inc; *.md</tExt>
-    <pExt>*.plm</pExt>
-    <CppX>*.cpp</CppX>
-    <nMigrate>0</nMigrate>
-  </Extensions>
-
-  <DaveTm>
-    <dwLowDateTime>0</dwLowDateTime>
-    <dwHighDateTime>0</dwHighDateTime>
-  </DaveTm>
-
-  <Target>
-    <TargetName>los_demo</TargetName>
-    <ToolsetNumber>0x4</ToolsetNumber>
-    <ToolsetName>ARM-ADS</ToolsetName>
-    <TargetOption>
-      <CLKADS>8000000</CLKADS>
-      <OPTTT>
-        <gFlags>1</gFlags>
-        <BeepAtEnd>1</BeepAtEnd>
-        <RunSim>1</RunSim>
-        <RunTarget>0</RunTarget>
-        <RunAbUc>0</RunAbUc>
-      </OPTTT>
-      <OPTHX>
-        <HexSelection>1</HexSelection>
-        <FlashByte>65535</FlashByte>
-        <HexRangeLowAddress>0</HexRangeLowAddress>
-        <HexRangeHighAddress>0</HexRangeHighAddress>
-        <HexOffset>0</HexOffset>
-      </OPTHX>
-      <OPTLEX>
-        <PageWidth>79</PageWidth>
-        <PageLength>66</PageLength>
-        <TabStop>8</TabStop>
-        <ListingPath>.\output\</ListingPath>
-      </OPTLEX>
-      <ListingPage>
-        <CreateCListing>1</CreateCListing>
-        <CreateAListing>1</CreateAListing>
-        <CreateLListing>1</CreateLListing>
-        <CreateIListing>0</CreateIListing>
-        <AsmCond>1</AsmCond>
-        <AsmSymb>1</AsmSymb>
-        <AsmXref>0</AsmXref>
-        <CCond>1</CCond>
-        <CCode>0</CCode>
-        <CListInc>0</CListInc>
-        <CSymb>0</CSymb>
-        <LinkerCodeListing>0</LinkerCodeListing>
-      </ListingPage>
-      <OPTXL>
-        <LMap>1</LMap>
-        <LComments>1</LComments>
-        <LGenerateSymbols>1</LGenerateSymbols>
-        <LLibSym>1</LLibSym>
-        <LLines>1</LLines>
-        <LLocSym>1</LLocSym>
-        <LPubSym>1</LPubSym>
-        <LXref>0</LXref>
-        <LExpSel>0</LExpSel>
-      </OPTXL>
-      <OPTFL>
-        <tvExp>1</tvExp>
-        <tvExpOptDlg>0</tvExpOptDlg>
-        <IsCurrentTarget>1</IsCurrentTarget>
-      </OPTFL>
-      <CpuCode>255</CpuCode>
-      <Books>
-        <Book>
-          <Number>0</Number>
-          <Title>Reference Manual</Title>
-          <Path>DATASHTS\ST\STM32F10xxx.PDF</Path>
-        </Book>
-        <Book>
-          <Number>1</Number>
-          <Title>Technical Reference Manual</Title>
-          <Path>datashts\arm\cortex_m3\r1p1\DDI0337E_CORTEX_M3_R1P1_TRM.PDF</Path>
-        </Book>
-        <Book>
-          <Number>2</Number>
-          <Title>Generic User Guide</Title>
-          <Path>datashts\arm\cortex_m3\r2p1\DUI0552A_CORTEX_M3_DGUG.PDF</Path>
-        </Book>
-      </Books>
-      <DebugOpt>
-        <uSim>1</uSim>
-        <uTrg>0</uTrg>
-        <sLdApp>1</sLdApp>
-        <sGomain>1</sGomain>
-        <sRbreak>1</sRbreak>
-        <sRwatch>1</sRwatch>
-        <sRmem>1</sRmem>
-        <sRfunc>1</sRfunc>
-        <sRbox>1</sRbox>
-        <tLdApp>1</tLdApp>
-        <tGomain>0</tGomain>
-        <tRbreak>1</tRbreak>
-        <tRwatch>1</tRwatch>
-        <tRmem>1</tRmem>
-        <tRfunc>0</tRfunc>
-        <tRbox>1</tRbox>
-        <tRtrace>1</tRtrace>
-        <sRSysVw>1</sRSysVw>
-        <tRSysVw>1</tRSysVw>
-        <sRunDeb>0</sRunDeb>
-        <sLrtime>0</sLrtime>
-        <bEvRecOn>1</bEvRecOn>
-        <bSchkAxf>0</bSchkAxf>
-        <bTchkAxf>0</bTchkAxf>
-        <nTsel>0</nTsel>
-        <sDll></sDll>
-        <sDllPa></sDllPa>
-        <sDlgDll></sDlgDll>
-        <sDlgPa></sDlgPa>
-        <sIfile></sIfile>
-        <tDll></tDll>
-        <tDllPa></tDllPa>
-        <tDlgDll></tDlgDll>
-        <tDlgPa></tDlgPa>
-        <tIfile></tIfile>
-        <pMon>BIN\UL2CM3.DLL</pMon>
-      </DebugOpt>
-      <TargetDriverDllRegistry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>ARMRTXEVENTFLAGS</Key>
-          <Name>-L70 -Z18 -C0 -M0 -T1</Name>
-        </SetRegEntry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>DLGDARM</Key>
-          <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(234=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0)</Name>
-        </SetRegEntry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>ARMDBGFLAGS</Key>
-          <Name>-T0</Name>
-        </SetRegEntry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>UL2CM3</Key>
-          <Name>UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7  -FN1 -FC800 -FD20000000 -FF0STM32F10x_128 -FL020000 -FS08000000</Name>
-        </SetRegEntry>
-      </TargetDriverDllRegistry>
-      <Breakpoint>
-        <Bp>
-          <Number>0</Number>
-          <Type>0</Type>
-          <LineNumber>60</LineNumber>
-          <EnabledFlag>1</EnabledFlag>
-          <Address>0</Address>
-          <ByteObject>0</ByteObject>
-          <HtxType>0</HtxType>
-          <ManyObjects>0</ManyObjects>
-          <SizeOfObject>0</SizeOfObject>
-          <BreakByAccess>0</BreakByAccess>
-          <BreakIfRCount>0</BreakIfRCount>
-          <Filename>..\main.c</Filename>
-          <ExecCommand></ExecCommand>
-          <Expression></Expression>
-        </Bp>
-      </Breakpoint>
-      <Tracepoint>
-        <THDelay>0</THDelay>
-      </Tracepoint>
-      <DebugFlag>
-        <trace>0</trace>
-        <periodic>1</periodic>
-        <aLwin>1</aLwin>
-        <aCover>0</aCover>
-        <aSer1>0</aSer1>
-        <aSer2>0</aSer2>
-        <aPa>0</aPa>
-        <viewmode>1</viewmode>
-        <vrSel>0</vrSel>
-        <aSym>0</aSym>
-        <aTbox>0</aTbox>
-        <AscS1>0</AscS1>
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-        <aSer3>0</aSer3>
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-        <aPa1>0</aPa1>
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-        <aSer4>0</aSer4>
-        <StkLoc>0</StkLoc>
-        <TrcWin>0</TrcWin>
-        <newCpu>0</newCpu>
-        <uProt>0</uProt>
-      </DebugFlag>
-      <LintExecutable></LintExecutable>
-      <LintConfigFile></LintConfigFile>
-      <bLintAuto>0</bLintAuto>
-      <bAutoGenD>0</bAutoGenD>
-      <LntExFlags>0</LntExFlags>
-      <pMisraName></pMisraName>
-      <pszMrule></pszMrule>
-      <pSingCmds></pSingCmds>
-      <pMultCmds></pMultCmds>
-      <pMisraNamep></pMisraNamep>
-      <pszMrulep></pszMrulep>
-      <pSingCmdsp></pSingCmdsp>
-      <pMultCmdsp></pMultCmdsp>
-    </TargetOption>
-  </Target>
-
-  <Group>
-    <GroupName>liteos-m</GroupName>
-    <tvExp>0</tvExp>
-    <tvExpOptDlg>0</tvExpOptDlg>
-    <cbSel>0</cbSel>
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-      <tvExp>0</tvExp>
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-      <bDave2>0</bDave2>
-      <PathWithFileName>..\..\..\kernel\src\los_event.c</PathWithFileName>
-      <FilenameWithoutPath>los_event.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>1</GroupNumber>
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-      <bDave2>0</bDave2>
-      <PathWithFileName>..\..\..\kernel\src\los_init.c</PathWithFileName>
-      <FilenameWithoutPath>los_init.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>1</GroupNumber>
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-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\..\..\kernel\src\los_mux.c</PathWithFileName>
-      <FilenameWithoutPath>los_mux.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>1</GroupNumber>
-      <FileNumber>4</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
-      <tvExpOptDlg>0</tvExpOptDlg>
-      <bDave2>0</bDave2>
-      <PathWithFileName>..\..\..\kernel\src\los_queue.c</PathWithFileName>
-      <FilenameWithoutPath>los_queue.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>1</GroupNumber>
-      <FileNumber>5</FileNumber>
-      <FileType>1</FileType>
-      <tvExp>0</tvExp>
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-      <bDave2>0</bDave2>
-      <PathWithFileName>..\..\..\kernel\src\los_sem.c</PathWithFileName>
-      <FilenameWithoutPath>los_sem.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
-      <bShared>0</bShared>
-    </File>
-    <File>
-      <GroupNumber>1</GroupNumber>
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-      <bDave2>0</bDave2>
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-    <File>
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-      <FilenameWithoutPath>los_tick.c</FilenameWithoutPath>
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-      <FilenameWithoutPath>los_membox.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
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-      <bDave2>0</bDave2>
-      <PathWithFileName>..\..\..\kernel\src\mm\los_memory.c</PathWithFileName>
-      <FilenameWithoutPath>los_memory.c</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
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-      <PathWithFileName>..\..\..\kernel\arch\arm\cortex-m3\keil\los_dispatch.S</PathWithFileName>
-      <FilenameWithoutPath>los_dispatch.S</FilenameWithoutPath>
-      <RteFlg>0</RteFlg>
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-      <FilenameWithoutPath>ARMCM3.h</FilenameWithoutPath>
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-                <Size>0x0</Size>
-              </OCR_RVCT7>
-              <OCR_RVCT8>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT8>
-              <OCR_RVCT9>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x500000</Size>
-              </OCR_RVCT9>
-              <OCR_RVCT10>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT10>
-            </OnChipMemories>
-            <RvctStartVector></RvctStartVector>
-          </ArmAdsMisc>
-          <Cads>
-            <interw>1</interw>
-            <Optim>1</Optim>
-            <oTime>0</oTime>
-            <SplitLS>0</SplitLS>
-            <OneElfS>0</OneElfS>
-            <Strict>0</Strict>
-            <EnumInt>0</EnumInt>
-            <PlainCh>0</PlainCh>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <wLevel>0</wLevel>
-            <uThumb>0</uThumb>
-            <uSurpInc>0</uSurpInc>
-            <uC99>0</uC99>
-            <uGnu>0</uGnu>
-            <useXO>0</useXO>
-            <v6Lang>1</v6Lang>
-            <v6LangP>1</v6LangP>
-            <vShortEn>1</vShortEn>
-            <vShortWch>1</vShortWch>
-            <v6Lto>0</v6Lto>
-            <v6WtE>0</v6WtE>
-            <v6Rtti>0</v6Rtti>
-            <VariousControls>
-              <MiscControls>--gnu</MiscControls>
-              <Define></Define>
-              <Undefine></Undefine>
-              <IncludePath>..\..\cortex-m3_stm32f103_simulator_keil;..\..\..\kernel\include;..\..\..\kernel\arch\arm\cortex-m3\keil;..\..\..\kernel\arch\arm\cortex-m3\keil\cmsis;..\..\..\kernel\src;..\..\..\components\bounds_checking_function\include;..\..\..\components\cpup;..\..\..\utils;..\..\..\kernel\arch\include;..\..\..\components\exchook</IncludePath>
-            </VariousControls>
-          </Cads>
-          <Aads>
-            <interw>1</interw>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <thumb>0</thumb>
-            <SplitLS>0</SplitLS>
-            <SwStkChk>0</SwStkChk>
-            <NoWarn>0</NoWarn>
-            <uSurpInc>0</uSurpInc>
-            <useXO>0</useXO>
-            <ClangAsOpt>1</ClangAsOpt>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define></Define>
-              <Undefine></Undefine>
-              <IncludePath></IncludePath>
-            </VariousControls>
-          </Aads>
-          <LDads>
-            <umfTarg>0</umfTarg>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <noStLib>0</noStLib>
-            <RepFail>1</RepFail>
-            <useFile>0</useFile>
-            <TextAddressRange>0x08000000</TextAddressRange>
-            <DataAddressRange>0x20000000</DataAddressRange>
-            <pXoBase></pXoBase>
-            <ScatterFile>.\los_demo.sct</ScatterFile>
-            <IncludeLibs></IncludeLibs>
-            <IncludeLibsPath></IncludeLibsPath>
-            <Misc></Misc>
-            <LinkerInputFile></LinkerInputFile>
-            <DisabledWarnings></DisabledWarnings>
-          </LDads>
-        </TargetArmAds>
-      </TargetOption>
-      <Groups>
-        <Group>
-          <GroupName>liteos-m</GroupName>
-          <Files>
-            <File>
-              <FileName>los_event.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\kernel\src\los_event.c</FilePath>
-            </File>
-            <File>
-              <FileName>los_init.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\kernel\src\los_init.c</FilePath>
-            </File>
-            <File>
-              <FileName>los_mux.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\kernel\src\los_mux.c</FilePath>
-            </File>
-            <File>
-              <FileName>los_queue.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\kernel\src\los_queue.c</FilePath>
-            </File>
-            <File>
-              <FileName>los_sem.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\kernel\src\los_sem.c</FilePath>
-            </File>
-            <File>
-              <FileName>los_swtmr.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\kernel\src\los_swtmr.c</FilePath>
-            </File>
-            <File>
-              <FileName>los_task.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\kernel\src\los_task.c</FilePath>
-            </File>
-            <File>
-              <FileName>los_tick.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\kernel\src\los_tick.c</FilePath>
-            </File>
-            <File>
-              <FileName>los_membox.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\kernel\src\mm\los_membox.c</FilePath>
-            </File>
-            <File>
-              <FileName>los_memory.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\kernel\src\mm\los_memory.c</FilePath>
-            </File>
-            <File>
-              <FileName>los_dispatch.S</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\..\..\kernel\arch\arm\cortex-m3\keil\los_dispatch.S</FilePath>
-            </File>
-            <File>
-              <FileName>ARMCM3.h</FileName>
-              <FileType>5</FileType>
-              <FilePath>..\..\..\kernel\arch\arm\cortex-m3\keil\cmsis\ARMCM3.h</FilePath>
-            </File>
-            <File>
-              <FileName>core_cm3.h</FileName>
-              <FileType>5</FileType>
-              <FilePath>..\..\..\kernel\arch\arm\cortex-m3\keil\cmsis\core_cm3.h</FilePath>
-            </File>
-            <File>
-              <FileName>core_cmFunc.h</FileName>
-              <FileType>5</FileType>
-              <FilePath>..\..\..\kernel\arch\arm\cortex-m3\keil\cmsis\core_cmFunc.h</FilePath>
-            </File>
-            <File>
-              <FileName>core_cmInstr.h</FileName>
-              <FileType>5</FileType>
-              <FilePath>..\..\..\kernel\arch\arm\cortex-m3\keil\cmsis\core_cmInstr.h</FilePath>
-            </File>
-            <File>
-              <FileName>los_cpup.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\cpup\los_cpup.c</FilePath>
-            </File>
-            <File>
-              <FileName>los_interrupt.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\kernel\arch\arm\cortex-m3\keil\los_interrupt.c</FilePath>
-            </File>
-            <File>
-              <FileName>los_error.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\utils\los_error.c</FilePath>
-            </File>
-            <File>
-              <FileName>los_context.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\kernel\arch\arm\cortex-m3\keil\los_context.c</FilePath>
-            </File>
-            <File>
-              <FileName>los_timer.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\kernel\arch\arm\cortex-m3\keil\los_timer.c</FilePath>
-            </File>
-            <File>
-              <FileName>los_exc.S</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\..\..\kernel\arch\arm\cortex-m3\keil\los_exc.S</FilePath>
-            </File>
-            <File>
-              <FileName>los_startup.s</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\..\..\kernel\arch\arm\cortex-m3\keil\los_startup.s</FilePath>
-            </File>
-            <File>
-              <FileName>los_debug.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\utils\los_debug.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>main</GroupName>
-          <Files>
-            <File>
-              <FileName>uart.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\Driver\STM32F103\uart.c</FilePath>
-            </File>
-            <File>
-              <FileName>main.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\main.c</FilePath>
-            </File>
-            <File>
-              <FileName>target_config.h</FileName>
-              <FileType>5</FileType>
-              <FilePath>..\target_config.h</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>component</GroupName>
-          <Files>
-            <File>
-              <FileName>memcpy_s.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\bounds_checking_function\src\memcpy_s.c</FilePath>
-            </File>
-            <File>
-              <FileName>memmove_s.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\bounds_checking_function\src\memmove_s.c</FilePath>
-            </File>
-            <File>
-              <FileName>memset_s.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\bounds_checking_function\src\memset_s.c</FilePath>
-            </File>
-            <File>
-              <FileName>strcpy_s.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\bounds_checking_function\src\strcpy_s.c</FilePath>
-            </File>
-            <File>
-              <FileName>strncpy_s.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\bounds_checking_function\src\strncpy_s.c</FilePath>
-            </File>
-            <File>
-              <FileName>los_exc_info.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\exchook\los_exc_info.c</FilePath>
-            </File>
-            <File>
-              <FileName>los_exc_info.h</FileName>
-              <FileType>5</FileType>
-              <FilePath>..\..\..\components\exchook\los_exc_info.h</FilePath>
-            </File>
-            <File>
-              <FileName>los_exchook.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\exchook\los_exchook.c</FilePath>
-            </File>
-            <File>
-              <FileName>los_exchook.h</FileName>
-              <FileType>5</FileType>
-              <FilePath>..\..\..\components\exchook\los_exchook.h</FilePath>
-            </File>
-          </Files>
-        </Group>
-      </Groups>
-    </Target>
-  </Targets>
-
-</Project>

targets/cortex-m3_stm32f103_simulator_keil/target_config.h

@@ -1,111 +0,0 @@
-/*
- * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
- * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice, this list of
- *    conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice, this list
- *    of conditions and the following disclaimer in the documentation and/or other materials
- *    provided with the distribution.
- *
- * 3. Neither the name of the copyright holder nor the names of its contributors may be used
- *    to endorse or promote products derived from this software without specific prior written
- *    permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
- * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**@defgroup los_config System configuration items
- * @ingroup kernel
- */
-
-#ifndef _TARGET_CONFIG_H
-#define _TARGET_CONFIG_H
-
-#ifdef __cplusplus
-#if __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-#endif /* __cplusplus */
-
-/*=============================================================================
-                                        System clock module configuration
-=============================================================================*/
-#define OS_SYS_CLOCK                                        24000000
-#define LOSCFG_BASE_CORE_TICK_PER_SECOND                    (1000UL)
-#define LOSCFG_BASE_CORE_TICK_HW_TIME                       0
-/*=============================================================================
-                                        Hardware interrupt module configuration
-=============================================================================*/
-#define LOSCFG_PLATFORM_HWI                                 1
-#define LOSCFG_PLATFORM_HWI_LIMIT                           128
-/*=============================================================================
-                                       Task module configuration
-=============================================================================*/
-#define LOSCFG_BASE_CORE_TSK_LIMIT                          24
-#define LOSCFG_BASE_CORE_TSK_IDLE_STACK_SIZE                (0x500U)
-#define LOSCFG_BASE_CORE_TSK_DEFAULT_STACK_SIZE             (0x2D0U)
-#define LOSCFG_BASE_CORE_TSK_MIN_STACK_SIZE                 (0x130U)
-#define LOSCFG_BASE_CORE_TIMESLICE                          1
-#define LOSCFG_BASE_CORE_TIMESLICE_TIMEOUT                  10
-/*=============================================================================
-                                       Semaphore module configuration
-=============================================================================*/
-#define LOSCFG_BASE_IPC_SEM                                 1
-#define LOSCFG_BASE_IPC_SEM_LIMIT                           48
-/*=============================================================================
-                                       Mutex module configuration
-=============================================================================*/
-#define LOSCFG_BASE_IPC_MUX                                 1
-#define LOSCFG_BASE_IPC_MUX_LIMIT                           24
-/*=============================================================================
-                                       Queue module configuration
-=============================================================================*/
-#define LOSCFG_BASE_IPC_QUEUE                               1
-#define LOSCFG_BASE_IPC_QUEUE_LIMIT                         24
-/*=============================================================================
-                                       Software timer module configuration
-=============================================================================*/
-#define LOSCFG_BASE_CORE_SWTMR                              1
-#define LOSCFG_BASE_CORE_SWTMR_ALIGN                        1
-#define LOSCFG_BASE_CORE_SWTMR_LIMIT                        48
-/*=============================================================================
-                                       Memory module configuration
-=============================================================================*/
-extern unsigned char g_memStart[];
-#define LOSCFG_SYS_EXTERNAL_HEAP                            1
-#define LOSCFG_SYS_HEAP_ADDR                                (&g_memStart[0])
-#define LOSCFG_SYS_HEAP_SIZE                                0x00013000
-#define LOSCFG_MEM_MUL_POOL                                 1
-#define OS_SYS_MEM_NUM                                      20
-/*=============================================================================
-                                       Exception module configuration
-=============================================================================*/
-#define LOSCFG_PLATFORM_EXC                                 1
-/* =============================================================================
-                                       printf module configuration
-============================================================================= */
-#define LOSCFG_KERNEL_PRINTF                                1
-
-#ifdef __cplusplus
-#if __cplusplus
-}
-#endif /* __cplusplus */
-#endif /* __cplusplus */
-
-
-#endif /* _TARGET_CONFIG_H */

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h

@@ -1,105 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f4xx.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    09-November-2016
-  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
-  ******************************************************************************  
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************  
-  */ 
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f4xx_system
-  * @{
-  */  
-  
-/**
-  * @brief Define to prevent recursive inclusion
-  */
-#ifndef __SYSTEM_STM32F4XX_H
-#define __SYSTEM_STM32F4XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup STM32F4xx_System_Includes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32F4xx_System_Exported_types
-  * @{
-  */
-
-extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Exported_Functions
-  * @{
-  */
-  
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32F4XX_H */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */  
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f401xx.s

@@ -1,507 +0,0 @@
-;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name          : startup_stm32f401x.s
-;* Author             : MCD Application Team
-;* @version           : V1.8.0
-;* @date              : 09-November-2016
-;* Description        : STM32F401xx devices vector table for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M4 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-;* You may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at:
-;* 
-;*        http://www.st.com/software_license_agreement_liberty_v2
-;* 
-;* Unless required by applicable law or agreed to in writing, software 
-;* distributed under the License is distributed on an "AS IS" BASIS, 
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;* 
-;*******************************************************************************/
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
-        DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
-        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
-        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
-        DCD     FLASH_IRQHandler                  ; FLASH                                           
-        DCD     RCC_IRQHandler                    ; RCC                                             
-        DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
-        DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
-        DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
-        DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
-        DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
-        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
-        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
-        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
-        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
-        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
-        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
-        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
-        DCD     ADC_IRQHandler                    ; ADC1                            
-        DCD     0                                 ; Reserved                                               
-        DCD     0                                 ; Reserved                                               
-        DCD     0                                 ; Reserved                                               
-        DCD     0                                 ; Reserved                                               
-        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
-        DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
-        DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
-        DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
-        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
-        DCD     TIM2_IRQHandler                   ; TIM2                                            
-        DCD     TIM3_IRQHandler                   ; TIM3                                            
-        DCD     TIM4_IRQHandler                   ; TIM4                                            
-        DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
-        DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
-        DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
-        DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
-        DCD     SPI1_IRQHandler                   ; SPI1                                            
-        DCD     SPI2_IRQHandler                   ; SPI2                                            
-        DCD     USART1_IRQHandler                 ; USART1                                          
-        DCD     USART2_IRQHandler                 ; USART2                                          
-        DCD     0                                 ; Reserved                                         
-        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
-        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
-        DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
-        DCD     0                                 ; Reserved                 
-        DCD     0                                 ; Reserved                 
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved                                 
-        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
-        DCD     0                                 ; Reserved                                            
-        DCD     SDIO_IRQHandler                   ; SDIO                                            
-        DCD     TIM5_IRQHandler                   ; TIM5                                            
-        DCD     SPI3_IRQHandler                   ; SPI3                                            
-        DCD     0                                 ; Reserved                                          
-        DCD     0                                 ; Reserved                                          
-        DCD     0                                 ; Reserved                   
-        DCD     0                                 ; Reserved                  
-        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
-        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
-        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
-        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
-        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
-        DCD     0                                 ; Reserved                                        
-        DCD     0                                 ; Reserved                      
-        DCD     0                                 ; Reserved                                               
-        DCD     0                                 ; Reserved                                               
-        DCD     0                                 ; Reserved                                              
-        DCD     0                                 ; Reserved                                               
-        DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
-        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
-        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
-        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
-        DCD     USART6_IRQHandler                 ; USART6                                           
-        DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
-        DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
-        DCD     0                                 ; Reserved                     
-        DCD     0                                 ; Reserved                      
-        DCD     0                                 ; Reserved                         
-        DCD     0                                 ; Reserved                                      
-        DCD     0                                 ; Reserved                                          
-        DCD     0                                 ; Reserved                                     
-        DCD     0                                 ; Reserved
-        DCD     FPU_IRQHandler                    ; FPU
-        DCD     0                                 ; Reserved                                          
-        DCD     0                                 ; Reserved  
-        DCD     SPI4_IRQHandler                   ; SPI4 
-    
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler  
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler  
-        B PVD_IRQHandler
-
-        PUBWEAK TAMP_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TAMP_STAMP_IRQHandler  
-        B TAMP_STAMP_IRQHandler
-
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-RTC_WKUP_IRQHandler  
-        B RTC_WKUP_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler  
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler  
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler  
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler  
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler  
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-EXTI4_IRQHandler  
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream0_IRQHandler  
-        B DMA1_Stream0_IRQHandler
-
-        PUBWEAK DMA1_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream1_IRQHandler  
-        B DMA1_Stream1_IRQHandler
-
-        PUBWEAK DMA1_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream2_IRQHandler  
-        B DMA1_Stream2_IRQHandler
-
-        PUBWEAK DMA1_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream3_IRQHandler  
-        B DMA1_Stream3_IRQHandler
-
-        PUBWEAK DMA1_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream4_IRQHandler  
-        B DMA1_Stream4_IRQHandler
-
-        PUBWEAK DMA1_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream5_IRQHandler  
-        B DMA1_Stream5_IRQHandler
-
-        PUBWEAK DMA1_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream6_IRQHandler  
-        B DMA1_Stream6_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC_IRQHandler  
-        B ADC_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-EXTI9_5_IRQHandler  
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_BRK_TIM9_IRQHandler  
-        B TIM1_BRK_TIM9_IRQHandler
-
-        PUBWEAK TIM1_UP_TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_UP_TIM10_IRQHandler  
-        B TIM1_UP_TIM10_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_TRG_COM_TIM11_IRQHandler  
-        B TIM1_TRG_COM_TIM11_IRQHandler
-        
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_CC_IRQHandler  
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler  
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler  
-        B TIM3_IRQHandler
-
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler  
-        B TIM4_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C1_EV_IRQHandler  
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C1_ER_IRQHandler  
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C2_EV_IRQHandler  
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C2_ER_IRQHandler  
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler  
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler  
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler  
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler  
-        B USART2_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-EXTI15_10_IRQHandler  
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-RTC_Alarm_IRQHandler  
-        B RTC_Alarm_IRQHandler
-
-        PUBWEAK OTG_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_FS_WKUP_IRQHandler  
-        B OTG_FS_WKUP_IRQHandler
-
-        PUBWEAK DMA1_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream7_IRQHandler  
-        B DMA1_Stream7_IRQHandler
-
-        PUBWEAK SDIO_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO_IRQHandler  
-        B SDIO_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler  
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler  
-        B SPI3_IRQHandler
-
-        PUBWEAK DMA2_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream0_IRQHandler  
-        B DMA2_Stream0_IRQHandler
-
-        PUBWEAK DMA2_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream1_IRQHandler  
-        B DMA2_Stream1_IRQHandler
-
-        PUBWEAK DMA2_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream2_IRQHandler  
-        B DMA2_Stream2_IRQHandler
-
-        PUBWEAK DMA2_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream3_IRQHandler  
-        B DMA2_Stream3_IRQHandler
-
-        PUBWEAK DMA2_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream4_IRQHandler  
-        B DMA2_Stream4_IRQHandler
-
-        PUBWEAK OTG_FS_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_IRQHandler  
-        B OTG_FS_IRQHandler
-
-        PUBWEAK DMA2_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream5_IRQHandler  
-        B DMA2_Stream5_IRQHandler
-
-        PUBWEAK DMA2_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream6_IRQHandler  
-        B DMA2_Stream6_IRQHandler
-
-        PUBWEAK DMA2_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream7_IRQHandler  
-        B DMA2_Stream7_IRQHandler
-
-        PUBWEAK USART6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler  
-        B USART6_IRQHandler
-
-        PUBWEAK I2C3_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C3_EV_IRQHandler  
-        B I2C3_EV_IRQHandler
-
-        PUBWEAK I2C3_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C3_ER_IRQHandler  
-        B I2C3_ER_IRQHandler
-
-        PUBWEAK FPU_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-FPU_IRQHandler  
-        B FPU_IRQHandler
-
-        PUBWEAK SPI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI4_IRQHandler  
-        B SPI4_IRQHandler
-        
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f40_41xxx.s

@@ -1,636 +0,0 @@
-;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name          : startup_stm32f40_41xxx.s
-;* Author             : MCD Application Team
-;* @version           : V1.8.0
-;* @date              : 09-November-2016
-;* Description        : STM32F40xxx/41xxx devices vector table for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock and the external SRAM mounted on 
-;*                        STM324xG-EVAL board to be used as data memory (optional, 
-;*                        to be enabled by user)
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M4 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-;* You may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at:
-;* 
-;*        http://www.st.com/software_license_agreement_liberty_v2
-;* 
-;* Unless required by applicable law or agreed to in writing, software 
-;* distributed under the License is distributed on an "AS IS" BASIS, 
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;* 
-;*******************************************************************************/
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
-        DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
-        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
-        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
-        DCD     FLASH_IRQHandler                  ; FLASH                                           
-        DCD     RCC_IRQHandler                    ; RCC                                             
-        DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
-        DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
-        DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
-        DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
-        DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
-        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
-        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
-        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
-        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
-        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
-        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
-        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
-        DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
-        DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
-        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
-        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
-        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
-        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
-        DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
-        DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
-        DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
-        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
-        DCD     TIM2_IRQHandler                   ; TIM2                                            
-        DCD     TIM3_IRQHandler                   ; TIM3                                            
-        DCD     TIM4_IRQHandler                   ; TIM4                                            
-        DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
-        DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
-        DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
-        DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
-        DCD     SPI1_IRQHandler                   ; SPI1                                            
-        DCD     SPI2_IRQHandler                   ; SPI2                                            
-        DCD     USART1_IRQHandler                 ; USART1                                          
-        DCD     USART2_IRQHandler                 ; USART2                                          
-        DCD     USART3_IRQHandler                 ; USART3                                          
-        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
-        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
-        DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
-        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
-        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
-        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
-        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
-        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
-        DCD     FSMC_IRQHandler                   ; FSMC                                            
-        DCD     SDIO_IRQHandler                   ; SDIO                                            
-        DCD     TIM5_IRQHandler                   ; TIM5                                            
-        DCD     SPI3_IRQHandler                   ; SPI3                                            
-        DCD     UART4_IRQHandler                  ; UART4                                           
-        DCD     UART5_IRQHandler                  ; UART5                                           
-        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
-        DCD     TIM7_IRQHandler                   ; TIM7                   
-        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
-        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
-        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
-        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
-        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
-        DCD     ETH_IRQHandler                    ; Ethernet                                        
-        DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
-        DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
-        DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
-        DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
-        DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
-        DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
-        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
-        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
-        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
-        DCD     USART6_IRQHandler                 ; USART6                                           
-        DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
-        DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
-        DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
-        DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
-        DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
-        DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
-        DCD     DCMI_IRQHandler                   ; DCMI                                            
-        DCD     CRYP_IRQHandler                   ; CRYP crypto                                     
-        DCD     HASH_RNG_IRQHandler               ; Hash and Rng
-        DCD     FPU_IRQHandler                    ; FPU
-    
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler  
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler  
-        B PVD_IRQHandler
-
-        PUBWEAK TAMP_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TAMP_STAMP_IRQHandler  
-        B TAMP_STAMP_IRQHandler
-
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-RTC_WKUP_IRQHandler  
-        B RTC_WKUP_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler  
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler  
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler  
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler  
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler  
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-EXTI4_IRQHandler  
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream0_IRQHandler  
-        B DMA1_Stream0_IRQHandler
-
-        PUBWEAK DMA1_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream1_IRQHandler  
-        B DMA1_Stream1_IRQHandler
-
-        PUBWEAK DMA1_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream2_IRQHandler  
-        B DMA1_Stream2_IRQHandler
-
-        PUBWEAK DMA1_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream3_IRQHandler  
-        B DMA1_Stream3_IRQHandler
-
-        PUBWEAK DMA1_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream4_IRQHandler  
-        B DMA1_Stream4_IRQHandler
-
-        PUBWEAK DMA1_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream5_IRQHandler  
-        B DMA1_Stream5_IRQHandler
-
-        PUBWEAK DMA1_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream6_IRQHandler  
-        B DMA1_Stream6_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC_IRQHandler  
-        B ADC_IRQHandler
-
-        PUBWEAK CAN1_TX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-CAN1_TX_IRQHandler  
-        B CAN1_TX_IRQHandler
-
-        PUBWEAK CAN1_RX0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN1_RX0_IRQHandler  
-        B CAN1_RX0_IRQHandler
-
-        PUBWEAK CAN1_RX1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN1_RX1_IRQHandler  
-        B CAN1_RX1_IRQHandler
-
-        PUBWEAK CAN1_SCE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN1_SCE_IRQHandler  
-        B CAN1_SCE_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-EXTI9_5_IRQHandler  
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_BRK_TIM9_IRQHandler  
-        B TIM1_BRK_TIM9_IRQHandler
-
-        PUBWEAK TIM1_UP_TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_UP_TIM10_IRQHandler  
-        B TIM1_UP_TIM10_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_TRG_COM_TIM11_IRQHandler  
-        B TIM1_TRG_COM_TIM11_IRQHandler
-        
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_CC_IRQHandler  
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler  
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler  
-        B TIM3_IRQHandler
-
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler  
-        B TIM4_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C1_EV_IRQHandler  
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C1_ER_IRQHandler  
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C2_EV_IRQHandler  
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C2_ER_IRQHandler  
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler  
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler  
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler  
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler  
-        B USART2_IRQHandler
-
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler  
-        B USART3_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-EXTI15_10_IRQHandler  
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-RTC_Alarm_IRQHandler  
-        B RTC_Alarm_IRQHandler
-
-        PUBWEAK OTG_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_FS_WKUP_IRQHandler  
-        B OTG_FS_WKUP_IRQHandler
-      
-        PUBWEAK TIM8_BRK_TIM12_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM8_BRK_TIM12_IRQHandler  
-        B TIM8_BRK_TIM12_IRQHandler
-
-        PUBWEAK TIM8_UP_TIM13_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM8_UP_TIM13_IRQHandler  
-        B TIM8_UP_TIM13_IRQHandler
-
-        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM8_TRG_COM_TIM14_IRQHandler  
-        B TIM8_TRG_COM_TIM14_IRQHandler
-
-        PUBWEAK TIM8_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-TIM8_CC_IRQHandler  
-        B TIM8_CC_IRQHandler
-
-        PUBWEAK DMA1_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream7_IRQHandler  
-        B DMA1_Stream7_IRQHandler
-
-        PUBWEAK FSMC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FSMC_IRQHandler  
-        B FSMC_IRQHandler
-
-        PUBWEAK SDIO_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO_IRQHandler  
-        B SDIO_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler  
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler  
-        B SPI3_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler  
-        B UART4_IRQHandler
-
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler  
-        B UART5_IRQHandler
-
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-TIM6_DAC_IRQHandler  
-        B TIM6_DAC_IRQHandler
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-TIM7_IRQHandler  
-        B TIM7_IRQHandler
-
-        PUBWEAK DMA2_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream0_IRQHandler  
-        B DMA2_Stream0_IRQHandler
-
-        PUBWEAK DMA2_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream1_IRQHandler  
-        B DMA2_Stream1_IRQHandler
-
-        PUBWEAK DMA2_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream2_IRQHandler  
-        B DMA2_Stream2_IRQHandler
-
-        PUBWEAK DMA2_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream3_IRQHandler  
-        B DMA2_Stream3_IRQHandler
-
-        PUBWEAK DMA2_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream4_IRQHandler  
-        B DMA2_Stream4_IRQHandler
-
-        PUBWEAK ETH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ETH_IRQHandler  
-        B ETH_IRQHandler
-
-        PUBWEAK ETH_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-ETH_WKUP_IRQHandler  
-        B ETH_WKUP_IRQHandler
-
-        PUBWEAK CAN2_TX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-CAN2_TX_IRQHandler  
-        B CAN2_TX_IRQHandler
-
-        PUBWEAK CAN2_RX0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN2_RX0_IRQHandler  
-        B CAN2_RX0_IRQHandler
-
-        PUBWEAK CAN2_RX1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN2_RX1_IRQHandler  
-        B CAN2_RX1_IRQHandler
-
-        PUBWEAK CAN2_SCE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN2_SCE_IRQHandler  
-        B CAN2_SCE_IRQHandler
-
-        PUBWEAK OTG_FS_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_IRQHandler  
-        B OTG_FS_IRQHandler
-
-        PUBWEAK DMA2_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream5_IRQHandler  
-        B DMA2_Stream5_IRQHandler
-
-        PUBWEAK DMA2_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream6_IRQHandler  
-        B DMA2_Stream6_IRQHandler
-
-        PUBWEAK DMA2_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream7_IRQHandler  
-        B DMA2_Stream7_IRQHandler
-
-        PUBWEAK USART6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler  
-        B USART6_IRQHandler
-
-        PUBWEAK I2C3_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C3_EV_IRQHandler  
-        B I2C3_EV_IRQHandler
-
-        PUBWEAK I2C3_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C3_ER_IRQHandler  
-        B I2C3_ER_IRQHandler
-
-        PUBWEAK OTG_HS_EP1_OUT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_HS_EP1_OUT_IRQHandler  
-        B OTG_HS_EP1_OUT_IRQHandler
-
-        PUBWEAK OTG_HS_EP1_IN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_HS_EP1_IN_IRQHandler  
-        B OTG_HS_EP1_IN_IRQHandler
-
-        PUBWEAK OTG_HS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_HS_WKUP_IRQHandler  
-        B OTG_HS_WKUP_IRQHandler
-
-        PUBWEAK OTG_HS_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_IRQHandler  
-        B OTG_HS_IRQHandler
-
-        PUBWEAK DCMI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DCMI_IRQHandler  
-        B DCMI_IRQHandler
-
-        PUBWEAK CRYP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CRYP_IRQHandler  
-        B CRYP_IRQHandler
-
-        PUBWEAK HASH_RNG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-HASH_RNG_IRQHandler  
-        B HASH_RNG_IRQHandler
-
-        PUBWEAK FPU_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-FPU_IRQHandler  
-        B FPU_IRQHandler
-
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f40xx.s

@@ -1,637 +0,0 @@
-;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name          : startup_stm32f40xx.s
-;* Author             : MCD Application Team
-;* @version           : V1.8.0
-;* @date              : 09-November-2016
-;* Description        : STM32F40xxx/41xxx devices vector table for EWARM toolchain.
-;*                      Same as startup_stm32f40_41xxx.s and maintained for legacy purpose
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock and the external SRAM mounted on 
-;*                        STM324xG-EVAL board to be used as data memory (optional, 
-;*                        to be enabled by user)
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M4 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-;* You may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at:
-;* 
-;*        http://www.st.com/software_license_agreement_liberty_v2
-;* 
-;* Unless required by applicable law or agreed to in writing, software 
-;* distributed under the License is distributed on an "AS IS" BASIS, 
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;* 
-;*******************************************************************************/
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
-        DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
-        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
-        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
-        DCD     FLASH_IRQHandler                  ; FLASH                                           
-        DCD     RCC_IRQHandler                    ; RCC                                             
-        DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
-        DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
-        DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
-        DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
-        DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
-        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
-        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
-        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
-        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
-        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
-        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
-        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
-        DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
-        DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
-        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
-        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
-        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
-        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
-        DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
-        DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
-        DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
-        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
-        DCD     TIM2_IRQHandler                   ; TIM2                                            
-        DCD     TIM3_IRQHandler                   ; TIM3                                            
-        DCD     TIM4_IRQHandler                   ; TIM4                                            
-        DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
-        DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
-        DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
-        DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
-        DCD     SPI1_IRQHandler                   ; SPI1                                            
-        DCD     SPI2_IRQHandler                   ; SPI2                                            
-        DCD     USART1_IRQHandler                 ; USART1                                          
-        DCD     USART2_IRQHandler                 ; USART2                                          
-        DCD     USART3_IRQHandler                 ; USART3                                          
-        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
-        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
-        DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
-        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
-        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
-        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
-        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
-        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
-        DCD     FSMC_IRQHandler                   ; FSMC                                            
-        DCD     SDIO_IRQHandler                   ; SDIO                                            
-        DCD     TIM5_IRQHandler                   ; TIM5                                            
-        DCD     SPI3_IRQHandler                   ; SPI3                                            
-        DCD     UART4_IRQHandler                  ; UART4                                           
-        DCD     UART5_IRQHandler                  ; UART5                                           
-        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
-        DCD     TIM7_IRQHandler                   ; TIM7                   
-        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
-        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
-        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
-        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
-        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
-        DCD     ETH_IRQHandler                    ; Ethernet                                        
-        DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
-        DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
-        DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
-        DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
-        DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
-        DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
-        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
-        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
-        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
-        DCD     USART6_IRQHandler                 ; USART6                                           
-        DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
-        DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
-        DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
-        DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
-        DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
-        DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
-        DCD     DCMI_IRQHandler                   ; DCMI                                            
-        DCD     CRYP_IRQHandler                   ; CRYP crypto                                     
-        DCD     HASH_RNG_IRQHandler               ; Hash and Rng
-        DCD     FPU_IRQHandler                    ; FPU
-    
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler  
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler  
-        B PVD_IRQHandler
-
-        PUBWEAK TAMP_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TAMP_STAMP_IRQHandler  
-        B TAMP_STAMP_IRQHandler
-
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-RTC_WKUP_IRQHandler  
-        B RTC_WKUP_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler  
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler  
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler  
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler  
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler  
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-EXTI4_IRQHandler  
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream0_IRQHandler  
-        B DMA1_Stream0_IRQHandler
-
-        PUBWEAK DMA1_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream1_IRQHandler  
-        B DMA1_Stream1_IRQHandler
-
-        PUBWEAK DMA1_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream2_IRQHandler  
-        B DMA1_Stream2_IRQHandler
-
-        PUBWEAK DMA1_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream3_IRQHandler  
-        B DMA1_Stream3_IRQHandler
-
-        PUBWEAK DMA1_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream4_IRQHandler  
-        B DMA1_Stream4_IRQHandler
-
-        PUBWEAK DMA1_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream5_IRQHandler  
-        B DMA1_Stream5_IRQHandler
-
-        PUBWEAK DMA1_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream6_IRQHandler  
-        B DMA1_Stream6_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC_IRQHandler  
-        B ADC_IRQHandler
-
-        PUBWEAK CAN1_TX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-CAN1_TX_IRQHandler  
-        B CAN1_TX_IRQHandler
-
-        PUBWEAK CAN1_RX0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN1_RX0_IRQHandler  
-        B CAN1_RX0_IRQHandler
-
-        PUBWEAK CAN1_RX1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN1_RX1_IRQHandler  
-        B CAN1_RX1_IRQHandler
-
-        PUBWEAK CAN1_SCE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN1_SCE_IRQHandler  
-        B CAN1_SCE_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-EXTI9_5_IRQHandler  
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_BRK_TIM9_IRQHandler  
-        B TIM1_BRK_TIM9_IRQHandler
-
-        PUBWEAK TIM1_UP_TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_UP_TIM10_IRQHandler  
-        B TIM1_UP_TIM10_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_TRG_COM_TIM11_IRQHandler  
-        B TIM1_TRG_COM_TIM11_IRQHandler
-        
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_CC_IRQHandler  
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler  
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler  
-        B TIM3_IRQHandler
-
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler  
-        B TIM4_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C1_EV_IRQHandler  
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C1_ER_IRQHandler  
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C2_EV_IRQHandler  
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C2_ER_IRQHandler  
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler  
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler  
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler  
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler  
-        B USART2_IRQHandler
-
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler  
-        B USART3_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-EXTI15_10_IRQHandler  
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-RTC_Alarm_IRQHandler  
-        B RTC_Alarm_IRQHandler
-
-        PUBWEAK OTG_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_FS_WKUP_IRQHandler  
-        B OTG_FS_WKUP_IRQHandler
-      
-        PUBWEAK TIM8_BRK_TIM12_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM8_BRK_TIM12_IRQHandler  
-        B TIM8_BRK_TIM12_IRQHandler
-
-        PUBWEAK TIM8_UP_TIM13_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM8_UP_TIM13_IRQHandler  
-        B TIM8_UP_TIM13_IRQHandler
-
-        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM8_TRG_COM_TIM14_IRQHandler  
-        B TIM8_TRG_COM_TIM14_IRQHandler
-
-        PUBWEAK TIM8_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-TIM8_CC_IRQHandler  
-        B TIM8_CC_IRQHandler
-
-        PUBWEAK DMA1_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream7_IRQHandler  
-        B DMA1_Stream7_IRQHandler
-
-        PUBWEAK FSMC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FSMC_IRQHandler  
-        B FSMC_IRQHandler
-
-        PUBWEAK SDIO_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO_IRQHandler  
-        B SDIO_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler  
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler  
-        B SPI3_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler  
-        B UART4_IRQHandler
-
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler  
-        B UART5_IRQHandler
-
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-TIM6_DAC_IRQHandler  
-        B TIM6_DAC_IRQHandler
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-TIM7_IRQHandler  
-        B TIM7_IRQHandler
-
-        PUBWEAK DMA2_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream0_IRQHandler  
-        B DMA2_Stream0_IRQHandler
-
-        PUBWEAK DMA2_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream1_IRQHandler  
-        B DMA2_Stream1_IRQHandler
-
-        PUBWEAK DMA2_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream2_IRQHandler  
-        B DMA2_Stream2_IRQHandler
-
-        PUBWEAK DMA2_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream3_IRQHandler  
-        B DMA2_Stream3_IRQHandler
-
-        PUBWEAK DMA2_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream4_IRQHandler  
-        B DMA2_Stream4_IRQHandler
-
-        PUBWEAK ETH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ETH_IRQHandler  
-        B ETH_IRQHandler
-
-        PUBWEAK ETH_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-ETH_WKUP_IRQHandler  
-        B ETH_WKUP_IRQHandler
-
-        PUBWEAK CAN2_TX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-CAN2_TX_IRQHandler  
-        B CAN2_TX_IRQHandler
-
-        PUBWEAK CAN2_RX0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN2_RX0_IRQHandler  
-        B CAN2_RX0_IRQHandler
-
-        PUBWEAK CAN2_RX1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN2_RX1_IRQHandler  
-        B CAN2_RX1_IRQHandler
-
-        PUBWEAK CAN2_SCE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN2_SCE_IRQHandler  
-        B CAN2_SCE_IRQHandler
-
-        PUBWEAK OTG_FS_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_IRQHandler  
-        B OTG_FS_IRQHandler
-
-        PUBWEAK DMA2_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream5_IRQHandler  
-        B DMA2_Stream5_IRQHandler
-
-        PUBWEAK DMA2_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream6_IRQHandler  
-        B DMA2_Stream6_IRQHandler
-
-        PUBWEAK DMA2_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream7_IRQHandler  
-        B DMA2_Stream7_IRQHandler
-
-        PUBWEAK USART6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler  
-        B USART6_IRQHandler
-
-        PUBWEAK I2C3_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C3_EV_IRQHandler  
-        B I2C3_EV_IRQHandler
-
-        PUBWEAK I2C3_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C3_ER_IRQHandler  
-        B I2C3_ER_IRQHandler
-
-        PUBWEAK OTG_HS_EP1_OUT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_HS_EP1_OUT_IRQHandler  
-        B OTG_HS_EP1_OUT_IRQHandler
-
-        PUBWEAK OTG_HS_EP1_IN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_HS_EP1_IN_IRQHandler  
-        B OTG_HS_EP1_IN_IRQHandler
-
-        PUBWEAK OTG_HS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_HS_WKUP_IRQHandler  
-        B OTG_HS_WKUP_IRQHandler
-
-        PUBWEAK OTG_HS_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_IRQHandler  
-        B OTG_HS_IRQHandler
-
-        PUBWEAK DCMI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DCMI_IRQHandler  
-        B DCMI_IRQHandler
-
-        PUBWEAK CRYP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CRYP_IRQHandler  
-        B CRYP_IRQHandler
-
-        PUBWEAK HASH_RNG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-HASH_RNG_IRQHandler  
-        B HASH_RNG_IRQHandler
-
-        PUBWEAK FPU_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-FPU_IRQHandler  
-        B FPU_IRQHandler
-
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f410xx.s

@@ -1,510 +0,0 @@
-;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name          : startup_stm32f410xx.s
-;* Author             : MCD Application Team
-;* @version           : V1.8.0
-;* @date              : 09-November-2016
-;* Description        : STM32F410xx devices vector table for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M4 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;* 
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler                   ; Window WatchDog
-        DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection
-        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
-        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
-        DCD     FLASH_IRQHandler                  ; FLASH
-        DCD     RCC_IRQHandler                    ; RCC
-        DCD     EXTI0_IRQHandler                  ; EXTI Line0
-        DCD     EXTI1_IRQHandler                  ; EXTI Line1
-        DCD     EXTI2_IRQHandler                  ; EXTI Line2
-        DCD     EXTI3_IRQHandler                  ; EXTI Line3
-        DCD     EXTI4_IRQHandler                  ; EXTI Line4
-        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
-        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
-        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
-        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
-        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
-        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
-        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
-        DCD     ADC_IRQHandler                    ; ADC1
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
-        DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9
-        DCD     TIM1_UP_IRQHandler                ; TIM1 Update
-        DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
-        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
-        DCD     SPI1_IRQHandler                   ; SPI1
-        DCD     SPI2_IRQHandler                   ; SPI2
-        DCD     USART1_IRQHandler                 ; USART1
-        DCD     USART2_IRQHandler                 ; USART2
-        DCD     0                                 ; Reserved
-        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s
-        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     TIM5_IRQHandler                   ; TIM5
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-		DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC
-        DCD     0                                 ; Reserved
-        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
-        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
-        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
-        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
-        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
-        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
-        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
-        DCD     USART6_IRQHandler                 ; USART6
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     RNG_IRQHandler                    ; RNG
-        DCD     FPU_IRQHandler                    ; FPU
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     SPI5_IRQHandler                   ; SPI5
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     FMPI2C1_EV_IRQHandler             ; FMPI2C1 Event
-        DCD     FMPI2C1_ER_IRQHandler             ; FMPI2C1 Error
-        DCD     LPTIM1_IRQHandler                 ; LP TIM1
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler  
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler  
-        B PVD_IRQHandler
-
-        PUBWEAK TAMP_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMP_STAMP_IRQHandler  
-        B TAMP_STAMP_IRQHandler
-
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler  
-        B RTC_WKUP_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler  
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler  
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler  
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler  
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler  
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler  
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream0_IRQHandler  
-        B DMA1_Stream0_IRQHandler
-
-        PUBWEAK DMA1_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream1_IRQHandler  
-        B DMA1_Stream1_IRQHandler
-
-        PUBWEAK DMA1_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream2_IRQHandler  
-        B DMA1_Stream2_IRQHandler
-
-        PUBWEAK DMA1_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream3_IRQHandler  
-        B DMA1_Stream3_IRQHandler
-
-        PUBWEAK DMA1_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream4_IRQHandler  
-        B DMA1_Stream4_IRQHandler
-
-        PUBWEAK DMA1_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream5_IRQHandler  
-        B DMA1_Stream5_IRQHandler
-
-        PUBWEAK DMA1_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream6_IRQHandler  
-        B DMA1_Stream6_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC_IRQHandler  
-        B ADC_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler  
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_BRK_TIM9_IRQHandler  
-        B TIM1_BRK_TIM9_IRQHandler
-
-        PUBWEAK TIM1_UP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_UP_IRQHandler  
-        B TIM1_UP_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_TRG_COM_TIM11_IRQHandler  
-        B TIM1_TRG_COM_TIM11_IRQHandler
-        
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_CC_IRQHandler  
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler  
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler  
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler  
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler  
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler  
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler  
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler  
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler  
-        B USART2_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler  
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler  
-        B RTC_Alarm_IRQHandler
-
-        PUBWEAK DMA1_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream7_IRQHandler  
-        B DMA1_Stream7_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler  
-        B TIM5_IRQHandler
-
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_DAC_IRQHandler  
-        B TIM6_DAC_IRQHandler
-
-        PUBWEAK DMA2_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream0_IRQHandler  
-        B DMA2_Stream0_IRQHandler
-
-        PUBWEAK DMA2_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream1_IRQHandler  
-        B DMA2_Stream1_IRQHandler
-
-        PUBWEAK DMA2_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream2_IRQHandler  
-        B DMA2_Stream2_IRQHandler
-
-        PUBWEAK DMA2_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream3_IRQHandler  
-        B DMA2_Stream3_IRQHandler
-
-        PUBWEAK DMA2_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream4_IRQHandler  
-        B DMA2_Stream4_IRQHandler
-
-        PUBWEAK DMA2_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream5_IRQHandler  
-        B DMA2_Stream5_IRQHandler
-
-        PUBWEAK DMA2_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream6_IRQHandler  
-        B DMA2_Stream6_IRQHandler
-
-        PUBWEAK DMA2_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream7_IRQHandler  
-        B DMA2_Stream7_IRQHandler
-
-        PUBWEAK USART6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler  
-        B USART6_IRQHandler
-
-        PUBWEAK RNG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RNG_IRQHandler
-        B RNG_IRQHandler
-
-        PUBWEAK FPU_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FPU_IRQHandler  
-        B FPU_IRQHandler
-		
-        PUBWEAK SPI5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI5_IRQHandler  
-        B SPI5_IRQHandler
-
-        PUBWEAK FMPI2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FMPI2C1_EV_IRQHandler  
-        B FMPI2C1_EV_IRQHandler
-
-        PUBWEAK FMPI2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FMPI2C1_ER_IRQHandler
-        B FMPI2C1_ER_IRQHandler
-
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f411xe.s

@@ -1,513 +0,0 @@
-;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name          : startup_stm32f411xe.s
-;* Author             : MCD Application Team
-;* @version           : V1.8.0
-;* @date              : 09-November-2016
-;* Description        : STM32F401xx devices vector table for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M4 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-;* You may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at:
-;* 
-;*        http://www.st.com/software_license_agreement_liberty_v2
-;* 
-;* Unless required by applicable law or agreed to in writing, software 
-;* distributed under the License is distributed on an "AS IS" BASIS, 
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;* 
-;*******************************************************************************/
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler                   ; Window WatchDog
-        DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection
-        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
-        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
-        DCD     FLASH_IRQHandler                  ; FLASH
-        DCD     RCC_IRQHandler                    ; RCC
-        DCD     EXTI0_IRQHandler                  ; EXTI Line0
-        DCD     EXTI1_IRQHandler                  ; EXTI Line1
-        DCD     EXTI2_IRQHandler                  ; EXTI Line2
-        DCD     EXTI3_IRQHandler                  ; EXTI Line3
-        DCD     EXTI4_IRQHandler                  ; EXTI Line4
-        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
-        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
-        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
-        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
-        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
-        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
-        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
-        DCD     ADC_IRQHandler                    ; ADC1
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
-        DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9
-        DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10
-        DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
-        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
-        DCD     TIM2_IRQHandler                   ; TIM2
-        DCD     TIM3_IRQHandler                   ; TIM3
-        DCD     TIM4_IRQHandler                   ; TIM4
-        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
-        DCD     SPI1_IRQHandler                   ; SPI1
-        DCD     SPI2_IRQHandler                   ; SPI2
-        DCD     USART1_IRQHandler                 ; USART1
-        DCD     USART2_IRQHandler                 ; USART2
-        DCD     0                                 ; Reserved
-        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s
-        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
-        DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
-        DCD     0                                 ; Reserved
-        DCD     SDIO_IRQHandler                   ; SDIO
-        DCD     TIM5_IRQHandler                   ; TIM5
-        DCD     SPI3_IRQHandler                   ; SPI3
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
-        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
-        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
-        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
-        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     OTG_FS_IRQHandler                 ; USB OTG FS
-        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
-        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
-        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
-        DCD     USART6_IRQHandler                 ; USART6
-        DCD     I2C3_EV_IRQHandler                ; I2C3 event
-        DCD     I2C3_ER_IRQHandler                ; I2C3 error
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     FPU_IRQHandler                    ; FPU
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     SPI4_IRQHandler                   ; SPI4
-        DCD     SPI5_IRQHandler                   ; SPI5
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler  
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler  
-        B PVD_IRQHandler
-
-        PUBWEAK TAMP_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMP_STAMP_IRQHandler  
-        B TAMP_STAMP_IRQHandler
-
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler  
-        B RTC_WKUP_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler  
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler  
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler  
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler  
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler  
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler  
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream0_IRQHandler  
-        B DMA1_Stream0_IRQHandler
-
-        PUBWEAK DMA1_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream1_IRQHandler  
-        B DMA1_Stream1_IRQHandler
-
-        PUBWEAK DMA1_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream2_IRQHandler  
-        B DMA1_Stream2_IRQHandler
-
-        PUBWEAK DMA1_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream3_IRQHandler  
-        B DMA1_Stream3_IRQHandler
-
-        PUBWEAK DMA1_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream4_IRQHandler  
-        B DMA1_Stream4_IRQHandler
-
-        PUBWEAK DMA1_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream5_IRQHandler  
-        B DMA1_Stream5_IRQHandler
-
-        PUBWEAK DMA1_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream6_IRQHandler  
-        B DMA1_Stream6_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC_IRQHandler  
-        B ADC_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler  
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_BRK_TIM9_IRQHandler  
-        B TIM1_BRK_TIM9_IRQHandler
-
-        PUBWEAK TIM1_UP_TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_UP_TIM10_IRQHandler  
-        B TIM1_UP_TIM10_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_TRG_COM_TIM11_IRQHandler  
-        B TIM1_TRG_COM_TIM11_IRQHandler
-        
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_CC_IRQHandler  
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler  
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler  
-        B TIM3_IRQHandler
-
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler  
-        B TIM4_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler  
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler  
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler  
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler  
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler  
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler  
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler  
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler  
-        B USART2_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler  
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler  
-        B RTC_Alarm_IRQHandler
-
-        PUBWEAK OTG_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_WKUP_IRQHandler  
-        B OTG_FS_WKUP_IRQHandler
-
-        PUBWEAK DMA1_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream7_IRQHandler  
-        B DMA1_Stream7_IRQHandler
-
-        PUBWEAK SDIO_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO_IRQHandler  
-        B SDIO_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler  
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler  
-        B SPI3_IRQHandler
-
-        PUBWEAK DMA2_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream0_IRQHandler  
-        B DMA2_Stream0_IRQHandler
-
-        PUBWEAK DMA2_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream1_IRQHandler  
-        B DMA2_Stream1_IRQHandler
-
-        PUBWEAK DMA2_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream2_IRQHandler  
-        B DMA2_Stream2_IRQHandler
-
-        PUBWEAK DMA2_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream3_IRQHandler  
-        B DMA2_Stream3_IRQHandler
-
-        PUBWEAK DMA2_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream4_IRQHandler  
-        B DMA2_Stream4_IRQHandler
-
-        PUBWEAK OTG_FS_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_IRQHandler  
-        B OTG_FS_IRQHandler
-
-        PUBWEAK DMA2_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream5_IRQHandler  
-        B DMA2_Stream5_IRQHandler
-
-        PUBWEAK DMA2_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream6_IRQHandler  
-        B DMA2_Stream6_IRQHandler
-
-        PUBWEAK DMA2_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream7_IRQHandler  
-        B DMA2_Stream7_IRQHandler
-
-        PUBWEAK USART6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler  
-        B USART6_IRQHandler
-
-        PUBWEAK I2C3_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler  
-        B I2C3_EV_IRQHandler
-
-        PUBWEAK I2C3_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ER_IRQHandler  
-        B I2C3_ER_IRQHandler
-
-        PUBWEAK FPU_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FPU_IRQHandler  
-        B FPU_IRQHandler
-
-        PUBWEAK SPI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI4_IRQHandler  
-        B SPI4_IRQHandler
-		
-        PUBWEAK SPI5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI5_IRQHandler  
-        B SPI5_IRQHandler
-        
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f412xg.s

@@ -1,634 +0,0 @@
-;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name          : startup_stm32f412xg.s
-;* Author             : MCD Application Team
-;* @version           : V1.8.0
-;* @date              : 09-November-2016
-;* Description        : STM32F412xGxx devices vector table for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M4 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-;* You may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at:
-;* 
-;*        http://www.st.com/software_license_agreement_liberty_v2
-;* 
-;* Unless required by applicable law or agreed to in writing, software 
-;* distributed under the License is distributed on an "AS IS" BASIS, 
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;* 
-;*******************************************************************************/
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler                   ; Window WatchDog
-        DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection
-        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
-        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
-        DCD     FLASH_IRQHandler                  ; FLASH
-        DCD     RCC_IRQHandler                    ; RCC
-        DCD     EXTI0_IRQHandler                  ; EXTI Line0
-        DCD     EXTI1_IRQHandler                  ; EXTI Line1
-        DCD     EXTI2_IRQHandler                  ; EXTI Line2
-        DCD     EXTI3_IRQHandler                  ; EXTI Line3
-        DCD     EXTI4_IRQHandler                  ; EXTI Line4
-        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
-        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
-        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
-        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
-        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
-        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
-        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
-        DCD     ADC_IRQHandler                    ; ADC1
-        DCD     CAN1_TX_IRQHandler                ; CAN1 TX
-        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
-        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
-        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
-        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
-        DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9
-        DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10
-        DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
-        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
-        DCD     TIM2_IRQHandler                   ; TIM2
-        DCD     TIM3_IRQHandler                   ; TIM3
-        DCD     TIM4_IRQHandler                   ; TIM4
-        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
-        DCD     SPI1_IRQHandler                   ; SPI1
-        DCD     SPI2_IRQHandler                   ; SPI2
-        DCD     USART1_IRQHandler                 ; USART1
-        DCD     USART2_IRQHandler                 ; USART2
-        DCD     USART3_IRQHandler                 ; USART3
-        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s
-        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
-        DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line
-        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12
-        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13
-        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
-        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare
-        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
-        DCD     FMC_IRQHandler                    ; FMC
-        DCD     SDIO_IRQHandler                   ; SDIO
-        DCD     TIM5_IRQHandler                   ; TIM5
-        DCD     SPI3_IRQHandler                   ; SPI3
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     TIM6_IRQHandler                   ; TIM6
-        DCD     TIM7_IRQHandler                   ; TIM7
-        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
-        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
-        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
-        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
-        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
-        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter 0 global interrupt
-        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter 1 global interrupt
-        DCD     CAN2_TX_IRQHandler                ; CAN2 TX
-        DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0
-        DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1
-        DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE
-        DCD     OTG_FS_IRQHandler                 ; USB OTG FS
-        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
-        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
-        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
-        DCD     USART6_IRQHandler                 ; USART6
-        DCD     I2C3_EV_IRQHandler                ; I2C3 event
-        DCD     I2C3_ER_IRQHandler                ; I2C3 error
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     RNG_IRQHandler                    ; RNG
-        DCD     FPU_IRQHandler                    ; FPU
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     SPI4_IRQHandler                   ; SPI4
-        DCD     SPI5_IRQHandler                   ; SPI5
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     QUADSPI_IRQHandler                ; QuadSPI
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     FMPI2C1_EV_IRQHandler             ; FMPI2C1 Event
-        DCD     FMPI2C1_ER_IRQHandler             ; FMPI2C1 Error
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler  
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler  
-        B PVD_IRQHandler
-
-        PUBWEAK TAMP_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMP_STAMP_IRQHandler  
-        B TAMP_STAMP_IRQHandler
-
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler  
-        B RTC_WKUP_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler  
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler  
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler  
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler  
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler  
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler  
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream0_IRQHandler  
-        B DMA1_Stream0_IRQHandler
-
-        PUBWEAK DMA1_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream1_IRQHandler  
-        B DMA1_Stream1_IRQHandler
-
-        PUBWEAK DMA1_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream2_IRQHandler  
-        B DMA1_Stream2_IRQHandler
-
-        PUBWEAK DMA1_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream3_IRQHandler  
-        B DMA1_Stream3_IRQHandler
-
-        PUBWEAK DMA1_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream4_IRQHandler  
-        B DMA1_Stream4_IRQHandler
-
-        PUBWEAK DMA1_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream5_IRQHandler  
-        B DMA1_Stream5_IRQHandler
-
-        PUBWEAK DMA1_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream6_IRQHandler  
-        B DMA1_Stream6_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC_IRQHandler  
-        B ADC_IRQHandler
-
-        PUBWEAK CAN1_TX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_TX_IRQHandler  
-        B CAN1_TX_IRQHandler
-		
-        PUBWEAK CAN1_RX0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX0_IRQHandler  
-        B CAN1_RX0_IRQHandler
-		
-        PUBWEAK CAN1_RX1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler  
-        B CAN1_RX1_IRQHandler
-		
-        PUBWEAK CAN1_SCE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SCE_IRQHandler  
-        B CAN1_SCE_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler  
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_BRK_TIM9_IRQHandler  
-        B TIM1_BRK_TIM9_IRQHandler
-
-        PUBWEAK TIM1_UP_TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_UP_TIM10_IRQHandler  
-        B TIM1_UP_TIM10_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_TRG_COM_TIM11_IRQHandler  
-        B TIM1_TRG_COM_TIM11_IRQHandler
-        
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_CC_IRQHandler  
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler  
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler  
-        B TIM3_IRQHandler
-
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler  
-        B TIM4_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler  
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler  
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler  
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler  
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler  
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler  
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler  
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler  
-        B USART2_IRQHandler
-
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler  
-        B USART3_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler  
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler  
-        B RTC_Alarm_IRQHandler
-
-        PUBWEAK OTG_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_WKUP_IRQHandler  
-        B OTG_FS_WKUP_IRQHandler
-
-        PUBWEAK TIM8_BRK_TIM12_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_BRK_TIM12_IRQHandler  
-        B TIM8_BRK_TIM12_IRQHandler
-		
-        PUBWEAK TIM8_UP_TIM13_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_UP_TIM13_IRQHandler  
-        B TIM8_UP_TIM13_IRQHandler
-		
-        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_TRG_COM_TIM14_IRQHandler  
-        B TIM8_TRG_COM_TIM14_IRQHandler
-		
-        PUBWEAK TIM8_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_CC_IRQHandler  
-        B TIM8_CC_IRQHandler
-
-        PUBWEAK DMA1_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream7_IRQHandler  
-        B DMA1_Stream7_IRQHandler
-
-        PUBWEAK FMC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FMC_IRQHandler  
-        B FMC_IRQHandler
-
-        PUBWEAK SDIO_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO_IRQHandler  
-        B SDIO_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler  
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler  
-        B SPI3_IRQHandler
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler  
-        B TIM6_IRQHandler
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler  
-        B TIM7_IRQHandler
-
-        PUBWEAK DMA2_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream0_IRQHandler  
-        B DMA2_Stream0_IRQHandler
-
-        PUBWEAK DMA2_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream1_IRQHandler  
-        B DMA2_Stream1_IRQHandler
-
-        PUBWEAK DMA2_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream2_IRQHandler  
-        B DMA2_Stream2_IRQHandler
-
-        PUBWEAK DMA2_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream3_IRQHandler  
-        B DMA2_Stream3_IRQHandler
-
-        PUBWEAK DMA2_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream4_IRQHandler  
-        B DMA2_Stream4_IRQHandler
-		
-        PUBWEAK DFSDM1_FLT0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DFSDM1_FLT0_IRQHandler  
-        B DFSDM1_FLT0_IRQHandler
-
-        PUBWEAK DFSDM1_FLT1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DFSDM1_FLT1_IRQHandler  
-        B DFSDM1_FLT1_IRQHandler
-		
-        PUBWEAK CAN2_TX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler  
-        B CAN2_TX_IRQHandler
-
-        PUBWEAK CAN2_RX0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler  
-        B CAN2_RX0_IRQHandler
-
-        PUBWEAK CAN2_RX1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler  
-        B CAN2_RX1_IRQHandler
-
-        PUBWEAK CAN2_SCE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SCE_IRQHandler  
-        B CAN2_SCE_IRQHandler
-
-        PUBWEAK OTG_FS_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_IRQHandler  
-        B OTG_FS_IRQHandler
-
-        PUBWEAK DMA2_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream5_IRQHandler  
-        B DMA2_Stream5_IRQHandler
-
-        PUBWEAK DMA2_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream6_IRQHandler  
-        B DMA2_Stream6_IRQHandler
-
-        PUBWEAK DMA2_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream7_IRQHandler  
-        B DMA2_Stream7_IRQHandler
-
-        PUBWEAK USART6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler  
-        B USART6_IRQHandler
-
-        PUBWEAK I2C3_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler  
-        B I2C3_EV_IRQHandler
-
-        PUBWEAK I2C3_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ER_IRQHandler  
-        B I2C3_ER_IRQHandler
-
-        PUBWEAK RNG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RNG_IRQHandler
-        B RNG_IRQHandler
-
-        PUBWEAK FPU_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FPU_IRQHandler  
-        B FPU_IRQHandler
-
-        PUBWEAK SPI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI4_IRQHandler  
-        B SPI4_IRQHandler
-		
-        PUBWEAK SPI5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI5_IRQHandler  
-        B SPI5_IRQHandler
-
-        PUBWEAK QUADSPI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-QUADSPI_IRQHandler  
-        B QUADSPI_IRQHandler
-
-        PUBWEAK FMPI2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FMPI2C1_EV_IRQHandler  
-        B FMPI2C1_EV_IRQHandler
-
-        PUBWEAK FMPI2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FMPI2C1_ER_IRQHandler
-        B FMPI2C1_ER_IRQHandler
-        
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f413_423xx.s

@@ -1,734 +0,0 @@
-;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name          : startup_stm32f423xx.s
-;* Author             : MCD Application Team
-;* @version           : V1.8.0
-;* @date              : 09-November-2016
-;* Description        : STM32F423xx devices vector table for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M4 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;* 
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler                   ; Window WatchDog
-        DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection
-        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
-        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
-        DCD     FLASH_IRQHandler                  ; FLASH
-        DCD     RCC_IRQHandler                    ; RCC
-        DCD     EXTI0_IRQHandler                  ; EXTI Line0
-        DCD     EXTI1_IRQHandler                  ; EXTI Line1
-        DCD     EXTI2_IRQHandler                  ; EXTI Line2
-        DCD     EXTI3_IRQHandler                  ; EXTI Line3
-        DCD     EXTI4_IRQHandler                  ; EXTI Line4
-        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
-        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
-        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
-        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
-        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
-        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
-        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
-        DCD     ADC_IRQHandler                    ; ADC1
-        DCD     CAN1_TX_IRQHandler                ; CAN1 TX
-        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
-        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
-        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
-        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
-        DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9
-        DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10
-        DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
-        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
-        DCD     TIM2_IRQHandler                   ; TIM2
-        DCD     TIM3_IRQHandler                   ; TIM3
-        DCD     TIM4_IRQHandler                   ; TIM4
-        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
-        DCD     SPI1_IRQHandler                   ; SPI1
-        DCD     SPI2_IRQHandler                   ; SPI2
-        DCD     USART1_IRQHandler                 ; USART1
-        DCD     USART2_IRQHandler                 ; USART2
-        DCD     USART3_IRQHandler                 ; USART3
-        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s
-        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
-        DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line
-        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12
-        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13
-        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
-        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare
-        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
-        DCD     FSMC_IRQHandler                   ; FSMC
-        DCD     SDIO_IRQHandler                   ; SDIO
-        DCD     TIM5_IRQHandler                   ; TIM5
-        DCD     SPI3_IRQHandler                   ; SPI3
-        DCD     UART4_IRQHandler                  ; UART4
-        DCD     UART5_IRQHandler                  ; UART5
-        DCD     TIM6_DAC_IRQHandler               ; TIM6, DAC1 and DAC2
-        DCD     TIM7_IRQHandler                   ; TIM7
-        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
-        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
-        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
-        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
-        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
-        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM1 Filter0
-        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM1 Filter1
-        DCD     CAN2_TX_IRQHandler                ; CAN2 TX
-        DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0
-        DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1
-        DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE
-        DCD     OTG_FS_IRQHandler                 ; USB OTG FS
-        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
-        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
-        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
-        DCD     USART6_IRQHandler                 ; USART6
-        DCD     I2C3_EV_IRQHandler                ; I2C3 event
-        DCD     I2C3_ER_IRQHandler                ; I2C3 error
-        DCD     CAN3_TX_IRQHandler                ; CAN3 TX
-        DCD     CAN3_RX0_IRQHandler               ; CAN3 RX0
-        DCD     CAN3_RX1_IRQHandler               ; CAN3 RX1
-        DCD     CAN3_SCE_IRQHandler               ; CAN3 SCE
-        DCD     0                                 ; Reserved
-        DCD     AES_IRQHandler                    ; AES
-        DCD     RNG_IRQHandler                    ; RNG
-        DCD     FPU_IRQHandler                    ; FPU
-        DCD     UART7_IRQHandler                  ; UART7
-        DCD     UART8_IRQHandler                  ; UART8
-        DCD     SPI4_IRQHandler                   ; SPI4
-        DCD     SPI5_IRQHandler                   ; SPI5
-        DCD     0                                 ; Reserved
-        DCD     SAI1_IRQHandler                   ; SAI1
-        DCD     UART9_IRQHandler                  ; UART9
-        DCD     UART10_IRQHandler                 ; UART10
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     QUADSPI_IRQHandler                ; QuadSPI
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     FMPI2C1_EV_IRQHandler             ; FMPI2C1 Event
-        DCD     FMPI2C1_ER_IRQHandler             ; FMPI2C1 Error
-        DCD     LPTIM1_IRQHandler                 ; LPTIM1
-        DCD     DFSDM2_FLT0_IRQHandler            ; DFSDM2 Filter0
-        DCD     DFSDM2_FLT1_IRQHandler            ; DFSDM2 Filter1
-        DCD     DFSDM2_FLT2_IRQHandler            ; DFSDM2 Filter2
-        DCD     DFSDM2_FLT3_IRQHandler            ; DFSDM2 Filter3
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler  
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler  
-        B PVD_IRQHandler
-
-        PUBWEAK TAMP_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMP_STAMP_IRQHandler  
-        B TAMP_STAMP_IRQHandler
-
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler  
-        B RTC_WKUP_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler  
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler  
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler  
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler  
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler  
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler  
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream0_IRQHandler  
-        B DMA1_Stream0_IRQHandler
-
-        PUBWEAK DMA1_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream1_IRQHandler  
-        B DMA1_Stream1_IRQHandler
-
-        PUBWEAK DMA1_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream2_IRQHandler  
-        B DMA1_Stream2_IRQHandler
-
-        PUBWEAK DMA1_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream3_IRQHandler  
-        B DMA1_Stream3_IRQHandler
-
-        PUBWEAK DMA1_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream4_IRQHandler  
-        B DMA1_Stream4_IRQHandler
-
-        PUBWEAK DMA1_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream5_IRQHandler  
-        B DMA1_Stream5_IRQHandler
-
-        PUBWEAK DMA1_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream6_IRQHandler  
-        B DMA1_Stream6_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC_IRQHandler  
-        B ADC_IRQHandler
-
-        PUBWEAK CAN1_TX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_TX_IRQHandler  
-        B CAN1_TX_IRQHandler
-
-        PUBWEAK CAN1_RX0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX0_IRQHandler  
-        B CAN1_RX0_IRQHandler
-
-        PUBWEAK CAN1_RX1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler  
-        B CAN1_RX1_IRQHandler
-
-        PUBWEAK CAN1_SCE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SCE_IRQHandler  
-        B CAN1_SCE_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler  
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_BRK_TIM9_IRQHandler  
-        B TIM1_BRK_TIM9_IRQHandler
-
-        PUBWEAK TIM1_UP_TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_UP_TIM10_IRQHandler  
-        B TIM1_UP_TIM10_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_TRG_COM_TIM11_IRQHandler  
-        B TIM1_TRG_COM_TIM11_IRQHandler
-        
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_CC_IRQHandler  
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler  
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler  
-        B TIM3_IRQHandler
-
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler  
-        B TIM4_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler  
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler  
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler  
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler  
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler  
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler  
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler  
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler  
-        B USART2_IRQHandler
-
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler  
-        B USART3_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler  
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler  
-        B RTC_Alarm_IRQHandler
-
-        PUBWEAK OTG_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_WKUP_IRQHandler  
-        B OTG_FS_WKUP_IRQHandler
-
-        PUBWEAK TIM8_BRK_TIM12_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_BRK_TIM12_IRQHandler  
-        B TIM8_BRK_TIM12_IRQHandler
-
-        PUBWEAK TIM8_UP_TIM13_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_UP_TIM13_IRQHandler  
-        B TIM8_UP_TIM13_IRQHandler
-
-        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_TRG_COM_TIM14_IRQHandler  
-        B TIM8_TRG_COM_TIM14_IRQHandler
-
-        PUBWEAK TIM8_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_CC_IRQHandler  
-        B TIM8_CC_IRQHandler
-
-        PUBWEAK DMA1_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream7_IRQHandler  
-        B DMA1_Stream7_IRQHandler
-		
-        PUBWEAK FSMC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FSMC_IRQHandler  
-        B FSMC_IRQHandler		
-
-        PUBWEAK SDIO_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO_IRQHandler  
-        B SDIO_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler  
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler  
-        B SPI3_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler  
-        B UART4_IRQHandler
-
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
-        B UART5_IRQHandler
-
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_DAC_IRQHandler  
-        B TIM6_DAC_IRQHandler
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler  
-        B TIM7_IRQHandler
-
-        PUBWEAK DMA2_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream0_IRQHandler  
-        B DMA2_Stream0_IRQHandler
-
-        PUBWEAK DMA2_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream1_IRQHandler  
-        B DMA2_Stream1_IRQHandler
-
-        PUBWEAK DMA2_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream2_IRQHandler  
-        B DMA2_Stream2_IRQHandler
-
-        PUBWEAK DMA2_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream3_IRQHandler  
-        B DMA2_Stream3_IRQHandler
-
-        PUBWEAK DMA2_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream4_IRQHandler  
-        B DMA2_Stream4_IRQHandler
-
-        PUBWEAK DFSDM1_FLT0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DFSDM1_FLT0_IRQHandler  
-        B DFSDM1_FLT0_IRQHandler
-
-        PUBWEAK DFSDM1_FLT1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DFSDM1_FLT1_IRQHandler  
-        B DFSDM1_FLT1_IRQHandler
-
-        PUBWEAK CAN2_TX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler  
-        B CAN2_TX_IRQHandler
-
-        PUBWEAK CAN2_RX0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler  
-        B CAN2_RX0_IRQHandler
-
-        PUBWEAK CAN2_RX1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler  
-        B CAN2_RX1_IRQHandler
-
-        PUBWEAK CAN2_SCE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SCE_IRQHandler  
-        B CAN2_SCE_IRQHandler
-
-        PUBWEAK OTG_FS_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_IRQHandler  
-        B OTG_FS_IRQHandler
-
-        PUBWEAK DMA2_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream5_IRQHandler  
-        B DMA2_Stream5_IRQHandler
-
-        PUBWEAK DMA2_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream6_IRQHandler  
-        B DMA2_Stream6_IRQHandler
-
-        PUBWEAK DMA2_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream7_IRQHandler  
-        B DMA2_Stream7_IRQHandler
-
-        PUBWEAK USART6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler  
-        B USART6_IRQHandler
-
-        PUBWEAK I2C3_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler  
-        B I2C3_EV_IRQHandler
-
-        PUBWEAK I2C3_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ER_IRQHandler  
-        B I2C3_ER_IRQHandler
-
-        PUBWEAK CAN3_TX_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1) 
-CAN3_TX_IRQHandler 
-        B CAN3_TX_IRQHandler
-
-        PUBWEAK CAN3_RX0_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1) 
-CAN3_RX0_IRQHandler 
-        B CAN3_RX0_IRQHandler
-
-        PUBWEAK CAN3_RX1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1) 
-CAN3_RX1_IRQHandler 
-        B CAN3_RX1_IRQHandler
-
-        PUBWEAK CAN3_SCE_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1) 
-CAN3_SCE_IRQHandler 
-        B CAN3_SCE_IRQHandler
-		
-        PUBWEAK AES_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-AES_IRQHandler  
-        B AES_IRQHandler		
-
-        PUBWEAK RNG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RNG_IRQHandler
-        B RNG_IRQHandler
-
-        PUBWEAK FPU_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FPU_IRQHandler  
-        B FPU_IRQHandler
-
-        PUBWEAK UART7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART7_IRQHandler 
-        B UART7_IRQHandler  
-
-        PUBWEAK UART8_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART8_IRQHandler             
-        B UART8_IRQHandler
-        
-        PUBWEAK SPI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-SPI4_IRQHandler  
-        B SPI4_IRQHandler
-
-        PUBWEAK SPI5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI5_IRQHandler  
-        B SPI5_IRQHandler
-
-        PUBWEAK SAI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-SAI1_IRQHandler  
-        B SAI1_IRQHandler
-
-        PUBWEAK UART9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART9_IRQHandler             
-        B UART9_IRQHandler
-        
-        PUBWEAK UART10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART10_IRQHandler             
-        B UART10_IRQHandler
-        
-        PUBWEAK QUADSPI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-QUADSPI_IRQHandler  
-        B QUADSPI_IRQHandler
-
-        PUBWEAK FMPI2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FMPI2C1_EV_IRQHandler  
-        B FMPI2C1_EV_IRQHandler
-
-        PUBWEAK FMPI2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FMPI2C1_ER_IRQHandler
-        B FMPI2C1_ER_IRQHandler
-		
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1) 
-LPTIM1_IRQHandler 
-        B LPTIM1_IRQHandler		
-
-        PUBWEAK DFSDM2_FLT0_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1) 
-DFSDM2_FLT0_IRQHandler 
-        B DFSDM2_FLT0_IRQHandler
-
-        PUBWEAK DFSDM2_FLT1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1) 
-DFSDM2_FLT1_IRQHandler 
-        B DFSDM2_FLT1_IRQHandler
-
-        PUBWEAK DFSDM2_FLT2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1) 
-DFSDM2_FLT2_IRQHandler 
-        B DFSDM2_FLT2_IRQHandler
-
-        PUBWEAK DFSDM2_FLT3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1) 
-DFSDM2_FLT3_IRQHandler 
-        B DFSDM2_FLT3_IRQHandler
-        
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f427_437xx.s

@@ -1,681 +0,0 @@
-;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name          : startup_stm32f427_437xx.s
-;* Author             : MCD Application Team
-;* @version           : V1.8.0
-;* @date              : 09-November-2016
-;* Description        : STM32F427xx/437xx devices vector table for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock and the external SRAM/SDRAM mounted 
-;*                        on STM324x7I-EVAL board to be used as data memory (optional, 
-;*                        to be enabled by user)
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M4 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-;* You may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at:
-;* 
-;*        http://www.st.com/software_license_agreement_liberty_v2
-;* 
-;* Unless required by applicable law or agreed to in writing, software 
-;* distributed under the License is distributed on an "AS IS" BASIS, 
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;* 
-;*******************************************************************************/
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
-        DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
-        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
-        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
-        DCD     FLASH_IRQHandler                  ; FLASH                                           
-        DCD     RCC_IRQHandler                    ; RCC                                             
-        DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
-        DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
-        DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
-        DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
-        DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
-        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
-        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
-        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
-        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
-        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
-        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
-        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
-        DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
-        DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
-        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
-        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
-        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
-        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
-        DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
-        DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
-        DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
-        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
-        DCD     TIM2_IRQHandler                   ; TIM2                                            
-        DCD     TIM3_IRQHandler                   ; TIM3                                            
-        DCD     TIM4_IRQHandler                   ; TIM4                                            
-        DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
-        DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
-        DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
-        DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
-        DCD     SPI1_IRQHandler                   ; SPI1                                            
-        DCD     SPI2_IRQHandler                   ; SPI2                                            
-        DCD     USART1_IRQHandler                 ; USART1                                          
-        DCD     USART2_IRQHandler                 ; USART2                                          
-        DCD     USART3_IRQHandler                 ; USART3                                          
-        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
-        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
-        DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
-        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
-        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
-        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
-        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
-        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
-        DCD     FMC_IRQHandler                    ; FMC                                            
-        DCD     SDIO_IRQHandler                   ; SDIO                                            
-        DCD     TIM5_IRQHandler                   ; TIM5                                            
-        DCD     SPI3_IRQHandler                   ; SPI3                                            
-        DCD     UART4_IRQHandler                  ; UART4                                           
-        DCD     UART5_IRQHandler                  ; UART5                                           
-        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
-        DCD     TIM7_IRQHandler                   ; TIM7                   
-        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
-        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
-        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
-        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
-        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
-        DCD     ETH_IRQHandler                    ; Ethernet                                        
-        DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
-        DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
-        DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
-        DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
-        DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
-        DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
-        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
-        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
-        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
-        DCD     USART6_IRQHandler                 ; USART6                                           
-        DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
-        DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
-        DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
-        DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
-        DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
-        DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
-        DCD     DCMI_IRQHandler                   ; DCMI                                            
-        DCD     CRYP_IRQHandler                   ; CRYP crypto                                     
-        DCD     HASH_RNG_IRQHandler               ; Hash and Rng
-        DCD     FPU_IRQHandler                    ; FPU
-        DCD     UART7_IRQHandler                  ; UART7
-        DCD     UART8_IRQHandler                  ; UART8
-        DCD     SPI4_IRQHandler                   ; SPI4
-        DCD     SPI5_IRQHandler                   ; SPI5
-        DCD     SPI6_IRQHandler                   ; SPI6
-        DCD     SAI1_IRQHandler                   ; SAI1
-        DCD     0                                 ; Reserved 
-        DCD     0                                 ; Reserved 
-        DCD     DMA2D_IRQHandler                  ; DMA2D
-    
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler  
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler  
-        B PVD_IRQHandler
-
-        PUBWEAK TAMP_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TAMP_STAMP_IRQHandler  
-        B TAMP_STAMP_IRQHandler
-
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-RTC_WKUP_IRQHandler  
-        B RTC_WKUP_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler  
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler  
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler  
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler  
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler  
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-EXTI4_IRQHandler  
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream0_IRQHandler  
-        B DMA1_Stream0_IRQHandler
-
-        PUBWEAK DMA1_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream1_IRQHandler  
-        B DMA1_Stream1_IRQHandler
-
-        PUBWEAK DMA1_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream2_IRQHandler  
-        B DMA1_Stream2_IRQHandler
-
-        PUBWEAK DMA1_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream3_IRQHandler  
-        B DMA1_Stream3_IRQHandler
-
-        PUBWEAK DMA1_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream4_IRQHandler  
-        B DMA1_Stream4_IRQHandler
-
-        PUBWEAK DMA1_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream5_IRQHandler  
-        B DMA1_Stream5_IRQHandler
-
-        PUBWEAK DMA1_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream6_IRQHandler  
-        B DMA1_Stream6_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC_IRQHandler  
-        B ADC_IRQHandler
-
-        PUBWEAK CAN1_TX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-CAN1_TX_IRQHandler  
-        B CAN1_TX_IRQHandler
-
-        PUBWEAK CAN1_RX0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN1_RX0_IRQHandler  
-        B CAN1_RX0_IRQHandler
-
-        PUBWEAK CAN1_RX1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN1_RX1_IRQHandler  
-        B CAN1_RX1_IRQHandler
-
-        PUBWEAK CAN1_SCE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN1_SCE_IRQHandler  
-        B CAN1_SCE_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-EXTI9_5_IRQHandler  
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_BRK_TIM9_IRQHandler  
-        B TIM1_BRK_TIM9_IRQHandler
-
-        PUBWEAK TIM1_UP_TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_UP_TIM10_IRQHandler  
-        B TIM1_UP_TIM10_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_TRG_COM_TIM11_IRQHandler  
-        B TIM1_TRG_COM_TIM11_IRQHandler
-        
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_CC_IRQHandler  
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler  
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler  
-        B TIM3_IRQHandler
-
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler  
-        B TIM4_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C1_EV_IRQHandler  
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C1_ER_IRQHandler  
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C2_EV_IRQHandler  
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C2_ER_IRQHandler  
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler  
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler  
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler  
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler  
-        B USART2_IRQHandler
-
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler  
-        B USART3_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-EXTI15_10_IRQHandler  
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-RTC_Alarm_IRQHandler  
-        B RTC_Alarm_IRQHandler
-
-        PUBWEAK OTG_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_FS_WKUP_IRQHandler  
-        B OTG_FS_WKUP_IRQHandler
-      
-        PUBWEAK TIM8_BRK_TIM12_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM8_BRK_TIM12_IRQHandler  
-        B TIM8_BRK_TIM12_IRQHandler
-
-        PUBWEAK TIM8_UP_TIM13_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM8_UP_TIM13_IRQHandler  
-        B TIM8_UP_TIM13_IRQHandler
-
-        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM8_TRG_COM_TIM14_IRQHandler  
-        B TIM8_TRG_COM_TIM14_IRQHandler
-
-        PUBWEAK TIM8_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-TIM8_CC_IRQHandler  
-        B TIM8_CC_IRQHandler
-
-        PUBWEAK DMA1_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream7_IRQHandler  
-        B DMA1_Stream7_IRQHandler
-
-        PUBWEAK FMC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FMC_IRQHandler  
-        B FMC_IRQHandler
-
-        PUBWEAK SDIO_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO_IRQHandler  
-        B SDIO_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler  
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler  
-        B SPI3_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler  
-        B UART4_IRQHandler
-
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler  
-        B UART5_IRQHandler
-
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-TIM6_DAC_IRQHandler  
-        B TIM6_DAC_IRQHandler
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-TIM7_IRQHandler  
-        B TIM7_IRQHandler
-
-        PUBWEAK DMA2_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream0_IRQHandler  
-        B DMA2_Stream0_IRQHandler
-
-        PUBWEAK DMA2_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream1_IRQHandler  
-        B DMA2_Stream1_IRQHandler
-
-        PUBWEAK DMA2_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream2_IRQHandler  
-        B DMA2_Stream2_IRQHandler
-
-        PUBWEAK DMA2_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream3_IRQHandler  
-        B DMA2_Stream3_IRQHandler
-
-        PUBWEAK DMA2_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream4_IRQHandler  
-        B DMA2_Stream4_IRQHandler
-
-        PUBWEAK ETH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ETH_IRQHandler  
-        B ETH_IRQHandler
-
-        PUBWEAK ETH_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-ETH_WKUP_IRQHandler  
-        B ETH_WKUP_IRQHandler
-
-        PUBWEAK CAN2_TX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-CAN2_TX_IRQHandler  
-        B CAN2_TX_IRQHandler
-
-        PUBWEAK CAN2_RX0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN2_RX0_IRQHandler  
-        B CAN2_RX0_IRQHandler
-
-        PUBWEAK CAN2_RX1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN2_RX1_IRQHandler  
-        B CAN2_RX1_IRQHandler
-
-        PUBWEAK CAN2_SCE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN2_SCE_IRQHandler  
-        B CAN2_SCE_IRQHandler
-
-        PUBWEAK OTG_FS_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_IRQHandler  
-        B OTG_FS_IRQHandler
-
-        PUBWEAK DMA2_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream5_IRQHandler  
-        B DMA2_Stream5_IRQHandler
-
-        PUBWEAK DMA2_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream6_IRQHandler  
-        B DMA2_Stream6_IRQHandler
-
-        PUBWEAK DMA2_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream7_IRQHandler  
-        B DMA2_Stream7_IRQHandler
-
-        PUBWEAK USART6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler  
-        B USART6_IRQHandler
-
-        PUBWEAK I2C3_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C3_EV_IRQHandler  
-        B I2C3_EV_IRQHandler
-
-        PUBWEAK I2C3_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C3_ER_IRQHandler  
-        B I2C3_ER_IRQHandler
-
-        PUBWEAK OTG_HS_EP1_OUT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_HS_EP1_OUT_IRQHandler  
-        B OTG_HS_EP1_OUT_IRQHandler
-
-        PUBWEAK OTG_HS_EP1_IN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_HS_EP1_IN_IRQHandler  
-        B OTG_HS_EP1_IN_IRQHandler
-
-        PUBWEAK OTG_HS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_HS_WKUP_IRQHandler  
-        B OTG_HS_WKUP_IRQHandler
-
-        PUBWEAK OTG_HS_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_IRQHandler  
-        B OTG_HS_IRQHandler
-
-        PUBWEAK DCMI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DCMI_IRQHandler  
-        B DCMI_IRQHandler
-
-        PUBWEAK CRYP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CRYP_IRQHandler  
-        B CRYP_IRQHandler
-
-        PUBWEAK HASH_RNG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-HASH_RNG_IRQHandler  
-        B HASH_RNG_IRQHandler
-
-        PUBWEAK FPU_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-FPU_IRQHandler  
-        B FPU_IRQHandler
-
-        PUBWEAK UART7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)      
-UART7_IRQHandler 
-        B UART7_IRQHandler  
-
-        PUBWEAK UART8_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-UART8_IRQHandler             
-        B UART8_IRQHandler
-        
-        PUBWEAK SPI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-SPI4_IRQHandler
-        B SPI4_IRQHandler                 
-
-        PUBWEAK SPI5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-SPI5_IRQHandler   
-        B SPI5_IRQHandler                  
-
-        PUBWEAK SPI6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-SPI6_IRQHandler 
-        B SPI6_IRQHandler                    
-
-        PUBWEAK SAI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-SAI1_IRQHandler  
-        B SAI1_IRQHandler                
-
-        PUBWEAK DMA2D_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-DMA2D_IRQHandler 
-        B DMA2D_IRQHandler                  
-
-
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f427x.s

@@ -1,692 +0,0 @@
-;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name          : startup_stm32f427x.s
-;* Author             : MCD Application Team
-;* @version           : V1.8.0
-;* @date              : 09-November-2016
-;* Description        : STM32F427xx/437xx devices vector table for EWARM toolchain.
-;*                      Same as startup_stm32f42_43xxx.s and maintained for legacy purpose
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock and the external SRAM/SDRAM mounted 
-;*                        on STM324x7I-EVAL boards to be used as data memory  
-;*                        (optional, to be enabled by user)
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M4 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-;* You may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at:
-;* 
-;*        http://www.st.com/software_license_agreement_liberty_v2
-;* 
-;* Unless required by applicable law or agreed to in writing, software 
-;* distributed under the License is distributed on an "AS IS" BASIS, 
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;* 
-;*******************************************************************************/
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
-        DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
-        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
-        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
-        DCD     FLASH_IRQHandler                  ; FLASH                                           
-        DCD     RCC_IRQHandler                    ; RCC                                             
-        DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
-        DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
-        DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
-        DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
-        DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
-        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
-        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
-        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
-        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
-        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
-        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
-        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
-        DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
-        DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
-        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
-        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
-        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
-        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
-        DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
-        DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
-        DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
-        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
-        DCD     TIM2_IRQHandler                   ; TIM2                                            
-        DCD     TIM3_IRQHandler                   ; TIM3                                            
-        DCD     TIM4_IRQHandler                   ; TIM4                                            
-        DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
-        DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
-        DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
-        DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
-        DCD     SPI1_IRQHandler                   ; SPI1                                            
-        DCD     SPI2_IRQHandler                   ; SPI2                                            
-        DCD     USART1_IRQHandler                 ; USART1                                          
-        DCD     USART2_IRQHandler                 ; USART2                                          
-        DCD     USART3_IRQHandler                 ; USART3                                          
-        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
-        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
-        DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
-        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
-        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
-        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
-        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
-        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
-        DCD     FMC_IRQHandler                    ; FMC                                            
-        DCD     SDIO_IRQHandler                   ; SDIO                                            
-        DCD     TIM5_IRQHandler                   ; TIM5                                            
-        DCD     SPI3_IRQHandler                   ; SPI3                                            
-        DCD     UART4_IRQHandler                  ; UART4                                           
-        DCD     UART5_IRQHandler                  ; UART5                                           
-        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
-        DCD     TIM7_IRQHandler                   ; TIM7                   
-        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
-        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
-        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
-        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
-        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
-        DCD     ETH_IRQHandler                    ; Ethernet                                        
-        DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
-        DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
-        DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
-        DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
-        DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
-        DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
-        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
-        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
-        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
-        DCD     USART6_IRQHandler                 ; USART6                                           
-        DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
-        DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
-        DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
-        DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
-        DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
-        DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
-        DCD     DCMI_IRQHandler                   ; DCMI                                            
-        DCD     CRYP_IRQHandler                   ; CRYP crypto                                     
-        DCD     HASH_RNG_IRQHandler               ; Hash and Rng
-        DCD     FPU_IRQHandler                    ; FPU
-        DCD     UART7_IRQHandler                  ; UART7
-        DCD     UART8_IRQHandler                  ; UART8
-        DCD     SPI4_IRQHandler                   ; SPI4
-        DCD     SPI5_IRQHandler                   ; SPI5
-        DCD     SPI6_IRQHandler                   ; SPI6
-        DCD     SAI1_IRQHandler                   ; SAI1
-        DCD     0                                 ; Reserved 
-        DCD     0                                 ; Reserved 
-        DCD     DMA2D_IRQHandler                  ; DMA2D
-    
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler  
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler  
-        B PVD_IRQHandler
-
-        PUBWEAK TAMP_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TAMP_STAMP_IRQHandler  
-        B TAMP_STAMP_IRQHandler
-
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-RTC_WKUP_IRQHandler  
-        B RTC_WKUP_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler  
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler  
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler  
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler  
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler  
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-EXTI4_IRQHandler  
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream0_IRQHandler  
-        B DMA1_Stream0_IRQHandler
-
-        PUBWEAK DMA1_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream1_IRQHandler  
-        B DMA1_Stream1_IRQHandler
-
-        PUBWEAK DMA1_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream2_IRQHandler  
-        B DMA1_Stream2_IRQHandler
-
-        PUBWEAK DMA1_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream3_IRQHandler  
-        B DMA1_Stream3_IRQHandler
-
-        PUBWEAK DMA1_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream4_IRQHandler  
-        B DMA1_Stream4_IRQHandler
-
-        PUBWEAK DMA1_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream5_IRQHandler  
-        B DMA1_Stream5_IRQHandler
-
-        PUBWEAK DMA1_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream6_IRQHandler  
-        B DMA1_Stream6_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC_IRQHandler  
-        B ADC_IRQHandler
-
-        PUBWEAK CAN1_TX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-CAN1_TX_IRQHandler  
-        B CAN1_TX_IRQHandler
-
-        PUBWEAK CAN1_RX0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN1_RX0_IRQHandler  
-        B CAN1_RX0_IRQHandler
-
-        PUBWEAK CAN1_RX1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN1_RX1_IRQHandler  
-        B CAN1_RX1_IRQHandler
-
-        PUBWEAK CAN1_SCE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN1_SCE_IRQHandler  
-        B CAN1_SCE_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-EXTI9_5_IRQHandler  
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_BRK_TIM9_IRQHandler  
-        B TIM1_BRK_TIM9_IRQHandler
-
-        PUBWEAK TIM1_UP_TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_UP_TIM10_IRQHandler  
-        B TIM1_UP_TIM10_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_TRG_COM_TIM11_IRQHandler  
-        B TIM1_TRG_COM_TIM11_IRQHandler
-        
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_CC_IRQHandler  
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler  
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler  
-        B TIM3_IRQHandler
-
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler  
-        B TIM4_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C1_EV_IRQHandler  
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C1_ER_IRQHandler  
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C2_EV_IRQHandler  
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C2_ER_IRQHandler  
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler  
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler  
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler  
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler  
-        B USART2_IRQHandler
-
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler  
-        B USART3_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-EXTI15_10_IRQHandler  
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-RTC_Alarm_IRQHandler  
-        B RTC_Alarm_IRQHandler
-
-        PUBWEAK OTG_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_FS_WKUP_IRQHandler  
-        B OTG_FS_WKUP_IRQHandler
-      
-        PUBWEAK TIM8_BRK_TIM12_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM8_BRK_TIM12_IRQHandler  
-        B TIM8_BRK_TIM12_IRQHandler
-
-        PUBWEAK TIM8_UP_TIM13_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM8_UP_TIM13_IRQHandler  
-        B TIM8_UP_TIM13_IRQHandler
-
-        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM8_TRG_COM_TIM14_IRQHandler  
-        B TIM8_TRG_COM_TIM14_IRQHandler
-
-        PUBWEAK TIM8_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-TIM8_CC_IRQHandler  
-        B TIM8_CC_IRQHandler
-
-        PUBWEAK DMA1_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream7_IRQHandler  
-        B DMA1_Stream7_IRQHandler
-
-        PUBWEAK FMC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FMC_IRQHandler  
-        B FMC_IRQHandler
-
-        PUBWEAK SDIO_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO_IRQHandler  
-        B SDIO_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler  
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler  
-        B SPI3_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler  
-        B UART4_IRQHandler
-
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler  
-        B UART5_IRQHandler
-
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-TIM6_DAC_IRQHandler  
-        B TIM6_DAC_IRQHandler
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-TIM7_IRQHandler  
-        B TIM7_IRQHandler
-
-        PUBWEAK DMA2_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream0_IRQHandler  
-        B DMA2_Stream0_IRQHandler
-
-        PUBWEAK DMA2_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream1_IRQHandler  
-        B DMA2_Stream1_IRQHandler
-
-        PUBWEAK DMA2_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream2_IRQHandler  
-        B DMA2_Stream2_IRQHandler
-
-        PUBWEAK DMA2_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream3_IRQHandler  
-        B DMA2_Stream3_IRQHandler
-
-        PUBWEAK DMA2_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream4_IRQHandler  
-        B DMA2_Stream4_IRQHandler
-
-        PUBWEAK ETH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ETH_IRQHandler  
-        B ETH_IRQHandler
-
-        PUBWEAK ETH_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-ETH_WKUP_IRQHandler  
-        B ETH_WKUP_IRQHandler
-
-        PUBWEAK CAN2_TX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-CAN2_TX_IRQHandler  
-        B CAN2_TX_IRQHandler
-
-        PUBWEAK CAN2_RX0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN2_RX0_IRQHandler  
-        B CAN2_RX0_IRQHandler
-
-        PUBWEAK CAN2_RX1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN2_RX1_IRQHandler  
-        B CAN2_RX1_IRQHandler
-
-        PUBWEAK CAN2_SCE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN2_SCE_IRQHandler  
-        B CAN2_SCE_IRQHandler
-
-        PUBWEAK OTG_FS_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_IRQHandler  
-        B OTG_FS_IRQHandler
-
-        PUBWEAK DMA2_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream5_IRQHandler  
-        B DMA2_Stream5_IRQHandler
-
-        PUBWEAK DMA2_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream6_IRQHandler  
-        B DMA2_Stream6_IRQHandler
-
-        PUBWEAK DMA2_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream7_IRQHandler  
-        B DMA2_Stream7_IRQHandler
-
-        PUBWEAK USART6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler  
-        B USART6_IRQHandler
-
-        PUBWEAK I2C3_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C3_EV_IRQHandler  
-        B I2C3_EV_IRQHandler
-
-        PUBWEAK I2C3_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C3_ER_IRQHandler  
-        B I2C3_ER_IRQHandler
-
-        PUBWEAK OTG_HS_EP1_OUT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_HS_EP1_OUT_IRQHandler  
-        B OTG_HS_EP1_OUT_IRQHandler
-
-        PUBWEAK OTG_HS_EP1_IN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_HS_EP1_IN_IRQHandler  
-        B OTG_HS_EP1_IN_IRQHandler
-
-        PUBWEAK OTG_HS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_HS_WKUP_IRQHandler  
-        B OTG_HS_WKUP_IRQHandler
-
-        PUBWEAK OTG_HS_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_IRQHandler  
-        B OTG_HS_IRQHandler
-
-        PUBWEAK DCMI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DCMI_IRQHandler  
-        B DCMI_IRQHandler
-
-        PUBWEAK CRYP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CRYP_IRQHandler  
-        B CRYP_IRQHandler
-
-        PUBWEAK HASH_RNG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-HASH_RNG_IRQHandler  
-        B HASH_RNG_IRQHandler
-
-        PUBWEAK FPU_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-FPU_IRQHandler  
-        B FPU_IRQHandler
-
-        PUBWEAK UART7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)      
-UART7_IRQHandler 
-        B UART7_IRQHandler  
-
-        PUBWEAK UART8_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-UART8_IRQHandler             
-        B UART8_IRQHandler
-        
-        PUBWEAK SPI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-SPI4_IRQHandler
-        B SPI4_IRQHandler                 
-
-        PUBWEAK SPI5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-SPI5_IRQHandler   
-        B SPI5_IRQHandler                  
-
-        PUBWEAK SPI6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-SPI6_IRQHandler 
-        B SPI6_IRQHandler                    
-
-        PUBWEAK SAI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-SAI1_IRQHandler  
-        B SAI1_IRQHandler                  
-
-        PUBWEAK LTDC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-LTDC_IRQHandler 
-        B LTDC_IRQHandler                     
-
-        PUBWEAK LTDC_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-LTDC_ER_IRQHandler 
-        B LTDC_ER_IRQHandler                 
-
-        PUBWEAK DMA2D_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-DMA2D_IRQHandler 
-        B DMA2D_IRQHandler                  
-
-
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f429_439xx.s

@@ -1,691 +0,0 @@
-/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name          : startup_stm32f429_439xx.s
-;* Author             : MCD Application Team
-;* @version           : V1.8.0
-;* @date              : 09-November-2016
-;* Description        : STM32F429xx/439xx devices vector table for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock and the external SRAM/SDRAM mounted 
-;*                        on STM324x9I-EVAL board to be used as data memory (optional, 
-;*                        to be enabled by user)
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M4 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-;* You may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at:
-;* 
-;*        http://www.st.com/software_license_agreement_liberty_v2
-;* 
-;* Unless required by applicable law or agreed to in writing, software 
-;* distributed under the License is distributed on an "AS IS" BASIS, 
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;* 
-;*******************************************************************************/
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
-        DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
-        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
-        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
-        DCD     FLASH_IRQHandler                  ; FLASH                                           
-        DCD     RCC_IRQHandler                    ; RCC                                             
-        DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
-        DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
-        DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
-        DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
-        DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
-        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
-        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
-        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
-        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
-        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
-        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
-        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
-        DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
-        DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
-        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
-        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
-        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
-        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
-        DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
-        DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
-        DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
-        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
-        DCD     TIM2_IRQHandler                   ; TIM2                                            
-        DCD     TIM3_IRQHandler                   ; TIM3                                            
-        DCD     TIM4_IRQHandler                   ; TIM4                                            
-        DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
-        DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
-        DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
-        DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
-        DCD     SPI1_IRQHandler                   ; SPI1                                            
-        DCD     SPI2_IRQHandler                   ; SPI2                                            
-        DCD     USART1_IRQHandler                 ; USART1                                          
-        DCD     USART2_IRQHandler                 ; USART2                                          
-        DCD     USART3_IRQHandler                 ; USART3                                          
-        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
-        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
-        DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
-        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
-        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
-        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
-        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
-        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
-        DCD     FMC_IRQHandler                    ; FMC                                            
-        DCD     SDIO_IRQHandler                   ; SDIO                                            
-        DCD     TIM5_IRQHandler                   ; TIM5                                            
-        DCD     SPI3_IRQHandler                   ; SPI3                                            
-        DCD     UART4_IRQHandler                  ; UART4                                           
-        DCD     UART5_IRQHandler                  ; UART5                                           
-        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
-        DCD     TIM7_IRQHandler                   ; TIM7                   
-        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
-        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
-        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
-        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
-        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
-        DCD     ETH_IRQHandler                    ; Ethernet                                        
-        DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
-        DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
-        DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
-        DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
-        DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
-        DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
-        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
-        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
-        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
-        DCD     USART6_IRQHandler                 ; USART6                                           
-        DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
-        DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
-        DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
-        DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
-        DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
-        DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
-        DCD     DCMI_IRQHandler                   ; DCMI                                            
-        DCD     CRYP_IRQHandler                   ; CRYP crypto                                     
-        DCD     HASH_RNG_IRQHandler               ; Hash and Rng
-        DCD     FPU_IRQHandler                    ; FPU
-        DCD     UART7_IRQHandler                  ; UART7
-        DCD     UART8_IRQHandler                  ; UART8
-        DCD     SPI4_IRQHandler                   ; SPI4
-        DCD     SPI5_IRQHandler                   ; SPI5
-        DCD     SPI6_IRQHandler                   ; SPI6
-        DCD     SAI1_IRQHandler                   ; SAI1
-        DCD     LTDC_IRQHandler                   ; LTDC
-        DCD     LTDC_ER_IRQHandler                ; LTDC error
-        DCD     DMA2D_IRQHandler                  ; DMA2D
-    
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler  
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler  
-        B PVD_IRQHandler
-
-        PUBWEAK TAMP_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TAMP_STAMP_IRQHandler  
-        B TAMP_STAMP_IRQHandler
-
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-RTC_WKUP_IRQHandler  
-        B RTC_WKUP_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler  
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler  
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler  
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler  
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler  
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-EXTI4_IRQHandler  
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream0_IRQHandler  
-        B DMA1_Stream0_IRQHandler
-
-        PUBWEAK DMA1_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream1_IRQHandler  
-        B DMA1_Stream1_IRQHandler
-
-        PUBWEAK DMA1_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream2_IRQHandler  
-        B DMA1_Stream2_IRQHandler
-
-        PUBWEAK DMA1_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream3_IRQHandler  
-        B DMA1_Stream3_IRQHandler
-
-        PUBWEAK DMA1_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream4_IRQHandler  
-        B DMA1_Stream4_IRQHandler
-
-        PUBWEAK DMA1_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream5_IRQHandler  
-        B DMA1_Stream5_IRQHandler
-
-        PUBWEAK DMA1_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream6_IRQHandler  
-        B DMA1_Stream6_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC_IRQHandler  
-        B ADC_IRQHandler
-
-        PUBWEAK CAN1_TX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-CAN1_TX_IRQHandler  
-        B CAN1_TX_IRQHandler
-
-        PUBWEAK CAN1_RX0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN1_RX0_IRQHandler  
-        B CAN1_RX0_IRQHandler
-
-        PUBWEAK CAN1_RX1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN1_RX1_IRQHandler  
-        B CAN1_RX1_IRQHandler
-
-        PUBWEAK CAN1_SCE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN1_SCE_IRQHandler  
-        B CAN1_SCE_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-EXTI9_5_IRQHandler  
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_BRK_TIM9_IRQHandler  
-        B TIM1_BRK_TIM9_IRQHandler
-
-        PUBWEAK TIM1_UP_TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_UP_TIM10_IRQHandler  
-        B TIM1_UP_TIM10_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_TRG_COM_TIM11_IRQHandler  
-        B TIM1_TRG_COM_TIM11_IRQHandler
-        
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM1_CC_IRQHandler  
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler  
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler  
-        B TIM3_IRQHandler
-
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler  
-        B TIM4_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C1_EV_IRQHandler  
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C1_ER_IRQHandler  
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C2_EV_IRQHandler  
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C2_ER_IRQHandler  
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler  
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler  
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler  
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler  
-        B USART2_IRQHandler
-
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler  
-        B USART3_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-EXTI15_10_IRQHandler  
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-RTC_Alarm_IRQHandler  
-        B RTC_Alarm_IRQHandler
-
-        PUBWEAK OTG_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_FS_WKUP_IRQHandler  
-        B OTG_FS_WKUP_IRQHandler
-      
-        PUBWEAK TIM8_BRK_TIM12_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM8_BRK_TIM12_IRQHandler  
-        B TIM8_BRK_TIM12_IRQHandler
-
-        PUBWEAK TIM8_UP_TIM13_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM8_UP_TIM13_IRQHandler  
-        B TIM8_UP_TIM13_IRQHandler
-
-        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-TIM8_TRG_COM_TIM14_IRQHandler  
-        B TIM8_TRG_COM_TIM14_IRQHandler
-
-        PUBWEAK TIM8_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-TIM8_CC_IRQHandler  
-        B TIM8_CC_IRQHandler
-
-        PUBWEAK DMA1_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA1_Stream7_IRQHandler  
-        B DMA1_Stream7_IRQHandler
-
-        PUBWEAK FMC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FMC_IRQHandler  
-        B FMC_IRQHandler
-
-        PUBWEAK SDIO_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO_IRQHandler  
-        B SDIO_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler  
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler  
-        B SPI3_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler  
-        B UART4_IRQHandler
-
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler  
-        B UART5_IRQHandler
-
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-TIM6_DAC_IRQHandler  
-        B TIM6_DAC_IRQHandler
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)   
-TIM7_IRQHandler  
-        B TIM7_IRQHandler
-
-        PUBWEAK DMA2_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream0_IRQHandler  
-        B DMA2_Stream0_IRQHandler
-
-        PUBWEAK DMA2_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream1_IRQHandler  
-        B DMA2_Stream1_IRQHandler
-
-        PUBWEAK DMA2_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream2_IRQHandler  
-        B DMA2_Stream2_IRQHandler
-
-        PUBWEAK DMA2_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream3_IRQHandler  
-        B DMA2_Stream3_IRQHandler
-
-        PUBWEAK DMA2_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream4_IRQHandler  
-        B DMA2_Stream4_IRQHandler
-
-        PUBWEAK ETH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ETH_IRQHandler  
-        B ETH_IRQHandler
-
-        PUBWEAK ETH_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-ETH_WKUP_IRQHandler  
-        B ETH_WKUP_IRQHandler
-
-        PUBWEAK CAN2_TX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-CAN2_TX_IRQHandler  
-        B CAN2_TX_IRQHandler
-
-        PUBWEAK CAN2_RX0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN2_RX0_IRQHandler  
-        B CAN2_RX0_IRQHandler
-
-        PUBWEAK CAN2_RX1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN2_RX1_IRQHandler  
-        B CAN2_RX1_IRQHandler
-
-        PUBWEAK CAN2_SCE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-CAN2_SCE_IRQHandler  
-        B CAN2_SCE_IRQHandler
-
-        PUBWEAK OTG_FS_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_IRQHandler  
-        B OTG_FS_IRQHandler
-
-        PUBWEAK DMA2_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream5_IRQHandler  
-        B DMA2_Stream5_IRQHandler
-
-        PUBWEAK DMA2_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream6_IRQHandler  
-        B DMA2_Stream6_IRQHandler
-
-        PUBWEAK DMA2_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-DMA2_Stream7_IRQHandler  
-        B DMA2_Stream7_IRQHandler
-
-        PUBWEAK USART6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler  
-        B USART6_IRQHandler
-
-        PUBWEAK I2C3_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C3_EV_IRQHandler  
-        B I2C3_EV_IRQHandler
-
-        PUBWEAK I2C3_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C3_ER_IRQHandler  
-        B I2C3_ER_IRQHandler
-
-        PUBWEAK OTG_HS_EP1_OUT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_HS_EP1_OUT_IRQHandler  
-        B OTG_HS_EP1_OUT_IRQHandler
-
-        PUBWEAK OTG_HS_EP1_IN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_HS_EP1_IN_IRQHandler  
-        B OTG_HS_EP1_IN_IRQHandler
-
-        PUBWEAK OTG_HS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)    
-OTG_HS_WKUP_IRQHandler  
-        B OTG_HS_WKUP_IRQHandler
-
-        PUBWEAK OTG_HS_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_IRQHandler  
-        B OTG_HS_IRQHandler
-
-        PUBWEAK DCMI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DCMI_IRQHandler  
-        B DCMI_IRQHandler
-
-        PUBWEAK CRYP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CRYP_IRQHandler  
-        B CRYP_IRQHandler
-
-        PUBWEAK HASH_RNG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-HASH_RNG_IRQHandler  
-        B HASH_RNG_IRQHandler
-
-        PUBWEAK FPU_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)  
-FPU_IRQHandler  
-        B FPU_IRQHandler
-
-        PUBWEAK UART7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)      
-UART7_IRQHandler 
-        B UART7_IRQHandler  
-
-        PUBWEAK UART8_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-UART8_IRQHandler             
-        B UART8_IRQHandler
-        
-        PUBWEAK SPI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-SPI4_IRQHandler
-        B SPI4_IRQHandler                 
-
-        PUBWEAK SPI5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-SPI5_IRQHandler   
-        B SPI5_IRQHandler                  
-
-        PUBWEAK SPI6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-SPI6_IRQHandler 
-        B SPI6_IRQHandler                    
-
-        PUBWEAK SAI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-SAI1_IRQHandler  
-        B SAI1_IRQHandler                  
-
-        PUBWEAK LTDC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-LTDC_IRQHandler 
-        B LTDC_IRQHandler                     
-
-        PUBWEAK LTDC_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-LTDC_ER_IRQHandler 
-        B LTDC_ER_IRQHandler                 
-
-        PUBWEAK DMA2D_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-DMA2D_IRQHandler 
-        B DMA2D_IRQHandler                  
-
-
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f446xx.s

@@ -1,678 +0,0 @@
-;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name          : startup_stm32f446xx.s
-;* Author             : MCD Application Team
-;* @version           : V1.8.0
-;* @date              : 09-November-2016
-;* Description        : STM32F446xx devices vector table for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M4 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;* 
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler                   ; Window WatchDog
-        DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection
-        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
-        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
-        DCD     FLASH_IRQHandler                  ; FLASH
-        DCD     RCC_IRQHandler                    ; RCC
-        DCD     EXTI0_IRQHandler                  ; EXTI Line0
-        DCD     EXTI1_IRQHandler                  ; EXTI Line1
-        DCD     EXTI2_IRQHandler                  ; EXTI Line2
-        DCD     EXTI3_IRQHandler                  ; EXTI Line3
-        DCD     EXTI4_IRQHandler                  ; EXTI Line4
-        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
-        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
-        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
-        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
-        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
-        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
-        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
-        DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s
-        DCD     CAN1_TX_IRQHandler                ; CAN1 TX
-        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
-        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
-        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
-        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
-        DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9
-        DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10
-        DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
-        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
-        DCD     TIM2_IRQHandler                   ; TIM2
-        DCD     TIM3_IRQHandler                   ; TIM3
-        DCD     TIM4_IRQHandler                   ; TIM4
-        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
-        DCD     SPI1_IRQHandler                   ; SPI1
-        DCD     SPI2_IRQHandler                   ; SPI2
-        DCD     USART1_IRQHandler                 ; USART1
-        DCD     USART2_IRQHandler                 ; USART2
-        DCD     USART3_IRQHandler                 ; USART3
-        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s
-        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
-        DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line
-        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12
-        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13
-        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
-        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare
-        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
-        DCD     FMC_IRQHandler                    ; FMC
-        DCD     SDIO_IRQHandler                   ; SDIO
-        DCD     TIM5_IRQHandler                   ; TIM5
-        DCD     SPI3_IRQHandler                   ; SPI3
-        DCD     UART4_IRQHandler                  ; UART4
-        DCD     UART5_IRQHandler                  ; UART5
-        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
-        DCD     TIM7_IRQHandler                   ; TIM7
-        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
-        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
-        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
-        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
-        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     CAN2_TX_IRQHandler                ; CAN2 TX
-        DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0
-        DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1
-        DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE
-        DCD     OTG_FS_IRQHandler                 ; USB OTG FS
-        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
-        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
-        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
-        DCD     USART6_IRQHandler                 ; USART6
-        DCD     I2C3_EV_IRQHandler                ; I2C3 event
-        DCD     I2C3_ER_IRQHandler                ; I2C3 error
-        DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out
-        DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In
-        DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI
-        DCD     OTG_HS_IRQHandler                 ; USB OTG HS
-        DCD     DCMI_IRQHandler                   ; DCMI
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     FPU_IRQHandler                    ; FPU
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     SPI4_IRQHandler                   ; SPI4
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     SAI1_IRQHandler                   ; SAI1
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     SAI2_IRQHandler                   ; SAI2
-        DCD     QUADSPI_IRQHandler                ; QUADSPI
-        DCD     CEC_IRQHandler                    ; CEC
-        DCD     SPDIF_RX_IRQHandler               ; SPDIF RX
-        DCD     FMPI2C1_Event_IRQHandler          ; I2C 4 Event
-        DCD     FMPI2C1_Error_IRQHandler          ; I2C 4 Error
-  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler  
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler  
-        B PVD_IRQHandler
-
-        PUBWEAK TAMP_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMP_STAMP_IRQHandler  
-        B TAMP_STAMP_IRQHandler
-
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler  
-        B RTC_WKUP_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler  
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler  
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler  
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler  
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler  
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler  
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream0_IRQHandler  
-        B DMA1_Stream0_IRQHandler
-
-        PUBWEAK DMA1_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream1_IRQHandler  
-        B DMA1_Stream1_IRQHandler
-
-        PUBWEAK DMA1_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream2_IRQHandler  
-        B DMA1_Stream2_IRQHandler
-
-        PUBWEAK DMA1_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream3_IRQHandler  
-        B DMA1_Stream3_IRQHandler
-
-        PUBWEAK DMA1_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream4_IRQHandler  
-        B DMA1_Stream4_IRQHandler
-
-        PUBWEAK DMA1_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream5_IRQHandler  
-        B DMA1_Stream5_IRQHandler
-
-        PUBWEAK DMA1_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream6_IRQHandler  
-        B DMA1_Stream6_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC_IRQHandler  
-        B ADC_IRQHandler
-
-        PUBWEAK CAN1_TX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-CAN1_TX_IRQHandler  
-        B CAN1_TX_IRQHandler
-
-        PUBWEAK CAN1_RX0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX0_IRQHandler  
-        B CAN1_RX0_IRQHandler
-
-        PUBWEAK CAN1_RX1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler  
-        B CAN1_RX1_IRQHandler
-
-        PUBWEAK CAN1_SCE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SCE_IRQHandler  
-        B CAN1_SCE_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler  
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_BRK_TIM9_IRQHandler  
-        B TIM1_BRK_TIM9_IRQHandler
-
-        PUBWEAK TIM1_UP_TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_UP_TIM10_IRQHandler  
-        B TIM1_UP_TIM10_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_TRG_COM_TIM11_IRQHandler  
-        B TIM1_TRG_COM_TIM11_IRQHandler
-        
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_CC_IRQHandler  
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler  
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler  
-        B TIM3_IRQHandler
-
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler  
-        B TIM4_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler  
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler  
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler  
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler  
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler  
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler  
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler  
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler  
-        B USART2_IRQHandler
-
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler  
-        B USART3_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler  
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler  
-        B RTC_Alarm_IRQHandler
-
-        PUBWEAK OTG_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_WKUP_IRQHandler  
-        B OTG_FS_WKUP_IRQHandler
-      
-        PUBWEAK TIM8_BRK_TIM12_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_BRK_TIM12_IRQHandler  
-        B TIM8_BRK_TIM12_IRQHandler
-
-        PUBWEAK TIM8_UP_TIM13_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_UP_TIM13_IRQHandler  
-        B TIM8_UP_TIM13_IRQHandler
-
-        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_TRG_COM_TIM14_IRQHandler  
-        B TIM8_TRG_COM_TIM14_IRQHandler
-
-        PUBWEAK TIM8_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_CC_IRQHandler  
-        B TIM8_CC_IRQHandler
-
-        PUBWEAK DMA1_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream7_IRQHandler  
-        B DMA1_Stream7_IRQHandler
-
-        PUBWEAK FMC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FMC_IRQHandler  
-        B FMC_IRQHandler
-
-        PUBWEAK SDIO_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO_IRQHandler  
-        B SDIO_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler  
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler  
-        B SPI3_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler  
-        B UART4_IRQHandler
-
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler  
-        B UART5_IRQHandler
-
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_DAC_IRQHandler  
-        B TIM6_DAC_IRQHandler
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler  
-        B TIM7_IRQHandler
-
-        PUBWEAK DMA2_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream0_IRQHandler  
-        B DMA2_Stream0_IRQHandler
-
-        PUBWEAK DMA2_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream1_IRQHandler  
-        B DMA2_Stream1_IRQHandler
-
-        PUBWEAK DMA2_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream2_IRQHandler
-        B DMA2_Stream2_IRQHandler
-
-        PUBWEAK DMA2_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream3_IRQHandler
-        B DMA2_Stream3_IRQHandler
-
-        PUBWEAK DMA2_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream4_IRQHandler  
-        B DMA2_Stream4_IRQHandler
-
-        PUBWEAK CAN2_TX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler  
-        B CAN2_TX_IRQHandler
-
-        PUBWEAK CAN2_RX0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler  
-        B CAN2_RX0_IRQHandler
-
-        PUBWEAK CAN2_RX1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler  
-        B CAN2_RX1_IRQHandler
-
-        PUBWEAK CAN2_SCE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SCE_IRQHandler  
-        B CAN2_SCE_IRQHandler
-
-        PUBWEAK OTG_FS_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_IRQHandler  
-        B OTG_FS_IRQHandler
-
-        PUBWEAK DMA2_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream5_IRQHandler  
-        B DMA2_Stream5_IRQHandler
-
-        PUBWEAK DMA2_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream6_IRQHandler  
-        B DMA2_Stream6_IRQHandler
-
-        PUBWEAK DMA2_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream7_IRQHandler  
-        B DMA2_Stream7_IRQHandler
-
-        PUBWEAK USART6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler  
-        B USART6_IRQHandler
-
-        PUBWEAK I2C3_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler  
-        B I2C3_EV_IRQHandler
-
-        PUBWEAK I2C3_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1) 
-I2C3_ER_IRQHandler  
-        B I2C3_ER_IRQHandler
-
-        PUBWEAK OTG_HS_EP1_OUT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_EP1_OUT_IRQHandler  
-        B OTG_HS_EP1_OUT_IRQHandler
-
-        PUBWEAK OTG_HS_EP1_IN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_EP1_IN_IRQHandler  
-        B OTG_HS_EP1_IN_IRQHandler
-
-        PUBWEAK OTG_HS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_WKUP_IRQHandler  
-        B OTG_HS_WKUP_IRQHandler
-
-        PUBWEAK OTG_HS_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_IRQHandler  
-        B OTG_HS_IRQHandler
-
-        PUBWEAK DCMI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DCMI_IRQHandler  
-        B DCMI_IRQHandler
-
-        PUBWEAK FPU_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FPU_IRQHandler  
-        B FPU_IRQHandler 
-        
-        PUBWEAK SPI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI4_IRQHandler
-        B SPI4_IRQHandler   
-
-        PUBWEAK SAI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SAI1_IRQHandler  
-        B SAI1_IRQHandler
-
-        PUBWEAK SAI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SAI2_IRQHandler 
-        B SAI2_IRQHandler
-
-        PUBWEAK QUADSPI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-QUADSPI_IRQHandler 
-        B QUADSPI_IRQHandler
-
-        PUBWEAK CEC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CEC_IRQHandler 
-        B CEC_IRQHandler
-
-        PUBWEAK SPDIF_RX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPDIF_RX_IRQHandler 
-        B SPDIF_RX_IRQHandler
-
-        PUBWEAK FMPI2C1_Event_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FMPI2C1_Event_IRQHandler 
-        B FMPI2C1_Event_IRQHandler
-
-        PUBWEAK FMPI2C1_Error_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FMPI2C1_Error_IRQHandler 
-        B FMPI2C1_Error_IRQHandler
-
-
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/CMSIS/Device/ST/STM32F4xx/Source/Templates/iar/startup_stm32f469_479xx.s

@@ -1,699 +0,0 @@
-;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
-;* File Name          : startup_stm32f469_479xx.s
-;* Author             : MCD Application Team
-;* @version           : V1.8.0
-;* @date              : 09-November-2016
-;* Description        : STM32F469xx/479xx devices vector table for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M4 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-;* You may not use this file except in compliance with the License.
-;* You may obtain a copy of the License at:
-;* 
-;*        http://www.st.com/software_license_agreement_liberty_v2
-;* 
-;* Unless required by applicable law or agreed to in writing, software 
-;* distributed under the License is distributed on an "AS IS" BASIS, 
-;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-;* See the License for the specific language governing permissions and
-;* limitations under the License.
-;* 
-;*******************************************************************************/
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler                   ; Window WatchDog
-        DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection
-        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line
-        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
-        DCD     FLASH_IRQHandler                  ; FLASH
-        DCD     RCC_IRQHandler                    ; RCC
-        DCD     EXTI0_IRQHandler                  ; EXTI Line0
-        DCD     EXTI1_IRQHandler                  ; EXTI Line1
-        DCD     EXTI2_IRQHandler                  ; EXTI Line2
-        DCD     EXTI3_IRQHandler                  ; EXTI Line3
-        DCD     EXTI4_IRQHandler                  ; EXTI Line4
-        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
-        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
-        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
-        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
-        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
-        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
-        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
-        DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s
-        DCD     CAN1_TX_IRQHandler                ; CAN1 TX
-        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0
-        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1
-        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE
-        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
-        DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9
-        DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10
-        DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
-        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
-        DCD     TIM2_IRQHandler                   ; TIM2
-        DCD     TIM3_IRQHandler                   ; TIM3
-        DCD     TIM4_IRQHandler                   ; TIM4
-        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
-        DCD     SPI1_IRQHandler                   ; SPI1
-        DCD     SPI2_IRQHandler                   ; SPI2
-        DCD     USART1_IRQHandler                 ; USART1
-        DCD     USART2_IRQHandler                 ; USART2
-        DCD     USART3_IRQHandler                 ; USART3
-        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s
-        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
-        DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line
-        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12
-        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13
-        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
-        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare
-        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
-        DCD     FMC_IRQHandler                    ; FMC
-        DCD     SDIO_IRQHandler                   ; SDIO
-        DCD     TIM5_IRQHandler                   ; TIM5
-        DCD     SPI3_IRQHandler                   ; SPI3
-        DCD     UART4_IRQHandler                  ; UART4
-        DCD     UART5_IRQHandler                  ; UART5
-        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
-        DCD     TIM7_IRQHandler                   ; TIM7
-        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
-        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
-        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
-        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
-        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
-        DCD     ETH_IRQHandler                    ; Ethernet
-        DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line
-        DCD     CAN2_TX_IRQHandler                ; CAN2 TX
-        DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0
-        DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1
-        DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE
-        DCD     OTG_FS_IRQHandler                 ; USB OTG FS
-        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
-        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
-        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
-        DCD     USART6_IRQHandler                 ; USART6
-        DCD     I2C3_EV_IRQHandler                ; I2C3 event
-        DCD     I2C3_ER_IRQHandler                ; I2C3 error
-        DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out
-        DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In 
-        DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI
-        DCD     OTG_HS_IRQHandler                 ; USB OTG HS
-        DCD     DCMI_IRQHandler                   ; DCMI
-        DCD     CRYP_IRQHandler                   ; CRYP crypto
-        DCD     HASH_RNG_IRQHandler               ; Hash and Rng
-        DCD     FPU_IRQHandler                    ; FPU
-        DCD     UART7_IRQHandler                  ; UART7
-        DCD     UART8_IRQHandler                  ; UART8
-        DCD     SPI4_IRQHandler                   ; SPI4
-        DCD     SPI5_IRQHandler                   ; SPI5
-        DCD     SPI6_IRQHandler                   ; SPI6
-        DCD     SAI1_IRQHandler                   ; SAI1
-        DCD     LTDC_IRQHandler                   ; LTDC
-        DCD     LTDC_ER_IRQHandler                ; LTDC error
-        DCD     DMA2D_IRQHandler                  ; DMA2D
-        DCD     QUADSPI_IRQHandler                ; QUADSPI
-        DCD     DSI_IRQHandler                    ; DSI Controller
-    
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler  
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler  
-        B PVD_IRQHandler
-
-        PUBWEAK TAMP_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMP_STAMP_IRQHandler  
-        B TAMP_STAMP_IRQHandler
-
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler  
-        B RTC_WKUP_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler  
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler  
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler  
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler  
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler  
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler  
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream0_IRQHandler  
-        B DMA1_Stream0_IRQHandler
-
-        PUBWEAK DMA1_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream1_IRQHandler  
-        B DMA1_Stream1_IRQHandler
-
-        PUBWEAK DMA1_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream2_IRQHandler  
-        B DMA1_Stream2_IRQHandler
-
-        PUBWEAK DMA1_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream3_IRQHandler  
-        B DMA1_Stream3_IRQHandler
-
-        PUBWEAK DMA1_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream4_IRQHandler  
-        B DMA1_Stream4_IRQHandler
-
-        PUBWEAK DMA1_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream5_IRQHandler  
-        B DMA1_Stream5_IRQHandler
-
-        PUBWEAK DMA1_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream6_IRQHandler  
-        B DMA1_Stream6_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC_IRQHandler  
-        B ADC_IRQHandler
-
-        PUBWEAK CAN1_TX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_TX_IRQHandler  
-        B CAN1_TX_IRQHandler
-
-        PUBWEAK CAN1_RX0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX0_IRQHandler  
-        B CAN1_RX0_IRQHandler
-
-        PUBWEAK CAN1_RX1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_RX1_IRQHandler  
-        B CAN1_RX1_IRQHandler
-
-        PUBWEAK CAN1_SCE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN1_SCE_IRQHandler  
-        B CAN1_SCE_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler  
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_BRK_TIM9_IRQHandler  
-        B TIM1_BRK_TIM9_IRQHandler
-
-        PUBWEAK TIM1_UP_TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_UP_TIM10_IRQHandler  
-        B TIM1_UP_TIM10_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_TRG_COM_TIM11_IRQHandler  
-        B TIM1_TRG_COM_TIM11_IRQHandler
-        
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM1_CC_IRQHandler  
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler  
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler  
-        B TIM3_IRQHandler
-
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler  
-        B TIM4_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler  
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler  
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler  
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler  
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler  
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler  
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler  
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler  
-        B USART2_IRQHandler
-
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler  
-        B USART3_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler  
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler  
-        B RTC_Alarm_IRQHandler
-
-        PUBWEAK OTG_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_WKUP_IRQHandler  
-        B OTG_FS_WKUP_IRQHandler
-      
-        PUBWEAK TIM8_BRK_TIM12_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_BRK_TIM12_IRQHandler  
-        B TIM8_BRK_TIM12_IRQHandler
-
-        PUBWEAK TIM8_UP_TIM13_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_UP_TIM13_IRQHandler  
-        B TIM8_UP_TIM13_IRQHandler
-
-        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_TRG_COM_TIM14_IRQHandler  
-        B TIM8_TRG_COM_TIM14_IRQHandler
-
-        PUBWEAK TIM8_CC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM8_CC_IRQHandler  
-        B TIM8_CC_IRQHandler
-
-        PUBWEAK DMA1_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Stream7_IRQHandler  
-        B DMA1_Stream7_IRQHandler
-
-        PUBWEAK FMC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FMC_IRQHandler  
-        B FMC_IRQHandler
-
-        PUBWEAK SDIO_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SDIO_IRQHandler  
-        B SDIO_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler  
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler  
-        B SPI3_IRQHandler
-
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler  
-        B UART4_IRQHandler
-
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler  
-        B UART5_IRQHandler
-
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_DAC_IRQHandler  
-        B TIM6_DAC_IRQHandler
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler  
-        B TIM7_IRQHandler
-
-        PUBWEAK DMA2_Stream0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream0_IRQHandler  
-        B DMA2_Stream0_IRQHandler
-
-        PUBWEAK DMA2_Stream1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream1_IRQHandler  
-        B DMA2_Stream1_IRQHandler
-
-        PUBWEAK DMA2_Stream2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream2_IRQHandler  
-        B DMA2_Stream2_IRQHandler
-
-        PUBWEAK DMA2_Stream3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream3_IRQHandler  
-        B DMA2_Stream3_IRQHandler
-
-        PUBWEAK DMA2_Stream4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream4_IRQHandler  
-        B DMA2_Stream4_IRQHandler
-
-        PUBWEAK ETH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ETH_IRQHandler  
-        B ETH_IRQHandler
-
-        PUBWEAK ETH_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ETH_WKUP_IRQHandler  
-        B ETH_WKUP_IRQHandler
-
-        PUBWEAK CAN2_TX_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_TX_IRQHandler  
-        B CAN2_TX_IRQHandler
-
-        PUBWEAK CAN2_RX0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX0_IRQHandler  
-        B CAN2_RX0_IRQHandler
-
-        PUBWEAK CAN2_RX1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_RX1_IRQHandler  
-        B CAN2_RX1_IRQHandler
-
-        PUBWEAK CAN2_SCE_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CAN2_SCE_IRQHandler  
-        B CAN2_SCE_IRQHandler
-
-        PUBWEAK OTG_FS_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_FS_IRQHandler  
-        B OTG_FS_IRQHandler
-
-        PUBWEAK DMA2_Stream5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream5_IRQHandler  
-        B DMA2_Stream5_IRQHandler
-
-        PUBWEAK DMA2_Stream6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream6_IRQHandler  
-        B DMA2_Stream6_IRQHandler
-
-        PUBWEAK DMA2_Stream7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Stream7_IRQHandler  
-        B DMA2_Stream7_IRQHandler
-
-        PUBWEAK USART6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART6_IRQHandler  
-        B USART6_IRQHandler
-
-        PUBWEAK I2C3_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_EV_IRQHandler  
-        B I2C3_EV_IRQHandler
-
-        PUBWEAK I2C3_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C3_ER_IRQHandler  
-        B I2C3_ER_IRQHandler
-
-        PUBWEAK OTG_HS_EP1_OUT_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_EP1_OUT_IRQHandler  
-        B OTG_HS_EP1_OUT_IRQHandler
-
-        PUBWEAK OTG_HS_EP1_IN_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_EP1_IN_IRQHandler  
-        B OTG_HS_EP1_IN_IRQHandler
-
-        PUBWEAK OTG_HS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_WKUP_IRQHandler  
-        B OTG_HS_WKUP_IRQHandler
-
-        PUBWEAK OTG_HS_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-OTG_HS_IRQHandler  
-        B OTG_HS_IRQHandler
-
-        PUBWEAK DCMI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DCMI_IRQHandler  
-        B DCMI_IRQHandler
-
-        PUBWEAK CRYP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-CRYP_IRQHandler  
-        B CRYP_IRQHandler
-
-        PUBWEAK HASH_RNG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HASH_RNG_IRQHandler  
-        B HASH_RNG_IRQHandler
-
-        PUBWEAK FPU_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FPU_IRQHandler  
-        B FPU_IRQHandler
-
-        PUBWEAK UART7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART7_IRQHandler 
-        B UART7_IRQHandler  
-
-        PUBWEAK UART8_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART8_IRQHandler
-        B UART8_IRQHandler
-
-        PUBWEAK SPI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI4_IRQHandler
-        B SPI4_IRQHandler
-
-        PUBWEAK SPI5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI5_IRQHandler   
-        B SPI5_IRQHandler
-
-        PUBWEAK SPI6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI6_IRQHandler 
-        B SPI6_IRQHandler
-
-        PUBWEAK SAI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SAI1_IRQHandler  
-        B SAI1_IRQHandler
-
-        PUBWEAK LTDC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LTDC_IRQHandler 
-        B LTDC_IRQHandler
-
-        PUBWEAK LTDC_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LTDC_ER_IRQHandler 
-        B LTDC_ER_IRQHandler
-
-        PUBWEAK DMA2D_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2D_IRQHandler 
-        B DMA2D_IRQHandler
-
-        PUBWEAK QUADSPI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-QUADSPI_IRQHandler 
-        B QUADSPI_IRQHandler
-
-        PUBWEAK DSI_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DSI_IRQHandler 
-        B DSI_IRQHandler
-
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/CMSIS/README.txt

@@ -1,42 +0,0 @@
-* -------------------------------------------------------------------
-* Copyright (C) 2011-2014 ARM Limited. All rights reserved.  
-* 
-* Date:        17 February 2014  
-* Revision:    V4.00 
-*  
-* Project:     Cortex Microcontroller Software Interface Standard (CMSIS)
-* Title:       Release Note for CMSIS
-*
-* -------------------------------------------------------------------
-
-
-NOTE - Open the index.html file to access CMSIS documentation
-
-
-The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all 
-Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects 
-and reduces time-to-market for new embedded applications.
-
-CMSIS is released under the terms of the end user license agreement ("CMSIS_END_USER_LICENCE_AGREEMENT.pdf").
-Any user of the software package is bound to the terms and conditions of the end user license agreement.
-
-
-You will find the following sub-directories:
-
-Documentation           - Contains CMSIS documentation.
- 
-DSP_Lib                 - MDK project files, Examples and source files etc.. to build the 
-                          CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
-
-Include                 - CMSIS Core Support and CMSIS DSP Include Files.
-
-Lib                     - CMSIS DSP Libraries.
-
-RTOS                    - CMSIS RTOS API template header file.
-
-Driver                  - CMSIS Peripheral Driver Interface.
-
-Pack                    - CMSIS Software Packs.
-                          Mechanism to install software, device support, APIs, and example projects.
-
-SVD                     - CMSIS SVD Schema files and Conversion Utility.

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h

@@ -1,178 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    misc.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the miscellaneous
-  *          firmware library functions (add-on to CMSIS functions).
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __MISC_H
-#define __MISC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup MISC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  NVIC Init Structure definition  
-  */
-
-typedef struct
-{
-  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
-                                                   This parameter can be an enumerator of @ref IRQn_Type 
-                                                   enumeration (For the complete STM32 Devices IRQ Channels
-                                                   list, please refer to stm32f4xx.h file) */
-
-  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
-                                                   specified in NVIC_IRQChannel. This parameter can be a value
-                                                   between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
-                                                   A lower priority value indicates a higher priority */
-
-  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
-                                                   in NVIC_IRQChannel. This parameter can be a value
-                                                   between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
-                                                   A lower priority value indicates a higher priority */
-
-  FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
-                                                   will be enabled or disabled. 
-                                                   This parameter can be set either to ENABLE or DISABLE */   
-} NVIC_InitTypeDef;
- 
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup MISC_Exported_Constants
-  * @{
-  */
-
-/** @defgroup MISC_Vector_Table_Base 
-  * @{
-  */
-
-#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
-#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
-#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
-                                  ((VECTTAB) == NVIC_VectTab_FLASH))
-/**
-  * @}
-  */
-
-/** @defgroup MISC_System_Low_Power 
-  * @{
-  */
-
-#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
-#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
-#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
-#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
-                        ((LP) == NVIC_LP_SLEEPDEEP) || \
-                        ((LP) == NVIC_LP_SLEEPONEXIT))
-/**
-  * @}
-  */
-
-/** @defgroup MISC_Preemption_Priority_Group 
-  * @{
-  */
-
-#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
-                                                            4 bits for subpriority */
-#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
-                                                            3 bits for subpriority */
-#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
-                                                            2 bits for subpriority */
-#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
-                                                            1 bits for subpriority */
-#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
-                                                            0 bits for subpriority */
-
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
-                                       ((GROUP) == NVIC_PriorityGroup_1) || \
-                                       ((GROUP) == NVIC_PriorityGroup_2) || \
-                                       ((GROUP) == NVIC_PriorityGroup_3) || \
-                                       ((GROUP) == NVIC_PriorityGroup_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
-
-#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x000FFFFF)
-
-/**
-  * @}
-  */
-
-/** @defgroup MISC_SysTick_clock_source 
-  * @{
-  */
-
-#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
-#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
-                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
-void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __MISC_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h

@@ -1,656 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_adc.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the ADC firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_ADC_H
-#define __STM32F4xx_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup ADC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief   ADC Init structure definition  
-  */ 
-typedef struct
-{
-  uint32_t ADC_Resolution;                /*!< Configures the ADC resolution dual mode. 
-                                               This parameter can be a value of @ref ADC_resolution */                                   
-  FunctionalState ADC_ScanConvMode;       /*!< Specifies whether the conversion 
-                                               is performed in Scan (multichannels) 
-                                               or Single (one channel) mode.
-                                               This parameter can be set to ENABLE or DISABLE */ 
-  FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion 
-                                               is performed in Continuous or Single mode.
-                                               This parameter can be set to ENABLE or DISABLE. */
-  uint32_t ADC_ExternalTrigConvEdge;      /*!< Select the external trigger edge and
-                                               enable the trigger of a regular group. 
-                                               This parameter can be a value of 
-                                               @ref ADC_external_trigger_edge_for_regular_channels_conversion */
-  uint32_t ADC_ExternalTrigConv;          /*!< Select the external event used to trigger 
-                                               the start of conversion of a regular group.
-                                               This parameter can be a value of 
-                                               @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */
-  uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data  alignment
-                                               is left or right. This parameter can be 
-                                               a value of @ref ADC_data_align */
-  uint8_t  ADC_NbrOfConversion;           /*!< Specifies the number of ADC conversions
-                                               that will be done using the sequencer for
-                                               regular channel group.
-                                               This parameter must range from 1 to 16. */
-}ADC_InitTypeDef;
-  
-/** 
-  * @brief   ADC Common Init structure definition  
-  */ 
-typedef struct 
-{
-  uint32_t ADC_Mode;                      /*!< Configures the ADC to operate in 
-                                               independent or multi mode. 
-                                               This parameter can be a value of @ref ADC_Common_mode */                                              
-  uint32_t ADC_Prescaler;                 /*!< Select the frequency of the clock 
-                                               to the ADC. The clock is common for all the ADCs.
-                                               This parameter can be a value of @ref ADC_Prescaler */
-  uint32_t ADC_DMAAccessMode;             /*!< Configures the Direct memory access 
-                                              mode for multi ADC mode.
-                                               This parameter can be a value of 
-                                               @ref ADC_Direct_memory_access_mode_for_multi_mode */
-  uint32_t ADC_TwoSamplingDelay;          /*!< Configures the Delay between 2 sampling phases.
-                                               This parameter can be a value of 
-                                               @ref ADC_delay_between_2_sampling_phases */
-  
-}ADC_CommonInitTypeDef;
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Constants
-  * @{
-  */ 
-#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
-                                   ((PERIPH) == ADC2) || \
-                                   ((PERIPH) == ADC3))  
-
-/** @defgroup ADC_Common_mode 
-  * @{
-  */ 
-#define ADC_Mode_Independent                       ((uint32_t)0x00000000)       
-#define ADC_DualMode_RegSimult_InjecSimult         ((uint32_t)0x00000001)
-#define ADC_DualMode_RegSimult_AlterTrig           ((uint32_t)0x00000002)
-#define ADC_DualMode_InjecSimult                   ((uint32_t)0x00000005)
-#define ADC_DualMode_RegSimult                     ((uint32_t)0x00000006)
-#define ADC_DualMode_Interl                        ((uint32_t)0x00000007)
-#define ADC_DualMode_AlterTrig                     ((uint32_t)0x00000009)
-#define ADC_TripleMode_RegSimult_InjecSimult       ((uint32_t)0x00000011)
-#define ADC_TripleMode_RegSimult_AlterTrig         ((uint32_t)0x00000012)
-#define ADC_TripleMode_InjecSimult                 ((uint32_t)0x00000015)
-#define ADC_TripleMode_RegSimult                   ((uint32_t)0x00000016)
-#define ADC_TripleMode_Interl                      ((uint32_t)0x00000017)
-#define ADC_TripleMode_AlterTrig                   ((uint32_t)0x00000019)
-#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
-                           ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \
-                           ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \
-                           ((MODE) == ADC_DualMode_InjecSimult) || \
-                           ((MODE) == ADC_DualMode_RegSimult) || \
-                           ((MODE) == ADC_DualMode_Interl) || \
-                           ((MODE) == ADC_DualMode_AlterTrig) || \
-                           ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \
-                           ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \
-                           ((MODE) == ADC_TripleMode_InjecSimult) || \
-                           ((MODE) == ADC_TripleMode_RegSimult) || \
-                           ((MODE) == ADC_TripleMode_Interl) || \
-                           ((MODE) == ADC_TripleMode_AlterTrig))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_Prescaler 
-  * @{
-  */ 
-#define ADC_Prescaler_Div2                         ((uint32_t)0x00000000)
-#define ADC_Prescaler_Div4                         ((uint32_t)0x00010000)
-#define ADC_Prescaler_Div6                         ((uint32_t)0x00020000)
-#define ADC_Prescaler_Div8                         ((uint32_t)0x00030000)
-#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \
-                                     ((PRESCALER) == ADC_Prescaler_Div4) || \
-                                     ((PRESCALER) == ADC_Prescaler_Div6) || \
-                                     ((PRESCALER) == ADC_Prescaler_Div8))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode 
-  * @{
-  */ 
-#define ADC_DMAAccessMode_Disabled      ((uint32_t)0x00000000)     /* DMA mode disabled */
-#define ADC_DMAAccessMode_1             ((uint32_t)0x00004000)     /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
-#define ADC_DMAAccessMode_2             ((uint32_t)0x00008000)     /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
-#define ADC_DMAAccessMode_3             ((uint32_t)0x0000C000)     /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
-#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
-                                      ((MODE) == ADC_DMAAccessMode_1) || \
-                                      ((MODE) == ADC_DMAAccessMode_2) || \
-                                      ((MODE) == ADC_DMAAccessMode_3))
-                                     
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_delay_between_2_sampling_phases 
-  * @{
-  */ 
-#define ADC_TwoSamplingDelay_5Cycles               ((uint32_t)0x00000000)
-#define ADC_TwoSamplingDelay_6Cycles               ((uint32_t)0x00000100)
-#define ADC_TwoSamplingDelay_7Cycles               ((uint32_t)0x00000200)
-#define ADC_TwoSamplingDelay_8Cycles               ((uint32_t)0x00000300)
-#define ADC_TwoSamplingDelay_9Cycles               ((uint32_t)0x00000400)
-#define ADC_TwoSamplingDelay_10Cycles              ((uint32_t)0x00000500)
-#define ADC_TwoSamplingDelay_11Cycles              ((uint32_t)0x00000600)
-#define ADC_TwoSamplingDelay_12Cycles              ((uint32_t)0x00000700)
-#define ADC_TwoSamplingDelay_13Cycles              ((uint32_t)0x00000800)
-#define ADC_TwoSamplingDelay_14Cycles              ((uint32_t)0x00000900)
-#define ADC_TwoSamplingDelay_15Cycles              ((uint32_t)0x00000A00)
-#define ADC_TwoSamplingDelay_16Cycles              ((uint32_t)0x00000B00)
-#define ADC_TwoSamplingDelay_17Cycles              ((uint32_t)0x00000C00)
-#define ADC_TwoSamplingDelay_18Cycles              ((uint32_t)0x00000D00)
-#define ADC_TwoSamplingDelay_19Cycles              ((uint32_t)0x00000E00)
-#define ADC_TwoSamplingDelay_20Cycles              ((uint32_t)0x00000F00)
-#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \
-                                      ((DELAY) == ADC_TwoSamplingDelay_20Cycles))
-                                     
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_resolution 
-  * @{
-  */ 
-#define ADC_Resolution_12b                         ((uint32_t)0x00000000)
-#define ADC_Resolution_10b                         ((uint32_t)0x01000000)
-#define ADC_Resolution_8b                          ((uint32_t)0x02000000)
-#define ADC_Resolution_6b                          ((uint32_t)0x03000000)
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
-                                       ((RESOLUTION) == ADC_Resolution_10b) || \
-                                       ((RESOLUTION) == ADC_Resolution_8b) || \
-                                       ((RESOLUTION) == ADC_Resolution_6b))
-                                      
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion 
-  * @{
-  */ 
-#define ADC_ExternalTrigConvEdge_None          ((uint32_t)0x00000000)
-#define ADC_ExternalTrigConvEdge_Rising        ((uint32_t)0x10000000)
-#define ADC_ExternalTrigConvEdge_Falling       ((uint32_t)0x20000000)
-#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
-#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
-                             ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
-                             ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
-                             ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion 
-  * @{
-  */ 
-#define ADC_ExternalTrigConv_T1_CC1                ((uint32_t)0x00000000)
-#define ADC_ExternalTrigConv_T1_CC2                ((uint32_t)0x01000000)
-#define ADC_ExternalTrigConv_T1_CC3                ((uint32_t)0x02000000)
-#define ADC_ExternalTrigConv_T2_CC2                ((uint32_t)0x03000000)
-#define ADC_ExternalTrigConv_T2_CC3                ((uint32_t)0x04000000)
-#define ADC_ExternalTrigConv_T2_CC4                ((uint32_t)0x05000000)
-#define ADC_ExternalTrigConv_T2_TRGO               ((uint32_t)0x06000000)
-#define ADC_ExternalTrigConv_T3_CC1                ((uint32_t)0x07000000)
-#define ADC_ExternalTrigConv_T3_TRGO               ((uint32_t)0x08000000)
-#define ADC_ExternalTrigConv_T4_CC4                ((uint32_t)0x09000000)
-#define ADC_ExternalTrigConv_T5_CC1                ((uint32_t)0x0A000000)
-#define ADC_ExternalTrigConv_T5_CC2                ((uint32_t)0x0B000000)
-#define ADC_ExternalTrigConv_T5_CC3                ((uint32_t)0x0C000000)
-#define ADC_ExternalTrigConv_T8_CC1                ((uint32_t)0x0D000000)
-#define ADC_ExternalTrigConv_T8_TRGO               ((uint32_t)0x0E000000)
-#define ADC_ExternalTrigConv_Ext_IT11              ((uint32_t)0x0F000000)
-#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
-                                  ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_data_align 
-  * @{
-  */ 
-#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
-#define ADC_DataAlign_Left                         ((uint32_t)0x00000800)
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
-                                  ((ALIGN) == ADC_DataAlign_Left))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_channels 
-  * @{
-  */ 
-#define ADC_Channel_0                               ((uint8_t)0x00)
-#define ADC_Channel_1                               ((uint8_t)0x01)
-#define ADC_Channel_2                               ((uint8_t)0x02)
-#define ADC_Channel_3                               ((uint8_t)0x03)
-#define ADC_Channel_4                               ((uint8_t)0x04)
-#define ADC_Channel_5                               ((uint8_t)0x05)
-#define ADC_Channel_6                               ((uint8_t)0x06)
-#define ADC_Channel_7                               ((uint8_t)0x07)
-#define ADC_Channel_8                               ((uint8_t)0x08)
-#define ADC_Channel_9                               ((uint8_t)0x09)
-#define ADC_Channel_10                              ((uint8_t)0x0A)
-#define ADC_Channel_11                              ((uint8_t)0x0B)
-#define ADC_Channel_12                              ((uint8_t)0x0C)
-#define ADC_Channel_13                              ((uint8_t)0x0D)
-#define ADC_Channel_14                              ((uint8_t)0x0E)
-#define ADC_Channel_15                              ((uint8_t)0x0F)
-#define ADC_Channel_16                              ((uint8_t)0x10)
-#define ADC_Channel_17                              ((uint8_t)0x11)
-#define ADC_Channel_18                              ((uint8_t)0x12)
-
-#if defined (STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
-#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE)
-#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_18)
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE */
-
-#define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_17)
-#define ADC_Channel_Vbat                            ((uint8_t)ADC_Channel_18)
-
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \
-                                 ((CHANNEL) == ADC_Channel_1) || \
-                                 ((CHANNEL) == ADC_Channel_2) || \
-                                 ((CHANNEL) == ADC_Channel_3) || \
-                                 ((CHANNEL) == ADC_Channel_4) || \
-                                 ((CHANNEL) == ADC_Channel_5) || \
-                                 ((CHANNEL) == ADC_Channel_6) || \
-                                 ((CHANNEL) == ADC_Channel_7) || \
-                                 ((CHANNEL) == ADC_Channel_8) || \
-                                 ((CHANNEL) == ADC_Channel_9) || \
-                                 ((CHANNEL) == ADC_Channel_10) || \
-                                 ((CHANNEL) == ADC_Channel_11) || \
-                                 ((CHANNEL) == ADC_Channel_12) || \
-                                 ((CHANNEL) == ADC_Channel_13) || \
-                                 ((CHANNEL) == ADC_Channel_14) || \
-                                 ((CHANNEL) == ADC_Channel_15) || \
-                                 ((CHANNEL) == ADC_Channel_16) || \
-                                 ((CHANNEL) == ADC_Channel_17) || \
-                                 ((CHANNEL) == ADC_Channel_18))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_sampling_times 
-  * @{
-  */ 
-#define ADC_SampleTime_3Cycles                    ((uint8_t)0x00)
-#define ADC_SampleTime_15Cycles                   ((uint8_t)0x01)
-#define ADC_SampleTime_28Cycles                   ((uint8_t)0x02)
-#define ADC_SampleTime_56Cycles                   ((uint8_t)0x03)
-#define ADC_SampleTime_84Cycles                   ((uint8_t)0x04)
-#define ADC_SampleTime_112Cycles                  ((uint8_t)0x05)
-#define ADC_SampleTime_144Cycles                  ((uint8_t)0x06)
-#define ADC_SampleTime_480Cycles                  ((uint8_t)0x07)
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \
-                                  ((TIME) == ADC_SampleTime_15Cycles) || \
-                                  ((TIME) == ADC_SampleTime_28Cycles) || \
-                                  ((TIME) == ADC_SampleTime_56Cycles) || \
-                                  ((TIME) == ADC_SampleTime_84Cycles) || \
-                                  ((TIME) == ADC_SampleTime_112Cycles) || \
-                                  ((TIME) == ADC_SampleTime_144Cycles) || \
-                                  ((TIME) == ADC_SampleTime_480Cycles))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion 
-  * @{
-  */ 
-#define ADC_ExternalTrigInjecConvEdge_None          ((uint32_t)0x00000000)
-#define ADC_ExternalTrigInjecConvEdge_Rising        ((uint32_t)0x00100000)
-#define ADC_ExternalTrigInjecConvEdge_Falling       ((uint32_t)0x00200000)
-#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
-#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
-                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
-                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
-                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
-                                            
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion 
-  * @{
-  */ 
-#define ADC_ExternalTrigInjecConv_T1_CC4            ((uint32_t)0x00000000)
-#define ADC_ExternalTrigInjecConv_T1_TRGO           ((uint32_t)0x00010000)
-#define ADC_ExternalTrigInjecConv_T2_CC1            ((uint32_t)0x00020000)
-#define ADC_ExternalTrigInjecConv_T2_TRGO           ((uint32_t)0x00030000)
-#define ADC_ExternalTrigInjecConv_T3_CC2            ((uint32_t)0x00040000)
-#define ADC_ExternalTrigInjecConv_T3_CC4            ((uint32_t)0x00050000)
-#define ADC_ExternalTrigInjecConv_T4_CC1            ((uint32_t)0x00060000)
-#define ADC_ExternalTrigInjecConv_T4_CC2            ((uint32_t)0x00070000)
-#define ADC_ExternalTrigInjecConv_T4_CC3            ((uint32_t)0x00080000)
-#define ADC_ExternalTrigInjecConv_T4_TRGO           ((uint32_t)0x00090000)
-#define ADC_ExternalTrigInjecConv_T5_CC4            ((uint32_t)0x000A0000)
-#define ADC_ExternalTrigInjecConv_T5_TRGO           ((uint32_t)0x000B0000)
-#define ADC_ExternalTrigInjecConv_T8_CC2            ((uint32_t)0x000C0000)
-#define ADC_ExternalTrigInjecConv_T8_CC3            ((uint32_t)0x000D0000)
-#define ADC_ExternalTrigInjecConv_T8_CC4            ((uint32_t)0x000E0000)
-#define ADC_ExternalTrigInjecConv_Ext_IT15          ((uint32_t)0x000F0000)
-#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
-                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_injected_channel_selection 
-  * @{
-  */ 
-#define ADC_InjectedChannel_1                       ((uint8_t)0x14)
-#define ADC_InjectedChannel_2                       ((uint8_t)0x18)
-#define ADC_InjectedChannel_3                       ((uint8_t)0x1C)
-#define ADC_InjectedChannel_4                       ((uint8_t)0x20)
-#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
-                                          ((CHANNEL) == ADC_InjectedChannel_2) || \
-                                          ((CHANNEL) == ADC_InjectedChannel_3) || \
-                                          ((CHANNEL) == ADC_InjectedChannel_4))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_analog_watchdog_selection 
-  * @{
-  */ 
-#define ADC_AnalogWatchdog_SingleRegEnable         ((uint32_t)0x00800200)
-#define ADC_AnalogWatchdog_SingleInjecEnable       ((uint32_t)0x00400200)
-#define ADC_AnalogWatchdog_SingleRegOrInjecEnable  ((uint32_t)0x00C00200)
-#define ADC_AnalogWatchdog_AllRegEnable            ((uint32_t)0x00800000)
-#define ADC_AnalogWatchdog_AllInjecEnable          ((uint32_t)0x00400000)
-#define ADC_AnalogWatchdog_AllRegAllInjecEnable    ((uint32_t)0x00C00000)
-#define ADC_AnalogWatchdog_None                    ((uint32_t)0x00000000)
-#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
-                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
-                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
-                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
-                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
-                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
-                                          ((WATCHDOG) == ADC_AnalogWatchdog_None))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_interrupts_definition 
-  * @{
-  */ 
-#define ADC_IT_EOC                                 ((uint16_t)0x0205)  
-#define ADC_IT_AWD                                 ((uint16_t)0x0106)  
-#define ADC_IT_JEOC                                ((uint16_t)0x0407)  
-#define ADC_IT_OVR                                 ((uint16_t)0x201A)  
-#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
-                       ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_flags_definition 
-  * @{
-  */ 
-#define ADC_FLAG_AWD                               ((uint8_t)0x01)
-#define ADC_FLAG_EOC                               ((uint8_t)0x02)
-#define ADC_FLAG_JEOC                              ((uint8_t)0x04)
-#define ADC_FLAG_JSTRT                             ((uint8_t)0x08)
-#define ADC_FLAG_STRT                              ((uint8_t)0x10)
-#define ADC_FLAG_OVR                               ((uint8_t)0x20)   
-  
-#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00))   
-#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \
-                               ((FLAG) == ADC_FLAG_EOC) || \
-                               ((FLAG) == ADC_FLAG_JEOC) || \
-                               ((FLAG)== ADC_FLAG_JSTRT) || \
-                               ((FLAG) == ADC_FLAG_STRT) || \
-                               ((FLAG)== ADC_FLAG_OVR))     
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_thresholds 
-  * @{
-  */ 
-#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_injected_offset 
-  * @{
-  */ 
-#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_injected_length 
-  * @{
-  */ 
-#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_injected_rank 
-  * @{
-  */ 
-#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_regular_length 
-  * @{
-  */ 
-#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_regular_rank 
-  * @{
-  */ 
-#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup ADC_regular_discontinuous_mode_number 
-  * @{
-  */ 
-#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
-/**
-  * @}
-  */ 
-
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/  
-
-/*  Function used to set the ADC configuration to the default reset state *****/  
-void ADC_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
-void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
-void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-
-/* Analog Watchdog configuration functions ************************************/
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
-
-/* Temperature Sensor, Vrefint and VBAT management functions ******************/
-void ADC_TempSensorVrefintCmd(FunctionalState NewState);
-void ADC_VBATCmd(FunctionalState NewState);
-
-/* Regular Channels Configuration functions ***********************************/
-void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
-void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
-FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
-void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
-uint32_t ADC_GetMultiModeConversionValue(void);
-
-/* Regular Channels DMA Configuration functions *******************************/
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState);
-
-/* Injected channels Configuration functions **********************************/
-void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
-void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
-void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
-void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
-void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
-void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
-FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
-void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
-
-/* Interrupts and flags management functions **********************************/
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_ADC_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h

@@ -1,657 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_can.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the CAN firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_CAN_H
-#define __STM32F4xx_CAN_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup CAN
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(STM32F413_423xx)
-#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
-                                   ((PERIPH) == CAN2) || \
-                                   ((PERIPH) == CAN3))
-#else
-#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
-                                   ((PERIPH) == CAN2))
-#endif /* STM32F413_423xx */
-
-/** 
-  * @brief  CAN init structure definition
-  */
-typedef struct
-{
-  uint16_t CAN_Prescaler;   /*!< Specifies the length of a time quantum. 
-                                 It ranges from 1 to 1024. */
-  
-  uint8_t CAN_Mode;         /*!< Specifies the CAN operating mode.
-                                 This parameter can be a value of @ref CAN_operating_mode */
-
-  uint8_t CAN_SJW;          /*!< Specifies the maximum number of time quanta 
-                                 the CAN hardware is allowed to lengthen or 
-                                 shorten a bit to perform resynchronization.
-                                 This parameter can be a value of @ref CAN_synchronisation_jump_width */
-
-  uint8_t CAN_BS1;          /*!< Specifies the number of time quanta in Bit 
-                                 Segment 1. This parameter can be a value of 
-                                 @ref CAN_time_quantum_in_bit_segment_1 */
-
-  uint8_t CAN_BS2;          /*!< Specifies the number of time quanta in Bit Segment 2.
-                                 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
-  
-  FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
-                                This parameter can be set either to ENABLE or DISABLE. */
-  
-  FunctionalState CAN_ABOM;  /*!< Enable or disable the automatic bus-off management.
-                                  This parameter can be set either to ENABLE or DISABLE. */
-
-  FunctionalState CAN_AWUM;  /*!< Enable or disable the automatic wake-up mode. 
-                                  This parameter can be set either to ENABLE or DISABLE. */
-
-  FunctionalState CAN_NART;  /*!< Enable or disable the non-automatic retransmission mode.
-                                  This parameter can be set either to ENABLE or DISABLE. */
-
-  FunctionalState CAN_RFLM;  /*!< Enable or disable the Receive FIFO Locked mode.
-                                  This parameter can be set either to ENABLE or DISABLE. */
-
-  FunctionalState CAN_TXFP;  /*!< Enable or disable the transmit FIFO priority.
-                                  This parameter can be set either to ENABLE or DISABLE. */
-} CAN_InitTypeDef;
-
-/** 
-  * @brief  CAN filter init structure definition
-  */
-typedef struct
-{
-  uint16_t CAN_FilterIdHigh;         /*!< Specifies the filter identification number (MSBs for a 32-bit
-                                              configuration, first one for a 16-bit configuration).
-                                              This parameter can be a value between 0x0000 and 0xFFFF */
-
-  uint16_t CAN_FilterIdLow;          /*!< Specifies the filter identification number (LSBs for a 32-bit
-                                              configuration, second one for a 16-bit configuration).
-                                              This parameter can be a value between 0x0000 and 0xFFFF */
-
-  uint16_t CAN_FilterMaskIdHigh;     /*!< Specifies the filter mask number or identification number,
-                                              according to the mode (MSBs for a 32-bit configuration,
-                                              first one for a 16-bit configuration).
-                                              This parameter can be a value between 0x0000 and 0xFFFF */
-
-  uint16_t CAN_FilterMaskIdLow;      /*!< Specifies the filter mask number or identification number,
-                                              according to the mode (LSBs for a 32-bit configuration,
-                                              second one for a 16-bit configuration).
-                                              This parameter can be a value between 0x0000 and 0xFFFF */
-
-  uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
-                                              This parameter can be a value of @ref CAN_filter_FIFO */
-  
-  uint8_t CAN_FilterNumber;          /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
-
-  uint8_t CAN_FilterMode;            /*!< Specifies the filter mode to be initialized.
-                                              This parameter can be a value of @ref CAN_filter_mode */
-
-  uint8_t CAN_FilterScale;           /*!< Specifies the filter scale.
-                                              This parameter can be a value of @ref CAN_filter_scale */
-
-  FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
-                                              This parameter can be set either to ENABLE or DISABLE. */
-} CAN_FilterInitTypeDef;
-
-/** 
-  * @brief  CAN Tx message structure definition  
-  */
-typedef struct
-{
-  uint32_t StdId;  /*!< Specifies the standard identifier.
-                        This parameter can be a value between 0 to 0x7FF. */
-
-  uint32_t ExtId;  /*!< Specifies the extended identifier.
-                        This parameter can be a value between 0 to 0x1FFFFFFF. */
-
-  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
-                        will be transmitted. This parameter can be a value 
-                        of @ref CAN_identifier_type */
-
-  uint8_t RTR;     /*!< Specifies the type of frame for the message that will 
-                        be transmitted. This parameter can be a value of 
-                        @ref CAN_remote_transmission_request */
-
-  uint8_t DLC;     /*!< Specifies the length of the frame that will be 
-                        transmitted. This parameter can be a value between 
-                        0 to 8 */
-
-  uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 
-                        to 0xFF. */
-} CanTxMsg;
-
-/** 
-  * @brief  CAN Rx message structure definition  
-  */
-typedef struct
-{
-  uint32_t StdId;  /*!< Specifies the standard identifier.
-                        This parameter can be a value between 0 to 0x7FF. */
-
-  uint32_t ExtId;  /*!< Specifies the extended identifier.
-                        This parameter can be a value between 0 to 0x1FFFFFFF. */
-
-  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
-                        will be received. This parameter can be a value of 
-                        @ref CAN_identifier_type */
-
-  uint8_t RTR;     /*!< Specifies the type of frame for the received message.
-                        This parameter can be a value of 
-                        @ref CAN_remote_transmission_request */
-
-  uint8_t DLC;     /*!< Specifies the length of the frame that will be received.
-                        This parameter can be a value between 0 to 8 */
-
-  uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 
-                        0xFF. */
-
-  uint8_t FMI;     /*!< Specifies the index of the filter the message stored in 
-                        the mailbox passes through. This parameter can be a 
-                        value between 0 to 0xFF */
-} CanRxMsg;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CAN_Exported_Constants
-  * @{
-  */
-
-/** @defgroup CAN_InitStatus 
-  * @{
-  */
-
-#define CAN_InitStatus_Failed              ((uint8_t)0x00) /*!< CAN initialization failed */
-#define CAN_InitStatus_Success             ((uint8_t)0x01) /*!< CAN initialization OK */
-
-
-/* Legacy defines */
-#define CANINITFAILED    CAN_InitStatus_Failed
-#define CANINITOK        CAN_InitStatus_Success
-/**
-  * @}
-  */
-
-/** @defgroup CAN_operating_mode 
-  * @{
-  */
-
-#define CAN_Mode_Normal             ((uint8_t)0x00)  /*!< normal mode */
-#define CAN_Mode_LoopBack           ((uint8_t)0x01)  /*!< loopback mode */
-#define CAN_Mode_Silent             ((uint8_t)0x02)  /*!< silent mode */
-#define CAN_Mode_Silent_LoopBack    ((uint8_t)0x03)  /*!< loopback combined with silent mode */
-
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
-                           ((MODE) == CAN_Mode_LoopBack)|| \
-                           ((MODE) == CAN_Mode_Silent) || \
-                           ((MODE) == CAN_Mode_Silent_LoopBack))
-/**
-  * @}
-  */
-
-
- /**
-  * @defgroup CAN_operating_mode 
-  * @{
-  */  
-#define CAN_OperatingMode_Initialization  ((uint8_t)0x00) /*!< Initialization mode */
-#define CAN_OperatingMode_Normal          ((uint8_t)0x01) /*!< Normal mode */
-#define CAN_OperatingMode_Sleep           ((uint8_t)0x02) /*!< sleep mode */
-
-
-#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
-                                    ((MODE) == CAN_OperatingMode_Normal)|| \
-																		((MODE) == CAN_OperatingMode_Sleep))
-/**
-  * @}
-  */
-  
-/**
-  * @defgroup CAN_operating_mode_status
-  * @{
-  */  
-
-#define CAN_ModeStatus_Failed    ((uint8_t)0x00)                /*!< CAN entering the specific mode failed */
-#define CAN_ModeStatus_Success   ((uint8_t)!CAN_ModeStatus_Failed)   /*!< CAN entering the specific mode Succeed */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_synchronisation_jump_width 
-  * @{
-  */
-#define CAN_SJW_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
-#define CAN_SJW_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
-#define CAN_SJW_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
-#define CAN_SJW_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
-
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
-                         ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
-/**
-  * @}
-  */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_1 
-  * @{
-  */
-#define CAN_BS1_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
-#define CAN_BS1_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
-#define CAN_BS1_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
-#define CAN_BS1_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
-#define CAN_BS1_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
-#define CAN_BS1_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
-#define CAN_BS1_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
-#define CAN_BS1_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
-#define CAN_BS1_9tq                 ((uint8_t)0x08)  /*!< 9 time quantum */
-#define CAN_BS1_10tq                ((uint8_t)0x09)  /*!< 10 time quantum */
-#define CAN_BS1_11tq                ((uint8_t)0x0A)  /*!< 11 time quantum */
-#define CAN_BS1_12tq                ((uint8_t)0x0B)  /*!< 12 time quantum */
-#define CAN_BS1_13tq                ((uint8_t)0x0C)  /*!< 13 time quantum */
-#define CAN_BS1_14tq                ((uint8_t)0x0D)  /*!< 14 time quantum */
-#define CAN_BS1_15tq                ((uint8_t)0x0E)  /*!< 15 time quantum */
-#define CAN_BS1_16tq                ((uint8_t)0x0F)  /*!< 16 time quantum */
-
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
-/**
-  * @}
-  */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_2 
-  * @{
-  */
-#define CAN_BS2_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
-#define CAN_BS2_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
-#define CAN_BS2_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
-#define CAN_BS2_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
-#define CAN_BS2_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
-#define CAN_BS2_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
-#define CAN_BS2_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
-#define CAN_BS2_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
-
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
-/**
-  * @}
-  */
-
-/** @defgroup CAN_clock_prescaler 
-  * @{
-  */
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_number 
-  * @{
-  */
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_mode 
-  * @{
-  */
-#define CAN_FilterMode_IdMask       ((uint8_t)0x00)  /*!< identifier/mask mode */
-#define CAN_FilterMode_IdList       ((uint8_t)0x01)  /*!< identifier list mode */
-
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
-                                  ((MODE) == CAN_FilterMode_IdList))
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_scale 
-  * @{
-  */
-#define CAN_FilterScale_16bit       ((uint8_t)0x00) /*!< Two 16-bit filters */
-#define CAN_FilterScale_32bit       ((uint8_t)0x01) /*!< One 32-bit filter */
-
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
-                                    ((SCALE) == CAN_FilterScale_32bit))
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_FIFO
-  * @{
-  */
-#define CAN_Filter_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_Filter_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
-                                  ((FIFO) == CAN_FilterFIFO1))
-
-/* Legacy defines */
-#define CAN_FilterFIFO0  CAN_Filter_FIFO0
-#define CAN_FilterFIFO1  CAN_Filter_FIFO1
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Start_bank_filter_for_slave_CAN 
-  * @{
-  */
-#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Tx 
-  * @{
-  */
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
-#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
-#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
-/**
-  * @}
-  */
-
-/** @defgroup CAN_identifier_type 
-  * @{
-  */
-#define CAN_Id_Standard             ((uint32_t)0x00000000)  /*!< Standard Id */
-#define CAN_Id_Extended             ((uint32_t)0x00000004)  /*!< Extended Id */
-#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
-                               ((IDTYPE) == CAN_Id_Extended))
-
-/* Legacy defines */
-#define CAN_ID_STD      CAN_Id_Standard           
-#define CAN_ID_EXT      CAN_Id_Extended
-/**
-  * @}
-  */
-
-/** @defgroup CAN_remote_transmission_request 
-  * @{
-  */
-#define CAN_RTR_Data                ((uint32_t)0x00000000)  /*!< Data frame */
-#define CAN_RTR_Remote              ((uint32_t)0x00000002)  /*!< Remote frame */
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
-
-/* Legacy defines */
-#define CAN_RTR_DATA     CAN_RTR_Data         
-#define CAN_RTR_REMOTE   CAN_RTR_Remote
-/**
-  * @}
-  */
-
-/** @defgroup CAN_transmit_constants 
-  * @{
-  */
-#define CAN_TxStatus_Failed         ((uint8_t)0x00)/*!< CAN transmission failed */
-#define CAN_TxStatus_Ok             ((uint8_t)0x01) /*!< CAN transmission succeeded */
-#define CAN_TxStatus_Pending        ((uint8_t)0x02) /*!< CAN transmission pending */
-#define CAN_TxStatus_NoMailBox      ((uint8_t)0x04) /*!< CAN cell did not provide 
-                                                         an empty mailbox */
-/* Legacy defines */	
-#define CANTXFAILED                  CAN_TxStatus_Failed
-#define CANTXOK                      CAN_TxStatus_Ok
-#define CANTXPENDING                 CAN_TxStatus_Pending
-#define CAN_NO_MB                    CAN_TxStatus_NoMailBox
-/**
-  * @}
-  */
-
-/** @defgroup CAN_receive_FIFO_number_constants 
-  * @{
-  */
-#define CAN_FIFO0                 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
-#define CAN_FIFO1                 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
-
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
-/**
-  * @}
-  */
-
-/** @defgroup CAN_sleep_constants 
-  * @{
-  */
-#define CAN_Sleep_Failed     ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
-#define CAN_Sleep_Ok         ((uint8_t)0x01) /*!< CAN entered the sleep mode */
-
-/* Legacy defines */	
-#define CANSLEEPFAILED   CAN_Sleep_Failed
-#define CANSLEEPOK       CAN_Sleep_Ok
-/**
-  * @}
-  */
-
-/** @defgroup CAN_wake_up_constants 
-  * @{
-  */
-#define CAN_WakeUp_Failed        ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
-#define CAN_WakeUp_Ok            ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
-
-/* Legacy defines */
-#define CANWAKEUPFAILED   CAN_WakeUp_Failed        
-#define CANWAKEUPOK       CAN_WakeUp_Ok        
-/**
-  * @}
-  */
-
-/**
-  * @defgroup CAN_Error_Code_constants
-  * @{
-  */                                                         
-#define CAN_ErrorCode_NoErr           ((uint8_t)0x00) /*!< No Error */ 
-#define	CAN_ErrorCode_StuffErr        ((uint8_t)0x10) /*!< Stuff Error */ 
-#define	CAN_ErrorCode_FormErr         ((uint8_t)0x20) /*!< Form Error */ 
-#define	CAN_ErrorCode_ACKErr          ((uint8_t)0x30) /*!< Acknowledgment Error */ 
-#define	CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ 
-#define	CAN_ErrorCode_BitDominantErr  ((uint8_t)0x50) /*!< Bit Dominant Error */ 
-#define	CAN_ErrorCode_CRCErr          ((uint8_t)0x60) /*!< CRC Error  */ 
-#define	CAN_ErrorCode_SoftwareSetErr  ((uint8_t)0x70) /*!< Software Set Error */ 
-/**
-  * @}
-  */
-
-/** @defgroup CAN_flags 
-  * @{
-  */
-/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
-   and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with 
-   CAN_GetFlagStatus() function.  */
-
-/* Transmit Flags */
-#define CAN_FLAG_RQCP0             ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
-#define CAN_FLAG_RQCP1             ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
-#define CAN_FLAG_RQCP2             ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
-
-/* Receive Flags */
-#define CAN_FLAG_FMP0              ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
-#define CAN_FLAG_FF0               ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag            */
-#define CAN_FLAG_FOV0              ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag         */
-#define CAN_FLAG_FMP1              ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
-#define CAN_FLAG_FF1               ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag            */
-#define CAN_FLAG_FOV1              ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag         */
-
-/* Operating Mode Flags */
-#define CAN_FLAG_WKU               ((uint32_t)0x31000008) /*!< Wake up Flag */
-#define CAN_FLAG_SLAK              ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
-/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. 
-         In this case the SLAK bit can be polled.*/
-
-/* Error Flags */
-#define CAN_FLAG_EWG               ((uint32_t)0x10F00001) /*!< Error Warning Flag   */
-#define CAN_FLAG_EPV               ((uint32_t)0x10F00002) /*!< Error Passive Flag   */
-#define CAN_FLAG_BOF               ((uint32_t)0x10F00004) /*!< Bus-Off Flag         */
-#define CAN_FLAG_LEC               ((uint32_t)0x30F00070) /*!< Last error code Flag */
-
-#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC)  || ((FLAG) == CAN_FLAG_BOF)   || \
-                               ((FLAG) == CAN_FLAG_EPV)  || ((FLAG) == CAN_FLAG_EWG)   || \
-                               ((FLAG) == CAN_FLAG_WKU)  || ((FLAG) == CAN_FLAG_FOV0)  || \
-                               ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FMP0)  || \
-                               ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1)   || \
-                               ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
-                               ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
-                               ((FLAG) == CAN_FLAG_SLAK ))
-
-#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
-                                ((FLAG) == CAN_FLAG_RQCP1)  || ((FLAG) == CAN_FLAG_RQCP0) || \
-                                ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FOV0) ||\
-                                ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
-                                ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
-/**
-  * @}
-  */
-
-  
-/** @defgroup CAN_interrupts 
-  * @{
-  */ 
-#define CAN_IT_TME                  ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
-
-/* Receive Interrupts */
-#define CAN_IT_FMP0                 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
-#define CAN_IT_FF0                  ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
-#define CAN_IT_FOV0                 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
-#define CAN_IT_FMP1                 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
-#define CAN_IT_FF1                  ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
-#define CAN_IT_FOV1                 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
-
-/* Operating Mode Interrupts */
-#define CAN_IT_WKU                  ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
-#define CAN_IT_SLK                  ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
-
-/* Error Interrupts */
-#define CAN_IT_EWG                  ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
-#define CAN_IT_EPV                  ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
-#define CAN_IT_BOF                  ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
-#define CAN_IT_LEC                  ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
-#define CAN_IT_ERR                  ((uint32_t)0x00008000) /*!< Error Interrupt*/
-
-/* Flags named as Interrupts : kept only for FW compatibility */
-#define CAN_IT_RQCP0   CAN_IT_TME
-#define CAN_IT_RQCP1   CAN_IT_TME
-#define CAN_IT_RQCP2   CAN_IT_TME
-
-
-#define IS_CAN_IT(IT)        (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0)  ||\
-                             ((IT) == CAN_IT_FF0)  || ((IT) == CAN_IT_FOV0)  ||\
-                             ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1)   ||\
-                             ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG)   ||\
-                             ((IT) == CAN_IT_EPV)  || ((IT) == CAN_IT_BOF)   ||\
-                             ((IT) == CAN_IT_LEC)  || ((IT) == CAN_IT_ERR)   ||\
-                             ((IT) == CAN_IT_WKU)  || ((IT) == CAN_IT_SLK))
-
-#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0)    ||\
-                             ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1)    ||\
-                             ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG)    ||\
-                             ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)    ||\
-                             ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR)    ||\
-                             ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/  
-
-/*  Function used to set the CAN configuration to the default reset state *****/ 
-void CAN_DeInit(CAN_TypeDef* CANx);
-
-/* Initialization and Configuration functions *********************************/ 
-uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
-#if defined(STM32F413_423xx)
-void CAN_FilterInit(CAN_TypeDef* CANx, CAN_FilterInitTypeDef* CAN_FilterInitStruct);
-#else
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
-#endif /* STM32F413_423xx */
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
-#if defined(STM32F413_423xx)
-void CAN_SlaveStartBank(CAN_TypeDef* CANx, uint8_t CAN_BankNumber);
-#else
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
-#endif /* STM32F413_423xx */
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
-void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
-
-/* CAN Frames Transmission functions ******************************************/
-uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
-uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
-void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
-
-/* CAN Frames Reception functions *********************************************/
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
-void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
-uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
-
-/* Operation modes functions **************************************************/
-uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
-uint8_t CAN_Sleep(CAN_TypeDef* CANx);
-uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
-
-/* CAN Bus Error management functions *****************************************/
-uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
-uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
-uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
-
-/* Interrupts and flags management functions **********************************/
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
-void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
-ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
-void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_CAN_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cec.h

@@ -1,301 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_cec.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the CEC firmware 
-  *          library, applicable only for STM32F466xx devices.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4XX_CEC_H
-#define __STM32F4XX_CEC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup CEC
-  * @{
-  */
-#if defined(STM32F446xx)
-/* Exported types ------------------------------------------------------------*/
-  
-/** 
-  * @brief CEC Init structure definition 
-  */
-typedef struct
-{
-  uint32_t CEC_SignalFreeTime;     /*!< Specifies the CEC Signal Free Time configuration.
-                                   This parameter can be a value of @ref CEC_Signal_Free_Time */
-  uint32_t CEC_RxTolerance;        /*!< Specifies the CEC Reception Tolerance.
-                                   This parameter can be a value of @ref CEC_RxTolerance */
-  uint32_t CEC_StopReception;      /*!< Specifies the CEC Stop Reception.
-                                   This parameter can be a value of @ref CEC_Stop_Reception */
-  uint32_t CEC_BitRisingError;     /*!< Specifies the CEC Bit Rising Error generation.
-                                   This parameter can be a value of @ref CEC_Bit_Rising_Error_Generation */
-  uint32_t CEC_LongBitPeriodError; /*!< Specifies the CEC Long Bit Error generation.
-                                   This parameter can be a value of @ref CEC_Long_Bit_Error_Generation */
-  uint32_t CEC_BRDNoGen;           /*!< Specifies the CEC Broadcast Error generation.
-                                   This parameter can be a value of @ref CEC_BDR_No_Gen */
-  uint32_t CEC_SFTOption;          /*!< Specifies the CEC Signal Free Time option.
-                                   This parameter can be a value of @ref CEC_SFT_Option */
-
-}CEC_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CEC_Exported_Constants
-  * @{
-  */
-
-/** @defgroup CEC_Signal_Free_Time
-  * @{
-  */
-#define CEC_SignalFreeTime_Standard     ((uint32_t)0x00000000) /*!< CEC Signal Free Time Standard         */
-#define CEC_SignalFreeTime_1T           ((uint32_t)0x00000001) /*!< CEC  1.5 nominal data bit periods     */
-#define CEC_SignalFreeTime_2T           ((uint32_t)0x00000002) /*!< CEC  2.5 nominal data bit periods     */
-#define CEC_SignalFreeTime_3T           ((uint32_t)0x00000003) /*!< CEC  3.5 nominal data bit periods     */
-#define CEC_SignalFreeTime_4T           ((uint32_t)0x00000004) /*!< CEC  4.5 nominal data bit periods     */
-#define CEC_SignalFreeTime_5T           ((uint32_t)0x00000005) /*!< CEC  5.5 nominal data bit periods     */
-#define CEC_SignalFreeTime_6T           ((uint32_t)0x00000006) /*!< CEC  6.5 nominal data bit periods     */
-#define CEC_SignalFreeTime_7T           ((uint32_t)0x00000007) /*!< CEC  7.5 nominal data bit periods     */
-
-#define IS_CEC_SIGNAL_FREE_TIME(TIME) (((TIME) == CEC_SignalFreeTime_Standard) || \
-                                       ((TIME) == CEC_SignalFreeTime_1T)|| \
-                                       ((TIME) == CEC_SignalFreeTime_2T)|| \
-                                       ((TIME) == CEC_SignalFreeTime_3T)|| \
-                                       ((TIME) == CEC_SignalFreeTime_4T)|| \
-                                       ((TIME) == CEC_SignalFreeTime_5T)|| \
-                                       ((TIME) == CEC_SignalFreeTime_6T)|| \
-                                       ((TIME) == CEC_SignalFreeTime_7T))
-/**
-  * @}
-  */
-
-/** @defgroup CEC_RxTolerance
-  * @{
-  */
-#define CEC_RxTolerance_Standard        ((uint32_t)0x00000000) /*!< Standard Tolerance Margin            */
-#define CEC_RxTolerance_Extended        CEC_CFGR_RXTOL         /*!< Extended Tolerance Margin            */
-
-#define IS_CEC_RX_TOLERANCE(TOLERANCE) (((TOLERANCE) == CEC_RxTolerance_Standard) || \
-                                        ((TOLERANCE) == CEC_RxTolerance_Extended))
-/**
-  * @}
-  */
-
-/** @defgroup CEC_Stop_Reception
-  * @{
-  */
-#define CEC_StopReception_Off           ((uint32_t)0x00000000) /*!< No RX Stop on bit Rising Error (BRE) */
-#define CEC_StopReception_On            CEC_CFGR_BRESTP        /*!< RX Stop on bit Rising Error (BRE)    */
-
-#define IS_CEC_STOP_RECEPTION(RECEPTION) (((RECEPTION) == CEC_StopReception_On) || \
-                                          ((RECEPTION) == CEC_StopReception_Off))
-/**
-  * @}
-  */
-
-/** @defgroup CEC_Bit_Rising_Error_Generation
-  * @{
-  */
-#define CEC_BitRisingError_Off          ((uint32_t)0x00000000) /*!< Bit Rising Error generation turned Off */
-#define CEC_BitRisingError_On           CEC_CFGR_BREGEN        /*!< Bit Rising Error generation turned On  */
-
-#define IS_CEC_BIT_RISING_ERROR(ERROR) (((ERROR) == CEC_BitRisingError_Off) || \
-                                        ((ERROR) == CEC_BitRisingError_On))
-/**
-  * @}
-  */
-
-/** @defgroup CEC_Long_Bit_Error_Generation
-  * @{
-  */
-#define CEC_LongBitPeriodError_Off      ((uint32_t)0x00000000)  /*!< Long Bit Period Error generation turned Off */
-#define CEC_LongBitPeriodError_On       CEC_CFGR_LREGEN         /*!< Long Bit Period Error generation turned On  */
-
-#define IS_CEC_LONG_BIT_PERIOD_ERROR(ERROR) (((ERROR) == CEC_LongBitPeriodError_Off) || \
-                                             ((ERROR) == CEC_LongBitPeriodError_On))
-/**
-  * @}
-  */
-
-/** @defgroup CEC_BDR_No_Gen
-  * @{
-  */
-
-#define CEC_BRDNoGen_Off      ((uint32_t)0x00000000)  /*!< Broadcast Bit Rising Error generation turned Off */
-#define CEC_BRDNoGen_On       CEC_CFGR_BRDNOGEN       /*!< Broadcast Bit Rising Error generation turned On  */
-
-#define IS_CEC_BDR_NO_GEN_ERROR(ERROR) (((ERROR) == CEC_BRDNoGen_Off) || \
-                                        ((ERROR) == CEC_BRDNoGen_On))
-/**
-  * @}
-  */
-
-/** @defgroup CEC_SFT_Option
-  * @{
-  */
-#define CEC_SFTOption_Off              ((uint32_t)0x00000000)  /*!< SFT option turned Off                   */
-#define CEC_SFTOption_On               CEC_CFGR_SFTOPT         /*!< SFT option turned On                    */
-
-#define IS_CEC_SFT_OPTION(OPTION) (((OPTION) == CEC_SFTOption_Off) || \
-                                  ((OPTION) == CEC_SFTOption_On))
-/**
-  * @}
-  */
-
-/** @defgroup CEC_Own_Address
-  * @{
-  */
-#define IS_CEC_ADDRESS(ADDRESS)         ((ADDRESS) < 0x10)
-
-/**
-  * @}
-  */
-
-/** @defgroup CEC_Interrupt_Configuration_definition
-  * @{
-  */
-#define CEC_IT_TXACKE                   CEC_IER_TXACKEIE
-#define CEC_IT_TXERR                    CEC_IER_TXERRIE
-#define CEC_IT_TXUDR                    CEC_IER_TXUDRIE
-#define CEC_IT_TXEND                    CEC_IER_TXENDIE
-#define CEC_IT_TXBR                     CEC_IER_TXBRIE
-#define CEC_IT_ARBLST                   CEC_IER_ARBLSTIE
-#define CEC_IT_RXACKE                   CEC_IER_RXACKEIE
-#define CEC_IT_LBPE                     CEC_IER_LBPEIE
-#define CEC_IT_SBPE                     CEC_IER_SBPEIE
-#define CEC_IT_BRE                      CEC_IER_BREIEIE
-#define CEC_IT_RXOVR                    CEC_IER_RXOVRIE
-#define CEC_IT_RXEND                    CEC_IER_RXENDIE
-#define CEC_IT_RXBR                     CEC_IER_RXBRIE
-
-#define IS_CEC_IT(IT) ((((IT) & (uint32_t)0xFFFFE000) == 0x00) && ((IT) != 0x00))
-
-#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TXACKE) || \
-                           ((IT) == CEC_IT_TXERR)|| \
-                           ((IT) == CEC_IT_TXUDR)|| \
-                           ((IT) == CEC_IT_TXEND)|| \
-                           ((IT) == CEC_IT_TXBR)|| \
-                           ((IT) == CEC_IT_ARBLST)|| \
-                           ((IT) == CEC_IT_RXACKE)|| \
-                           ((IT) == CEC_IT_LBPE)|| \
-                           ((IT) == CEC_IT_SBPE)|| \
-                           ((IT) == CEC_IT_BRE)|| \
-                           ((IT) == CEC_IT_RXOVR)|| \
-                           ((IT) == CEC_IT_RXEND)|| \
-                           ((IT) == CEC_IT_RXBR))
-/**
-  * @}
-  */
-
-/** @defgroup CEC_ISR_register_flags_definition
-  * @{
-  */
-#define CEC_FLAG_TXACKE                 CEC_ISR_TXACKE
-#define CEC_FLAG_TXERR                  CEC_ISR_TXERR
-#define CEC_FLAG_TXUDR                  CEC_ISR_TXUDR
-#define CEC_FLAG_TXEND                  CEC_ISR_TXEND
-#define CEC_FLAG_TXBR                   CEC_ISR_TXBR
-#define CEC_FLAG_ARBLST                 CEC_ISR_ARBLST
-#define CEC_FLAG_RXACKE                 CEC_ISR_RXACKE
-#define CEC_FLAG_LBPE                   CEC_ISR_LBPE
-#define CEC_FLAG_SBPE                   CEC_ISR_SBPE
-#define CEC_FLAG_BRE                    CEC_ISR_BRE
-#define CEC_FLAG_RXOVR                  CEC_ISR_RXOVR
-#define CEC_FLAG_RXEND                  CEC_ISR_RXEND
-#define CEC_FLAG_RXBR                   CEC_ISR_RXBR
-
-#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE000) == 0x00) && ((FLAG) != 0x00))
-
-#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_TXACKE) || \
-                               ((FLAG) == CEC_FLAG_TXERR)|| \
-                               ((FLAG) == CEC_FLAG_TXUDR)|| \
-                               ((FLAG) == CEC_FLAG_TXEND)|| \
-                               ((FLAG) == CEC_FLAG_TXBR)|| \
-                               ((FLAG) == CEC_FLAG_ARBLST)|| \
-                               ((FLAG) == CEC_FLAG_RXACKE)|| \
-                               ((FLAG) == CEC_FLAG_LBPE)|| \
-                               ((FLAG) == CEC_FLAG_SBPE)|| \
-                               ((FLAG) == CEC_FLAG_BRE)|| \
-                               ((FLAG) == CEC_FLAG_RXOVR)|| \
-                               ((FLAG) == CEC_FLAG_RXEND)|| \
-                               ((FLAG) == CEC_FLAG_RXBR))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/*  Function used to set the CEC configuration to the default reset state *****/
-void CEC_DeInit(void);
-
-/* CEC_Initialization and Configuration functions *****************************/
-void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
-void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct);
-void CEC_Cmd(FunctionalState NewState);
-void CEC_ListenModeCmd(FunctionalState NewState);
-void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
-void CEC_OwnAddressClear(void);
-
-/* CEC_Data transfers functions ***********************************************/
-void CEC_SendData(uint8_t Data);
-uint8_t CEC_ReceiveData(void);
-void CEC_StartOfMessage(void);
-void CEC_EndOfMessage(void);
-
-/* CEC_Interrupts and flags management functions ******************************/
-void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState);
-FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);
-void CEC_ClearFlag(uint32_t CEC_FLAG);
-ITStatus CEC_GetITStatus(uint16_t CEC_IT);
-void CEC_ClearITPendingBit(uint16_t CEC_IT);
-#endif /* STM32F446xx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_CEC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h

@@ -1,83 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_crc.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the CRC firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_CRC_H
-#define __STM32F4xx_CRC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup CRC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CRC_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/  
-
-void CRC_ResetDR(void);
-uint32_t CRC_CalcCRC(uint32_t Data);
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
-uint32_t CRC_GetCRC(void);
-void CRC_SetIDRegister(uint8_t IDValue);
-uint8_t CRC_GetIDRegister(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_CRC_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h

@@ -1,384 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_cryp.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the Cryptographic
-  *          processor(CRYP) firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_CRYP_H
-#define __STM32F4xx_CRYP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup CRYP
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief   CRYP Init structure definition  
-  */ 
-typedef struct
-{
-  uint32_t CRYP_AlgoDir;   /*!< Encrypt or Decrypt. This parameter can be a 
-                                value of @ref CRYP_Algorithm_Direction */
-  uint32_t CRYP_AlgoMode;  /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, 
-                                AES-CBC, AES-CTR, AES-Key, AES-GCM and AES-CCM.
-                                This parameter can be a value of @ref CRYP_Algorithm_Mode */
-  uint32_t CRYP_DataType;  /*!< 32-bit data, 16-bit data, bit data or bit string.
-                                This parameter can be a value of @ref CRYP_Data_Type */ 
-  uint32_t CRYP_KeySize;   /*!< Used only in AES mode only : 128, 192 or 256 bit 
-                                key length. This parameter can be a value of 
-                                @ref CRYP_Key_Size_for_AES_only */
-}CRYP_InitTypeDef;
-
-/** 
-  * @brief   CRYP Key(s) structure definition  
-  */ 
-typedef struct
-{
-  uint32_t CRYP_Key0Left;  /*!< Key 0 Left  */
-  uint32_t CRYP_Key0Right; /*!< Key 0 Right */
-  uint32_t CRYP_Key1Left;  /*!< Key 1 left  */
-  uint32_t CRYP_Key1Right; /*!< Key 1 Right */
-  uint32_t CRYP_Key2Left;  /*!< Key 2 left  */
-  uint32_t CRYP_Key2Right; /*!< Key 2 Right */
-  uint32_t CRYP_Key3Left;  /*!< Key 3 left  */
-  uint32_t CRYP_Key3Right; /*!< Key 3 Right */
-}CRYP_KeyInitTypeDef;
-/** 
-  * @brief   CRYP Initialization Vectors (IV) structure definition  
-  */ 
-typedef struct
-{
-  uint32_t CRYP_IV0Left;  /*!< Init Vector 0 Left  */
-  uint32_t CRYP_IV0Right; /*!< Init Vector 0 Right */
-  uint32_t CRYP_IV1Left;  /*!< Init Vector 1 left  */
-  uint32_t CRYP_IV1Right; /*!< Init Vector 1 Right */
-}CRYP_IVInitTypeDef;
-
-/** 
-  * @brief  CRYP context swapping structure definition  
-  */ 
-typedef struct
-{
-  /*!< Current Configuration */
-  uint32_t CR_CurrentConfig;
-  /*!< IV */
-  uint32_t CRYP_IV0LR;
-  uint32_t CRYP_IV0RR;
-  uint32_t CRYP_IV1LR;
-  uint32_t CRYP_IV1RR;
-  /*!< KEY */
-  uint32_t CRYP_K0LR;
-  uint32_t CRYP_K0RR;
-  uint32_t CRYP_K1LR;
-  uint32_t CRYP_K1RR;
-  uint32_t CRYP_K2LR;
-  uint32_t CRYP_K2RR;
-  uint32_t CRYP_K3LR;
-  uint32_t CRYP_K3RR;
-  uint32_t CRYP_CSGCMCCMR[8];
-  uint32_t CRYP_CSGCMR[8];
-}CRYP_Context;
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CRYP_Exported_Constants
-  * @{
-  */
-
-/** @defgroup CRYP_Algorithm_Direction 
-  * @{
-  */
-#define CRYP_AlgoDir_Encrypt      ((uint16_t)0x0000)
-#define CRYP_AlgoDir_Decrypt      ((uint16_t)0x0004)
-#define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \
-                                  ((ALGODIR) == CRYP_AlgoDir_Decrypt))
-
-/**
-  * @}
-  */ 
- 
-/** @defgroup CRYP_Algorithm_Mode 
-  * @{
-  */
-
-/*!< TDES Modes */
-#define CRYP_AlgoMode_TDES_ECB    ((uint32_t)0x00000000)
-#define CRYP_AlgoMode_TDES_CBC    ((uint32_t)0x00000008)
-
-/*!< DES Modes */
-#define CRYP_AlgoMode_DES_ECB     ((uint32_t)0x00000010)
-#define CRYP_AlgoMode_DES_CBC     ((uint32_t)0x00000018)
-
-/*!< AES Modes */
-#define CRYP_AlgoMode_AES_ECB     ((uint32_t)0x00000020)
-#define CRYP_AlgoMode_AES_CBC     ((uint32_t)0x00000028)
-#define CRYP_AlgoMode_AES_CTR     ((uint32_t)0x00000030)
-#define CRYP_AlgoMode_AES_Key     ((uint32_t)0x00000038)
-#define CRYP_AlgoMode_AES_GCM     ((uint32_t)0x00080000)
-#define CRYP_AlgoMode_AES_CCM     ((uint32_t)0x00080008)
-
-#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \
-                                   ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \
-                                   ((ALGOMODE) == CRYP_AlgoMode_DES_ECB) || \
-                                   ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \
-                                   ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \
-                                   ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \
-                                   ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \
-                                   ((ALGOMODE) == CRYP_AlgoMode_AES_Key) || \
-                                   ((ALGOMODE) == CRYP_AlgoMode_AES_GCM) || \
-                                   ((ALGOMODE) == CRYP_AlgoMode_AES_CCM))
-/**
-  * @}
-  */ 
-
-/** @defgroup CRYP_Phase 
-  * @{
-  */
-
-/*!< The phases are valid only for AES-GCM and AES-CCM modes */
-#define CRYP_Phase_Init           ((uint32_t)0x00000000)
-#define CRYP_Phase_Header         CRYP_CR_GCM_CCMPH_0
-#define CRYP_Phase_Payload        CRYP_CR_GCM_CCMPH_1
-#define CRYP_Phase_Final          CRYP_CR_GCM_CCMPH
-
-#define IS_CRYP_PHASE(PHASE) (((PHASE) == CRYP_Phase_Init)    || \
-                              ((PHASE) == CRYP_Phase_Header)  || \
-                              ((PHASE) == CRYP_Phase_Payload) || \
-                              ((PHASE) == CRYP_Phase_Final))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup CRYP_Data_Type 
-  * @{
-  */
-#define CRYP_DataType_32b         ((uint16_t)0x0000)
-#define CRYP_DataType_16b         ((uint16_t)0x0040)
-#define CRYP_DataType_8b          ((uint16_t)0x0080)
-#define CRYP_DataType_1b          ((uint16_t)0x00C0)
-#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \
-                                    ((DATATYPE) == CRYP_DataType_16b)|| \
-                                    ((DATATYPE) == CRYP_DataType_8b)|| \
-                                    ((DATATYPE) == CRYP_DataType_1b))  
-/**
-  * @}
-  */
-                                     
-/** @defgroup CRYP_Key_Size_for_AES_only 
-  * @{
-  */
-#define CRYP_KeySize_128b         ((uint16_t)0x0000)
-#define CRYP_KeySize_192b         ((uint16_t)0x0100)
-#define CRYP_KeySize_256b         ((uint16_t)0x0200)
-#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \
-                                  ((KEYSIZE) == CRYP_KeySize_192b)|| \
-                                  ((KEYSIZE) == CRYP_KeySize_256b))
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_flags_definition 
-  * @{
-  */
-#define CRYP_FLAG_BUSY            ((uint8_t)0x10)  /*!< The CRYP core is currently 
-                                                        processing a block of data 
-                                                        or a key preparation (for 
-                                                        AES decryption). */
-#define CRYP_FLAG_IFEM            ((uint8_t)0x01)  /*!< Input Fifo Empty */
-#define CRYP_FLAG_IFNF            ((uint8_t)0x02)  /*!< Input Fifo is Not Full */
-#define CRYP_FLAG_INRIS           ((uint8_t)0x22)  /*!< Raw interrupt pending */
-#define CRYP_FLAG_OFNE            ((uint8_t)0x04)  /*!< Input Fifo service raw 
-                                                        interrupt status */
-#define CRYP_FLAG_OFFU            ((uint8_t)0x08)  /*!< Output Fifo is Full */
-#define CRYP_FLAG_OUTRIS          ((uint8_t)0x21)  /*!< Output Fifo service raw 
-                                                        interrupt status */
-
-#define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM)  || \
-                                ((FLAG) == CRYP_FLAG_IFNF)  || \
-                                ((FLAG) == CRYP_FLAG_OFNE)  || \
-                                ((FLAG) == CRYP_FLAG_OFFU)  || \
-                                ((FLAG) == CRYP_FLAG_BUSY)  || \
-                                ((FLAG) == CRYP_FLAG_OUTRIS)|| \
-                                ((FLAG) == CRYP_FLAG_INRIS))
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_interrupts_definition 
-  * @{
-  */
-#define CRYP_IT_INI               ((uint8_t)0x01) /*!< IN Fifo Interrupt */
-#define CRYP_IT_OUTI              ((uint8_t)0x02) /*!< OUT Fifo Interrupt */
-#define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))
-#define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI))
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_Encryption_Decryption_modes_definition 
-  * @{
-  */
-#define MODE_ENCRYPT             ((uint8_t)0x01)
-#define MODE_DECRYPT             ((uint8_t)0x00)
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_DMA_transfer_requests 
-  * @{
-  */
-#define CRYP_DMAReq_DataIN             ((uint8_t)0x01)
-#define CRYP_DMAReq_DataOUT            ((uint8_t)0x02)
-#define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00))
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/*  Function used to set the CRYP configuration to the default reset state ****/
-void CRYP_DeInit(void);
-
-/* CRYP Initialization and Configuration functions ****************************/
-void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct);
-void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct);
-void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
-void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
-void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
-void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
-void CRYP_Cmd(FunctionalState NewState);
-void CRYP_PhaseConfig(uint32_t CRYP_Phase);
-void CRYP_FIFOFlush(void);
-/* CRYP Data processing functions *********************************************/
-void CRYP_DataIn(uint32_t Data);
-uint32_t CRYP_DataOut(void);
-
-/* CRYP Context swapping functions ********************************************/
-ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
-                             CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
-void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore);
-
-/* CRYP DMA interface function ************************************************/
-void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState);
-ITStatus CRYP_GetITStatus(uint8_t CRYP_IT);
-FunctionalState CRYP_GetCmdStatus(void);
-FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG);
-
-/* High Level AES functions **************************************************/
-ErrorStatus CRYP_AES_ECB(uint8_t Mode,
-                         uint8_t *Key, uint16_t Keysize,
-                         uint8_t *Input, uint32_t Ilength,
-                         uint8_t *Output);
-
-ErrorStatus CRYP_AES_CBC(uint8_t Mode,
-                         uint8_t InitVectors[16],
-                         uint8_t *Key, uint16_t Keysize,
-                         uint8_t *Input, uint32_t Ilength,
-                         uint8_t *Output);
-
-ErrorStatus CRYP_AES_CTR(uint8_t Mode,
-                         uint8_t InitVectors[16],
-                         uint8_t *Key, uint16_t Keysize,
-                         uint8_t *Input, uint32_t Ilength,
-                         uint8_t *Output);
-
-ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16],
-                         uint8_t *Key, uint16_t Keysize,
-                         uint8_t *Input, uint32_t ILength,
-                         uint8_t *Header, uint32_t HLength,
-                         uint8_t *Output, uint8_t *AuthTAG);
-
-ErrorStatus CRYP_AES_CCM(uint8_t Mode, 
-                         uint8_t* Nonce, uint32_t NonceSize,
-                         uint8_t* Key, uint16_t Keysize,
-                         uint8_t* Input, uint32_t ILength,
-                         uint8_t* Header, uint32_t HLength, uint8_t *HBuffer,
-                         uint8_t* Output,
-                         uint8_t* AuthTAG, uint32_t TAGSize);
-
-/* High Level TDES functions **************************************************/
-ErrorStatus CRYP_TDES_ECB(uint8_t Mode,
-                           uint8_t Key[24], 
-                           uint8_t *Input, uint32_t Ilength,
-                           uint8_t *Output);
-
-ErrorStatus CRYP_TDES_CBC(uint8_t Mode,
-                          uint8_t Key[24],
-                          uint8_t InitVectors[8],
-                          uint8_t *Input, uint32_t Ilength,
-                          uint8_t *Output);
-
-/* High Level DES functions **************************************************/
-ErrorStatus CRYP_DES_ECB(uint8_t Mode,
-                         uint8_t Key[8],
-                         uint8_t *Input, uint32_t Ilength,
-                         uint8_t *Output);
-
-ErrorStatus CRYP_DES_CBC(uint8_t Mode,
-                         uint8_t Key[8],
-                         uint8_t InitVectors[8],
-                         uint8_t *Input,uint32_t Ilength,
-                         uint8_t *Output);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_CRYP_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h

@@ -1,304 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_dac.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the DAC firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_DAC_H
-#define __STM32F4xx_DAC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup DAC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  DAC Init structure definition
-  */
-
-typedef struct
-{
-  uint32_t DAC_Trigger;                      /*!< Specifies the external trigger for the selected DAC channel.
-                                                  This parameter can be a value of @ref DAC_trigger_selection */
-
-  uint32_t DAC_WaveGeneration;               /*!< Specifies whether DAC channel noise waves or triangle waves
-                                                  are generated, or whether no wave is generated.
-                                                  This parameter can be a value of @ref DAC_wave_generation */
-
-  uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
-                                                  the maximum amplitude triangle generation for the DAC channel. 
-                                                  This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
-
-  uint32_t DAC_OutputBuffer;                 /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
-                                                  This parameter can be a value of @ref DAC_output_buffer */
-}DAC_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Constants
-  * @{
-  */
-
-/** @defgroup DAC_trigger_selection 
-  * @{
-  */
-
-#define DAC_Trigger_None                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
-                                                                       has been loaded, and not by external trigger */
-#define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T4_TRGO                ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T5_TRGO                ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T7_TRGO                ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_T8_TRGO                ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */                                                                       
-
-#define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_Trigger_Software               ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
-                                 ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
-                                 ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
-                                 ((TRIGGER) == DAC_Trigger_Software))
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_wave_generation 
-  * @{
-  */
-
-#define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
-#define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
-#define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
-#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
-                                    ((WAVE) == DAC_WaveGeneration_Noise) || \
-                                    ((WAVE) == DAC_WaveGeneration_Triangle))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_lfsrunmask_triangleamplitude
-  * @{
-  */
-
-#define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUnmask_Bits1_0             ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits2_0             ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits3_0             ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits4_0             ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits5_0             ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits6_0             ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits7_0             ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits8_0             ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits9_0             ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits10_0            ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits11_0            ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
-#define DAC_TriangleAmplitude_3            ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
-#define DAC_TriangleAmplitude_7            ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
-#define DAC_TriangleAmplitude_15           ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
-#define DAC_TriangleAmplitude_31           ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
-#define DAC_TriangleAmplitude_63           ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
-#define DAC_TriangleAmplitude_127          ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
-#define DAC_TriangleAmplitude_255          ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
-#define DAC_TriangleAmplitude_511          ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
-#define DAC_TriangleAmplitude_1023         ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TriangleAmplitude_2047         ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TriangleAmplitude_4095         ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
-
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
-                                                      ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_1) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_3) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_7) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_15) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_31) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_63) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_127) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_255) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_511) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_1023) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_2047) || \
-                                                      ((VALUE) == DAC_TriangleAmplitude_4095))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_output_buffer 
-  * @{
-  */
-
-#define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
-#define DAC_OutputBuffer_Disable           ((uint32_t)0x00000002)
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
-                                           ((STATE) == DAC_OutputBuffer_Disable))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Channel_selection 
-  * @{
-  */
-
-#define DAC_Channel_1                      ((uint32_t)0x00000000)
-#define DAC_Channel_2                      ((uint32_t)0x00000010)
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
-                                 ((CHANNEL) == DAC_Channel_2))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_data_alignement 
-  * @{
-  */
-
-#define DAC_Align_12b_R                    ((uint32_t)0x00000000)
-#define DAC_Align_12b_L                    ((uint32_t)0x00000004)
-#define DAC_Align_8b_R                     ((uint32_t)0x00000008)
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
-                             ((ALIGN) == DAC_Align_12b_L) || \
-                             ((ALIGN) == DAC_Align_8b_R))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_wave_generation 
-  * @{
-  */
-
-#define DAC_Wave_Noise                     ((uint32_t)0x00000040)
-#define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
-                           ((WAVE) == DAC_Wave_Triangle))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_data 
-  * @{
-  */
-
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) 
-/**
-  * @}
-  */
-  
-/** @defgroup DAC_interrupts_definition 
-  * @{
-  */   
-#define DAC_IT_DMAUDR                      ((uint32_t)0x00002000)  
-#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup DAC_flags_definition 
-  * @{
-  */ 
-  
-#define DAC_FLAG_DMAUDR                    ((uint32_t)0x00002000)  
-#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))  
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/  
-
-/*  Function used to set the DAC configuration to the default reset state *****/  
-void DAC_DeInit(void);
-
-/*  DAC channels configuration: trigger, output buffer, data format functions */
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
-
-/* DMA management functions ***************************************************/
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_DAC_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h

@@ -1,109 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_dbgmcu.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the DBGMCU firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_DBGMCU_H
-#define __STM32F4xx_DBGMCU_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup DBGMCU
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DBGMCU_Exported_Constants
-  * @{
-  */ 
-#define DBGMCU_SLEEP                 ((uint32_t)0x00000001)
-#define DBGMCU_STOP                  ((uint32_t)0x00000002)
-#define DBGMCU_STANDBY               ((uint32_t)0x00000004)
-#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
-
-#define DBGMCU_TIM2_STOP             ((uint32_t)0x00000001)
-#define DBGMCU_TIM3_STOP             ((uint32_t)0x00000002)
-#define DBGMCU_TIM4_STOP             ((uint32_t)0x00000004)
-#define DBGMCU_TIM5_STOP             ((uint32_t)0x00000008)
-#define DBGMCU_TIM6_STOP             ((uint32_t)0x00000010)
-#define DBGMCU_TIM7_STOP             ((uint32_t)0x00000020)
-#define DBGMCU_TIM12_STOP            ((uint32_t)0x00000040)
-#define DBGMCU_TIM13_STOP            ((uint32_t)0x00000080)
-#define DBGMCU_TIM14_STOP            ((uint32_t)0x00000100)
-#define DBGMCU_RTC_STOP              ((uint32_t)0x00000400)
-#define DBGMCU_WWDG_STOP             ((uint32_t)0x00000800)
-#define DBGMCU_IWDG_STOP             ((uint32_t)0x00001000)
-#define DBGMCU_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)
-#define DBGMCU_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00400000)
-#define DBGMCU_I2C3_SMBUS_TIMEOUT    ((uint32_t)0x00800000)
-#define DBGMCU_CAN1_STOP             ((uint32_t)0x02000000)
-#define DBGMCU_CAN2_STOP             ((uint32_t)0x04000000)
-#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00))
-
-#define DBGMCU_TIM1_STOP             ((uint32_t)0x00000001)
-#define DBGMCU_TIM8_STOP             ((uint32_t)0x00000002)
-#define DBGMCU_TIM9_STOP             ((uint32_t)0x00010000)
-#define DBGMCU_TIM10_STOP            ((uint32_t)0x00020000)
-#define DBGMCU_TIM11_STOP            ((uint32_t)0x00040000)
-#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00))
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/ 
-uint32_t DBGMCU_GetREVID(void);
-uint32_t DBGMCU_GetDEVID(void);
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
-void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
-void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_DBGMCU_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h

@@ -1,312 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_dcmi.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the DCMI firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_DCMI_H
-#define __STM32F4xx_DCMI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup DCMI
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** 
-  * @brief   DCMI Init structure definition  
-  */ 
-typedef struct
-{
-  uint16_t DCMI_CaptureMode;      /*!< Specifies the Capture Mode: Continuous or Snapshot.
-                                       This parameter can be a value of @ref DCMI_Capture_Mode */
-
-  uint16_t DCMI_SynchroMode;      /*!< Specifies the Synchronization Mode: Hardware or Embedded.
-                                       This parameter can be a value of @ref DCMI_Synchronization_Mode */
-
-  uint16_t DCMI_PCKPolarity;      /*!< Specifies the Pixel clock polarity: Falling or Rising.
-                                       This parameter can be a value of @ref DCMI_PIXCK_Polarity */
-
-  uint16_t DCMI_VSPolarity;       /*!< Specifies the Vertical synchronization polarity: High or Low.
-                                       This parameter can be a value of @ref DCMI_VSYNC_Polarity */
-
-  uint16_t DCMI_HSPolarity;       /*!< Specifies the Horizontal synchronization polarity: High or Low.
-                                       This parameter can be a value of @ref DCMI_HSYNC_Polarity */
-
-  uint16_t DCMI_CaptureRate;      /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
-                                       This parameter can be a value of @ref DCMI_Capture_Rate */
-
-  uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
-                                       This parameter can be a value of @ref DCMI_Extended_Data_Mode */
-} DCMI_InitTypeDef;
-
-/** 
-  * @brief   DCMI CROP Init structure definition  
-  */ 
-typedef struct
-{
-  uint16_t DCMI_VerticalStartLine;      /*!< Specifies the Vertical start line count from which the image capture
-                                             will start. This parameter can be a value between 0x00 and 0x1FFF */
-
-  uint16_t DCMI_HorizontalOffsetCount;  /*!< Specifies the number of pixel clocks to count before starting a capture.
-                                             This parameter can be a value between 0x00 and 0x3FFF */
-
-  uint16_t DCMI_VerticalLineCount;      /*!< Specifies the number of lines to be captured from the starting point.
-                                             This parameter can be a value between 0x00 and 0x3FFF */
-
-  uint16_t DCMI_CaptureCount;           /*!< Specifies the number of pixel clocks to be captured from the starting
-                                             point on the same line.
-                                             This parameter can be a value between 0x00 and 0x3FFF */
-} DCMI_CROPInitTypeDef;
-
-/** 
-  * @brief   DCMI Embedded Synchronisation CODE Init structure definition  
-  */ 
-typedef struct
-{
-  uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
-  uint8_t DCMI_LineStartCode;  /*!< Specifies the code of the line start delimiter. */
-  uint8_t DCMI_LineEndCode;    /*!< Specifies the code of the line end delimiter. */
-  uint8_t DCMI_FrameEndCode;   /*!< Specifies the code of the frame end delimiter. */
-} DCMI_CodesInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DCMI_Exported_Constants
-  * @{
-  */
-
-/** @defgroup DCMI_Capture_Mode 
-  * @{
-  */ 
-#define DCMI_CaptureMode_Continuous    ((uint16_t)0x0000) /*!< The received data are transferred continuously 
-                                                               into the destination memory through the DMA */
-#define DCMI_CaptureMode_SnapShot      ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of 
-                                                               frame and then transfers a single frame through the DMA */
-#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \
-                                   ((MODE) == DCMI_CaptureMode_SnapShot))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DCMI_Synchronization_Mode
-  * @{
-  */ 
-#define DCMI_SynchroMode_Hardware    ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop)
-                                                             is synchronized with the HSYNC/VSYNC signals */
-#define DCMI_SynchroMode_Embedded    ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with 
-                                                             synchronization codes embedded in the data flow */
-#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \
-                              ((MODE) == DCMI_SynchroMode_Embedded))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DCMI_PIXCK_Polarity 
-  * @{
-  */ 
-#define DCMI_PCKPolarity_Falling    ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */
-#define DCMI_PCKPolarity_Rising     ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */
-#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \
-                                      ((POLARITY) == DCMI_PCKPolarity_Rising))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DCMI_VSYNC_Polarity 
-  * @{
-  */ 
-#define DCMI_VSPolarity_Low     ((uint16_t)0x0000) /*!< Vertical synchronization active Low */
-#define DCMI_VSPolarity_High    ((uint16_t)0x0080) /*!< Vertical synchronization active High */
-#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \
-                                     ((POLARITY) == DCMI_VSPolarity_High))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DCMI_HSYNC_Polarity 
-  * @{
-  */ 
-#define DCMI_HSPolarity_Low     ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */
-#define DCMI_HSPolarity_High    ((uint16_t)0x0040) /*!< Horizontal synchronization active High */
-#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \
-                                     ((POLARITY) == DCMI_HSPolarity_High))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DCMI_Capture_Rate 
-  * @{
-  */ 
-#define DCMI_CaptureRate_All_Frame     ((uint16_t)0x0000) /*!< All frames are captured */
-#define DCMI_CaptureRate_1of2_Frame    ((uint16_t)0x0100) /*!< Every alternate frame captured */
-#define DCMI_CaptureRate_1of4_Frame    ((uint16_t)0x0200) /*!< One frame in 4 frames captured */
-#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \
-                                    ((RATE) == DCMI_CaptureRate_1of2_Frame) ||\
-                                    ((RATE) == DCMI_CaptureRate_1of4_Frame))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DCMI_Extended_Data_Mode 
-  * @{
-  */ 
-#define DCMI_ExtendedDataMode_8b     ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */
-#define DCMI_ExtendedDataMode_10b    ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */
-#define DCMI_ExtendedDataMode_12b    ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */
-#define DCMI_ExtendedDataMode_14b    ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */
-#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \
-                                    ((DATA) == DCMI_ExtendedDataMode_10b) ||\
-                                    ((DATA) == DCMI_ExtendedDataMode_12b) ||\
-                                    ((DATA) == DCMI_ExtendedDataMode_14b))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DCMI_interrupt_sources 
-  * @{
-  */ 
-#define DCMI_IT_FRAME    ((uint16_t)0x0001)
-#define DCMI_IT_OVF      ((uint16_t)0x0002)
-#define DCMI_IT_ERR      ((uint16_t)0x0004)
-#define DCMI_IT_VSYNC    ((uint16_t)0x0008)
-#define DCMI_IT_LINE     ((uint16_t)0x0010)
-#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000))
-#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \
-                            ((IT) == DCMI_IT_OVF) || \
-                            ((IT) == DCMI_IT_ERR) || \
-                            ((IT) == DCMI_IT_VSYNC) || \
-                            ((IT) == DCMI_IT_LINE))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DCMI_Flags 
-  * @{
-  */ 
-/** 
-  * @brief   DCMI SR register  
-  */ 
-#define DCMI_FLAG_HSYNC     ((uint16_t)0x2001)
-#define DCMI_FLAG_VSYNC     ((uint16_t)0x2002)
-#define DCMI_FLAG_FNE       ((uint16_t)0x2004)
-/** 
-  * @brief   DCMI RISR register  
-  */ 
-#define DCMI_FLAG_FRAMERI    ((uint16_t)0x0001)
-#define DCMI_FLAG_OVFRI      ((uint16_t)0x0002)
-#define DCMI_FLAG_ERRRI      ((uint16_t)0x0004)
-#define DCMI_FLAG_VSYNCRI    ((uint16_t)0x0008)
-#define DCMI_FLAG_LINERI     ((uint16_t)0x0010)
-/** 
-  * @brief   DCMI MISR register  
-  */ 
-#define DCMI_FLAG_FRAMEMI    ((uint16_t)0x1001)
-#define DCMI_FLAG_OVFMI      ((uint16_t)0x1002)
-#define DCMI_FLAG_ERRMI      ((uint16_t)0x1004)
-#define DCMI_FLAG_VSYNCMI    ((uint16_t)0x1008)
-#define DCMI_FLAG_LINEMI     ((uint16_t)0x1010)
-#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \
-                                ((FLAG) == DCMI_FLAG_VSYNC) || \
-                                ((FLAG) == DCMI_FLAG_FNE) || \
-                                ((FLAG) == DCMI_FLAG_FRAMERI) || \
-                                ((FLAG) == DCMI_FLAG_OVFRI) || \
-                                ((FLAG) == DCMI_FLAG_ERRRI) || \
-                                ((FLAG) == DCMI_FLAG_VSYNCRI) || \
-                                ((FLAG) == DCMI_FLAG_LINERI) || \
-                                ((FLAG) == DCMI_FLAG_FRAMEMI) || \
-                                ((FLAG) == DCMI_FLAG_OVFMI) || \
-                                ((FLAG) == DCMI_FLAG_ERRMI) || \
-                                ((FLAG) == DCMI_FLAG_VSYNCMI) || \
-                                ((FLAG) == DCMI_FLAG_LINEMI))
-                                
-#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000))
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/ 
-
-/*  Function used to set the DCMI configuration to the default reset state ****/ 
-void DCMI_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct);
-void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct);
-void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct);
-void DCMI_CROPCmd(FunctionalState NewState);
-void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct);
-void DCMI_JPEGCmd(FunctionalState NewState);
-
-/* Image capture functions ****************************************************/
-void DCMI_Cmd(FunctionalState NewState);
-void DCMI_CaptureCmd(FunctionalState NewState);
-uint32_t DCMI_ReadData(void);
-
-/* Interrupts and flags management functions **********************************/
-void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState);
-FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG);
-void DCMI_ClearFlag(uint16_t DCMI_FLAG);
-ITStatus DCMI_GetITStatus(uint16_t DCMI_IT);
-void DCMI_ClearITPendingBit(uint16_t DCMI_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_DCMI_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dfsdm.h

@@ -1,829 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_dfsdm.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the DFSDM
-  *          firmware library
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software
-  * distributed under the License is distributed on an "AS IS" BASIS,
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4XX_DFSDM_H
-#define __STM32F4XX_DFSDM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup DFSDM
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  DFSDM Transceiver init structure definition
-  */
-typedef struct
-{
-  uint32_t DFSDM_Interface;                 /*!< Selects the serial interface type and input clock phase.
-                                            This parameter can be a value of @ref DFSDM_Interface_Selection */
-
-  uint32_t DFSDM_Clock;                     /*!< Specifies the clock source for the serial interface transceiver.
-                                            This parameter can be a value of @ref DFSDM_Clock_Selection */
-
-  uint32_t DFSDM_Input;                     /*!< Specifies the Input mode for the serial interface transceiver.
-                                            This parameter can be a value of @ref DFSDM_Input_Selection */
-
-  uint32_t DFSDM_Redirection;               /*!< Specifies if the channel input is redirected from channel channel (y+1).
-                                            This parameter can be a value of @ref DFSDM_Redirection_Selection */
-
-  uint32_t DFSDM_PackingMode;               /*!< Specifies the packing mode for the serial interface transceiver.
-                                            This parameter can be a value of @ref DFSDM_Pack_Selection */
-
-  uint32_t DFSDM_DataRightShift;            /*!< Defines the final data right bit shift.
-                                            This parameter can be a value between 0 and 31 */
-
-  uint32_t DFSDM_Offset;                    /*!< Sets the calibration offset.
-                                            This parameter can be a value between 0 and 0xFFFFFF */
-
-  uint32_t DFSDM_CLKAbsenceDetector;        /*!< Enables or disables the Clock Absence Detector.
-                                            This parameter can be a value of @ref DFSDM_Clock_Absence_Detector_state */
-
-  uint32_t DFSDM_ShortCircuitDetector;      /*!< Enables or disables the Short Circuit Detector.
-                                            This parameter can be a value of @ref DFSDM_Short_Circuit_Detector_state */
-}DFSDM_TransceiverInitTypeDef;
-
-/** 
-  * @brief  DFSDM filter analog parameters structure definition  
-  */
-typedef struct
-{
-  uint32_t DFSDM_SincOrder;                  /*!< Sets the Sinc Filter Order .
-                                             This parameter can be a value of @ref DFSDM_Sinc_Order */
-
-  uint32_t DFSDM_FilterOversamplingRatio;    /*!< Sets the Sinc Filter Oversampling Ratio.
-                                             This parameter can be a value between 1 and 1024 */
-
-  uint32_t DFSDM_IntegratorOversamplingRatio;/*!< Sets the Integrator Oversampling Ratio.
-                                             This parameter can be a value between 1 and 256 */
-}DFSDM_FilterInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DFSDM_Interface_Selection
-  * @{
-  */
-#define DFSDM_Interface_SPI_RisingEdge   ((uint32_t)0x00000000)  /*!<  DFSDM SPI interface with rising edge to strobe data */
-#define DFSDM_Interface_SPI_FallingEdge  ((uint32_t)0x00000001)  /*!<  DFSDM SPI interface with falling edge to strobe data */
-#define DFSDM_Interface_Manchester1      ((uint32_t)0x00000002)  /*!<  DFSDM Manchester coded input, rising edge = logic 0, falling edge = logic 1 */
-#define DFSDM_Interface_Manchester2      ((uint32_t)0x00000003)  /*!<  DFSDM Manchester coded input, rising edge = logic 1, falling edge = logic 0 */
-
-#define IS_DFSDM_INTERFACE(INTERFACE)    (((INTERFACE) == DFSDM_Interface_SPI_RisingEdge) || \
-                                         ((INTERFACE) == DFSDM_Interface_SPI_FallingEdge) || \
-                                         ((INTERFACE) == DFSDM_Interface_Manchester1)     || \
-                                         ((INTERFACE) == DFSDM_Interface_Manchester2))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Clock_Selection
-  * @{
-  */
-#define DFSDM_Clock_External             ((uint32_t)0x00000000)  /*!<  DFSDM clock coming from external DFSDM_CKINy input */
-#define DFSDM_Clock_Internal             ((uint32_t)0x00000004)  /*!<  DFSDM clock coming from internal DFSDM_CKOUT output */
-#define DFSDM_Clock_InternalDiv2_Mode1   ((uint32_t)0x00000008)  /*!<  DFSDM clock coming from internal DFSDM_CKOUT output divided by 2
-                                                                       and clock change is on every rising edge of DFSDM_CKOUT output signal */
-#define DFSDM_Clock_InternalDiv2_Mode2   ((uint32_t)0x0000000C)  /*!<  DFSDM clock coming from internal DFSDM_CKOUT output divided by 2
-                                                                       and clock change is on every falling edge of DFSDM_CKOUT output signal */
-
-#define IS_DFSDM_CLOCK(CLOCK)            (((CLOCK) == DFSDM_Clock_External)          || \
-                                         ((CLOCK) == DFSDM_Clock_Internal)           || \
-                                         ((CLOCK) == DFSDM_Clock_InternalDiv2_Mode1) || \
-                                         ((CLOCK) == DFSDM_Clock_InternalDiv2_Mode2))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Input_Selection
-  * @{
-  */
-#define DFSDM_Input_External     ((uint32_t)0x00000000)  /*!<  DFSDM clock coming from external DFSDM_CKINy input */
-#define DFSDM_Input_ADC          ((uint32_t)0x00001000)  /*!<  DFSDM clock coming from internal DFSDM_CKOUT output */
-#define DFSDM_Input_Internal     ((uint32_t)0x00002000)  /*!<  DFSDM clock coming from internal DFSDM_CKOUT output divided by 2
-                                                               and clock change is on every rising edge of DFSDM_CKOUT output signal */
-
-#define IS_DFSDM_Input_MODE(INPUT)      (((INPUT) == DFSDM_Input_External) || \
-                                         ((INPUT) == DFSDM_Input_ADC)      || \
-                                         ((INPUT) == DFSDM_Input_Internal))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Redirection_Selection
-  * @{
-  */
-#define DFSDM_Redirection_Disabled       ((uint32_t)0x00000000)  /*!< DFSDM Channel serial inputs are taken from pins of the same channel y */
-#define DFSDM_Redirection_Enabled         DFSDM_CHCFGR1_CHINSEL  /*!< DFSDM Channel serial inputs are taken from pins of the channel (y+1) modulo 8 */
-
-#define IS_DFSDM_Redirection_STATE(STATE)      (((STATE) == DFSDM_Redirection_Disabled) || \
-                                                ((STATE) == DFSDM_Redirection_Enabled))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Pack_Selection
-  * @{
-  */
-#define DFSDM_PackingMode_Standard     ((uint32_t)0x00000000)  /*!<  DFSDM Input data in DFSDM_CHDATINyR register are stored only in INDAT0[15:0] */
-#define DFSDM_PackingMode_Interleaved  ((uint32_t)0x00004000)  /*!<  DFSDM Input data in DFSDM_CHDATINyR register are stored as two samples:
-                                                                        - first sample in INDAT0[15:0] - assigned to channel y
-                                                                        - second sample INDAT1[15:0]   - assigned to channel y */
-#define DFSDM_PackingMode_Dual         ((uint32_t)0x00008000)  /*!<  DFSDM Input data in DFSDM_CHDATINyR register are stored as two samples:
-                                                                        - first sample INDAT0[15:0]    - assigned to channel y
-                                                                        - second sample INDAT1[15:0]   - assigned to channel (y+1) */
-
-#define IS_DFSDM_PACK_MODE(MODE)        (((MODE) == DFSDM_PackingMode_Standard)    || \
-                                         ((MODE) == DFSDM_PackingMode_Interleaved) || \
-                                         ((MODE) == DFSDM_PackingMode_Dual))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Clock_Absence_Detector_state
-  * @{
-  */
-#define DFSDM_CLKAbsenceDetector_Enable     DFSDM_CHCFGR1_CKABEN    /*!<  DFSDM Clock Absence Detector is Enabled */
-#define DFSDM_CLKAbsenceDetector_Disable    ((uint32_t)0x00000000)  /*!<  DFSDM Clock Absence Detector is Disabled */
-
-#define IS_DFSDM_CLK_DETECTOR_STATE(STATE)  (((STATE) == DFSDM_CLKAbsenceDetector_Enable) || \
-                                             ((STATE) == DFSDM_CLKAbsenceDetector_Disable))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Short_Circuit_Detector_state
-  * @{
-  */
-#define DFSDM_ShortCircuitDetector_Enable   DFSDM_CHCFGR1_SCDEN     /*!<  DFSDM Short Circuit Detector is Enabled */
-#define DFSDM_ShortCircuitDetector_Disable  ((uint32_t)0x00000000)  /*!<  DFSDM Short Circuit Detector is Disabled */
-
-#define IS_DFSDM_SC_DETECTOR_STATE(STATE)  (((STATE) == DFSDM_ShortCircuitDetector_Enable) || \
-                                            ((STATE) == DFSDM_ShortCircuitDetector_Disable))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Sinc_Order
-  * @{
-  */
-#define DFSDM_SincOrder_FastSinc        ((uint32_t)0x00000000)  /*!<  DFSDM Sinc filter order = Fast sinc */
-#define DFSDM_SincOrder_Sinc1           ((uint32_t)0x20000000)  /*!<  DFSDM Sinc filter order = 1 */
-#define DFSDM_SincOrder_Sinc2           ((uint32_t)0x40000000)  /*!<  DFSDM Sinc filter order = 2 */
-#define DFSDM_SincOrder_Sinc3           ((uint32_t)0x60000000)  /*!<  DFSDM Sinc filter order = 3 */
-#define DFSDM_SincOrder_Sinc4           ((uint32_t)0x80000000)  /*!<  DFSDM Sinc filter order = 4 */
-#define DFSDM_SincOrder_Sinc5           ((uint32_t)0xA0000000)  /*!<  DFSDM Sinc filter order = 5 */
-
-#define IS_DFSDM_SINC_ORDER(ORDER)        (((ORDER) == DFSDM_SincOrder_FastSinc) || \
-                                          ((ORDER) == DFSDM_SincOrder_Sinc1)     || \
-                                          ((ORDER) == DFSDM_SincOrder_Sinc2)     || \
-                                          ((ORDER) == DFSDM_SincOrder_Sinc3)     || \
-                                          ((ORDER) == DFSDM_SincOrder_Sinc4)     || \
-                                          ((ORDER) == DFSDM_SincOrder_Sinc5))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Break_Signal_Assignment
-  * @{
-  */
-#define DFSDM_SCDBreak_0                 ((uint32_t)0x00001000)  /*!<  DFSDM Break 0 signal assigned to short circuit detector */
-#define DFSDM_SCDBreak_1                 ((uint32_t)0x00002000)  /*!<  DFSDM Break 1 signal assigned to short circuit detector */
-#define DFSDM_SCDBreak_2                 ((uint32_t)0x00004000)  /*!<  DFSDM Break 2 signal assigned to short circuit detector */
-#define DFSDM_SCDBreak_3                 ((uint32_t)0x00008000)  /*!<  DFSDM Break 3 signal assigned to short circuit detector */
-
-#define IS_DFSDM_SCD_BREAK_SIGNAL(RANK)    (((RANK) == DFSDM_SCDBreak_0) || \
-                                           ((RANK) == DFSDM_SCDBreak_1)  || \
-                                           ((RANK) == DFSDM_SCDBreak_2)  || \
-                                           ((RANK) == DFSDM_SCDBreak_3))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_AWD_Sinc_Order
-  * @{
-  */
-#define DFSDM_AWDSincOrder_Fast            ((uint32_t)0x00000000)  /*!<  DFSDM Fast sinc filter */
-#define DFSDM_AWDSincOrder_Sinc1           ((uint32_t)0x00400000)  /*!<  DFSDM sinc1 filter */
-#define DFSDM_AWDSincOrder_Sinc2           ((uint32_t)0x00800000)  /*!<  DFSDM sinc2 filter */
-#define DFSDM_AWDSincOrder_Sinc3           ((uint32_t)0x00C00000)  /*!<  DFSDM sinc3 filter */
-
-#define IS_DFSDM_AWD_SINC_ORDER(ORDER)    (((ORDER) == DFSDM_AWDSincOrder_Fast)  || \
-                                           ((ORDER) == DFSDM_AWDSincOrder_Sinc1) || \
-                                           ((ORDER) == DFSDM_AWDSincOrder_Sinc2) || \
-                                           ((ORDER) == DFSDM_AWDSincOrder_Sinc3))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_AWD_CHANNEL
-  * @{
-  */
-#define DFSDM_AWDChannel0               ((uint32_t)0x00010000)  /*!<  DFSDM AWDx guard channel 0 */
-#define DFSDM_AWDChannel1               ((uint32_t)0x00020000)  /*!<  DFSDM AWDx guard channel 1 */
-#define DFSDM_AWDChannel2               ((uint32_t)0x00040000)  /*!<  DFSDM AWDx guard channel 2 */
-#define DFSDM_AWDChannel3               ((uint32_t)0x00080000)  /*!<  DFSDM AWDx guard channel 3 */
-#define DFSDM_AWDChannel4               ((uint32_t)0x00100000)  /*!<  DFSDM AWDx guard channel 4 */
-#define DFSDM_AWDChannel5               ((uint32_t)0x00200000)  /*!<  DFSDM AWDx guard channel 5 */
-#define DFSDM_AWDChannel6               ((uint32_t)0x00400000)  /*!<  DFSDM AWDx guard channel 6 */
-#define DFSDM_AWDChannel7               ((uint32_t)0x00800000)  /*!<  DFSDM AWDx guard channel 7 */
-
-#define IS_DFSDM_AWD_CHANNEL(CHANNEL)    (((CHANNEL) == DFSDM_AWDChannel0) || \
-                                          ((CHANNEL) == DFSDM_AWDChannel1) || \
-                                          ((CHANNEL) == DFSDM_AWDChannel2) || \
-                                          ((CHANNEL) == DFSDM_AWDChannel3) || \
-                                          ((CHANNEL) == DFSDM_AWDChannel4) || \
-                                          ((CHANNEL) == DFSDM_AWDChannel5) || \
-                                          ((CHANNEL) == DFSDM_AWDChannel6) || \
-                                          ((CHANNEL) == DFSDM_AWDChannel7))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Threshold_Selection
-  * @{
-  */
-#define DFSDM_Threshold_Low               ((uint8_t)0x00)  /*!<  DFSDM Low threshold */
-#define DFSDM_Threshold_High              ((uint8_t)0x08)  /*!<  DFSDM High threshold */
-
-#define IS_DFSDM_Threshold(THR)          (((THR) == DFSDM_Threshold_Low) || \
-                                          ((THR) == DFSDM_Threshold_High))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_AWD_Fast_Mode_Selection
-  * @{
-  */
-#define DFSDM_AWDFastMode_Disable         ((uint32_t)0x00000000)  /*!<  DFSDM Fast mode for AWD is disabled */
-#define DFSDM_AWDFastMode_Enable          ((uint32_t)0x40000000)  /*!<  DFSDM Fast mode for AWD is enabled */
-
-#define IS_DFSDM_AWD_MODE(MODE)          (((MODE) == DFSDM_AWDFastMode_Disable) || \
-                                          ((MODE) == DFSDM_AWDFastMode_Enable))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Clock_Output_Source_Selection
-  * @{
-  */
-#define DFSDM_ClkOutSource_SysClock        ((uint32_t)0x00000000)  /*!<  DFSDM Source for output clock is comming from system clock */
-#define DFSDM_ClkOutSource_AudioClock      DFSDM_CHCFGR1_CKOUTSRC  /*!<  DFSDM Source for output clock is comming from audio clock */
-
-#define IS_DFSDM_CLOCK_OUT_SOURCE(SRC)    (((SRC) == DFSDM_ClkOutSource_SysClock) || \
-                                           ((SRC) == DFSDM_ClkOutSource_AudioClock))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Conversion_Mode
-  * @{
-  */
-#define DFSDM_DMAConversionMode_Regular     ((uint32_t)0x00000010)  /*!<  DFSDM Regular mode */
-#define DFSDM_DMAConversionMode_Injected    ((uint32_t)0x00000000)  /*!<  DFSDM Injected mode */
-
-#define IS_DFSDM_CONVERSION_MODE(MODE)    (((MODE) == DFSDM_DMAConversionMode_Regular) || \
-                                           ((MODE) == DFSDM_DMAConversionMode_Injected))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Extremes_Channel_Selection
-  * @{
-  */
-#define DFSDM_ExtremChannel0              ((uint32_t)0x00000100)  /*!<  DFSDM Extreme detector guard channel 0 */
-#define DFSDM_ExtremChannel1              ((uint32_t)0x00000200)  /*!<  DFSDM Extreme detector guard channel 1 */
-#define DFSDM_ExtremChannel2              ((uint32_t)0x00000400)  /*!<  DFSDM Extreme detector guard channel 2 */
-#define DFSDM_ExtremChannel3              ((uint32_t)0x00000800)  /*!<  DFSDM Extreme detector guard channel 3 */
-#define DFSDM_ExtremChannel4              ((uint32_t)0x00001000)  /*!<  DFSDM Extreme detector guard channel 4 */
-#define DFSDM_ExtremChannel5              ((uint32_t)0x00002000)  /*!<  DFSDM Extreme detector guard channel 5 */
-#define DFSDM_ExtremChannel6              ((uint32_t)0x00004000)  /*!<  DFSDM Extreme detector guard channel 6 */
-#define DFSDM_ExtremChannel7              ((uint32_t)0x00008000)  /*!<  DFSDM Extreme detector guard channel 7 */
-
-#define IS_DFSDM_EXTREM_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_ExtremChannel0) || \
-                                          ((CHANNEL) == DFSDM_ExtremChannel1) || \
-                                          ((CHANNEL) == DFSDM_ExtremChannel2) || \
-                                          ((CHANNEL) == DFSDM_ExtremChannel3) || \
-                                          ((CHANNEL) == DFSDM_ExtremChannel4) || \
-                                          ((CHANNEL) == DFSDM_ExtremChannel5) || \
-                                          ((CHANNEL) == DFSDM_ExtremChannel6) || \
-                                          ((CHANNEL) == DFSDM_ExtremChannel7))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Injected_Channel_Selection
-  * @{
-  */
-#define DFSDM_InjectedChannel0            ((uint32_t)0x00000001)  /*!<  DFSDM channel 0 is selected as injected channel */
-#define DFSDM_InjectedChannel1            ((uint32_t)0x00000002)  /*!<  DFSDM channel 1 is selected as injected channel */
-#define DFSDM_InjectedChannel2            ((uint32_t)0x00000004)  /*!<  DFSDM channel 2 is selected as injected channel */
-#define DFSDM_InjectedChannel3            ((uint32_t)0x00000008)  /*!<  DFSDM channel 3 is selected as injected channel */
-#define DFSDM_InjectedChannel4            ((uint32_t)0x00000010)  /*!<  DFSDM channel 4 is selected as injected channel */
-#define DFSDM_InjectedChannel5            ((uint32_t)0x00000020)  /*!<  DFSDM channel 5 is selected as injected channel */
-#define DFSDM_InjectedChannel6            ((uint32_t)0x00000040)  /*!<  DFSDM channel 6 is selected as injected channel */
-#define DFSDM_InjectedChannel7            ((uint32_t)0x00000080)  /*!<  DFSDM channel 7 is selected as injected channel */
-
-#define IS_DFSDM_INJECT_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_InjectedChannel0) || \
-                                          ((CHANNEL) == DFSDM_InjectedChannel1) || \
-                                          ((CHANNEL) == DFSDM_InjectedChannel2) || \
-                                          ((CHANNEL) == DFSDM_InjectedChannel3) || \
-                                          ((CHANNEL) == DFSDM_InjectedChannel4) || \
-                                          ((CHANNEL) == DFSDM_InjectedChannel5) || \
-                                          ((CHANNEL) == DFSDM_InjectedChannel6) || \
-                                          ((CHANNEL) == DFSDM_InjectedChannel7))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Regular_Channel_Selection
-  * @{
-  */
-#define DFSDM_RegularChannel0             ((uint32_t)0x00000000)  /*!<  DFSDM channel 0 is selected as regular channel */
-#define DFSDM_RegularChannel1             ((uint32_t)0x01000000)  /*!<  DFSDM channel 1 is selected as regular channel */
-#define DFSDM_RegularChannel2             ((uint32_t)0x02000000)  /*!<  DFSDM channel 2 is selected as regular channel */
-#define DFSDM_RegularChannel3             ((uint32_t)0x03000000)  /*!<  DFSDM channel 3 is selected as regular channel */
-#define DFSDM_RegularChannel4             ((uint32_t)0x04000000)  /*!<  DFSDM channel 4 is selected as regular channel */
-#define DFSDM_RegularChannel5             ((uint32_t)0x05000000)  /*!<  DFSDM channel 5 is selected as regular channel */
-#define DFSDM_RegularChannel6             ((uint32_t)0x06000000)  /*!<  DFSDM channel 6 is selected as regular channel */
-#define DFSDM_RegularChannel7             ((uint32_t)0x07000000)  /*!<  DFSDM channel 7 is selected as regular channel */
-
-#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_RegularChannel0) || \
-                                           ((CHANNEL) == DFSDM_RegularChannel1) || \
-                                           ((CHANNEL) == DFSDM_RegularChannel2) || \
-                                           ((CHANNEL) == DFSDM_RegularChannel3) || \
-                                           ((CHANNEL) == DFSDM_RegularChannel4) || \
-                                           ((CHANNEL) == DFSDM_RegularChannel5) || \
-                                           ((CHANNEL) == DFSDM_RegularChannel6) || \
-                                           ((CHANNEL) == DFSDM_RegularChannel7))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Injected_Trigger_signal
-  * @{
-  */
-#define DFSDM_Trigger_TIM1_TRGO          ((uint32_t)0x00000000)  /*!<  DFSDM Internal trigger 0 */
-#define DFSDM_Trigger_TIM1_TRGO2         ((uint32_t)0x00000100)  /*!<  DFSDM Internal trigger 1 */
-#define DFSDM_Trigger_TIM8_TRGO          ((uint32_t)0x00000200)  /*!<  DFSDM Internal trigger 2 */
-#define DFSDM_Trigger_TIM8_TRGO2         ((uint32_t)0x00000300)  /*!<  DFSDM Internal trigger 3 */
-#define DFSDM_Trigger_TIM3_TRGO          ((uint32_t)0x00000300)  /*!<  DFSDM Internal trigger 4 */
-#define DFSDM_Trigger_TIM4_TRGO          ((uint32_t)0x00000400)  /*!<  DFSDM Internal trigger 5 */
-#define DFSDM_Trigger_TIM16_OC1          ((uint32_t)0x00000400)  /*!<  DFSDM Internal trigger 6 */
-#define DFSDM_Trigger_TIM6_TRGO          ((uint32_t)0x00000500)  /*!<  DFSDM Internal trigger 7 */
-#define DFSDM_Trigger_TIM7_TRGO          ((uint32_t)0x00000500)  /*!<  DFSDM Internal trigger 8 */
-#define DFSDM_Trigger_EXTI11             ((uint32_t)0x00000600)  /*!<  DFSDM External trigger 0 */
-#define DFSDM_Trigger_EXTI15             ((uint32_t)0x00000700)  /*!<  DFSDM External trigger 1 */
-
-#define IS_DFSDM0_INJ_TRIGGER(TRIG)      (((TRIG) == DFSDM_Trigger_TIM1_TRGO)  || \
-                                          ((TRIG) == DFSDM_Trigger_TIM1_TRGO2) || \
-                                          ((TRIG) == DFSDM_Trigger_TIM8_TRGO)  || \
-                                          ((TRIG) == DFSDM_Trigger_TIM8_TRGO2) || \
-                                          ((TRIG) == DFSDM_Trigger_TIM4_TRGO)  || \
-                                          ((TRIG) == DFSDM_Trigger_TIM6_TRGO)  || \
-                                          ((TRIG) == DFSDM_Trigger_TIM7_TRGO)  || \
-                                          ((TRIG) == DFSDM_Trigger_EXTI15)     || \
-                                          ((TRIG) == DFSDM_Trigger_TIM3_TRGO)  || \
-                                          ((TRIG) == DFSDM_Trigger_TIM16_OC1)  || \
-                                          ((TRIG) == DFSDM_Trigger_EXTI11))  
-
-#define IS_DFSDM1_INJ_TRIGGER(TRIG)      IS_DFSDM0_INJ_TRIGGER(TRIG)
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Trigger_Edge_selection
-  * @{
-  */
-#define DFSDM_TriggerEdge_Disabled        ((uint32_t)0x00000000)  /*!<  DFSDM Trigger detection disabled */
-#define DFSDM_TriggerEdge_Rising          ((uint32_t)0x00002000)  /*!<  DFSDM Each rising edge makes a request to launch an injected conversion */
-#define DFSDM_TriggerEdge_Falling         ((uint32_t)0x00004000)  /*!<  DFSDM Each falling edge makes a request to launch an injected conversion */
-#define DFSDM_TriggerEdge_BothEdges       ((uint32_t)0x00006000)  /*!<  DFSDM Both edges make a request to launch an injected conversion */
-
-#define IS_DFSDM_TRIGGER_EDGE(EDGE)      (((EDGE) == DFSDM_TriggerEdge_Disabled) || \
-                                          ((EDGE) == DFSDM_TriggerEdge_Rising) || \
-                                          ((EDGE) == DFSDM_TriggerEdge_Falling) || \
-                                          ((EDGE) == DFSDM_TriggerEdge_BothEdges))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Injected_Conversion_Mode_Selection
-  * @{
-  */
-#define DFSDM_InjectConvMode_Single        ((uint32_t)0x00000000)  /*!<  DFSDM Trigger detection disabled */
-#define DFSDM_InjectConvMode_Scan          ((uint32_t)0x00000010)  /*!<  DFSDM Each rising edge makes a request to launch an injected conversion */
-
-#define IS_DFSDM_INJ_CONV_MODE(MODE)      (((MODE) == DFSDM_InjectConvMode_Single) || \
-                                           ((MODE) == DFSDM_InjectConvMode_Scan))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Interrupts_Definition
-  * @{
-  */
-#define DFSDM_IT_JEOC                            DFSDM_FLTCR2_JEOCIE
-#define DFSDM_IT_REOC                            DFSDM_FLTCR2_REOCIE
-#define DFSDM_IT_JOVR                            DFSDM_FLTCR2_JOVRIE
-#define DFSDM_IT_ROVR                            DFSDM_FLTCR2_ROVRIE
-#define DFSDM_IT_AWD                             DFSDM_FLTCR2_AWDIE
-#define DFSDM_IT_SCD                             DFSDM_FLTCR2_SCDIE
-#define DFSDM_IT_CKAB                            DFSDM_FLTCR2_CKABIE
-
-#define IS_DFSDM_IT(IT)                         (((IT) == DFSDM_IT_JEOC) || \
-                                                 ((IT) == DFSDM_IT_REOC) || \
-                                                 ((IT) == DFSDM_IT_JOVR) || \
-                                                 ((IT) == DFSDM_IT_ROVR) || \
-                                                 ((IT) == DFSDM_IT_AWD)  || \
-                                                 ((IT) == DFSDM_IT_SCD)  || \
-                                                 ((IT) == DFSDM_IT_CKAB))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Flag_Definition
-  * @{
-  */
-#define DFSDM_FLAG_JEOC                          DFSDM_FLTISR_JEOCF
-#define DFSDM_FLAG_REOC                          DFSDM_FLTISR_REOCF
-#define DFSDM_FLAG_JOVR                          DFSDM_FLTISR_JOVRF
-#define DFSDM_FLAG_ROVR                          DFSDM_FLTISR_ROVRF
-#define DFSDM_FLAG_AWD                           DFSDM_FLTISR_AWDF
-#define DFSDM_FLAG_JCIP                          DFSDM_FLTISR_JCIP
-#define DFSDM_FLAG_RCIP                          DFSDM_FLTISR_RCIP
-
-#define IS_DFSDM_FLAG(FLAG)                     (((FLAG) == DFSDM_FLAG_JEOC) || \
-                                                 ((FLAG) == DFSDM_FLAG_REOC) || \
-                                                 ((FLAG) == DFSDM_FLAG_JOVR) || \
-                                                 ((FLAG) == DFSDM_FLAG_ROVR) || \
-                                                 ((FLAG) == DFSDM_FLAG_AWD)  || \
-                                                 ((FLAG) == DFSDM_FLAG_JCIP) || \
-                                                 ((FLAG) == DFSDM_FLAG_RCIP))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Clock_Absence_Flag_Definition
-  * @{
-  */
-#define DFSDM_FLAG_CLKAbsence_Channel0           ((uint32_t)0x00010000)
-#define DFSDM_FLAG_CLKAbsence_Channel1           ((uint32_t)0x00020000)
-#define DFSDM_FLAG_CLKAbsence_Channel2           ((uint32_t)0x00040000)
-#define DFSDM_FLAG_CLKAbsence_Channel3           ((uint32_t)0x00080000)
-#define DFSDM_FLAG_CLKAbsence_Channel4           ((uint32_t)0x00100000)
-#define DFSDM_FLAG_CLKAbsence_Channel5           ((uint32_t)0x00200000)
-#define DFSDM_FLAG_CLKAbsence_Channel6           ((uint32_t)0x00400000)
-#define DFSDM_FLAG_CLKAbsence_Channel7           ((uint32_t)0x00800000)
-
-#define IS_DFSDM_CLK_ABS_FLAG(FLAG)             (((FLAG) == DFSDM_FLAG_CLKAbsence_Channel0) || \
-                                                 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel1) || \
-                                                 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel2) || \
-                                                 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel3) || \
-                                                 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel4) || \
-                                                 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel5) || \
-                                                 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel6) || \
-                                                 ((FLAG) == DFSDM_FLAG_CLKAbsence_Channel7))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_SCD_Flag_Definition
-  * @{
-  */
-#define DFSDM_FLAG_SCD_Channel0                  ((uint32_t)0x01000000)
-#define DFSDM_FLAG_SCD_Channel1                  ((uint32_t)0x02000000)
-#define DFSDM_FLAG_SCD_Channel2                  ((uint32_t)0x04000000)
-#define DFSDM_FLAG_SCD_Channel3                  ((uint32_t)0x08000000)
-#define DFSDM_FLAG_SCD_Channel4                  ((uint32_t)0x10000000)
-#define DFSDM_FLAG_SCD_Channel5                  ((uint32_t)0x20000000)
-#define DFSDM_FLAG_SCD_Channel6                  ((uint32_t)0x40000000)
-#define DFSDM_FLAG_SCD_Channel7                  ((uint32_t)0x80000000)
-
-#define IS_DFSDM_SCD_FLAG(FLAG)                 (((FLAG) == DFSDM_FLAG_SCD_Channel0) || \
-                                                 ((FLAG) == DFSDM_FLAG_SCD_Channel1) || \
-                                                 ((FLAG) == DFSDM_FLAG_SCD_Channel2) || \
-                                                 ((FLAG) == DFSDM_FLAG_SCD_Channel3) || \
-                                                 ((FLAG) == DFSDM_FLAG_SCD_Channel4) || \
-                                                 ((FLAG) == DFSDM_FLAG_SCD_Channel5) || \
-                                                 ((FLAG) == DFSDM_FLAG_SCD_Channel6) || \
-                                                 ((FLAG) == DFSDM_FLAG_SCD_Channel7))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Clear_Flag_Definition
-  * @{
-  */
-#define DFSDM_CLEARF_JOVR                          DFSDM_FLTICR_CLRJOVRF
-#define DFSDM_CLEARF_ROVR                          DFSDM_FLTICR_CLRROVRF
-
-#define IS_DFSDM_CLEAR_FLAG(FLAG)                (((FLAG) == DFSDM_CLEARF_JOVR) || \
-                                                  ((FLAG) == DFSDM_CLEARF_ROVR))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Clear_ClockAbs_Flag_Definition
-  * @{
-  */
-#define DFSDM_CLEARF_CLKAbsence_Channel0           ((uint32_t)0x00010000)
-#define DFSDM_CLEARF_CLKAbsence_Channel1           ((uint32_t)0x00020000)
-#define DFSDM_CLEARF_CLKAbsence_Channel2           ((uint32_t)0x00040000)
-#define DFSDM_CLEARF_CLKAbsence_Channel3           ((uint32_t)0x00080000)
-#define DFSDM_CLEARF_CLKAbsence_Channel4           ((uint32_t)0x00100000)
-#define DFSDM_CLEARF_CLKAbsence_Channel5           ((uint32_t)0x00200000)
-#define DFSDM_CLEARF_CLKAbsence_Channel6           ((uint32_t)0x00400000)
-#define DFSDM_CLEARF_CLKAbsence_Channel7           ((uint32_t)0x00800000)
-
-#define IS_DFSDM_CLK_ABS_CLEARF(FLAG)           (((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel0) || \
-                                                 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel1) || \
-                                                 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel2) || \
-                                                 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel3) || \
-                                                 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel4) || \
-                                                 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel5) || \
-                                                 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel6) || \
-                                                 ((FLAG) == DFSDM_CLEARF_CLKAbsence_Channel7))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Clear_Short_Circuit_Flag_Definition
-  * @{
-  */
-#define DFSDM_CLEARF_SCD_Channel0           ((uint32_t)0x01000000)
-#define DFSDM_CLEARF_SCD_Channel1           ((uint32_t)0x02000000)
-#define DFSDM_CLEARF_SCD_Channel2           ((uint32_t)0x04000000)
-#define DFSDM_CLEARF_SCD_Channel3           ((uint32_t)0x08000000)
-#define DFSDM_CLEARF_SCD_Channel4           ((uint32_t)0x10000000)
-#define DFSDM_CLEARF_SCD_Channel5           ((uint32_t)0x20000000)
-#define DFSDM_CLEARF_SCD_Channel6           ((uint32_t)0x40000000)
-#define DFSDM_CLEARF_SCD_Channel7           ((uint32_t)0x80000000)
-
-#define IS_DFSDM_SCD_CHANNEL_FLAG(FLAG)         (((FLAG) == DFSDM_CLEARF_SCD_Channel0) || \
-                                                 ((FLAG) == DFSDM_CLEARF_SCD_Channel1) || \
-                                                 ((FLAG) == DFSDM_CLEARF_SCD_Channel2) || \
-                                                 ((FLAG) == DFSDM_CLEARF_SCD_Channel3) || \
-                                                 ((FLAG) == DFSDM_CLEARF_SCD_Channel4) || \
-                                                 ((FLAG) == DFSDM_CLEARF_SCD_Channel5) || \
-                                                 ((FLAG) == DFSDM_CLEARF_SCD_Channel6) || \
-                                                 ((FLAG) == DFSDM_CLEARF_SCD_Channel7))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_Clock_Absence_Interrupt_Definition
-  * @{
-  */
-#define DFSDM_IT_CLKAbsence_Channel0           ((uint32_t)0x00010000)
-#define DFSDM_IT_CLKAbsence_Channel1           ((uint32_t)0x00020000)
-#define DFSDM_IT_CLKAbsence_Channel2           ((uint32_t)0x00040000)
-#define DFSDM_IT_CLKAbsence_Channel3           ((uint32_t)0x00080000)
-#define DFSDM_IT_CLKAbsence_Channel4           ((uint32_t)0x00100000)
-#define DFSDM_IT_CLKAbsence_Channel5           ((uint32_t)0x00200000)
-#define DFSDM_IT_CLKAbsence_Channel6           ((uint32_t)0x00400000)
-#define DFSDM_IT_CLKAbsence_Channel7           ((uint32_t)0x00800000)
-
-#define IS_DFSDM_CLK_ABS_IT(IT)               (((IT) == DFSDM_IT_CLKAbsence_Channel0) || \
-                                               ((IT) == DFSDM_IT_CLKAbsence_Channel1) || \
-                                               ((IT) == DFSDM_IT_CLKAbsence_Channel2) || \
-                                               ((IT) == DFSDM_IT_CLKAbsence_Channel3) || \
-                                               ((IT) == DFSDM_IT_CLKAbsence_Channel4) || \
-                                               ((IT) == DFSDM_IT_CLKAbsence_Channel5) || \
-                                               ((IT) == DFSDM_IT_CLKAbsence_Channel6) || \
-                                               ((IT) == DFSDM_IT_CLKAbsence_Channel7))
-/**
-  * @}
-  */
-
-/** @defgroup DFSDM_SCD_Interrupt_Definition
-  * @{
-  */
-#define DFSDM_IT_SCD_Channel0                  ((uint32_t)0x01000000)
-#define DFSDM_IT_SCD_Channel1                  ((uint32_t)0x02000000)
-#define DFSDM_IT_SCD_Channel2                  ((uint32_t)0x04000000)
-#define DFSDM_IT_SCD_Channel3                  ((uint32_t)0x08000000)
-#define DFSDM_IT_SCD_Channel4                  ((uint32_t)0x10000000)
-#define DFSDM_IT_SCD_Channel5                  ((uint32_t)0x20000000)
-#define DFSDM_IT_SCD_Channel6                  ((uint32_t)0x40000000)
-#define DFSDM_IT_SCD_Channel7                  ((uint32_t)0x80000000)
-
-#define IS_DFSDM_SCD_IT(IT)                   (((IT) == DFSDM_IT_SCD_Channel0) || \
-                                               ((IT) == DFSDM_IT_SCD_Channel1) || \
-                                               ((IT) == DFSDM_IT_SCD_Channel2) || \
-                                               ((IT) == DFSDM_IT_SCD_Channel3) || \
-                                               ((IT) == DFSDM_IT_SCD_Channel4) || \
-                                               ((IT) == DFSDM_IT_SCD_Channel5) || \
-                                               ((IT) == DFSDM_IT_SCD_Channel6) || \
-                                               ((IT) == DFSDM_IT_SCD_Channel7))
-/**
-  * @}
-  */
-
-#define IS_DFSDM_DATA_RIGHT_BIT_SHIFT(SHIFT)  ((SHIFT) < 0x20 )
-
-#define IS_DFSDM_OFFSET(OFFSET)               ((OFFSET) < 0x01000000 )
-
-#if defined(STM32F413_423xx)
-#define IS_DFSDM_ALL_CHANNEL(CHANNEL)   (((CHANNEL) == DFSDM1_Channel0) || \
-                                         ((CHANNEL) == DFSDM1_Channel1) || \
-                                         ((CHANNEL) == DFSDM1_Channel2) || \
-                                         ((CHANNEL) == DFSDM1_Channel3) || \
-                                         ((CHANNEL) == DFSDM2_Channel0) || \
-                                         ((CHANNEL) == DFSDM2_Channel1) || \
-                                         ((CHANNEL) == DFSDM2_Channel2) || \
-                                         ((CHANNEL) == DFSDM2_Channel3) || \
-                                         ((CHANNEL) == DFSDM2_Channel4) || \
-                                         ((CHANNEL) == DFSDM2_Channel5) || \
-                                         ((CHANNEL) == DFSDM2_Channel6) || \
-                                         ((CHANNEL) == DFSDM2_Channel7))
-
-#define IS_DFSDM_ALL_FILTER(FILTER)     (((FILTER) == DFSDM1_0) || \
-                                         ((FILTER) == DFSDM1_1) || \
-                                         ((FILTER) == DFSDM2_0) || \
-                                         ((FILTER) == DFSDM2_1) || \
-                                         ((FILTER) == DFSDM2_2) || \
-                                         ((FILTER) == DFSDM2_3))
-
-#define IS_DFSDM_SYNC_FILTER(FILTER)    (((FILTER) == DFSDM1_0) || \
-                                         ((FILTER) == DFSDM1_1) || \
-                                         ((FILTER) == DFSDM2_0) || \
-                                         ((FILTER) == DFSDM2_1) || \
-                                         ((FILTER) == DFSDM2_2) || \
-                                         ((FILTER) == DFSDM2_3))
-#else
-#define IS_DFSDM_ALL_CHANNEL(CHANNEL)   (((CHANNEL) == DFSDM1_Channel0) || \
-                                         ((CHANNEL) == DFSDM1_Channel1) || \
-                                         ((CHANNEL) == DFSDM1_Channel2) || \
-                                         ((CHANNEL) == DFSDM1_Channel3))
-
-#define IS_DFSDM_ALL_FILTER(FILTER)     (((FILTER) == DFSDM1_0) || \
-                                         ((FILTER) == DFSDM1_1))
-
-#define IS_DFSDM_SYNC_FILTER(FILTER)    (((FILTER) == DFSDM1_0) || \
-                                         ((FILTER) == DFSDM1_1))
-#endif /* STM32F413_423xx */
-
-
-
-
-#define IS_DFSDM_SINC_OVRSMPL_RATIO(RATIO)  (((RATIO) < 0x401) && ((RATIO) >= 0x001))
-
-#define IS_DFSDM_INTG_OVRSMPL_RATIO(RATIO)  (((RATIO) < 0x101 ) && ((RATIO) >= 0x001))
-
-#define IS_DFSDM_CLOCK_OUT_DIVIDER(DIVIDER) ((DIVIDER) < 0x101 )
-
-#define IS_DFSDM_CSD_THRESHOLD_VALUE(VALUE) ((VALUE) < 256)
-
-#define IS_DFSDM_AWD_OVRSMPL_RATIO(RATIO)   ((RATIO) < 33) && ((RATIO) >= 0x001)
-
-#define IS_DFSDM_HIGH_THRESHOLD(VALUE)      ((VALUE) < 0x1000000)
-#define IS_DFSDM_LOW_THRESHOLD(VALUE)       ((VALUE) < 0x1000000)
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Initialization functions ***************************************************/
-void DFSDM_DeInit(void);
-void DFSDM_TransceiverInit(DFSDM_Channel_TypeDef* DFSDM_Channelx, DFSDM_TransceiverInitTypeDef* DFSDM_TransceiverInitStruct);
-void DFSDM_TransceiverStructInit(DFSDM_TransceiverInitTypeDef* DFSDM_TransceiverInitStruct);
-void DFSDM_FilterInit(DFSDM_Filter_TypeDef* DFSDMx, DFSDM_FilterInitTypeDef* DFSDM_FilterInitStruct);
-void DFSDM_FilterStructInit(DFSDM_FilterInitTypeDef* DFSDM_FilterInitStruct);
-
-/* Configuration functions ****************************************************/
-#if defined(STM32F412xG)
-void DFSDM_Command(FunctionalState NewState);
-#else /* STM32F413_423xx */
-void DFSDM_Cmd(uint32_t Instance, FunctionalState NewState);
-#endif /* STM32F412xG */
-void DFSDM_ChannelCmd(DFSDM_Channel_TypeDef* DFSDM_Channelx, FunctionalState NewState);
-void DFSDM_FilterCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState);
-#if defined(STM32F412xG)
-void DFSDM_ConfigClkOutputDivider(uint32_t DFSDM_ClkOutDivision);
-void DFSDM_ConfigClkOutputSource(uint32_t DFSDM_ClkOutSource);
-#else
-void DFSDM_ConfigClkOutputDivider(uint32_t Instance, uint32_t DFSDM_ClkOutDivision);
-void DFSDM_ConfigClkOutputSource(uint32_t Instance, uint32_t DFSDM_ClkOutSource);
-#endif /* STM32F412xG */
-void DFSDM_SelectInjectedConversionMode(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_InjectConvMode);
-void DFSDM_SelectInjectedChannel(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_InjectedChannelx);
-void DFSDM_SelectRegularChannel(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_RegularChannelx);
-void DFSDM_StartSoftwareInjectedConversion(DFSDM_Filter_TypeDef* DFSDMx);
-void DFSDM_StartSoftwareRegularConversion(DFSDM_Filter_TypeDef* DFSDMx);
-void DFSDM_SynchronousFilter0InjectedStart(DFSDM_Filter_TypeDef* DFSDMx);
-void DFSDM_SynchronousFilter0RegularStart(DFSDM_Filter_TypeDef* DFSDMx);
-void DFSDM_RegularContinuousModeCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState);
-void DFSDM_InjectedContinuousModeCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState);
-void DFSDM_FastModeCmd(DFSDM_Filter_TypeDef* DFSDMx, FunctionalState NewState);
-void DFSDM_ConfigInjectedTrigger(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_Trigger, uint32_t DFSDM_TriggerEdge);
-void DFSDM_ConfigBRKShortCircuitDetector(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDBreak_i, FunctionalState NewState);
-void DFSDM_ConfigBRKAnalogWatchDog(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDBreak_i, FunctionalState NewState);
-void DFSDM_ConfigShortCircuitThreshold(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_SCDThreshold);
-void DFSDM_ConfigAnalogWatchdog(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint32_t DFSDM_AWDFastMode);
-void DFSDM_ConfigAWDFilter(DFSDM_Channel_TypeDef* DFSDM_Channelx, uint32_t DFSDM_AWDSincOrder, uint32_t DFSDM_AWDSincOverSampleRatio);
-uint32_t DFSDM_GetAWDConversionValue(DFSDM_Channel_TypeDef* DFSDM_Channelx);
-void DFSDM_SetAWDThreshold(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_HighThreshold, uint32_t DFSDM_LowThreshold);
-void DFSDM_SelectExtremesDetectorChannel(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_ExtremChannelx);
-int32_t DFSDM_GetRegularConversionData(DFSDM_Filter_TypeDef* DFSDMx);
-int32_t DFSDM_GetInjectedConversionData(DFSDM_Filter_TypeDef* DFSDMx);
-int32_t DFSDM_GetMaxValue(DFSDM_Filter_TypeDef* DFSDMx);
-int32_t DFSDM_GetMinValue(DFSDM_Filter_TypeDef* DFSDMx);
-int32_t DFSDM_GetMaxValueChannel(DFSDM_Filter_TypeDef* DFSDMx);
-int32_t DFSDM_GetMinValueChannel(DFSDM_Filter_TypeDef* DFSDMx);
-uint32_t DFSDM_GetConversionTime(DFSDM_Filter_TypeDef* DFSDMx);
-void DFSDM_DMATransferConfig(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_DMAConversionMode, FunctionalState NewState);
-/* Interrupts and flags management functions **********************************/
-void DFSDM_ITConfig(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_IT, FunctionalState NewState);
-#if defined(STM32F412xG)
-void DFSDM_ITClockAbsenceCmd(FunctionalState NewState);
-void DFSDM_ITShortCircuitDetectorCmd(FunctionalState NewState);
-#else /* STM32F413_423xx */
-void DFSDM_ITClockAbsenceCmd(uint32_t Instance, FunctionalState NewState);
-void DFSDM_ITShortCircuitDetectorCmd(uint32_t Instance, FunctionalState NewState);
-#endif /* STM32F412xG */
-
-FlagStatus DFSDM_GetFlagStatus(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_FLAG);
-#if defined(STM32F412xG)
-FlagStatus DFSDM_GetClockAbsenceFlagStatus(uint32_t DFSDM_FLAG_CLKAbsence);
-FlagStatus DFSDM_GetShortCircuitFlagStatus(uint32_t DFSDM_FLAG_SCD);
-#else /* STM32F413_423xx */
-FlagStatus DFSDM_GetClockAbsenceFlagStatus(uint32_t Instance, uint32_t DFSDM_FLAG_CLKAbsence);
-FlagStatus DFSDM_GetShortCircuitFlagStatus(uint32_t Instance, uint32_t DFSDM_FLAG_SCD);
-#endif /* STM32F412xG */
-FlagStatus DFSDM_GetWatchdogFlagStatus(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint8_t DFSDM_Threshold);
-
-void DFSDM_ClearFlag(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_CLEARF);
-#if defined(STM32F412xG)
-void DFSDM_ClearClockAbsenceFlag(uint32_t DFSDM_CLEARF_CLKAbsence);
-void DFSDM_ClearShortCircuitFlag(uint32_t DFSDM_CLEARF_SCD);
-#else /* STM32F413_423xx */
-void DFSDM_ClearClockAbsenceFlag(uint32_t Instance, uint32_t DFSDM_CLEARF_CLKAbsence);
-void DFSDM_ClearShortCircuitFlag(uint32_t Instance, uint32_t DFSDM_CLEARF_SCD);
-#endif /* STM32F412xG */
-void DFSDM_ClearAnalogWatchdogFlag(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_AWDChannelx, uint8_t DFSDM_Threshold);
-
-ITStatus DFSDM_GetITStatus(DFSDM_Filter_TypeDef* DFSDMx, uint32_t DFSDM_IT);
-#if defined(STM32F412xG)
-ITStatus DFSDM_GetClockAbsenceITStatus(uint32_t DFSDM_IT_CLKAbsence);
-ITStatus DFSDM_GetShortCircuitITStatus(uint32_t DFSDM_IT_SCR);
-#else /* STM32F413_423xx */
-ITStatus DFSDM_GetClockAbsenceITStatus(uint32_t Instance, uint32_t DFSDM_IT_CLKAbsence);
-ITStatus DFSDM_GetShortCircuitITStatus(uint32_t Instance, uint32_t DFSDM_IT_SCR);
-#endif /* STM32F412xG */
-
-#endif /* STM32F412xG || STM32F413_423xx */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4XX_DFSDM_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h

@@ -1,609 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_dma.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the DMA firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************  
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_DMA_H
-#define __STM32F4xx_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup DMA
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  DMA Init structure definition
-  */
-
-typedef struct
-{
-  uint32_t DMA_Channel;            /*!< Specifies the channel used for the specified stream. 
-                                        This parameter can be a value of @ref DMA_channel */
- 
-  uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */
-
-  uint32_t DMA_Memory0BaseAddr;    /*!< Specifies the memory 0 base address for DMAy Streamx. 
-                                        This memory is the default memory used when double buffer mode is
-                                        not enabled. */
-
-  uint32_t DMA_DIR;                /*!< Specifies if the data will be transferred from memory to peripheral, 
-                                        from memory to memory or from peripheral to memory.
-                                        This parameter can be a value of @ref DMA_data_transfer_direction */
-
-  uint32_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Stream. 
-                                        The data unit is equal to the configuration set in DMA_PeripheralDataSize
-                                        or DMA_MemoryDataSize members depending in the transfer direction. */
-
-  uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register should be incremented or not.
-                                        This parameter can be a value of @ref DMA_peripheral_incremented_mode */
-
-  uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register should be incremented or not.
-                                        This parameter can be a value of @ref DMA_memory_incremented_mode */
-
-  uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
-                                        This parameter can be a value of @ref DMA_peripheral_data_size */
-
-  uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
-                                        This parameter can be a value of @ref DMA_memory_data_size */
-
-  uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Streamx.
-                                        This parameter can be a value of @ref DMA_circular_normal_mode
-                                        @note The circular buffer mode cannot be used if the memory-to-memory
-                                              data transfer is configured on the selected Stream */
-
-  uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Streamx.
-                                        This parameter can be a value of @ref DMA_priority_level */
-
-  uint32_t DMA_FIFOMode;          /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream.
-                                        This parameter can be a value of @ref DMA_fifo_direct_mode
-                                        @note The Direct mode (FIFO mode disabled) cannot be used if the 
-                                               memory-to-memory data transfer is configured on the selected Stream */
-
-  uint32_t DMA_FIFOThreshold;      /*!< Specifies the FIFO threshold level.
-                                        This parameter can be a value of @ref DMA_fifo_threshold_level */
-
-  uint32_t DMA_MemoryBurst;        /*!< Specifies the Burst transfer configuration for the memory transfers. 
-                                        It specifies the amount of data to be transferred in a single non interruptable 
-                                        transaction. This parameter can be a value of @ref DMA_memory_burst 
-                                        @note The burst mode is possible only if the address Increment mode is enabled. */
-
-  uint32_t DMA_PeripheralBurst;    /*!< Specifies the Burst transfer configuration for the peripheral transfers. 
-                                        It specifies the amount of data to be transferred in a single non interruptable 
-                                        transaction. This parameter can be a value of @ref DMA_peripheral_burst
-                                        @note The burst mode is possible only if the address Increment mode is enabled. */  
-}DMA_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants
-  * @{
-  */
-
-#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \
-                                   ((PERIPH) == DMA1_Stream1) || \
-                                   ((PERIPH) == DMA1_Stream2) || \
-                                   ((PERIPH) == DMA1_Stream3) || \
-                                   ((PERIPH) == DMA1_Stream4) || \
-                                   ((PERIPH) == DMA1_Stream5) || \
-                                   ((PERIPH) == DMA1_Stream6) || \
-                                   ((PERIPH) == DMA1_Stream7) || \
-                                   ((PERIPH) == DMA2_Stream0) || \
-                                   ((PERIPH) == DMA2_Stream1) || \
-                                   ((PERIPH) == DMA2_Stream2) || \
-                                   ((PERIPH) == DMA2_Stream3) || \
-                                   ((PERIPH) == DMA2_Stream4) || \
-                                   ((PERIPH) == DMA2_Stream5) || \
-                                   ((PERIPH) == DMA2_Stream6) || \
-                                   ((PERIPH) == DMA2_Stream7))
-
-#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \
-                                           ((CONTROLLER) == DMA2))
-
-/** @defgroup DMA_channel 
-  * @{
-  */ 
-#define DMA_Channel_0                     ((uint32_t)0x00000000)
-#define DMA_Channel_1                     ((uint32_t)0x02000000)
-#define DMA_Channel_2                     ((uint32_t)0x04000000)
-#define DMA_Channel_3                     ((uint32_t)0x06000000)
-#define DMA_Channel_4                     ((uint32_t)0x08000000)
-#define DMA_Channel_5                     ((uint32_t)0x0A000000)
-#define DMA_Channel_6                     ((uint32_t)0x0C000000)
-#define DMA_Channel_7                     ((uint32_t)0x0E000000)
-
-#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \
-                                 ((CHANNEL) == DMA_Channel_1) || \
-                                 ((CHANNEL) == DMA_Channel_2) || \
-                                 ((CHANNEL) == DMA_Channel_3) || \
-                                 ((CHANNEL) == DMA_Channel_4) || \
-                                 ((CHANNEL) == DMA_Channel_5) || \
-                                 ((CHANNEL) == DMA_Channel_6) || \
-                                 ((CHANNEL) == DMA_Channel_7))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_data_transfer_direction 
-  * @{
-  */ 
-#define DMA_DIR_PeripheralToMemory        ((uint32_t)0x00000000)
-#define DMA_DIR_MemoryToPeripheral        ((uint32_t)0x00000040) 
-#define DMA_DIR_MemoryToMemory            ((uint32_t)0x00000080)
-
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \
-                                     ((DIRECTION) == DMA_DIR_MemoryToPeripheral)  || \
-                                     ((DIRECTION) == DMA_DIR_MemoryToMemory)) 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_data_buffer_size 
-  * @{
-  */ 
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_peripheral_incremented_mode 
-  * @{
-  */ 
-#define DMA_PeripheralInc_Enable          ((uint32_t)0x00000200)
-#define DMA_PeripheralInc_Disable         ((uint32_t)0x00000000)
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
-                                            ((STATE) == DMA_PeripheralInc_Disable))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_memory_incremented_mode 
-  * @{
-  */ 
-#define DMA_MemoryInc_Enable              ((uint32_t)0x00000400)
-#define DMA_MemoryInc_Disable             ((uint32_t)0x00000000)
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
-                                        ((STATE) == DMA_MemoryInc_Disable))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_peripheral_data_size 
-  * @{
-  */ 
-#define DMA_PeripheralDataSize_Byte       ((uint32_t)0x00000000) 
-#define DMA_PeripheralDataSize_HalfWord   ((uint32_t)0x00000800) 
-#define DMA_PeripheralDataSize_Word       ((uint32_t)0x00001000)
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte)  || \
-                                           ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
-                                           ((SIZE) == DMA_PeripheralDataSize_Word))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_memory_data_size 
-  * @{
-  */ 
-#define DMA_MemoryDataSize_Byte           ((uint32_t)0x00000000) 
-#define DMA_MemoryDataSize_HalfWord       ((uint32_t)0x00002000) 
-#define DMA_MemoryDataSize_Word           ((uint32_t)0x00004000)
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte)  || \
-                                       ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
-                                       ((SIZE) == DMA_MemoryDataSize_Word ))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_circular_normal_mode 
-  * @{
-  */ 
-#define DMA_Mode_Normal                   ((uint32_t)0x00000000) 
-#define DMA_Mode_Circular                 ((uint32_t)0x00000100)
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \
-                           ((MODE) == DMA_Mode_Circular)) 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_priority_level 
-  * @{
-  */ 
-#define DMA_Priority_Low                  ((uint32_t)0x00000000)
-#define DMA_Priority_Medium               ((uint32_t)0x00010000) 
-#define DMA_Priority_High                 ((uint32_t)0x00020000)
-#define DMA_Priority_VeryHigh             ((uint32_t)0x00030000)
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low )   || \
-                                   ((PRIORITY) == DMA_Priority_Medium) || \
-                                   ((PRIORITY) == DMA_Priority_High)   || \
-                                   ((PRIORITY) == DMA_Priority_VeryHigh)) 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_fifo_direct_mode 
-  * @{
-  */ 
-#define DMA_FIFOMode_Disable              ((uint32_t)0x00000000) 
-#define DMA_FIFOMode_Enable               ((uint32_t)0x00000004)
-
-#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \
-                                       ((STATE) == DMA_FIFOMode_Enable)) 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_fifo_threshold_level 
-  * @{
-  */ 
-#define DMA_FIFOThreshold_1QuarterFull    ((uint32_t)0x00000000)
-#define DMA_FIFOThreshold_HalfFull        ((uint32_t)0x00000001) 
-#define DMA_FIFOThreshold_3QuartersFull   ((uint32_t)0x00000002)
-#define DMA_FIFOThreshold_Full            ((uint32_t)0x00000003)
-
-#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \
-                                          ((THRESHOLD) == DMA_FIFOThreshold_HalfFull)      || \
-                                          ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \
-                                          ((THRESHOLD) == DMA_FIFOThreshold_Full)) 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_memory_burst 
-  * @{
-  */ 
-#define DMA_MemoryBurst_Single            ((uint32_t)0x00000000)
-#define DMA_MemoryBurst_INC4              ((uint32_t)0x00800000)  
-#define DMA_MemoryBurst_INC8              ((uint32_t)0x01000000)
-#define DMA_MemoryBurst_INC16             ((uint32_t)0x01800000)
-
-#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \
-                                    ((BURST) == DMA_MemoryBurst_INC4)  || \
-                                    ((BURST) == DMA_MemoryBurst_INC8)  || \
-                                    ((BURST) == DMA_MemoryBurst_INC16))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_peripheral_burst 
-  * @{
-  */ 
-#define DMA_PeripheralBurst_Single        ((uint32_t)0x00000000)
-#define DMA_PeripheralBurst_INC4          ((uint32_t)0x00200000)  
-#define DMA_PeripheralBurst_INC8          ((uint32_t)0x00400000)
-#define DMA_PeripheralBurst_INC16         ((uint32_t)0x00600000)
-
-#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \
-                                        ((BURST) == DMA_PeripheralBurst_INC4)  || \
-                                        ((BURST) == DMA_PeripheralBurst_INC8)  || \
-                                        ((BURST) == DMA_PeripheralBurst_INC16))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_fifo_status_level 
-  * @{
-  */
-#define DMA_FIFOStatus_Less1QuarterFull   ((uint32_t)0x00000000 << 3)
-#define DMA_FIFOStatus_1QuarterFull       ((uint32_t)0x00000001 << 3)
-#define DMA_FIFOStatus_HalfFull           ((uint32_t)0x00000002 << 3) 
-#define DMA_FIFOStatus_3QuartersFull      ((uint32_t)0x00000003 << 3)
-#define DMA_FIFOStatus_Empty              ((uint32_t)0x00000004 << 3)
-#define DMA_FIFOStatus_Full               ((uint32_t)0x00000005 << 3)
-
-#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \
-                                    ((STATUS) == DMA_FIFOStatus_HalfFull)          || \
-                                    ((STATUS) == DMA_FIFOStatus_1QuarterFull)      || \
-                                    ((STATUS) == DMA_FIFOStatus_3QuartersFull)     || \
-                                    ((STATUS) == DMA_FIFOStatus_Full)              || \
-                                    ((STATUS) == DMA_FIFOStatus_Empty)) 
-/**
-  * @}
-  */ 
-
-/** @defgroup DMA_flags_definition 
-  * @{
-  */
-#define DMA_FLAG_FEIF0                    ((uint32_t)0x10800001)
-#define DMA_FLAG_DMEIF0                   ((uint32_t)0x10800004)
-#define DMA_FLAG_TEIF0                    ((uint32_t)0x10000008)
-#define DMA_FLAG_HTIF0                    ((uint32_t)0x10000010)
-#define DMA_FLAG_TCIF0                    ((uint32_t)0x10000020)
-#define DMA_FLAG_FEIF1                    ((uint32_t)0x10000040)
-#define DMA_FLAG_DMEIF1                   ((uint32_t)0x10000100)
-#define DMA_FLAG_TEIF1                    ((uint32_t)0x10000200)
-#define DMA_FLAG_HTIF1                    ((uint32_t)0x10000400)
-#define DMA_FLAG_TCIF1                    ((uint32_t)0x10000800)
-#define DMA_FLAG_FEIF2                    ((uint32_t)0x10010000)
-#define DMA_FLAG_DMEIF2                   ((uint32_t)0x10040000)
-#define DMA_FLAG_TEIF2                    ((uint32_t)0x10080000)
-#define DMA_FLAG_HTIF2                    ((uint32_t)0x10100000)
-#define DMA_FLAG_TCIF2                    ((uint32_t)0x10200000)
-#define DMA_FLAG_FEIF3                    ((uint32_t)0x10400000)
-#define DMA_FLAG_DMEIF3                   ((uint32_t)0x11000000)
-#define DMA_FLAG_TEIF3                    ((uint32_t)0x12000000)
-#define DMA_FLAG_HTIF3                    ((uint32_t)0x14000000)
-#define DMA_FLAG_TCIF3                    ((uint32_t)0x18000000)
-#define DMA_FLAG_FEIF4                    ((uint32_t)0x20000001)
-#define DMA_FLAG_DMEIF4                   ((uint32_t)0x20000004)
-#define DMA_FLAG_TEIF4                    ((uint32_t)0x20000008)
-#define DMA_FLAG_HTIF4                    ((uint32_t)0x20000010)
-#define DMA_FLAG_TCIF4                    ((uint32_t)0x20000020)
-#define DMA_FLAG_FEIF5                    ((uint32_t)0x20000040)
-#define DMA_FLAG_DMEIF5                   ((uint32_t)0x20000100)
-#define DMA_FLAG_TEIF5                    ((uint32_t)0x20000200)
-#define DMA_FLAG_HTIF5                    ((uint32_t)0x20000400)
-#define DMA_FLAG_TCIF5                    ((uint32_t)0x20000800)
-#define DMA_FLAG_FEIF6                    ((uint32_t)0x20010000)
-#define DMA_FLAG_DMEIF6                   ((uint32_t)0x20040000)
-#define DMA_FLAG_TEIF6                    ((uint32_t)0x20080000)
-#define DMA_FLAG_HTIF6                    ((uint32_t)0x20100000)
-#define DMA_FLAG_TCIF6                    ((uint32_t)0x20200000)
-#define DMA_FLAG_FEIF7                    ((uint32_t)0x20400000)
-#define DMA_FLAG_DMEIF7                   ((uint32_t)0x21000000)
-#define DMA_FLAG_TEIF7                    ((uint32_t)0x22000000)
-#define DMA_FLAG_HTIF7                    ((uint32_t)0x24000000)
-#define DMA_FLAG_TCIF7                    ((uint32_t)0x28000000)
-
-#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \
-                                 (((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00))
-
-#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0)  || ((FLAG) == DMA_FLAG_HTIF0)  || \
-                               ((FLAG) == DMA_FLAG_TEIF0)  || ((FLAG) == DMA_FLAG_DMEIF0) || \
-                               ((FLAG) == DMA_FLAG_FEIF0)  || ((FLAG) == DMA_FLAG_TCIF1)  || \
-                               ((FLAG) == DMA_FLAG_HTIF1)  || ((FLAG) == DMA_FLAG_TEIF1)  || \
-                               ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1)  || \
-                               ((FLAG) == DMA_FLAG_TCIF2)  || ((FLAG) == DMA_FLAG_HTIF2)  || \
-                               ((FLAG) == DMA_FLAG_TEIF2)  || ((FLAG) == DMA_FLAG_DMEIF2) || \
-                               ((FLAG) == DMA_FLAG_FEIF2)  || ((FLAG) == DMA_FLAG_TCIF3)  || \
-                               ((FLAG) == DMA_FLAG_HTIF3)  || ((FLAG) == DMA_FLAG_TEIF3)  || \
-                               ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3)  || \
-                               ((FLAG) == DMA_FLAG_TCIF4)  || ((FLAG) == DMA_FLAG_HTIF4)  || \
-                               ((FLAG) == DMA_FLAG_TEIF4)  || ((FLAG) == DMA_FLAG_DMEIF4) || \
-                               ((FLAG) == DMA_FLAG_FEIF4)  || ((FLAG) == DMA_FLAG_TCIF5)  || \
-                               ((FLAG) == DMA_FLAG_HTIF5)  || ((FLAG) == DMA_FLAG_TEIF5)  || \
-                               ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5)  || \
-                               ((FLAG) == DMA_FLAG_TCIF6)  || ((FLAG) == DMA_FLAG_HTIF6)  || \
-                               ((FLAG) == DMA_FLAG_TEIF6)  || ((FLAG) == DMA_FLAG_DMEIF6) || \
-                               ((FLAG) == DMA_FLAG_FEIF6)  || ((FLAG) == DMA_FLAG_TCIF7)  || \
-                               ((FLAG) == DMA_FLAG_HTIF7)  || ((FLAG) == DMA_FLAG_TEIF7)  || \
-                               ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_interrupt_enable_definitions 
-  * @{
-  */ 
-#define DMA_IT_TC                         ((uint32_t)0x00000010)
-#define DMA_IT_HT                         ((uint32_t)0x00000008)
-#define DMA_IT_TE                         ((uint32_t)0x00000004)
-#define DMA_IT_DME                        ((uint32_t)0x00000002)
-#define DMA_IT_FE                         ((uint32_t)0x00000080)
-
-#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_interrupts_definitions 
-  * @{
-  */ 
-#define DMA_IT_FEIF0                      ((uint32_t)0x90000001)
-#define DMA_IT_DMEIF0                     ((uint32_t)0x10001004)
-#define DMA_IT_TEIF0                      ((uint32_t)0x10002008)
-#define DMA_IT_HTIF0                      ((uint32_t)0x10004010)
-#define DMA_IT_TCIF0                      ((uint32_t)0x10008020)
-#define DMA_IT_FEIF1                      ((uint32_t)0x90000040)
-#define DMA_IT_DMEIF1                     ((uint32_t)0x10001100)
-#define DMA_IT_TEIF1                      ((uint32_t)0x10002200)
-#define DMA_IT_HTIF1                      ((uint32_t)0x10004400)
-#define DMA_IT_TCIF1                      ((uint32_t)0x10008800)
-#define DMA_IT_FEIF2                      ((uint32_t)0x90010000)
-#define DMA_IT_DMEIF2                     ((uint32_t)0x10041000)
-#define DMA_IT_TEIF2                      ((uint32_t)0x10082000)
-#define DMA_IT_HTIF2                      ((uint32_t)0x10104000)
-#define DMA_IT_TCIF2                      ((uint32_t)0x10208000)
-#define DMA_IT_FEIF3                      ((uint32_t)0x90400000)
-#define DMA_IT_DMEIF3                     ((uint32_t)0x11001000)
-#define DMA_IT_TEIF3                      ((uint32_t)0x12002000)
-#define DMA_IT_HTIF3                      ((uint32_t)0x14004000)
-#define DMA_IT_TCIF3                      ((uint32_t)0x18008000)
-#define DMA_IT_FEIF4                      ((uint32_t)0xA0000001)
-#define DMA_IT_DMEIF4                     ((uint32_t)0x20001004)
-#define DMA_IT_TEIF4                      ((uint32_t)0x20002008)
-#define DMA_IT_HTIF4                      ((uint32_t)0x20004010)
-#define DMA_IT_TCIF4                      ((uint32_t)0x20008020)
-#define DMA_IT_FEIF5                      ((uint32_t)0xA0000040)
-#define DMA_IT_DMEIF5                     ((uint32_t)0x20001100)
-#define DMA_IT_TEIF5                      ((uint32_t)0x20002200)
-#define DMA_IT_HTIF5                      ((uint32_t)0x20004400)
-#define DMA_IT_TCIF5                      ((uint32_t)0x20008800)
-#define DMA_IT_FEIF6                      ((uint32_t)0xA0010000)
-#define DMA_IT_DMEIF6                     ((uint32_t)0x20041000)
-#define DMA_IT_TEIF6                      ((uint32_t)0x20082000)
-#define DMA_IT_HTIF6                      ((uint32_t)0x20104000)
-#define DMA_IT_TCIF6                      ((uint32_t)0x20208000)
-#define DMA_IT_FEIF7                      ((uint32_t)0xA0400000)
-#define DMA_IT_DMEIF7                     ((uint32_t)0x21001000)
-#define DMA_IT_TEIF7                      ((uint32_t)0x22002000)
-#define DMA_IT_HTIF7                      ((uint32_t)0x24004000)
-#define DMA_IT_TCIF7                      ((uint32_t)0x28008000)
-
-#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \
-                             (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \
-                             (((IT) & 0x40820082) == 0x00))
-
-#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0)  || \
-                           ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \
-                           ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1)  || \
-                           ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1)  || \
-                           ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1)  || \
-                           ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2)  || \
-                           ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \
-                           ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3)  || \
-                           ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3)  || \
-                           ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3)  || \
-                           ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4)  || \
-                           ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \
-                           ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5)  || \
-                           ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5)  || \
-                           ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5)  || \
-                           ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6)  || \
-                           ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \
-                           ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7)  || \
-                           ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7)  || \
-                           ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_peripheral_increment_offset 
-  * @{
-  */ 
-#define DMA_PINCOS_Psize                  ((uint32_t)0x00000000)
-#define DMA_PINCOS_WordAligned            ((uint32_t)0x00008000)
-
-#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \
-                                  ((SIZE) == DMA_PINCOS_WordAligned))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_flow_controller_definitions 
-  * @{
-  */ 
-#define DMA_FlowCtrl_Memory               ((uint32_t)0x00000000)
-#define DMA_FlowCtrl_Peripheral           ((uint32_t)0x00000020)
-
-#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \
-                                ((CTRL) == DMA_FlowCtrl_Peripheral))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_memory_targets_definitions 
-  * @{
-  */ 
-#define DMA_Memory_0                      ((uint32_t)0x00000000)
-#define DMA_Memory_1                      ((uint32_t)0x00080000)
-
-#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/ 
-
-/*  Function used to set the DMA configuration to the default reset state *****/ 
-void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx);
-
-/* Initialization and Configuration functions *********************************/
-void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct);
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
-void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
-
-/* Optional Configuration functions *******************************************/
-void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos);
-void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl);
-
-/* Data Counter functions *****************************************************/
-void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
-uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
-
-/* Double Buffer mode functions ***********************************************/
-void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
-                                uint32_t DMA_CurrentMemory);
-void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
-void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
-                            uint32_t DMA_MemoryTarget);
-uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
-
-/* Interrupts and flags management functions **********************************/
-FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
-uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
-FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
-void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
-void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
-ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
-void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_DMA_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h

@@ -1,475 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_dma2d.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the DMA2D firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_DMA2D_H
-#define __STM32F4xx_DMA2D_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup DMA2D
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
- 
-/** 
-  * @brief  DMA2D Init structure definition  
-  */
-
-typedef struct
-{
-  uint32_t DMA2D_Mode;                           /*!< configures the DMA2D transfer mode.
-                                                 This parameter can be one value of @ref DMA2D_MODE */
-  
-  uint32_t DMA2D_CMode;                          /*!< configures the color format of the output image.
-                                                 This parameter can be one value of @ref DMA2D_CMODE */
-
-  uint32_t DMA2D_OutputBlue;                     /*!< configures the blue value of the output image. 
-                                                 This parameter must range:
-                                                 - from 0x00 to 0xFF if ARGB8888 color mode is slected
-                                                 - from 0x00 to 0xFF if RGB888 color mode is slected
-                                                 - from 0x00 to 0x1F if RGB565 color mode is slected
-                                                 - from 0x00 to 0x1F if ARGB1555 color mode is slected
-                                                 - from 0x00 to 0x0F if ARGB4444 color mode is slected  */
-
-  uint32_t DMA2D_OutputGreen;                    /*!< configures the green value of the output image. 
-                                                 This parameter must range:
-                                                 - from 0x00 to 0xFF if ARGB8888 color mode is selected
-                                                 - from 0x00 to 0xFF if RGB888 color mode is selected
-                                                 - from 0x00 to 0x2F if RGB565 color mode is selected
-                                                 - from 0x00 to 0x1F if ARGB1555 color mode is selected
-                                                 - from 0x00 to 0x0F if ARGB4444 color mode is selected  */
-            
-  uint32_t DMA2D_OutputRed;                      /*!< configures the red value of the output image. 
-                                                 This parameter must range:
-                                                 - from 0x00 to 0xFF if ARGB8888 color mode is slected
-                                                 - from 0x00 to 0xFF if RGB888 color mode is slected
-                                                 - from 0x00 to 0x1F if RGB565 color mode is slected
-                                                 - from 0x00 to 0x1F if ARGB1555 color mode is slected
-                                                 - from 0x00 to 0x0F if ARGB4444 color mode is slected  */
-  
-  uint32_t DMA2D_OutputAlpha;                    /*!< configures the alpha channel of the output color. 
-                                                 This parameter must range:
-                                                 - from 0x00 to 0xFF if ARGB8888 color mode is selected
-                                                 - from 0x00 to 0x01 if ARGB1555 color mode is selected
-                                                 - from 0x00 to 0x0F if ARGB4444 color mode is selected  */
-
-  uint32_t DMA2D_OutputMemoryAdd;                /*!< Specifies the memory address. This parameter 
-                                                 must be range from 0x00000000 to 0xFFFFFFFF. */
-
-  uint32_t DMA2D_OutputOffset;                   /*!< Specifies the Offset value. This parameter must be range from
-                                                 0x0000 to 0x3FFF. */
-
-  uint32_t DMA2D_NumberOfLine;                   /*!< Configures the number of line of the area to be transfered.
-                                                 This parameter must range from 0x0000 to 0xFFFF */
-            
-  uint32_t DMA2D_PixelPerLine;                   /*!< Configures the number pixel per line of the area to be transferred.
-                                                 This parameter must range from 0x0000 to 0x3FFF */
-} DMA2D_InitTypeDef;
-
-
-
-typedef struct
-{
-  uint32_t DMA2D_FGMA;                           /*!< configures the DMA2D foreground memory address.
-                                                 This parameter must be range from 0x00000000 to 0xFFFFFFFF. */
-  
-  uint32_t DMA2D_FGO;                            /*!< configures the DMA2D foreground offset.
-                                                 This parameter must be range from 0x0000 to 0x3FFF. */
-
-  uint32_t DMA2D_FGCM;                           /*!< configures the DMA2D foreground color mode . 
-                                                 This parameter can be one value of @ref DMA2D_FGCM */
-
-  uint32_t DMA2D_FG_CLUT_CM;                     /*!< configures the DMA2D foreground CLUT color mode. 
-                                                 This parameter can be one value of @ref DMA2D_FG_CLUT_CM */
-            
-  uint32_t DMA2D_FG_CLUT_SIZE;                   /*!< configures the DMA2D foreground CLUT size. 
-                                                 This parameter must range from 0x00 to 0xFF. */
-  
-  uint32_t DMA2D_FGPFC_ALPHA_MODE;               /*!< configures the DMA2D foreground alpha mode. 
-                                                 This parameter can be one value of @ref DMA2D_FGPFC_ALPHA_MODE */
-
-  uint32_t DMA2D_FGPFC_ALPHA_VALUE;              /*!< Specifies the DMA2D foreground alpha value 
-                                                 must be range from 0x00 to 0xFF. */
-
-  uint32_t DMA2D_FGC_BLUE;                       /*!< Specifies the DMA2D foreground blue value 
-                                                 must be range from 0x00 to 0xFF. */
-
-  uint32_t DMA2D_FGC_GREEN;                      /*!< Specifies the DMA2D foreground green value 
-                                                 must be range from 0x00 to 0xFF. */
-
-  uint32_t DMA2D_FGC_RED;                        /*!< Specifies the DMA2D foreground red value 
-                                                 must be range from 0x00 to 0xFF. */
-            
-  uint32_t DMA2D_FGCMAR;                         /*!< Configures the DMA2D foreground CLUT memory address.
-                                                 This parameter must range from 0x00000000 to 0xFFFFFFFF. */
-} DMA2D_FG_InitTypeDef;
-
-
-typedef struct
-{
-  uint32_t DMA2D_BGMA;                           /*!< configures the DMA2D background memory address.
-                                                 This parameter must be range from 0x00000000 to 0xFFFFFFFF. */
-  
-  uint32_t DMA2D_BGO;                            /*!< configures the DMA2D background offset.
-                                                 This parameter must be range from 0x0000 to 0x3FFF. */
-
-  uint32_t DMA2D_BGCM;                           /*!< configures the DMA2D background color mode . 
-                                                 This parameter can be one value of @ref DMA2D_FGCM */
-
-  uint32_t DMA2D_BG_CLUT_CM;                     /*!< configures the DMA2D background CLUT color mode. 
-                                                 This parameter can be one value of @ref DMA2D_FG_CLUT_CM */
-            
-  uint32_t DMA2D_BG_CLUT_SIZE;                   /*!< configures the DMA2D background CLUT size. 
-                                                 This parameter must range from 0x00 to 0xFF. */
-  
-  uint32_t DMA2D_BGPFC_ALPHA_MODE;               /*!< configures the DMA2D background alpha mode. 
-                                                 This parameter can be one value of @ref DMA2D_FGPFC_ALPHA_MODE */
-
-  uint32_t DMA2D_BGPFC_ALPHA_VALUE;              /*!< Specifies the DMA2D background alpha value 
-                                                 must be range from 0x00 to 0xFF. */
-
-  uint32_t DMA2D_BGC_BLUE;                       /*!< Specifies the DMA2D background blue value 
-                                                 must be range from 0x00 to 0xFF. */
-
-  uint32_t DMA2D_BGC_GREEN;                      /*!< Specifies the DMA2D background green value 
-                                                 must be range from 0x00 to 0xFF. */
-
-  uint32_t DMA2D_BGC_RED;                        /*!< Specifies the DMA2D background red value 
-                                                 must be range from 0x00 to 0xFF. */
-            
-  uint32_t DMA2D_BGCMAR;                         /*!< Configures the DMA2D background CLUT memory address.
-                                                 This parameter must range from 0x00000000 to 0xFFFFFFFF. */
-} DMA2D_BG_InitTypeDef;
-
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA2D_Exported_Constants
-  * @{
-  */  
-
-/** @defgroup DMA2D_MODE 
-  * @{
-  */
-
-
-#define DMA2D_M2M                            ((uint32_t)0x00000000)
-#define DMA2D_M2M_PFC                        ((uint32_t)0x00010000)
-#define DMA2D_M2M_BLEND                      ((uint32_t)0x00020000)
-#define DMA2D_R2M                            ((uint32_t)0x00030000)
-
-#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
-                             ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
-
-
-/**
-  * @}
-  */  
-
-/** @defgroup DMA2D_CMODE 
-  * @{
-  */
-#define DMA2D_ARGB8888                       ((uint32_t)0x00000000)
-#define DMA2D_RGB888                         ((uint32_t)0x00000001)
-#define DMA2D_RGB565                         ((uint32_t)0x00000002)
-#define DMA2D_ARGB1555                       ((uint32_t)0x00000003)
-#define DMA2D_ARGB4444                       ((uint32_t)0x00000004)
-
-#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \
-                                   ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \
-                                   ((MODE_ARGB) == DMA2D_ARGB4444))
-
-
-/**
-  * @}
-  */  
-
-/** @defgroup DMA2D_OUTPUT_COLOR 
-  * @{
-  */
-#define DMA2D_Output_Color                 ((uint32_t)0x000000FF)
-
-#define IS_DMA2D_OGREEN(OGREEN) ((OGREEN) <= DMA2D_Output_Color)
-#define IS_DMA2D_ORED(ORED)     ((ORED) <= DMA2D_Output_Color)
-#define IS_DMA2D_OBLUE(OBLUE)   ((OBLUE) <= DMA2D_Output_Color)
-#define IS_DMA2D_OALPHA(OALPHA) ((OALPHA) <= DMA2D_Output_Color)
-
-/**
-  * @}
-  */  
-
-/** @defgroup DMA2D_OUTPUT_OFFSET 
-  * @{
-  */
-#define DMA2D_OUTPUT_OFFSET      ((uint32_t)0x00003FFF)
-
-#define IS_DMA2D_OUTPUT_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OUTPUT_OFFSET)
-
-
-/**
-  * @}
-  */  
-
-/** @defgroup DMA2D_SIZE 
-  * @{
-  */
-
-#define DMA2D_pixel          ((uint32_t)0x00003FFF)
-#define DMA2D_Line           ((uint32_t)0x0000FFFF)
-
-#define IS_DMA2D_LINE(LINE)  ((LINE) <= DMA2D_Line)
-#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_pixel)
-
-
-/**
-  * @}
-  */  
-
-/** @defgroup DMA2D_OFFSET
-  * @{
-  */
-#define OFFSET               ((uint32_t)0x00003FFF)
-
-#define IS_DMA2D_FGO(FGO)  ((FGO) <= OFFSET)
-
-#define IS_DMA2D_BGO(BGO)  ((BGO) <= OFFSET) 
-
-/**
-  * @}
-  */  
-
-
-/** @defgroup DMA2D_FGCM
-  * @{
-  */
-
-#define CM_ARGB8888        ((uint32_t)0x00000000)
-#define CM_RGB888          ((uint32_t)0x00000001)
-#define CM_RGB565          ((uint32_t)0x00000002)
-#define CM_ARGB1555        ((uint32_t)0x00000003)
-#define CM_ARGB4444        ((uint32_t)0x00000004)
-#define CM_L8              ((uint32_t)0x00000005)
-#define CM_AL44            ((uint32_t)0x00000006)
-#define CM_AL88            ((uint32_t)0x00000007)
-#define CM_L4              ((uint32_t)0x00000008)
-#define CM_A8              ((uint32_t)0x00000009)
-#define CM_A4              ((uint32_t)0x0000000A)
-
-#define IS_DMA2D_FGCM(FGCM) (((FGCM) == CM_ARGB8888) || ((FGCM) == CM_RGB888) || \
-                             ((FGCM) == CM_RGB565) || ((FGCM) == CM_ARGB1555) || \
-                             ((FGCM) == CM_ARGB4444) || ((FGCM) == CM_L8) || \
-                             ((FGCM) == CM_AL44) || ((FGCM) == CM_AL88) || \
-                             ((FGCM) == CM_L4) || ((FGCM) == CM_A8) || \
-                             ((FGCM) == CM_A4))
-
-#define IS_DMA2D_BGCM(BGCM) (((BGCM) == CM_ARGB8888) || ((BGCM) == CM_RGB888) || \
-                             ((BGCM) == CM_RGB565) || ((BGCM) == CM_ARGB1555) || \
-                             ((BGCM) == CM_ARGB4444) || ((BGCM) == CM_L8) || \
-                             ((BGCM) == CM_AL44) || ((BGCM) == CM_AL88) || \
-                             ((BGCM) == CM_L4) || ((BGCM) == CM_A8) || \
-                             ((BGCM) == CM_A4))
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA2D_FG_CLUT_CM
-  * @{
-  */
-
-#define CLUT_CM_ARGB8888        ((uint32_t)0x00000000)
-#define CLUT_CM_RGB888          ((uint32_t)0x00000001)
-
-#define IS_DMA2D_FG_CLUT_CM(FG_CLUT_CM) (((FG_CLUT_CM) == CLUT_CM_ARGB8888) || ((FG_CLUT_CM) == CLUT_CM_RGB888))
-
-#define IS_DMA2D_BG_CLUT_CM(BG_CLUT_CM) (((BG_CLUT_CM) == CLUT_CM_ARGB8888) || ((BG_CLUT_CM) == CLUT_CM_RGB888))
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA2D_FG_COLOR_VALUE
-  * @{
-  */
-
-#define COLOR_VALUE             ((uint32_t)0x000000FF)
-
-#define IS_DMA2D_FG_CLUT_SIZE(FG_CLUT_SIZE) ((FG_CLUT_SIZE) <= COLOR_VALUE)
-
-#define IS_DMA2D_FG_ALPHA_VALUE(FG_ALPHA_VALUE) ((FG_ALPHA_VALUE) <= COLOR_VALUE)
-#define IS_DMA2D_FGC_BLUE(FGC_BLUE) ((FGC_BLUE) <= COLOR_VALUE)
-#define IS_DMA2D_FGC_GREEN(FGC_GREEN) ((FGC_GREEN) <= COLOR_VALUE)
-#define IS_DMA2D_FGC_RED(FGC_RED) ((FGC_RED) <= COLOR_VALUE)
-
-#define IS_DMA2D_BG_CLUT_SIZE(BG_CLUT_SIZE) ((BG_CLUT_SIZE) <= COLOR_VALUE)
-
-#define IS_DMA2D_BG_ALPHA_VALUE(BG_ALPHA_VALUE) ((BG_ALPHA_VALUE) <= COLOR_VALUE)
-#define IS_DMA2D_BGC_BLUE(BGC_BLUE) ((BGC_BLUE) <= COLOR_VALUE)
-#define IS_DMA2D_BGC_GREEN(BGC_GREEN) ((BGC_GREEN) <= COLOR_VALUE)
-#define IS_DMA2D_BGC_RED(BGC_RED) ((BGC_RED) <= COLOR_VALUE)
-
-/**
-  * @}
-  */
-
-/** DMA2D_FGPFC_ALPHA_MODE
-  * @{
-  */
-
-#define NO_MODIF_ALPHA_VALUE       ((uint32_t)0x00000000)
-#define REPLACE_ALPHA_VALUE        ((uint32_t)0x00000001)
-#define COMBINE_ALPHA_VALUE        ((uint32_t)0x00000002)
-
-#define IS_DMA2D_FG_ALPHA_MODE(FG_ALPHA_MODE) (((FG_ALPHA_MODE) ==  NO_MODIF_ALPHA_VALUE) || \
-                                              ((FG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \
-                                              ((FG_ALPHA_MODE) == COMBINE_ALPHA_VALUE))
-
-#define IS_DMA2D_BG_ALPHA_MODE(BG_ALPHA_MODE) (((BG_ALPHA_MODE) ==  NO_MODIF_ALPHA_VALUE) || \
-                                              ((BG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \
-                                              ((BG_ALPHA_MODE) == COMBINE_ALPHA_VALUE))
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA2D_Interrupts 
-  * @{
-  */
-
-#define DMA2D_IT_CE                      DMA2D_CR_CEIE
-#define DMA2D_IT_CTC                     DMA2D_CR_CTCIE
-#define DMA2D_IT_CAE                     DMA2D_CR_CAEIE
-#define DMA2D_IT_TW                      DMA2D_CR_TWIE
-#define DMA2D_IT_TC                      DMA2D_CR_TCIE
-#define DMA2D_IT_TE                      DMA2D_CR_TEIE
-
-#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
-                        ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
-                        ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
-
-/**
-  * @}
-  */
-      
-/** @defgroup DMA2D_Flag 
-  * @{
-  */
-
-#define DMA2D_FLAG_CE                      DMA2D_ISR_CEIF
-#define DMA2D_FLAG_CTC                     DMA2D_ISR_CTCIF
-#define DMA2D_FLAG_CAE                     DMA2D_ISR_CAEIF
-#define DMA2D_FLAG_TW                      DMA2D_ISR_TWIF
-#define DMA2D_FLAG_TC                      DMA2D_ISR_TCIF
-#define DMA2D_FLAG_TE                      DMA2D_ISR_TEIF
-
-
-#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
-                                ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
-                                ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) 
-
-
-/**
-  * @}
-  */
-      
-/** @defgroup DMA2D_DeadTime 
-  * @{
-  */
-
-#define DEADTIME                  ((uint32_t)0x000000FF)
-  
-#define IS_DMA2D_DEAD_TIME(DEAD_TIME) ((DEAD_TIME) <= DEADTIME)
-
-
-#define LINE_WATERMARK            DMA2D_LWR_LW
-
-#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/*  Function used to set the DMA2D configuration to the default reset state *****/
-void DMA2D_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void DMA2D_Init(DMA2D_InitTypeDef* DMA2D_InitStruct);
-void DMA2D_StructInit(DMA2D_InitTypeDef* DMA2D_InitStruct);
-void DMA2D_StartTransfer(void);
-void DMA2D_AbortTransfer(void);
-void DMA2D_Suspend(FunctionalState NewState);
-void DMA2D_FGConfig(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct);
-void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct);
-void DMA2D_BGConfig(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct);
-void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct);
-void DMA2D_FGStart(FunctionalState NewState);
-void DMA2D_BGStart(FunctionalState NewState);
-void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState);
-void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig);
-
-/* Interrupts and flags management functions **********************************/
-void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState);
-FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG);
-void DMA2D_ClearFlag(uint32_t DMA2D_FLAG);
-ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT);
-void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_DMA2D_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h

@@ -1,185 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_exti.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the EXTI firmware
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_EXTI_H
-#define __STM32F4xx_EXTI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup EXTI
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  EXTI mode enumeration  
-  */
-
-typedef enum
-{
-  EXTI_Mode_Interrupt = 0x00,
-  EXTI_Mode_Event = 0x04
-}EXTIMode_TypeDef;
-
-#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
-
-/** 
-  * @brief  EXTI Trigger enumeration  
-  */
-
-typedef enum
-{
-  EXTI_Trigger_Rising = 0x08,
-  EXTI_Trigger_Falling = 0x0C,  
-  EXTI_Trigger_Rising_Falling = 0x10
-}EXTITrigger_TypeDef;
-
-#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
-                                  ((TRIGGER) == EXTI_Trigger_Falling) || \
-                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))
-/** 
-  * @brief  EXTI Init Structure definition  
-  */
-
-typedef struct
-{
-  uint32_t EXTI_Line;               /*!< Specifies the EXTI lines to be enabled or disabled.
-                                         This parameter can be any combination value of @ref EXTI_Lines */
-   
-  EXTIMode_TypeDef EXTI_Mode;       /*!< Specifies the mode for the EXTI lines.
-                                         This parameter can be a value of @ref EXTIMode_TypeDef */
-
-  EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
-                                         This parameter can be a value of @ref EXTITrigger_TypeDef */
-
-  FunctionalState EXTI_LineCmd;     /*!< Specifies the new state of the selected EXTI lines.
-                                         This parameter can be set either to ENABLE or DISABLE */ 
-}EXTI_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup EXTI_Exported_Constants
-  * @{
-  */
-
-/** @defgroup EXTI_Lines 
-  * @{
-  */
-
-#define EXTI_Line0       ((uint32_t)0x00001)     /*!< External interrupt line 0 */
-#define EXTI_Line1       ((uint32_t)0x00002)     /*!< External interrupt line 1 */
-#define EXTI_Line2       ((uint32_t)0x00004)     /*!< External interrupt line 2 */
-#define EXTI_Line3       ((uint32_t)0x00008)     /*!< External interrupt line 3 */
-#define EXTI_Line4       ((uint32_t)0x00010)     /*!< External interrupt line 4 */
-#define EXTI_Line5       ((uint32_t)0x00020)     /*!< External interrupt line 5 */
-#define EXTI_Line6       ((uint32_t)0x00040)     /*!< External interrupt line 6 */
-#define EXTI_Line7       ((uint32_t)0x00080)     /*!< External interrupt line 7 */
-#define EXTI_Line8       ((uint32_t)0x00100)     /*!< External interrupt line 8 */
-#define EXTI_Line9       ((uint32_t)0x00200)     /*!< External interrupt line 9 */
-#define EXTI_Line10      ((uint32_t)0x00400)     /*!< External interrupt line 10 */
-#define EXTI_Line11      ((uint32_t)0x00800)     /*!< External interrupt line 11 */
-#define EXTI_Line12      ((uint32_t)0x01000)     /*!< External interrupt line 12 */
-#define EXTI_Line13      ((uint32_t)0x02000)     /*!< External interrupt line 13 */
-#define EXTI_Line14      ((uint32_t)0x04000)     /*!< External interrupt line 14 */
-#define EXTI_Line15      ((uint32_t)0x08000)     /*!< External interrupt line 15 */
-#define EXTI_Line16      ((uint32_t)0x10000)     /*!< External interrupt line 16 Connected to the PVD Output */
-#define EXTI_Line17      ((uint32_t)0x20000)     /*!< External interrupt line 17 Connected to the RTC Alarm event */
-#define EXTI_Line18      ((uint32_t)0x40000)     /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */                                    
-#define EXTI_Line19      ((uint32_t)0x80000)     /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
-#define EXTI_Line20      ((uint32_t)0x00100000)  /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event  */
-#define EXTI_Line21      ((uint32_t)0x00200000)  /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */                                               
-#define EXTI_Line22      ((uint32_t)0x00400000)  /*!< External interrupt line 22 Connected to the RTC Wakeup event */
-#define EXTI_Line23      ((uint32_t)0x00800000)  /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */
-
-                                          
-#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
-
-#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
-                                ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
-                                ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
-                                ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
-                                ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
-                                ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
-                                ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
-                                ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
-                                ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
-                                ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
-                                ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\
-                                ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23))
-                    
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/*  Function used to set the EXTI configuration to the default reset state *****/
-void EXTI_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
-
-/* Interrupts and flags management functions **********************************/
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
-void EXTI_ClearFlag(uint32_t EXTI_Line);
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_EXTI_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h

@@ -1,497 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_flash.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the FLASH 
-  *          firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_FLASH_H
-#define __STM32F4xx_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup FLASH
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** 
-  * @brief FLASH Status  
-  */ 
-typedef enum
-{ 
-  FLASH_BUSY = 1,
-  FLASH_ERROR_RD,
-  FLASH_ERROR_PGS,
-  FLASH_ERROR_PGP,
-  FLASH_ERROR_PGA,
-  FLASH_ERROR_WRP,
-  FLASH_ERROR_PROGRAM,
-  FLASH_ERROR_OPERATION,
-  FLASH_COMPLETE
-}FLASH_Status;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FLASH_Exported_Constants
-  * @{
-  */  
-
-/** @defgroup Flash_Latency 
-  * @{
-  */ 
-#define FLASH_Latency_0                ((uint8_t)0x0000)  /*!< FLASH Zero Latency cycle      */
-#define FLASH_Latency_1                ((uint8_t)0x0001)  /*!< FLASH One Latency cycle       */
-#define FLASH_Latency_2                ((uint8_t)0x0002)  /*!< FLASH Two Latency cycles      */
-#define FLASH_Latency_3                ((uint8_t)0x0003)  /*!< FLASH Three Latency cycles    */
-#define FLASH_Latency_4                ((uint8_t)0x0004)  /*!< FLASH Four Latency cycles     */
-#define FLASH_Latency_5                ((uint8_t)0x0005)  /*!< FLASH Five Latency cycles     */
-#define FLASH_Latency_6                ((uint8_t)0x0006)  /*!< FLASH Six Latency cycles      */
-#define FLASH_Latency_7                ((uint8_t)0x0007)  /*!< FLASH Seven Latency cycles    */
-#define FLASH_Latency_8                ((uint8_t)0x0008)  /*!< FLASH Eight Latency cycles    */
-#define FLASH_Latency_9                ((uint8_t)0x0009)  /*!< FLASH Nine Latency cycles     */
-#define FLASH_Latency_10               ((uint8_t)0x000A)  /*!< FLASH Ten Latency cycles      */
-#define FLASH_Latency_11               ((uint8_t)0x000B)  /*!< FLASH Eleven Latency cycles   */
-#define FLASH_Latency_12               ((uint8_t)0x000C)  /*!< FLASH Twelve Latency cycles   */
-#define FLASH_Latency_13               ((uint8_t)0x000D)  /*!< FLASH Thirteen Latency cycles */
-#define FLASH_Latency_14               ((uint8_t)0x000E)  /*!< FLASH Fourteen Latency cycles */
-#define FLASH_Latency_15               ((uint8_t)0x000F)  /*!< FLASH Fifteen Latency cycles  */
-
-
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0)  || \
-                                   ((LATENCY) == FLASH_Latency_1)  || \
-                                   ((LATENCY) == FLASH_Latency_2)  || \
-                                   ((LATENCY) == FLASH_Latency_3)  || \
-                                   ((LATENCY) == FLASH_Latency_4)  || \
-                                   ((LATENCY) == FLASH_Latency_5)  || \
-                                   ((LATENCY) == FLASH_Latency_6)  || \
-                                   ((LATENCY) == FLASH_Latency_7)  || \
-                                   ((LATENCY) == FLASH_Latency_8)  || \
-                                   ((LATENCY) == FLASH_Latency_9)  || \
-                                   ((LATENCY) == FLASH_Latency_10) || \
-                                   ((LATENCY) == FLASH_Latency_11) || \
-                                   ((LATENCY) == FLASH_Latency_12) || \
-                                   ((LATENCY) == FLASH_Latency_13) || \
-                                   ((LATENCY) == FLASH_Latency_14) || \
-                                   ((LATENCY) == FLASH_Latency_15))
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Voltage_Range 
-  * @{
-  */ 
-#define VoltageRange_1        ((uint8_t)0x00)  /*!< Device operating range: 1.8V to 2.1V */
-#define VoltageRange_2        ((uint8_t)0x01)  /*!<Device operating range: 2.1V to 2.7V */
-#define VoltageRange_3        ((uint8_t)0x02)  /*!<Device operating range: 2.7V to 3.6V */
-#define VoltageRange_4        ((uint8_t)0x03)  /*!<Device operating range: 2.7V to 3.6V + External Vpp */
-
-#define IS_VOLTAGERANGE(RANGE)(((RANGE) == VoltageRange_1) || \
-                               ((RANGE) == VoltageRange_2) || \
-                               ((RANGE) == VoltageRange_3) || \
-                               ((RANGE) == VoltageRange_4))
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Sectors
-  * @{
-  */
-#define FLASH_Sector_0     ((uint16_t)0x0000) /*!< Sector Number 0   */
-#define FLASH_Sector_1     ((uint16_t)0x0008) /*!< Sector Number 1   */
-#define FLASH_Sector_2     ((uint16_t)0x0010) /*!< Sector Number 2   */
-#define FLASH_Sector_3     ((uint16_t)0x0018) /*!< Sector Number 3   */
-#define FLASH_Sector_4     ((uint16_t)0x0020) /*!< Sector Number 4   */
-#define FLASH_Sector_5     ((uint16_t)0x0028) /*!< Sector Number 5   */
-#define FLASH_Sector_6     ((uint16_t)0x0030) /*!< Sector Number 6   */
-#define FLASH_Sector_7     ((uint16_t)0x0038) /*!< Sector Number 7   */
-#define FLASH_Sector_8     ((uint16_t)0x0040) /*!< Sector Number 8   */
-#define FLASH_Sector_9     ((uint16_t)0x0048) /*!< Sector Number 9   */
-#define FLASH_Sector_10    ((uint16_t)0x0050) /*!< Sector Number 10  */
-#define FLASH_Sector_11    ((uint16_t)0x0058) /*!< Sector Number 11  */
-#define FLASH_Sector_12    ((uint16_t)0x0080) /*!< Sector Number 12  */
-#define FLASH_Sector_13    ((uint16_t)0x0088) /*!< Sector Number 13  */
-#define FLASH_Sector_14    ((uint16_t)0x0090) /*!< Sector Number 14  */
-#define FLASH_Sector_15    ((uint16_t)0x0098) /*!< Sector Number 15  */
-#define FLASH_Sector_16    ((uint16_t)0x00A0) /*!< Sector Number 16  */
-#define FLASH_Sector_17    ((uint16_t)0x00A8) /*!< Sector Number 17  */
-#define FLASH_Sector_18    ((uint16_t)0x00B0) /*!< Sector Number 18  */
-#define FLASH_Sector_19    ((uint16_t)0x00B8) /*!< Sector Number 19  */
-#define FLASH_Sector_20    ((uint16_t)0x00C0) /*!< Sector Number 20  */
-#define FLASH_Sector_21    ((uint16_t)0x00C8) /*!< Sector Number 21  */
-#define FLASH_Sector_22    ((uint16_t)0x00D0) /*!< Sector Number 22  */
-#define FLASH_Sector_23    ((uint16_t)0x00D8) /*!< Sector Number 23  */
-
-#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0)   || ((SECTOR) == FLASH_Sector_1)   ||\
-                                 ((SECTOR) == FLASH_Sector_2)   || ((SECTOR) == FLASH_Sector_3)   ||\
-                                 ((SECTOR) == FLASH_Sector_4)   || ((SECTOR) == FLASH_Sector_5)   ||\
-                                 ((SECTOR) == FLASH_Sector_6)   || ((SECTOR) == FLASH_Sector_7)   ||\
-                                 ((SECTOR) == FLASH_Sector_8)   || ((SECTOR) == FLASH_Sector_9)   ||\
-                                 ((SECTOR) == FLASH_Sector_10)  || ((SECTOR) == FLASH_Sector_11)  ||\
-                                 ((SECTOR) == FLASH_Sector_12)  || ((SECTOR) == FLASH_Sector_13)  ||\
-                                 ((SECTOR) == FLASH_Sector_14)  || ((SECTOR) == FLASH_Sector_15)  ||\
-                                 ((SECTOR) == FLASH_Sector_16)  || ((SECTOR) == FLASH_Sector_17)  ||\
-                                 ((SECTOR) == FLASH_Sector_18)  || ((SECTOR) == FLASH_Sector_19)  ||\
-                                 ((SECTOR) == FLASH_Sector_20)  || ((SECTOR) == FLASH_Sector_21)  ||\
-                                 ((SECTOR) == FLASH_Sector_22)  || ((SECTOR) == FLASH_Sector_23))
-
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F469_479xx)
-#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x081FFFFF)) ||\
-                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))  
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
-
-#if defined (STM32F40_41xxx) || defined(STM32F412xG)
-#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF)) ||\
-                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) 
-#endif /* STM32F40_41xxx || STM32F412xG */
-
-#if defined (STM32F401xx)
-#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF)) ||\
-                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
-#endif /* STM32F401xx */
-
-#if defined (STM32F411xE) || defined (STM32F446xx)
-#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0807FFFF)) ||\
-                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
-#endif /* STM32F411xE || STM32F446xx */
-
-#if defined (STM32F410xx)
-#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF)) ||\
-                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
-#endif /* STM32F410xx */
-
-#if defined(STM32F413_423xx)
-#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0817FFFF)) ||\
-                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7BDF)))
-#endif /* STM32F413_423xx */
-/**
-  * @}
-  */ 
-
-/** @defgroup Option_Bytes_Write_Protection 
-  * @{
-  */ 
-#define OB_WRP_Sector_0       ((uint32_t)0x00000001) /*!< Write protection of Sector0     */
-#define OB_WRP_Sector_1       ((uint32_t)0x00000002) /*!< Write protection of Sector1     */
-#define OB_WRP_Sector_2       ((uint32_t)0x00000004) /*!< Write protection of Sector2     */
-#define OB_WRP_Sector_3       ((uint32_t)0x00000008) /*!< Write protection of Sector3     */
-#define OB_WRP_Sector_4       ((uint32_t)0x00000010) /*!< Write protection of Sector4     */
-#define OB_WRP_Sector_5       ((uint32_t)0x00000020) /*!< Write protection of Sector5     */
-#define OB_WRP_Sector_6       ((uint32_t)0x00000040) /*!< Write protection of Sector6     */
-#define OB_WRP_Sector_7       ((uint32_t)0x00000080) /*!< Write protection of Sector7     */
-#define OB_WRP_Sector_8       ((uint32_t)0x00000100) /*!< Write protection of Sector8     */
-#define OB_WRP_Sector_9       ((uint32_t)0x00000200) /*!< Write protection of Sector9     */
-#define OB_WRP_Sector_10      ((uint32_t)0x00000400) /*!< Write protection of Sector10    */
-#define OB_WRP_Sector_11      ((uint32_t)0x00000800) /*!< Write protection of Sector11    */
-#define OB_WRP_Sector_12      ((uint32_t)0x00000001) /*!< Write protection of Sector12    */
-#define OB_WRP_Sector_13      ((uint32_t)0x00000002) /*!< Write protection of Sector13    */
-#define OB_WRP_Sector_14      ((uint32_t)0x00000004) /*!< Write protection of Sector14    */
-#define OB_WRP_Sector_15      ((uint32_t)0x00000008) /*!< Write protection of Sector15    */
-#define OB_WRP_Sector_16      ((uint32_t)0x00000010) /*!< Write protection of Sector16    */
-#define OB_WRP_Sector_17      ((uint32_t)0x00000020) /*!< Write protection of Sector17    */
-#define OB_WRP_Sector_18      ((uint32_t)0x00000040) /*!< Write protection of Sector18    */
-#define OB_WRP_Sector_19      ((uint32_t)0x00000080) /*!< Write protection of Sector19    */
-#define OB_WRP_Sector_20      ((uint32_t)0x00000100) /*!< Write protection of Sector20    */
-#define OB_WRP_Sector_21      ((uint32_t)0x00000200) /*!< Write protection of Sector21    */
-#define OB_WRP_Sector_22      ((uint32_t)0x00000400) /*!< Write protection of Sector22    */
-#define OB_WRP_Sector_23      ((uint32_t)0x00000800) /*!< Write protection of Sector23    */
-#define OB_WRP_Sector_All     ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
-
-#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
-/**
-  * @}
-  */
-
-/** @defgroup  Selection_Protection_Mode
-  * @{
-  */
-#define OB_PcROP_Disable   ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
-#define OB_PcROP_Enable    ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i   */
-#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PcROP_Disable) || ((PCROP) == OB_PcROP_Enable))
-/**
-  * @}
-  */
-
-/** @defgroup Option_Bytes_PC_ReadWrite_Protection 
-  * @{
-  */ 
-#define OB_PCROP_Sector_0        ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0      */
-#define OB_PCROP_Sector_1        ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1      */
-#define OB_PCROP_Sector_2        ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2      */
-#define OB_PCROP_Sector_3        ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3      */
-#define OB_PCROP_Sector_4        ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4      */
-#define OB_PCROP_Sector_5        ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5      */
-#define OB_PCROP_Sector_6        ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6      */
-#define OB_PCROP_Sector_7        ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7      */
-#define OB_PCROP_Sector_8        ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8      */
-#define OB_PCROP_Sector_9        ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9      */
-#define OB_PCROP_Sector_10       ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10     */
-#define OB_PCROP_Sector_11       ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11     */
-#define OB_PCROP_Sector_12       ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12     */
-#define OB_PCROP_Sector_13       ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13     */
-#define OB_PCROP_Sector_14       ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14     */
-#define OB_PCROP_Sector_15       ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15     */
-#define OB_PCROP_Sector_16       ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16     */
-#define OB_PCROP_Sector_17       ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17     */
-#define OB_PCROP_Sector_18       ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18     */
-#define OB_PCROP_Sector_19       ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19     */
-#define OB_PCROP_Sector_20       ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20     */
-#define OB_PCROP_Sector_21       ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21     */
-#define OB_PCROP_Sector_22       ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22     */
-#define OB_PCROP_Sector_23       ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23     */
-#define OB_PCROP_Sector_All      ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors  */
-
-#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Option_Bytes_Read_Protection 
-  * @{
-  */
-#define OB_RDP_Level_0   ((uint8_t)0xAA)
-#define OB_RDP_Level_1   ((uint8_t)0x55)
-/*#define OB_RDP_Level_2   ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 
-                                                  it's no more possible to go back to level 1 or 0 */
-#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
-                          ((LEVEL) == OB_RDP_Level_1))/*||\
-                          ((LEVEL) == OB_RDP_Level_2))*/
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Option_Bytes_IWatchdog 
-  * @{
-  */ 
-#define OB_IWDG_SW                     ((uint8_t)0x20)  /*!< Software IWDG selected */
-#define OB_IWDG_HW                     ((uint8_t)0x00)  /*!< Hardware IWDG selected */
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Option_Bytes_nRST_STOP 
-  * @{
-  */ 
-#define OB_STOP_NoRST                  ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST                    ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup FLASH_Option_Bytes_nRST_STDBY 
-  * @{
-  */ 
-#define OB_STDBY_NoRST                 ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST                   ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
-/**
-  * @}
-  */
-  
-/** @defgroup FLASH_BOR_Reset_Level 
-  * @{
-  */  
-#define OB_BOR_LEVEL3          ((uint8_t)0x00)  /*!< Supply voltage ranges from 2.70 to 3.60 V */
-#define OB_BOR_LEVEL2          ((uint8_t)0x04)  /*!< Supply voltage ranges from 2.40 to 2.70 V */
-#define OB_BOR_LEVEL1          ((uint8_t)0x08)  /*!< Supply voltage ranges from 2.10 to 2.40 V */
-#define OB_BOR_OFF             ((uint8_t)0x0C)  /*!< Supply voltage ranges from 1.62 to 2.10 V */
-#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
-                          ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
-/**
-  * @}
-  */
-  
-/** @defgroup FLASH_Dual_Boot
-  * @{
-  */
-#define OB_Dual_BootEnabled   ((uint8_t)0x10) /*!< Dual Bank Boot Enable                             */
-#define OB_Dual_BootDisabled  ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */
-#define IS_OB_BOOT(BOOT) (((BOOT) == OB_Dual_BootEnabled) || ((BOOT) == OB_Dual_BootDisabled))
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Interrupts 
-  * @{
-  */ 
-#define FLASH_IT_EOP                   ((uint32_t)0x01000000)  /*!< End of FLASH Operation Interrupt source */
-#define FLASH_IT_ERR                   ((uint32_t)0x02000000)  /*!< Error Interrupt source */
-#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000))
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Flags 
-  * @{
-  */ 
-#define FLASH_FLAG_EOP                 ((uint32_t)0x00000001)  /*!< FLASH End of Operation flag               */
-#define FLASH_FLAG_OPERR               ((uint32_t)0x00000002)  /*!< FLASH operation Error flag                */
-#define FLASH_FLAG_WRPERR              ((uint32_t)0x00000010)  /*!< FLASH Write protected error flag          */
-#define FLASH_FLAG_PGAERR              ((uint32_t)0x00000020)  /*!< FLASH Programming Alignment error flag    */
-#define FLASH_FLAG_PGPERR              ((uint32_t)0x00000040)  /*!< FLASH Programming Parallelism error flag  */
-#define FLASH_FLAG_PGSERR              ((uint32_t)0x00000080)  /*!< FLASH Programming Sequence error flag     */
-#define FLASH_FLAG_RDERR               ((uint32_t)0x00000100)  /*!< Read Protection error flag (PCROP)        */
-#define FLASH_FLAG_BSY                 ((uint32_t)0x00010000)  /*!< FLASH Busy flag                           */ 
-#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000))
-#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_EOP)    || ((FLAG) == FLASH_FLAG_OPERR)  || \
-                                  ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \
-                                  ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \
-                                  ((FLAG) == FLASH_FLAG_BSY)    || ((FLAG) == FLASH_FLAG_RDERR))
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Program_Parallelism   
-  * @{
-  */
-#define FLASH_PSIZE_BYTE           ((uint32_t)0x00000000)
-#define FLASH_PSIZE_HALF_WORD      ((uint32_t)0x00000100)
-#define FLASH_PSIZE_WORD           ((uint32_t)0x00000200)
-#define FLASH_PSIZE_DOUBLE_WORD    ((uint32_t)0x00000300)
-#define CR_PSIZE_MASK              ((uint32_t)0xFFFFFCFF)
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Keys 
-  * @{
-  */ 
-#define RDP_KEY                  ((uint16_t)0x00A5)
-#define FLASH_KEY1               ((uint32_t)0x45670123)
-#define FLASH_KEY2               ((uint32_t)0xCDEF89AB)
-#define FLASH_OPT_KEY1           ((uint32_t)0x08192A3B)
-#define FLASH_OPT_KEY2           ((uint32_t)0x4C5D6E7F)
-/**
-  * @}
-  */ 
-
-/** 
-  * @brief   ACR register byte 0 (Bits[7:0]) base address  
-  */ 
-#define ACR_BYTE0_ADDRESS           ((uint32_t)0x40023C00) 
-/** 
-  * @brief   OPTCR register byte 0 (Bits[7:0]) base address  
-  */ 
-#define OPTCR_BYTE0_ADDRESS         ((uint32_t)0x40023C14)
-/** 
-  * @brief   OPTCR register byte 1 (Bits[15:8]) base address  
-  */ 
-#define OPTCR_BYTE1_ADDRESS         ((uint32_t)0x40023C15)
-/** 
-  * @brief   OPTCR register byte 2 (Bits[23:16]) base address  
-  */ 
-#define OPTCR_BYTE2_ADDRESS         ((uint32_t)0x40023C16)
-/** 
-  * @brief   OPTCR register byte 3 (Bits[31:24]) base address  
-  */ 
-#define OPTCR_BYTE3_ADDRESS         ((uint32_t)0x40023C17)
-
-/** 
-  * @brief   OPTCR1 register byte 0 (Bits[7:0]) base address  
-  */ 
-#define OPTCR1_BYTE2_ADDRESS         ((uint32_t)0x40023C1A)
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/ 
- 
-/* FLASH Interface configuration functions ************************************/
-void FLASH_SetLatency(uint32_t FLASH_Latency);
-void FLASH_PrefetchBufferCmd(FunctionalState NewState);
-void FLASH_InstructionCacheCmd(FunctionalState NewState);
-void FLASH_DataCacheCmd(FunctionalState NewState);
-void FLASH_InstructionCacheReset(void);
-void FLASH_DataCacheReset(void);
-
-/* FLASH Memory Programming functions *****************************************/   
-void         FLASH_Unlock(void);
-void         FLASH_Lock(void);
-FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange);
-FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange);
-FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange);
-FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange);
-FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data);
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
-FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
-
-/* Option Bytes Programming functions *****************************************/ 
-void         FLASH_OB_Unlock(void);
-void         FLASH_OB_Lock(void);
-void         FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
-void         FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState);
-void         FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP);
-void         FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState);
-void         FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState);
-void         FLASH_OB_RDPConfig(uint8_t OB_RDP);
-void         FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
-void         FLASH_OB_BORConfig(uint8_t OB_BOR);
-void         FLASH_OB_BootConfig(uint8_t OB_BOOT);
-FLASH_Status FLASH_OB_Launch(void);
-uint8_t      FLASH_OB_GetUser(void);
-uint16_t     FLASH_OB_GetWRP(void);
-uint16_t     FLASH_OB_GetWRP1(void);
-uint16_t     FLASH_OB_GetPCROP(void);
-uint16_t     FLASH_OB_GetPCROP1(void);
-FlagStatus   FLASH_OB_GetRDP(void);
-uint8_t      FLASH_OB_GetBOR(void);
-
-/* Interrupts and flags management functions **********************************/
-void         FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
-FlagStatus   FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
-void         FLASH_ClearFlag(uint32_t FLASH_FLAG);
-FLASH_Status FLASH_GetStatus(void);
-FLASH_Status FLASH_WaitForLastOperation(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_FLASH_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash_ramfunc.h

@@ -1,103 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_flash_ramfunc.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   Header file of FLASH RAMFUNC driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_FLASH_RAMFUNC_H
-#define __STM32F4xx_FLASH_RAMFUNC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup FLASH RAMFUNC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** 
-  * @brief  __RAM_FUNC definition
-  */ 
-#if defined ( __CC_ARM   )
-/* ARM Compiler
-   ------------
-   RAM functions are defined using the toolchain options. 
-   Functions that are executed in RAM should reside in a separate source module.
-   Using the 'Options for File' dialog you can simply change the 'Code / Const' 
-   area of a module to a memory space in physical RAM.
-   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
-   dialog. 
-*/
-#define __RAM_FUNC void 
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
-   ---------------
-   RAM functions are defined using a specific toolchain keyword "__ramfunc". 
-*/
-#define __RAM_FUNC __ramfunc void
-
-#elif defined   (  __GNUC__  )
-/* GNU Compiler
-   ------------
-  RAM functions are defined using a specific toolchain attribute 
-   "__attribute__((section(".RamFunc")))".
-*/
-#define __RAM_FUNC void  __attribute__((section(".RamFunc")))
-
-#endif
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-__RAM_FUNC FLASH_FlashInterfaceCmd(FunctionalState NewState);
-__RAM_FUNC FLASH_FlashSleepModeCmd(FunctionalState NewState);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_FLASH_RAMFUNC_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmpi2c.h

@@ -1,474 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_fmpi2c.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the I2C Fast Mode
-  *          Plus firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_FMPI2C_H
-#define __STM32F4xx_FMPI2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup FMPI2C
-  * @{
-  */
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-/* Exported types ------------------------------------------------------------*/
-
-/**
-  * @brief  FMPI2C Init structure definition
-  */
-
-typedef struct
-{
-  uint32_t FMPI2C_Timing;              /*!< Specifies the FMPI2C_TIMINGR_register value.
-                                         This parameter calculated by referring to FMPI2C initialization 
-                                         section in Reference manual*/
-
-  uint32_t FMPI2C_AnalogFilter;        /*!< Enables or disables analog noise filter.
-                                         This parameter can be a value of @ref FMPI2C_Analog_Filter */
-
-  uint32_t FMPI2C_DigitalFilter;       /*!< Configures the digital noise filter.
-                                         This parameter can be a number between 0x00 and 0x0F */
-
-  uint32_t FMPI2C_Mode;                /*!< Specifies the FMPI2C mode.
-                                         This parameter can be a value of @ref FMPI2C_mode */
-
-  uint32_t FMPI2C_OwnAddress1;         /*!< Specifies the device own address 1.
-                                         This parameter can be a 7-bit or 10-bit address */
-
-  uint32_t FMPI2C_Ack;                 /*!< Enables or disables the acknowledgement.
-                                         This parameter can be a value of @ref FMPI2C_acknowledgement */
-
-  uint32_t FMPI2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
-                                         This parameter can be a value of @ref FMPI2C_acknowledged_address */
-}FMPI2C_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-
-/** @defgroup FMPI2C_Exported_Constants
-  * @{
-  */
-
-#define IS_FMPI2C_ALL_PERIPH(PERIPH)       ((PERIPH) == FMPI2C1) 
-
-/** @defgroup FMPI2C_Analog_Filter 
-  * @{
-  */
-
-#define FMPI2C_AnalogFilter_Enable         ((uint32_t)0x00000000)
-#define FMPI2C_AnalogFilter_Disable        FMPI2C_CR1_ANFOFF
-
-#define IS_FMPI2C_ANALOG_FILTER(FILTER)    (((FILTER) == FMPI2C_AnalogFilter_Enable) || \
-                                         ((FILTER) == FMPI2C_AnalogFilter_Disable))
-/**
-  * @}
-  */
-     
-/** @defgroup FMPI2C_Digital_Filter
-  * @{
-  */
-
-#define IS_FMPI2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000F)
-/**
-  * @}
-  */
-
-/** @defgroup FMPI2C_mode 
-  * @{
-  */
-
-#define FMPI2C_Mode_FMPI2C                ((uint32_t)0x00000000)
-#define FMPI2C_Mode_SMBusDevice            FMPI2C_CR1_SMBDEN
-#define FMPI2C_Mode_SMBusHost              FMPI2C_CR1_SMBHEN
-
-#define IS_FMPI2C_MODE(MODE)               (((MODE) == FMPI2C_Mode_FMPI2C) || \
-                                         ((MODE) == FMPI2C_Mode_SMBusDevice) || \
-                                         ((MODE) == FMPI2C_Mode_SMBusHost))
-/**
-  * @}
-  */
-
-/** @defgroup FMPI2C_acknowledgement
-  * @{
-  */
-
-#define FMPI2C_Ack_Enable                  ((uint32_t)0x00000000)
-#define FMPI2C_Ack_Disable                 FMPI2C_CR2_NACK
-
-#define IS_FMPI2C_ACK(ACK)                 (((ACK) == FMPI2C_Ack_Enable) || \
-                                         ((ACK) == FMPI2C_Ack_Disable))
-/**
-  * @}
-  */
-
-/** @defgroup FMPI2C_acknowledged_address
-  * @{
-  */
-
-#define FMPI2C_AcknowledgedAddress_7bit    ((uint32_t)0x00000000)
-#define FMPI2C_AcknowledgedAddress_10bit   FMPI2C_OAR1_OA1MODE
-
-#define IS_FMPI2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == FMPI2C_AcknowledgedAddress_7bit) || \
-                                             ((ADDRESS) == FMPI2C_AcknowledgedAddress_10bit))
-/**
-  * @}
-  */ 
-
-/** @defgroup FMPI2C_own_address1
-  * @{
-  */
-
-#define IS_FMPI2C_OWN_ADDRESS1(ADDRESS1)   ((ADDRESS1) <= (uint32_t)0x000003FF)
-/**
-  * @}
-  */
-
-/** @defgroup FMPI2C_transfer_direction 
-  * @{
-  */
-
-#define FMPI2C_Direction_Transmitter       ((uint16_t)0x0000)
-#define FMPI2C_Direction_Receiver          ((uint16_t)0x0400)
-
-#define IS_FMPI2C_DIRECTION(DIRECTION)     (((DIRECTION) == FMPI2C_Direction_Transmitter) || \
-                                         ((DIRECTION) == FMPI2C_Direction_Receiver))
-/**
-  * @}
-  */
-
-/** @defgroup FMPI2C_DMA_transfer_requests 
-  * @{
-  */
-
-#define FMPI2C_DMAReq_Tx                   FMPI2C_CR1_TXDMAEN
-#define FMPI2C_DMAReq_Rx                   FMPI2C_CR1_RXDMAEN
-
-#define IS_FMPI2C_DMA_REQ(REQ)             ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00))
-/**
-  * @}
-  */
-
-/** @defgroup FMPI2C_slave_address
-  * @{
-  */
-
-#define IS_FMPI2C_SLAVE_ADDRESS(ADDRESS)   ((ADDRESS) <= (uint16_t)0x03FF)
-/**
-  * @}
-  */
-
-
-/** @defgroup FMPI2C_own_address2
-  * @{
-  */
-
-#define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2)   ((ADDRESS2) <= (uint16_t)0x00FF)
-
-/**
-  * @}
-  */
-
-/** @defgroup FMPI2C_own_address2_mask
-  * @{
-  */
-
-#define FMPI2C_OA2_NoMask                  ((uint8_t)0x00)
-#define FMPI2C_OA2_Mask01                  ((uint8_t)0x01)
-#define FMPI2C_OA2_Mask02                  ((uint8_t)0x02)
-#define FMPI2C_OA2_Mask03                  ((uint8_t)0x03)
-#define FMPI2C_OA2_Mask04                  ((uint8_t)0x04)
-#define FMPI2C_OA2_Mask05                  ((uint8_t)0x05)
-#define FMPI2C_OA2_Mask06                  ((uint8_t)0x06)
-#define FMPI2C_OA2_Mask07                  ((uint8_t)0x07)
-
-#define IS_FMPI2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == FMPI2C_OA2_NoMask) || \
-                                         ((MASK) == FMPI2C_OA2_Mask01) || \
-                                         ((MASK) == FMPI2C_OA2_Mask02) || \
-                                         ((MASK) == FMPI2C_OA2_Mask03) || \
-                                         ((MASK) == FMPI2C_OA2_Mask04) || \
-                                         ((MASK) == FMPI2C_OA2_Mask05) || \
-                                         ((MASK) == FMPI2C_OA2_Mask06) || \
-                                         ((MASK) == FMPI2C_OA2_Mask07))  
-
-/**
-  * @}
-  */
-
-/** @defgroup FMPI2C_timeout
-  * @{
-  */
-
-#define IS_FMPI2C_TIMEOUT(TIMEOUT)   ((TIMEOUT) <= (uint16_t)0x0FFF)
-
-/**
-  * @}
-  */
-
-/** @defgroup FMPI2C_registers 
-  * @{
-  */
-
-#define FMPI2C_Register_CR1                ((uint8_t)0x00)
-#define FMPI2C_Register_CR2                ((uint8_t)0x04)
-#define FMPI2C_Register_OAR1               ((uint8_t)0x08)
-#define FMPI2C_Register_OAR2               ((uint8_t)0x0C)
-#define FMPI2C_Register_TIMINGR            ((uint8_t)0x10)
-#define FMPI2C_Register_TIMEOUTR           ((uint8_t)0x14)
-#define FMPI2C_Register_ISR                ((uint8_t)0x18)
-#define FMPI2C_Register_ICR                ((uint8_t)0x1C)
-#define FMPI2C_Register_PECR               ((uint8_t)0x20)
-#define FMPI2C_Register_RXDR               ((uint8_t)0x24)
-#define FMPI2C_Register_TXDR               ((uint8_t)0x28)
-
-#define IS_FMPI2C_REGISTER(REGISTER)       (((REGISTER) == FMPI2C_Register_CR1) || \
-                                         ((REGISTER) == FMPI2C_Register_CR2) || \
-                                         ((REGISTER) == FMPI2C_Register_OAR1) || \
-                                         ((REGISTER) == FMPI2C_Register_OAR2) || \
-                                         ((REGISTER) == FMPI2C_Register_TIMINGR) || \
-                                         ((REGISTER) == FMPI2C_Register_TIMEOUTR) || \
-                                         ((REGISTER) == FMPI2C_Register_ISR) || \
-                                         ((REGISTER) == FMPI2C_Register_ICR) || \
-                                         ((REGISTER) == FMPI2C_Register_PECR) || \
-                                         ((REGISTER) == FMPI2C_Register_RXDR) || \
-                                         ((REGISTER) == FMPI2C_Register_TXDR))
-/**
-  * @}
-  */
-
-/** @defgroup FMPI2C_interrupts_definition 
-  * @{
-  */
-
-#define FMPI2C_IT_ERRI                     FMPI2C_CR1_ERRIE
-#define FMPI2C_IT_TCI                      FMPI2C_CR1_TCIE
-#define FMPI2C_IT_STOPI                    FMPI2C_CR1_STOPIE
-#define FMPI2C_IT_NACKI                    FMPI2C_CR1_NACKIE
-#define FMPI2C_IT_ADDRI                    FMPI2C_CR1_ADDRIE
-#define FMPI2C_IT_RXI                      FMPI2C_CR1_RXIE
-#define FMPI2C_IT_TXI                      FMPI2C_CR1_TXIE
-
-#define IS_FMPI2C_CONFIG_IT(IT)            ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00))
-
-/**
-  * @}
-  */
-
-/** @defgroup FMPI2C_flags_definition 
-  * @{
-  */
-
-#define  FMPI2C_FLAG_TXE                   FMPI2C_ISR_TXE
-#define  FMPI2C_FLAG_TXIS                  FMPI2C_ISR_TXIS
-#define  FMPI2C_FLAG_RXNE                  FMPI2C_ISR_RXNE
-#define  FMPI2C_FLAG_ADDR                  FMPI2C_ISR_ADDR
-#define  FMPI2C_FLAG_NACKF                 FMPI2C_ISR_NACKF
-#define  FMPI2C_FLAG_STOPF                 FMPI2C_ISR_STOPF
-#define  FMPI2C_FLAG_TC                    FMPI2C_ISR_TC
-#define  FMPI2C_FLAG_TCR                   FMPI2C_ISR_TCR
-#define  FMPI2C_FLAG_BERR                  FMPI2C_ISR_BERR
-#define  FMPI2C_FLAG_ARLO                  FMPI2C_ISR_ARLO
-#define  FMPI2C_FLAG_OVR                   FMPI2C_ISR_OVR
-#define  FMPI2C_FLAG_PECERR                FMPI2C_ISR_PECERR
-#define  FMPI2C_FLAG_TIMEOUT               FMPI2C_ISR_TIMEOUT
-#define  FMPI2C_FLAG_ALERT                 FMPI2C_ISR_ALERT
-#define  FMPI2C_FLAG_BUSY                  FMPI2C_ISR_BUSY
-
-#define IS_FMPI2C_CLEAR_FLAG(FLAG)         ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00))
-
-#define IS_FMPI2C_GET_FLAG(FLAG)           (((FLAG) == FMPI2C_FLAG_TXE) || ((FLAG) == FMPI2C_FLAG_TXIS) || \
-                                         ((FLAG) == FMPI2C_FLAG_RXNE) || ((FLAG) == FMPI2C_FLAG_ADDR) || \
-                                         ((FLAG) == FMPI2C_FLAG_NACKF) || ((FLAG) == FMPI2C_FLAG_STOPF) || \
-                                         ((FLAG) == FMPI2C_FLAG_TC) || ((FLAG) == FMPI2C_FLAG_TCR) || \
-                                         ((FLAG) == FMPI2C_FLAG_BERR) || ((FLAG) == FMPI2C_FLAG_ARLO) || \
-                                         ((FLAG) == FMPI2C_FLAG_OVR) || ((FLAG) == FMPI2C_FLAG_PECERR) || \
-                                         ((FLAG) == FMPI2C_FLAG_TIMEOUT) || ((FLAG) == FMPI2C_FLAG_ALERT) || \
-                                         ((FLAG) == FMPI2C_FLAG_BUSY))
-
-/**
-  * @}
-  */
-
-
-/** @defgroup FMPI2C_interrupts_definition 
-  * @{
-  */
-
-#define  FMPI2C_IT_TXIS                    FMPI2C_ISR_TXIS
-#define  FMPI2C_IT_RXNE                    FMPI2C_ISR_RXNE
-#define  FMPI2C_IT_ADDR                    FMPI2C_ISR_ADDR
-#define  FMPI2C_IT_NACKF                   FMPI2C_ISR_NACKF
-#define  FMPI2C_IT_STOPF                   FMPI2C_ISR_STOPF
-#define  FMPI2C_IT_TC                      FMPI2C_ISR_TC
-#define  FMPI2C_IT_TCR                     FMPI2C_ISR_TCR
-#define  FMPI2C_IT_BERR                    FMPI2C_ISR_BERR
-#define  FMPI2C_IT_ARLO                    FMPI2C_ISR_ARLO
-#define  FMPI2C_IT_OVR                     FMPI2C_ISR_OVR
-#define  FMPI2C_IT_PECERR                  FMPI2C_ISR_PECERR
-#define  FMPI2C_IT_TIMEOUT                 FMPI2C_ISR_TIMEOUT
-#define  FMPI2C_IT_ALERT                   FMPI2C_ISR_ALERT
-
-#define IS_FMPI2C_CLEAR_IT(IT)             ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00))
-                               
-#define IS_FMPI2C_GET_IT(IT)               (((IT) == FMPI2C_IT_TXIS) || ((IT) == FMPI2C_IT_RXNE) || \
-                                         ((IT) == FMPI2C_IT_ADDR) || ((IT) == FMPI2C_IT_NACKF) || \
-                                         ((IT) == FMPI2C_IT_STOPF) || ((IT) == FMPI2C_IT_TC) || \
-                                         ((IT) == FMPI2C_IT_TCR) || ((IT) == FMPI2C_IT_BERR) || \
-                                         ((IT) == FMPI2C_IT_ARLO) || ((IT) == FMPI2C_IT_OVR) || \
-                                         ((IT) == FMPI2C_IT_PECERR) || ((IT) == FMPI2C_IT_TIMEOUT) || \
-                                         ((IT) == FMPI2C_IT_ALERT))
-
-/**
-  * @}
-  */
-
-/** @defgroup FMPI2C_ReloadEndMode_definition 
-  * @{
-  */
-
-#define  FMPI2C_Reload_Mode                FMPI2C_CR2_RELOAD
-#define  FMPI2C_AutoEnd_Mode               FMPI2C_CR2_AUTOEND
-#define  FMPI2C_SoftEnd_Mode               ((uint32_t)0x00000000)
-
-                              
-#define IS_RELOAD_END_MODE(MODE)        (((MODE) == FMPI2C_Reload_Mode) || \
-                                         ((MODE) == FMPI2C_AutoEnd_Mode) || \
-                                         ((MODE) == FMPI2C_SoftEnd_Mode))
-                               
-
-/**
-  * @}
-  */
-
-/** @defgroup FMPI2C_StartStopMode_definition 
-  * @{
-  */
-
-#define  FMPI2C_No_StartStop                 ((uint32_t)0x00000000)
-#define  FMPI2C_Generate_Stop                FMPI2C_CR2_STOP
-#define  FMPI2C_Generate_Start_Read          (uint32_t)(FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN)
-#define  FMPI2C_Generate_Start_Write         FMPI2C_CR2_START
-
-                              
-#define IS_START_STOP_MODE(MODE)        (((MODE) == FMPI2C_Generate_Stop) || \
-                                         ((MODE) == FMPI2C_Generate_Start_Read) || \
-                                         ((MODE) == FMPI2C_Generate_Start_Write) || \
-                                         ((MODE) == FMPI2C_No_StartStop))
-                               
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-
-/* Initialization and Configuration functions *********************************/
-void FMPI2C_DeInit(FMPI2C_TypeDef* FMPI2Cx);
-void FMPI2C_Init(FMPI2C_TypeDef* FMPI2Cx, FMPI2C_InitTypeDef* FMPI2C_InitStruct);
-void FMPI2C_StructInit(FMPI2C_InitTypeDef* FMPI2C_InitStruct);
-void FMPI2C_Cmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_SoftwareResetCmd(FMPI2C_TypeDef* FMPI2Cx);
-void FMPI2C_ITConfig(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_IT, FunctionalState NewState);
-void FMPI2C_StretchClockCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_DualAddressCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_OwnAddress2Config(FMPI2C_TypeDef* FMPI2Cx, uint16_t Address, uint8_t Mask);
-void FMPI2C_GeneralCallCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_SlaveByteControlCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_SlaveAddressConfig(FMPI2C_TypeDef* FMPI2Cx, uint16_t Address);
-void FMPI2C_10BitAddressingModeCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-
-/* Communications handling functions ******************************************/
-void FMPI2C_AutoEndCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_ReloadCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_NumberOfBytesConfig(FMPI2C_TypeDef* FMPI2Cx, uint8_t Number_Bytes);
-void FMPI2C_MasterRequestConfig(FMPI2C_TypeDef* FMPI2Cx, uint16_t FMPI2C_Direction);
-void FMPI2C_GenerateSTART(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_GenerateSTOP(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_10BitAddressHeaderCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_AcknowledgeConfig(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-uint8_t FMPI2C_GetAddressMatched(FMPI2C_TypeDef* FMPI2Cx);
-uint16_t FMPI2C_GetTransferDirection(FMPI2C_TypeDef* FMPI2Cx);
-void FMPI2C_TransferHandling(FMPI2C_TypeDef* FMPI2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode);
-
-/*  SMBUS management functions ************************************************/
-void FMPI2C_SMBusAlertCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_ClockTimeoutCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_ExtendedClockTimeoutCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_IdleClockTimeoutCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_TimeoutAConfig(FMPI2C_TypeDef* FMPI2Cx, uint16_t Timeout);
-void FMPI2C_TimeoutBConfig(FMPI2C_TypeDef* FMPI2Cx, uint16_t Timeout);
-void FMPI2C_CalculatePEC(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-void FMPI2C_PECRequestCmd(FMPI2C_TypeDef* FMPI2Cx, FunctionalState NewState);
-uint8_t FMPI2C_GetPEC(FMPI2C_TypeDef* FMPI2Cx);
-
-/* FMPI2C registers management functions *****************************************/
-uint32_t FMPI2C_ReadRegister(FMPI2C_TypeDef* FMPI2Cx, uint8_t FMPI2C_Register);
-
-/* Data transfers management functions ****************************************/
-void FMPI2C_SendData(FMPI2C_TypeDef* FMPI2Cx, uint8_t Data);
-uint8_t FMPI2C_ReceiveData(FMPI2C_TypeDef* FMPI2Cx);
-
-/* DMA transfers management functions *****************************************/
-void FMPI2C_DMACmd(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_DMAReq, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-FlagStatus FMPI2C_GetFlagStatus(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_FLAG);
-void FMPI2C_ClearFlag(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_FLAG);
-ITStatus FMPI2C_GetITStatus(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_IT);
-void FMPI2C_ClearITPendingBit(FMPI2C_TypeDef* FMPI2Cx, uint32_t FMPI2C_IT);
-
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_FMPI2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h

@@ -1,675 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_fsmc.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the FSMC firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_FSMC_H
-#define __STM32F4xx_FSMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup FSMC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  Timing parameters For NOR/SRAM Banks  
-  */
-typedef struct
-{
-  uint32_t FSMC_AddressSetupTime;       /*!< Defines the number of HCLK cycles to configure
-                                             the duration of the address setup time. 
-                                             This parameter can be a value between 0 and 0xF.
-                                             @note This parameter is not used with synchronous NOR Flash memories. */
-
-  uint32_t FSMC_AddressHoldTime;        /*!< Defines the number of HCLK cycles to configure
-                                             the duration of the address hold time.
-                                             This parameter can be a value between 0 and 0xF. 
-                                             @note This parameter is not used with synchronous NOR Flash memories.*/
-
-  uint32_t FSMC_DataSetupTime;          /*!< Defines the number of HCLK cycles to configure
-                                             the duration of the data setup time.
-                                             This parameter can be a value between 0 and 0xFF.
-                                             @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
-
-  uint32_t FSMC_BusTurnAroundDuration;  /*!< Defines the number of HCLK cycles to configure
-                                             the duration of the bus turnaround.
-                                             This parameter can be a value between 0 and 0xF.
-                                             @note This parameter is only used for multiplexed NOR Flash memories. */
-
-  uint32_t FSMC_CLKDivision;            /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
-                                             This parameter can be a value between 1 and 0xF.
-                                             @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
-
-  uint32_t FSMC_DataLatency;            /*!< Defines the number of memory clock cycles to issue
-                                             to the memory before getting the first data.
-                                             The parameter value depends on the memory type as shown below:
-                                              - It must be set to 0 in case of a CRAM
-                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
-                                              - It may assume a value between 0 and 0xF in NOR Flash memories
-                                                with synchronous burst mode enable */
-
-  uint32_t FSMC_AccessMode;             /*!< Specifies the asynchronous access mode. 
-                                             This parameter can be a value of @ref FSMC_Access_Mode */
-}FSMC_NORSRAMTimingInitTypeDef;
-
-/** 
-  * @brief  FSMC NOR/SRAM Init structure definition
-  */
-typedef struct
-{
-  uint32_t FSMC_Bank;                /*!< Specifies the NOR/SRAM memory bank that will be used.
-                                          This parameter can be a value of @ref FSMC_NORSRAM_Bank */
-
-  uint32_t FSMC_DataAddressMux;      /*!< Specifies whether the address and data values are
-                                          multiplexed on the data bus or not. 
-                                          This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
-
-  uint32_t FSMC_MemoryType;          /*!< Specifies the type of external memory attached to
-                                          the corresponding memory bank.
-                                          This parameter can be a value of @ref FSMC_Memory_Type */
-
-  uint32_t FSMC_MemoryDataWidth;     /*!< Specifies the external memory device width.
-                                          This parameter can be a value of @ref FSMC_Data_Width */
-
-  uint32_t FSMC_BurstAccessMode;     /*!< Enables or disables the burst access mode for Flash memory,
-                                          valid only with synchronous burst Flash memories.
-                                          This parameter can be a value of @ref FSMC_Burst_Access_Mode */
-
-  uint32_t FSMC_AsynchronousWait;     /*!< Enables or disables wait signal during asynchronous transfers,
-                                          valid only with asynchronous Flash memories.
-                                          This parameter can be a value of @ref FSMC_AsynchronousWait */                                          
-
-  uint32_t FSMC_WaitSignalPolarity;  /*!< Specifies the wait signal polarity, valid only when accessing
-                                          the Flash memory in burst mode.
-                                          This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
-
-  uint32_t FSMC_WrapMode;            /*!< Enables or disables the Wrapped burst access mode for Flash
-                                          memory, valid only when accessing Flash memories in burst mode.
-                                          This parameter can be a value of @ref FSMC_Wrap_Mode */
-
-  uint32_t FSMC_WaitSignalActive;    /*!< Specifies if the wait signal is asserted by the memory one
-                                          clock cycle before the wait state or during the wait state,
-                                          valid only when accessing memories in burst mode. 
-                                          This parameter can be a value of @ref FSMC_Wait_Timing */
-
-  uint32_t FSMC_WriteOperation;      /*!< Enables or disables the write operation in the selected bank by the FSMC. 
-                                          This parameter can be a value of @ref FSMC_Write_Operation */
-
-  uint32_t FSMC_WaitSignal;          /*!< Enables or disables the wait state insertion via wait
-                                          signal, valid for Flash memory access in burst mode. 
-                                          This parameter can be a value of @ref FSMC_Wait_Signal */
-
-  uint32_t FSMC_ExtendedMode;        /*!< Enables or disables the extended mode.
-                                          This parameter can be a value of @ref FSMC_Extended_Mode */
-
-  uint32_t FSMC_WriteBurst;          /*!< Enables or disables the write burst operation.
-                                          This parameter can be a value of @ref FSMC_Write_Burst */ 
-
-  FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the  Extended Mode is not used*/  
-
-  FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;     /*!< Timing Parameters for write access if the  Extended Mode is used*/      
-}FSMC_NORSRAMInitTypeDef;
-
-/** 
-  * @brief  Timing parameters For FSMC NAND and PCCARD Banks
-  */
-typedef struct
-{
-  uint32_t FSMC_SetupTime;      /*!< Defines the number of HCLK cycles to setup address before
-                                     the command assertion for NAND Flash read or write access
-                                     to common/Attribute or I/O memory space (depending on
-                                     the memory space timing to be configured).
-                                     This parameter can be a value between 0 and 0xFF.*/
-
-  uint32_t FSMC_WaitSetupTime;  /*!< Defines the minimum number of HCLK cycles to assert the
-                                     command for NAND Flash read or write access to
-                                     common/Attribute or I/O memory space (depending on the
-                                     memory space timing to be configured). 
-                                     This parameter can be a number between 0x00 and 0xFF */
-
-  uint32_t FSMC_HoldSetupTime;  /*!< Defines the number of HCLK clock cycles to hold address
-                                     (and data for write access) after the command de-assertion
-                                     for NAND Flash read or write access to common/Attribute
-                                     or I/O memory space (depending on the memory space timing
-                                     to be configured).
-                                     This parameter can be a number between 0x00 and 0xFF */
-
-  uint32_t FSMC_HiZSetupTime;   /*!< Defines the number of HCLK clock cycles during which the
-                                     data bus is kept in HiZ after the start of a NAND Flash
-                                     write access to common/Attribute or I/O memory space (depending
-                                     on the memory space timing to be configured).
-                                     This parameter can be a number between 0x00 and 0xFF */
-}FSMC_NAND_PCCARDTimingInitTypeDef;
-
-/** 
-  * @brief  FSMC NAND Init structure definition
-  */
-typedef struct
-{
-  uint32_t FSMC_Bank;              /*!< Specifies the NAND memory bank that will be used.
-                                      This parameter can be a value of @ref FSMC_NAND_Bank */
-
-  uint32_t FSMC_Waitfeature;      /*!< Enables or disables the Wait feature for the NAND Memory Bank.
-                                       This parameter can be any value of @ref FSMC_Wait_feature */
-
-  uint32_t FSMC_MemoryDataWidth;  /*!< Specifies the external memory device width.
-                                       This parameter can be any value of @ref FSMC_Data_Width */
-
-  uint32_t FSMC_ECC;              /*!< Enables or disables the ECC computation.
-                                       This parameter can be any value of @ref FSMC_ECC */
-
-  uint32_t FSMC_ECCPageSize;      /*!< Defines the page size for the extended ECC.
-                                       This parameter can be any value of @ref FSMC_ECC_Page_Size */
-
-  uint32_t FSMC_TCLRSetupTime;    /*!< Defines the number of HCLK cycles to configure the
-                                       delay between CLE low and RE low.
-                                       This parameter can be a value between 0 and 0xFF. */
-
-  uint32_t FSMC_TARSetupTime;     /*!< Defines the number of HCLK cycles to configure the
-                                       delay between ALE low and RE low.
-                                       This parameter can be a number between 0x0 and 0xFF */ 
-
-  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;   /*!< FSMC Common Space Timing */ 
-
-  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
-}FSMC_NANDInitTypeDef;
-
-/** 
-  * @brief  FSMC PCCARD Init structure definition
-  */
-
-typedef struct
-{
-  uint32_t FSMC_Waitfeature;    /*!< Enables or disables the Wait feature for the Memory Bank.
-                                    This parameter can be any value of @ref FSMC_Wait_feature */
-
-  uint32_t FSMC_TCLRSetupTime;  /*!< Defines the number of HCLK cycles to configure the
-                                     delay between CLE low and RE low.
-                                     This parameter can be a value between 0 and 0xFF. */
-
-  uint32_t FSMC_TARSetupTime;   /*!< Defines the number of HCLK cycles to configure the
-                                     delay between ALE low and RE low.
-                                     This parameter can be a number between 0x0 and 0xFF */ 
-
-  
-  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
-
-  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;  /*!< FSMC Attribute Space Timing */ 
-  
-  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */  
-}FSMC_PCCARDInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FSMC_Exported_Constants
-  * @{
-  */
-
-/** @defgroup FSMC_NORSRAM_Bank 
-  * @{
-  */
-#define FSMC_Bank1_NORSRAM1                      ((uint32_t)0x00000000)
-#define FSMC_Bank1_NORSRAM2                      ((uint32_t)0x00000002)
-#define FSMC_Bank1_NORSRAM3                      ((uint32_t)0x00000004)
-#define FSMC_Bank1_NORSRAM4                      ((uint32_t)0x00000006)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_NAND_Bank 
-  * @{
-  */  
-#define FSMC_Bank2_NAND                          ((uint32_t)0x00000010)
-#define FSMC_Bank3_NAND                          ((uint32_t)0x00000100)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_PCCARD_Bank 
-  * @{
-  */    
-#define FSMC_Bank4_PCCARD                        ((uint32_t)0x00001000)
-/**
-  * @}
-  */
-
-#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
-                                    ((BANK) == FSMC_Bank1_NORSRAM2) || \
-                                    ((BANK) == FSMC_Bank1_NORSRAM3) || \
-                                    ((BANK) == FSMC_Bank1_NORSRAM4))
-
-#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
-                                 ((BANK) == FSMC_Bank3_NAND))
-
-#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
-                                    ((BANK) == FSMC_Bank3_NAND) || \
-                                    ((BANK) == FSMC_Bank4_PCCARD))
-
-#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
-                               ((BANK) == FSMC_Bank3_NAND) || \
-                               ((BANK) == FSMC_Bank4_PCCARD))
-
-/** @defgroup FSMC_NOR_SRAM_Controller 
-  * @{
-  */
-
-/** @defgroup FSMC_Data_Address_Bus_Multiplexing 
-  * @{
-  */
-
-#define FSMC_DataAddressMux_Disable                ((uint32_t)0x00000000)
-#define FSMC_DataAddressMux_Enable                 ((uint32_t)0x00000002)
-#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
-                          ((MUX) == FSMC_DataAddressMux_Enable))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Memory_Type 
-  * @{
-  */
-
-#define FSMC_MemoryType_SRAM                     ((uint32_t)0x00000000)
-#define FSMC_MemoryType_PSRAM                    ((uint32_t)0x00000004)
-#define FSMC_MemoryType_NOR                      ((uint32_t)0x00000008)
-#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
-                                ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
-                                ((MEMORY) == FSMC_MemoryType_NOR))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Data_Width 
-  * @{
-  */
-
-#define FSMC_MemoryDataWidth_8b                  ((uint32_t)0x00000000)
-#define FSMC_MemoryDataWidth_16b                 ((uint32_t)0x00000010)
-#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
-                                     ((WIDTH) == FSMC_MemoryDataWidth_16b))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Burst_Access_Mode 
-  * @{
-  */
-
-#define FSMC_BurstAccessMode_Disable             ((uint32_t)0x00000000) 
-#define FSMC_BurstAccessMode_Enable              ((uint32_t)0x00000100)
-#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
-                                  ((STATE) == FSMC_BurstAccessMode_Enable))
-/**
-  * @}
-  */
-    
-/** @defgroup FSMC_AsynchronousWait 
-  * @{
-  */
-#define FSMC_AsynchronousWait_Disable            ((uint32_t)0x00000000)
-#define FSMC_AsynchronousWait_Enable             ((uint32_t)0x00008000)
-#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
-                                 ((STATE) == FSMC_AsynchronousWait_Enable))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wait_Signal_Polarity 
-  * @{
-  */
-#define FSMC_WaitSignalPolarity_Low              ((uint32_t)0x00000000)
-#define FSMC_WaitSignalPolarity_High             ((uint32_t)0x00000200)
-#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
-                                         ((POLARITY) == FSMC_WaitSignalPolarity_High))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wrap_Mode 
-  * @{
-  */
-#define FSMC_WrapMode_Disable                    ((uint32_t)0x00000000)
-#define FSMC_WrapMode_Enable                     ((uint32_t)0x00000400) 
-#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
-                                 ((MODE) == FSMC_WrapMode_Enable))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wait_Timing 
-  * @{
-  */
-#define FSMC_WaitSignalActive_BeforeWaitState    ((uint32_t)0x00000000)
-#define FSMC_WaitSignalActive_DuringWaitState    ((uint32_t)0x00000800) 
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
-                                            ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Write_Operation 
-  * @{
-  */
-#define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
-#define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
-#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
-                                            ((OPERATION) == FSMC_WriteOperation_Enable))                         
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wait_Signal 
-  * @{
-  */
-#define FSMC_WaitSignal_Disable                  ((uint32_t)0x00000000)
-#define FSMC_WaitSignal_Enable                   ((uint32_t)0x00002000) 
-#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
-                                      ((SIGNAL) == FSMC_WaitSignal_Enable))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Extended_Mode 
-  * @{
-  */
-#define FSMC_ExtendedMode_Disable                ((uint32_t)0x00000000)
-#define FSMC_ExtendedMode_Enable                 ((uint32_t)0x00004000)
-
-#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
-                                     ((MODE) == FSMC_ExtendedMode_Enable)) 
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Write_Burst 
-  * @{
-  */
-
-#define FSMC_WriteBurst_Disable                  ((uint32_t)0x00000000)
-#define FSMC_WriteBurst_Enable                   ((uint32_t)0x00080000) 
-#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
-                                    ((BURST) == FSMC_WriteBurst_Enable))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Address_Setup_Time 
-  * @{
-  */
-#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Address_Hold_Time 
-  * @{
-  */
-#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Data_Setup_Time 
-  * @{
-  */
-#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Bus_Turn_around_Duration 
-  * @{
-  */
-#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_CLK_Division 
-  * @{
-  */
-#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Data_Latency 
-  * @{
-  */
-#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Access_Mode 
-  * @{
-  */
-#define FSMC_AccessMode_A                        ((uint32_t)0x00000000)
-#define FSMC_AccessMode_B                        ((uint32_t)0x10000000) 
-#define FSMC_AccessMode_C                        ((uint32_t)0x20000000)
-#define FSMC_AccessMode_D                        ((uint32_t)0x30000000)
-#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
-                                   ((MODE) == FSMC_AccessMode_B) || \
-                                   ((MODE) == FSMC_AccessMode_C) || \
-                                   ((MODE) == FSMC_AccessMode_D))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/** @defgroup FSMC_NAND_PCCARD_Controller 
-  * @{
-  */
-
-/** @defgroup FSMC_Wait_feature 
-  * @{
-  */
-#define FSMC_Waitfeature_Disable                 ((uint32_t)0x00000000)
-#define FSMC_Waitfeature_Enable                  ((uint32_t)0x00000002)
-#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
-                                       ((FEATURE) == FSMC_Waitfeature_Enable))
-/**
-  * @}
-  */
-
-
-/** @defgroup FSMC_ECC 
-  * @{
-  */
-#define FSMC_ECC_Disable                         ((uint32_t)0x00000000)
-#define FSMC_ECC_Enable                          ((uint32_t)0x00000040)
-#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
-                                  ((STATE) == FSMC_ECC_Enable))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_ECC_Page_Size 
-  * @{
-  */
-#define FSMC_ECCPageSize_256Bytes                ((uint32_t)0x00000000)
-#define FSMC_ECCPageSize_512Bytes                ((uint32_t)0x00020000)
-#define FSMC_ECCPageSize_1024Bytes               ((uint32_t)0x00040000)
-#define FSMC_ECCPageSize_2048Bytes               ((uint32_t)0x00060000)
-#define FSMC_ECCPageSize_4096Bytes               ((uint32_t)0x00080000)
-#define FSMC_ECCPageSize_8192Bytes               ((uint32_t)0x000A0000)
-#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
-                                    ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
-                                    ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
-                                    ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
-                                    ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
-                                    ((SIZE) == FSMC_ECCPageSize_8192Bytes))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_TCLR_Setup_Time 
-  * @{
-  */
-#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_TAR_Setup_Time 
-  * @{
-  */
-#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Setup_Time 
-  * @{
-  */
-#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wait_Setup_Time 
-  * @{
-  */
-#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Hold_Setup_Time 
-  * @{
-  */
-#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_HiZ_Setup_Time 
-  * @{
-  */
-#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Interrupt_sources 
-  * @{
-  */
-#define FSMC_IT_RisingEdge                       ((uint32_t)0x00000008)
-#define FSMC_IT_Level                            ((uint32_t)0x00000010)
-#define FSMC_IT_FallingEdge                      ((uint32_t)0x00000020)
-#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
-#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
-                            ((IT) == FSMC_IT_Level) || \
-                            ((IT) == FSMC_IT_FallingEdge)) 
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Flags 
-  * @{
-  */
-#define FSMC_FLAG_RisingEdge                     ((uint32_t)0x00000001)
-#define FSMC_FLAG_Level                          ((uint32_t)0x00000002)
-#define FSMC_FLAG_FallingEdge                    ((uint32_t)0x00000004)
-#define FSMC_FLAG_FEMPT                          ((uint32_t)0x00000040)
-#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
-                                ((FLAG) == FSMC_FLAG_Level) || \
-                                ((FLAG) == FSMC_FLAG_FallingEdge) || \
-                                ((FLAG) == FSMC_FLAG_FEMPT))
-
-#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/ 
-
-/* NOR/SRAM Controller functions **********************************************/
-void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
-void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
-void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
-void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-
-/* NAND Controller functions **************************************************/
-void FSMC_NANDDeInit(uint32_t FSMC_Bank);
-void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
-void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
-void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
-uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
-
-/* PCCARD Controller functions ************************************************/
-void FSMC_PCCARDDeInit(void);
-void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
-void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
-void FSMC_PCCARDCmd(FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
-FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
-void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
-ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
-void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_FSMC_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h

@@ -1,592 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_gpio.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the GPIO firmware
-  *          library.  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_GPIO_H
-#define __STM32F4xx_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup GPIO
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
-                                    ((PERIPH) == GPIOB) || \
-                                    ((PERIPH) == GPIOC) || \
-                                    ((PERIPH) == GPIOD) || \
-                                    ((PERIPH) == GPIOE) || \
-                                    ((PERIPH) == GPIOF) || \
-                                    ((PERIPH) == GPIOG) || \
-                                    ((PERIPH) == GPIOH) || \
-                                    ((PERIPH) == GPIOI) || \
-                                    ((PERIPH) == GPIOJ) || \
-                                    ((PERIPH) == GPIOK))
-
-/** 
-  * @brief  GPIO Configuration Mode enumeration 
-  */   
-typedef enum
-{ 
-  GPIO_Mode_IN   = 0x00, /*!< GPIO Input Mode */
-  GPIO_Mode_OUT  = 0x01, /*!< GPIO Output Mode */
-  GPIO_Mode_AF   = 0x02, /*!< GPIO Alternate function Mode */
-  GPIO_Mode_AN   = 0x03  /*!< GPIO Analog Mode */
-}GPIOMode_TypeDef;
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)  || ((MODE) == GPIO_Mode_OUT) || \
-                            ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
-
-/** 
-  * @brief  GPIO Output type enumeration 
-  */  
-typedef enum
-{ 
-  GPIO_OType_PP = 0x00,
-  GPIO_OType_OD = 0x01
-}GPIOOType_TypeDef;
-#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
-
-
-/** 
-  * @brief  GPIO Output Maximum frequency enumeration 
-  */  
-typedef enum
-{ 
-  GPIO_Low_Speed     = 0x00, /*!< Low speed    */
-  GPIO_Medium_Speed  = 0x01, /*!< Medium speed */
-  GPIO_Fast_Speed    = 0x02, /*!< Fast speed   */
-  GPIO_High_Speed    = 0x03  /*!< High speed   */
-}GPIOSpeed_TypeDef;
-
-/* Add legacy definition */
-#define  GPIO_Speed_2MHz    GPIO_Low_Speed    
-#define  GPIO_Speed_25MHz   GPIO_Medium_Speed 
-#define  GPIO_Speed_50MHz   GPIO_Fast_Speed 
-#define  GPIO_Speed_100MHz  GPIO_High_Speed  
-  
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \
-                              ((SPEED) == GPIO_Fast_Speed)||  ((SPEED) == GPIO_High_Speed)) 
-
-/** 
-  * @brief  GPIO Configuration PullUp PullDown enumeration 
-  */ 
-typedef enum
-{ 
-  GPIO_PuPd_NOPULL = 0x00,
-  GPIO_PuPd_UP     = 0x01,
-  GPIO_PuPd_DOWN   = 0x02
-}GPIOPuPd_TypeDef;
-#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
-                            ((PUPD) == GPIO_PuPd_DOWN))
-
-/** 
-  * @brief  GPIO Bit SET and Bit RESET enumeration 
-  */ 
-typedef enum
-{ 
-  Bit_RESET = 0,
-  Bit_SET
-}BitAction;
-#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
-
-
-/** 
-  * @brief   GPIO Init structure definition  
-  */ 
-typedef struct
-{
-  uint32_t GPIO_Pin;              /*!< Specifies the GPIO pins to be configured.
-                                       This parameter can be any value of @ref GPIO_pins_define */
-
-  GPIOMode_TypeDef GPIO_Mode;     /*!< Specifies the operating mode for the selected pins.
-                                       This parameter can be a value of @ref GPIOMode_TypeDef */
-
-  GPIOSpeed_TypeDef GPIO_Speed;   /*!< Specifies the speed for the selected pins.
-                                       This parameter can be a value of @ref GPIOSpeed_TypeDef */
-
-  GPIOOType_TypeDef GPIO_OType;   /*!< Specifies the operating output type for the selected pins.
-                                       This parameter can be a value of @ref GPIOOType_TypeDef */
-
-  GPIOPuPd_TypeDef GPIO_PuPd;     /*!< Specifies the operating Pull-up/Pull down for the selected pins.
-                                       This parameter can be a value of @ref GPIOPuPd_TypeDef */
-}GPIO_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants
-  * @{
-  */ 
-
-/** @defgroup GPIO_pins_define 
-  * @{
-  */ 
-#define GPIO_Pin_0                 ((uint16_t)0x0001)  /* Pin 0 selected */
-#define GPIO_Pin_1                 ((uint16_t)0x0002)  /* Pin 1 selected */
-#define GPIO_Pin_2                 ((uint16_t)0x0004)  /* Pin 2 selected */
-#define GPIO_Pin_3                 ((uint16_t)0x0008)  /* Pin 3 selected */
-#define GPIO_Pin_4                 ((uint16_t)0x0010)  /* Pin 4 selected */
-#define GPIO_Pin_5                 ((uint16_t)0x0020)  /* Pin 5 selected */
-#define GPIO_Pin_6                 ((uint16_t)0x0040)  /* Pin 6 selected */
-#define GPIO_Pin_7                 ((uint16_t)0x0080)  /* Pin 7 selected */
-#define GPIO_Pin_8                 ((uint16_t)0x0100)  /* Pin 8 selected */
-#define GPIO_Pin_9                 ((uint16_t)0x0200)  /* Pin 9 selected */
-#define GPIO_Pin_10                ((uint16_t)0x0400)  /* Pin 10 selected */
-#define GPIO_Pin_11                ((uint16_t)0x0800)  /* Pin 11 selected */
-#define GPIO_Pin_12                ((uint16_t)0x1000)  /* Pin 12 selected */
-#define GPIO_Pin_13                ((uint16_t)0x2000)  /* Pin 13 selected */
-#define GPIO_Pin_14                ((uint16_t)0x4000)  /* Pin 14 selected */
-#define GPIO_Pin_15                ((uint16_t)0x8000)  /* Pin 15 selected */
-#define GPIO_Pin_All               ((uint16_t)0xFFFF)  /* All pins selected */
-
-#define GPIO_PIN_MASK              ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
-#define IS_GPIO_PIN(PIN)           (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
-#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
-                              ((PIN) == GPIO_Pin_1) || \
-                              ((PIN) == GPIO_Pin_2) || \
-                              ((PIN) == GPIO_Pin_3) || \
-                              ((PIN) == GPIO_Pin_4) || \
-                              ((PIN) == GPIO_Pin_5) || \
-                              ((PIN) == GPIO_Pin_6) || \
-                              ((PIN) == GPIO_Pin_7) || \
-                              ((PIN) == GPIO_Pin_8) || \
-                              ((PIN) == GPIO_Pin_9) || \
-                              ((PIN) == GPIO_Pin_10) || \
-                              ((PIN) == GPIO_Pin_11) || \
-                              ((PIN) == GPIO_Pin_12) || \
-                              ((PIN) == GPIO_Pin_13) || \
-                              ((PIN) == GPIO_Pin_14) || \
-                              ((PIN) == GPIO_Pin_15))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup GPIO_Pin_sources 
-  * @{
-  */ 
-#define GPIO_PinSource0            ((uint8_t)0x00)
-#define GPIO_PinSource1            ((uint8_t)0x01)
-#define GPIO_PinSource2            ((uint8_t)0x02)
-#define GPIO_PinSource3            ((uint8_t)0x03)
-#define GPIO_PinSource4            ((uint8_t)0x04)
-#define GPIO_PinSource5            ((uint8_t)0x05)
-#define GPIO_PinSource6            ((uint8_t)0x06)
-#define GPIO_PinSource7            ((uint8_t)0x07)
-#define GPIO_PinSource8            ((uint8_t)0x08)
-#define GPIO_PinSource9            ((uint8_t)0x09)
-#define GPIO_PinSource10           ((uint8_t)0x0A)
-#define GPIO_PinSource11           ((uint8_t)0x0B)
-#define GPIO_PinSource12           ((uint8_t)0x0C)
-#define GPIO_PinSource13           ((uint8_t)0x0D)
-#define GPIO_PinSource14           ((uint8_t)0x0E)
-#define GPIO_PinSource15           ((uint8_t)0x0F)
-
-#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
-                                       ((PINSOURCE) == GPIO_PinSource1) || \
-                                       ((PINSOURCE) == GPIO_PinSource2) || \
-                                       ((PINSOURCE) == GPIO_PinSource3) || \
-                                       ((PINSOURCE) == GPIO_PinSource4) || \
-                                       ((PINSOURCE) == GPIO_PinSource5) || \
-                                       ((PINSOURCE) == GPIO_PinSource6) || \
-                                       ((PINSOURCE) == GPIO_PinSource7) || \
-                                       ((PINSOURCE) == GPIO_PinSource8) || \
-                                       ((PINSOURCE) == GPIO_PinSource9) || \
-                                       ((PINSOURCE) == GPIO_PinSource10) || \
-                                       ((PINSOURCE) == GPIO_PinSource11) || \
-                                       ((PINSOURCE) == GPIO_PinSource12) || \
-                                       ((PINSOURCE) == GPIO_PinSource13) || \
-                                       ((PINSOURCE) == GPIO_PinSource14) || \
-                                       ((PINSOURCE) == GPIO_PinSource15))
-/**
-  * @}
-  */ 
-
-/** @defgroup GPIO_Alternat_function_selection_define 
-  * @{
-  */ 
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping */
-#define GPIO_AF_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping */
-#define GPIO_AF_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping */
-#define GPIO_AF_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping */
-#if defined(STM32F446xx)
-#define GPIO_AF0_TIM2         ((uint8_t)0x00)  /* TIM2 Alternate Function mapping */
-#endif /* STM32F446xx */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
-#if defined(STM32F410xx) || defined(STM32F413_423xx)
-#define GPIO_AF_LPTIM         ((uint8_t)0x01)  /* LPTIM Alternate Function mapping */
-#endif /* STM32F410xx || STM32F413_423xx */
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping */
-#define GPIO_AF_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping */
-#define GPIO_AF_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
-#if defined(STM32F446xx)
-#define GPIO_AF3_CEC          ((uint8_t)0x03)  /* CEC Alternate Function mapping */
-#endif /* STM32F446xx */
-#if defined(STM32F413_423xx)
-#define GPIO_AF3_DFSDM2       ((uint8_t)0x03)  /* DFSDM2 Alternate Function mapping */
-#endif /* STM32F413_423xx */
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
-#if defined(STM32F446xx)
-#define GPIO_AF4_CEC          ((uint8_t)0x04)  /* CEC Alternate Function mapping */
-#endif /* STM32F446xx */
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-#define GPIO_AF_FMPI2C        ((uint8_t)0x04)  /* FMPI2C Alternate Function mapping */
-#endif /* STM32F410xx || STM32F446xx */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping */
-#define GPIO_AF_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_SPI3         ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping (Only for STM32F411xE and STM32F413_423xx Devices) */
-#define GPIO_AF_SPI4          ((uint8_t)0x05)  /* SPI4/I2S4 Alternate Function mapping */
-#define GPIO_AF_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping      */
-#define GPIO_AF_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping      */
-
-/** 
-  * @brief   AF 6 selection  
-  */ 
-#define GPIO_AF_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_SPI1         ((uint8_t)0x06)  /* SPI1 Alternate Function mapping (Only for STM32F410xx Devices) */
-#define GPIO_AF6_SPI2         ((uint8_t)0x06)  /* SPI2 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */
-#define GPIO_AF6_SPI4         ((uint8_t)0x06)  /* SPI4 Alternate Function mapping (Only for STM32F411xE Devices) */
-#define GPIO_AF6_SPI5         ((uint8_t)0x06)  /* SPI5 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */
-#define GPIO_AF_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping      */
-#define GPIO_AF_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping (only for STM32F412xG and STM32F413_423xx Devices) */
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-#define GPIO_AF6_DFSDM1       ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping */
-#endif /* STM32F412xG || STM32F413_423xx */
-#if defined(STM32F413_423xx)
-#define GPIO_AF6_DFSDM2       ((uint8_t)0x06)  /* DFSDM2 Alternate Function mapping */
-#endif /* STM32F413_423xx */
-
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF_USART1         ((uint8_t)0x07)  /* USART1 Alternate Function mapping  */
-#define GPIO_AF_USART2         ((uint8_t)0x07)  /* USART2 Alternate Function mapping  */
-#define GPIO_AF_USART3         ((uint8_t)0x07)  /* USART3 Alternate Function mapping  */
-#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3/I2S3ext Alternate Function mapping */
-#if defined(STM32F413_423xx)
-#define GPIO_AF7_DFSDM2        ((uint8_t)0x07)  /* DFSDM2 Alternate Function mapping     */
-#define GPIO_AF7_SAI1          ((uint8_t)0x07)  /* SAI1 Alternate Function mapping       */
-#endif /* STM32F413_423xx */
-
-/** 
-  * @brief   AF 7 selection Legacy 
-  */ 
-#define GPIO_AF_I2S3ext   GPIO_AF7_SPI3
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
-#define GPIO_AF_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
-#define GPIO_AF_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
-#define GPIO_AF_UART7         ((uint8_t)0x08)  /* UART7 Alternate Function mapping  */
-#define GPIO_AF_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-#define GPIO_AF8_USART3        ((uint8_t)0x08)  /* USART3 Alternate Function mapping */
-#define GPIO_AF8_DFSDM1        ((uint8_t)0x08)  /* DFSDM Alternate Function mapping  */
-#define GPIO_AF8_CAN1          ((uint8_t)0x08)  /* CAN1 Alternate Function mapping   */
-#endif /* STM32F412xG || STM32F413_423xx */
-#if defined(STM32F446xx)
-#define GPIO_AF8_SAI2          ((uint8_t)0x08)  /* SAI2 Alternate Function mapping */
-#define GPIO_AF_SPDIF         ((uint8_t)0x08)   /* SPDIF Alternate Function mapping */
-#endif /* STM32F446xx */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
-#define GPIO_AF_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */
-#define GPIO_AF_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
-#define GPIO_AF_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
-#define GPIO_AF_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
-#define GPIO_AF9_I2C2         ((uint8_t)0x09)  /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F410xx/STM32F411xE/STM32F412xG/STM32F413_423xx Devices) */
-#define GPIO_AF9_I2C3         ((uint8_t)0x09)  /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE/STM32F412xG and STM32F413_423xx Devices) */
-#if defined(STM32F446xx)
-#define GPIO_AF9_SAI2         ((uint8_t)0x09)  /* SAI2 Alternate Function mapping */
-#endif /* STM32F446xx */
-#define GPIO_AF9_LTDC         ((uint8_t)0x09)  /* LTDC Alternate Function mapping */
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define GPIO_AF9_QUADSPI      ((uint8_t)0x09)  /* QuadSPI Alternate Function mapping */
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-#define GPIO_AF9_FMPI2C       ((uint8_t)0x09)  /* FMPI2C Alternate Function mapping (Only for STM32F410xx Devices) */
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-#define GPIO_AF_OTG_FS         ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
-#define GPIO_AF_OTG_HS         ((uint8_t)0xA)  /* OTG_HS Alternate Function mapping */
-#if defined(STM32F446xx)
-#define GPIO_AF10_SAI2         ((uint8_t)0x0A)  /* SAI2 Alternate Function mapping */
-#endif /* STM32F446xx */
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define GPIO_AF10_QUADSPI      ((uint8_t)0x0A)  /* QuadSPI Alternate Function mapping */
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-#if defined(STM32F412xG) || defined(STM32F413_423xx)
-#define GPIO_AF10_FMC           ((uint8_t)0xA)  /* FMC Alternate Function mapping    */
-#define GPIO_AF10_DFSDM1         ((uint8_t)0xA) /* DFSDM Alternate Function mapping  */
-#endif /* STM32F412xG || STM32F413_423xx */
-#if defined(STM32F413_423xx)
-#define GPIO_AF10_DFSDM2        ((uint8_t)0x0A)  /* DFSDM2 Alternate Function mapping */
-#define GPIO_AF10_SAI1          ((uint8_t)0x0A)  /* SAI1 Alternate Function mapping   */
-#endif /* STM32F413_423xx */
-/** 
-  * @brief   AF 11 selection  
-  */ 
-#define GPIO_AF_ETH             ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
-#if defined(STM32F413_423xx)
-#define GPIO_AF11_UART4         ((uint8_t)0x0B)  /* UART4 Alternate Function mapping  */
-#define GPIO_AF11_UART5         ((uint8_t)0x0B)  /* UART5 Alternate Function mapping  */
-#define GPIO_AF11_UART9         ((uint8_t)0x0B)  /* UART9 Alternate Function mapping  */
-#define GPIO_AF11_UART10        ((uint8_t)0x0B)  /* UART10 Alternate Function mapping */
-#define GPIO_AF11_CAN3          ((uint8_t)0x0B)  /* CAN3 Alternate Function mapping   */
-#endif /* STM32F413_423xx */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-#define GPIO_AF_FSMC             ((uint8_t)0xC)  /* FSMC Alternate Function mapping                     */
-#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-#define GPIO_AF_FMC              ((uint8_t)0xC)  /* FMC Alternate Function mapping                      */
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
-
-#define GPIO_AF_OTG_HS_FS        ((uint8_t)0xC)  /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF_SDIO             ((uint8_t)0xC)  /* SDIO Alternate Function mapping                     */
-
-/** 
-  * @brief   AF 13 selection  
-  */ 
-#define GPIO_AF_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
-#if defined(STM32F469_479xx)
-#define GPIO_AF_DSI           ((uint8_t)0x0D)  /* DSI Alternate Function mapping */
-#endif /* STM32F469_479xx */
-/** 
-  * @brief   AF 14 selection  
-  */
-#define GPIO_AF_LTDC          ((uint8_t)0x0E)  /* LCD-TFT Alternate Function mapping */
-#if defined(STM32F413_423xx)
-#define GPIO_AF14_RNG         ((uint8_t)0x0E)  /* RNG Alternate Function mapping  */
-#endif /* STM32F413_423xx */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
-
-#if defined(STM32F40_41xxx)
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz)  || ((AF) == GPIO_AF_TIM14)     || \
-                          ((AF) == GPIO_AF_MCO)       || ((AF) == GPIO_AF_TAMPER)    || \
-                          ((AF) == GPIO_AF_SWJ)       || ((AF) == GPIO_AF_TRACE)     || \
-                          ((AF) == GPIO_AF_TIM1)      || ((AF) == GPIO_AF_TIM2)      || \
-                          ((AF) == GPIO_AF_TIM3)      || ((AF) == GPIO_AF_TIM4)      || \
-                          ((AF) == GPIO_AF_TIM5)      || ((AF) == GPIO_AF_TIM8)      || \
-                          ((AF) == GPIO_AF_I2C1)      || ((AF) == GPIO_AF_I2C2)      || \
-                          ((AF) == GPIO_AF_I2C3)      || ((AF) == GPIO_AF_SPI1)      || \
-                          ((AF) == GPIO_AF_SPI2)      || ((AF) == GPIO_AF_TIM13)     || \
-                          ((AF) == GPIO_AF_SPI3)      || ((AF) == GPIO_AF_TIM14)     || \
-                          ((AF) == GPIO_AF_USART1)    || ((AF) == GPIO_AF_USART2)    || \
-                          ((AF) == GPIO_AF_USART3)    || ((AF) == GPIO_AF_UART4)     || \
-                          ((AF) == GPIO_AF_UART5)     || ((AF) == GPIO_AF_USART6)    || \
-                          ((AF) == GPIO_AF_CAN1)      || ((AF) == GPIO_AF_CAN2)      || \
-                          ((AF) == GPIO_AF_OTG_FS)    || ((AF) == GPIO_AF_OTG_HS)    || \
-                          ((AF) == GPIO_AF_ETH)       || ((AF) == GPIO_AF_OTG_HS_FS) || \
-                          ((AF) == GPIO_AF_SDIO)      || ((AF) == GPIO_AF_DCMI)      || \
-                          ((AF) == GPIO_AF_EVENTOUT)  || ((AF) == GPIO_AF_FSMC))
-#endif /* STM32F40_41xxx */
-
-#if defined(STM32F401xx)
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz)  || ((AF) == GPIO_AF_TIM14)     || \
-                          ((AF) == GPIO_AF_MCO)       || ((AF) == GPIO_AF_TAMPER)    || \
-                          ((AF) == GPIO_AF_SWJ)       || ((AF) == GPIO_AF_TRACE)     || \
-                          ((AF) == GPIO_AF_TIM1)      || ((AF) == GPIO_AF_TIM2)      || \
-                          ((AF) == GPIO_AF_TIM3)      || ((AF) == GPIO_AF_TIM4)      || \
-                          ((AF) == GPIO_AF_TIM5)      || ((AF) == GPIO_AF_TIM8)      || \
-                          ((AF) == GPIO_AF_I2C1)      || ((AF) == GPIO_AF_I2C2)      || \
-                          ((AF) == GPIO_AF_I2C3)      || ((AF) == GPIO_AF_SPI1)      || \
-                          ((AF) == GPIO_AF_SPI2)      || ((AF) == GPIO_AF_TIM13)     || \
-                          ((AF) == GPIO_AF_SPI3)      || ((AF) == GPIO_AF_TIM14)     || \
-                          ((AF) == GPIO_AF_USART1)    || ((AF) == GPIO_AF_USART2)    || \
-                          ((AF) == GPIO_AF_SDIO)      || ((AF) == GPIO_AF_USART6)    || \
-                          ((AF) == GPIO_AF_OTG_FS)    || ((AF) == GPIO_AF_OTG_HS)    || \
-                          ((AF) == GPIO_AF_EVENTOUT)  || ((AF) == GPIO_AF_SPI4))
-#endif /* STM32F401xx */
-
-#if defined(STM32F411xE)
-#define IS_GPIO_AF(AF)   (((AF) < 16) && ((AF) != 11) && ((AF) != 13) && ((AF) != 14))
-#endif /* STM32F411xE */
-
-#if defined(STM32F410xx)
-#define IS_GPIO_AF(AF)   (((AF) < 10) || ((AF) == 15))
-#endif /* STM32F410xx */
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz)  || ((AF) == GPIO_AF_TIM14)     || \
-                          ((AF) == GPIO_AF_MCO)       || ((AF) == GPIO_AF_TAMPER)    || \
-                          ((AF) == GPIO_AF_SWJ)       || ((AF) == GPIO_AF_TRACE)     || \
-                          ((AF) == GPIO_AF_TIM1)      || ((AF) == GPIO_AF_TIM2)      || \
-                          ((AF) == GPIO_AF_TIM3)      || ((AF) == GPIO_AF_TIM4)      || \
-                          ((AF) == GPIO_AF_TIM5)      || ((AF) == GPIO_AF_TIM8)      || \
-                          ((AF) == GPIO_AF_I2C1)      || ((AF) == GPIO_AF_I2C2)      || \
-                          ((AF) == GPIO_AF_I2C3)      || ((AF) == GPIO_AF_SPI1)      || \
-                          ((AF) == GPIO_AF_SPI2)      || ((AF) == GPIO_AF_TIM13)     || \
-                          ((AF) == GPIO_AF_SPI3)      || ((AF) == GPIO_AF_TIM14)     || \
-                          ((AF) == GPIO_AF_USART1)    || ((AF) == GPIO_AF_USART2)    || \
-                          ((AF) == GPIO_AF_USART3)    || ((AF) == GPIO_AF_UART4)     || \
-                          ((AF) == GPIO_AF_UART5)     || ((AF) == GPIO_AF_USART6)    || \
-                          ((AF) == GPIO_AF_CAN1)      || ((AF) == GPIO_AF_CAN2)      || \
-                          ((AF) == GPIO_AF_OTG_FS)    || ((AF) == GPIO_AF_OTG_HS)    || \
-                          ((AF) == GPIO_AF_ETH)       || ((AF) == GPIO_AF_OTG_HS_FS) || \
-                          ((AF) == GPIO_AF_SDIO)      || ((AF) == GPIO_AF_DCMI)      || \
-                          ((AF) == GPIO_AF_EVENTOUT)  || ((AF) == GPIO_AF_SPI4)      || \
-                          ((AF) == GPIO_AF_SPI5)      || ((AF) == GPIO_AF_SPI6)      || \
-                          ((AF) == GPIO_AF_UART7)     || ((AF) == GPIO_AF_UART8)     || \
-                          ((AF) == GPIO_AF_FMC)       ||  ((AF) == GPIO_AF_SAI1)     || \
-                          ((AF) == GPIO_AF_LTDC))
-#endif /* STM32F427_437xx ||  STM32F429_439xx */
-
-#if defined(STM32F412xG)
-#define IS_GPIO_AF(AF)   (((AF) < 16) && ((AF) != 11) && ((AF) != 14))
-#endif /* STM32F412xG */
-
-#if defined(STM32F413_423xx)
-#define IS_GPIO_AF(AF)   (((AF) < 16) && ((AF) != 13))
-#endif /* STM32F413_423xx */
-
-#if defined(STM32F446xx)
-#define IS_GPIO_AF(AF)   (((AF) < 16) && ((AF) != 11) && ((AF) != 14))
-#endif /* STM32F446xx */
-
-#if defined(STM32F469_479xx)
-#define IS_GPIO_AF(AF)   ((AF) < 16)
-#endif /* STM32F469_479xx */
-
-/**
-  * @}
-  */ 
-
-/** @defgroup GPIO_Legacy 
-  * @{
-  */
-    
-#define GPIO_Mode_AIN           GPIO_Mode_AN
-
-#define GPIO_AF_OTG1_FS         GPIO_AF_OTG_FS
-#define GPIO_AF_OTG2_HS         GPIO_AF_OTG_HS
-#define GPIO_AF_OTG2_FS         GPIO_AF_OTG_HS_FS
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/*  Function used to set the GPIO configuration to the default reset state ****/
-void GPIO_DeInit(GPIO_TypeDef* GPIOx);
-
-/* Initialization and Configuration functions *********************************/
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-
-/* GPIO Read and Write functions **********************************************/
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
-void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-
-/* GPIO Alternate functions configuration function ****************************/
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_GPIO_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h

@@ -1,257 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hash.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the HASH 
-  *          firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HASH_H
-#define __STM32F4xx_HASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup HASH
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief   HASH Init structure definition
-  */ 
-typedef struct
-{
-  uint32_t HASH_AlgoSelection; /*!< SHA-1, SHA-224, SHA-256 or MD5. This parameter
-                                    can be a value of @ref HASH_Algo_Selection */
-  uint32_t HASH_AlgoMode;      /*!< HASH or HMAC. This parameter can be a value 
-                                    of @ref HASH_processor_Algorithm_Mode */
-  uint32_t HASH_DataType;      /*!< 32-bit data, 16-bit data, 8-bit data or 
-                                    bit string. This parameter can be a value of
-                                    @ref HASH_Data_Type */
-  uint32_t HASH_HMACKeyType;   /*!< HMAC Short key or HMAC Long Key. This parameter
-                                    can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */
-}HASH_InitTypeDef;
-
-/** 
-  * @brief  HASH message digest result structure definition  
-  */ 
-typedef struct
-{
-  uint32_t Data[8];      /*!< Message digest result : 8x 32bit wors for SHA-256,
-                                                      7x 32bit wors for SHA-224,
-                                                      5x 32bit words for SHA-1 or
-                                                      4x 32bit words for MD5  */
-} HASH_MsgDigest; 
-
-/** 
-  * @brief  HASH context swapping structure definition  
-  */ 
-typedef struct
-{
-  uint32_t HASH_IMR; 
-  uint32_t HASH_STR;      
-  uint32_t HASH_CR;     
-  uint32_t HASH_CSR[54];       
-}HASH_Context;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HASH_Exported_Constants
-  * @{
-  */ 
-
-/** @defgroup HASH_Algo_Selection 
-  * @{
-  */ 
-#define HASH_AlgoSelection_SHA1      ((uint32_t)0x0000) /*!< HASH function is SHA1   */
-#define HASH_AlgoSelection_SHA224    HASH_CR_ALGO_1     /*!< HASH function is SHA224 */
-#define HASH_AlgoSelection_SHA256    HASH_CR_ALGO       /*!< HASH function is SHA256 */
-#define HASH_AlgoSelection_MD5       HASH_CR_ALGO_0     /*!< HASH function is MD5    */
-
-#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \
-                                              ((ALGOSELECTION) == HASH_AlgoSelection_SHA224) || \
-                                              ((ALGOSELECTION) == HASH_AlgoSelection_SHA256) || \
-                                              ((ALGOSELECTION) == HASH_AlgoSelection_MD5))
-/**
-  * @}
-  */
-
-/** @defgroup HASH_processor_Algorithm_Mode 
-  * @{
-  */ 
-#define HASH_AlgoMode_HASH         ((uint32_t)0x00000000) /*!< Algorithm is HASH */ 
-#define HASH_AlgoMode_HMAC         HASH_CR_MODE           /*!< Algorithm is HMAC */
-
-#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \
-                                    ((ALGOMODE) == HASH_AlgoMode_HMAC))
-/**
-  * @}
-  */
-
-/** @defgroup HASH_Data_Type  
-  * @{
-  */  
-#define HASH_DataType_32b          ((uint32_t)0x0000) /*!< 32-bit data. No swapping                     */
-#define HASH_DataType_16b          HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped       */
-#define HASH_DataType_8b           HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped            */
-#define HASH_DataType_1b           HASH_CR_DATATYPE   /*!< 1-bit data. In the word all bits are swapped */
-
-#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \
-                                    ((DATATYPE) == HASH_DataType_16b)|| \
-                                    ((DATATYPE) == HASH_DataType_8b) || \
-                                    ((DATATYPE) == HASH_DataType_1b))
-/**
-  * @}
-  */
-
-/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode  
-  * @{
-  */ 
-#define HASH_HMACKeyType_ShortKey      ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */
-#define HASH_HMACKeyType_LongKey       HASH_CR_LKEY           /*!< HMAC Key is > 64 bytes  */
-
-#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \
-                                       ((KEYTYPE) == HASH_HMACKeyType_LongKey))
-/**
-  * @}
-  */
-
-/** @defgroup Number_of_valid_bits_in_last_word_of_the_message   
-  * @{
-  */  
-#define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F)
-
-/**
-  * @}
-  */
-
-/** @defgroup HASH_interrupts_definition   
-  * @{
-  */  
-#define HASH_IT_DINI               HASH_IMR_DINIM  /*!< A new block can be entered into the input buffer (DIN) */
-#define HASH_IT_DCI                HASH_IMR_DCIM   /*!< Digest calculation complete                            */
-
-#define IS_HASH_IT(IT) ((((IT) & (uint32_t)0xFFFFFFFC) == 0x00000000) && ((IT) != 0x00000000))
-#define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI))
-				   
-/**
-  * @}
-  */
-
-/** @defgroup HASH_flags_definition   
-  * @{
-  */  
-#define HASH_FLAG_DINIS            HASH_SR_DINIS  /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
-#define HASH_FLAG_DCIS             HASH_SR_DCIS   /*!< Digest calculation complete                                                         */
-#define HASH_FLAG_DMAS             HASH_SR_DMAS   /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing                          */
-#define HASH_FLAG_BUSY             HASH_SR_BUSY   /*!< The hash core is Busy : processing a block of data                                  */
-#define HASH_FLAG_DINNE            HASH_CR_DINNE  /*!< DIN not empty : The input buffer contains at least one word of data                 */
-
-#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \
-                                ((FLAG) == HASH_FLAG_DCIS)  || \
-                                ((FLAG) == HASH_FLAG_DMAS)  || \
-                                ((FLAG) == HASH_FLAG_BUSY)  || \
-                                ((FLAG) == HASH_FLAG_DINNE)) 
-
-#define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \
-                                 ((FLAG) == HASH_FLAG_DCIS))                                 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/ 
-  
-/*  Function used to set the HASH configuration to the default reset state ****/
-void HASH_DeInit(void);
-
-/* HASH Configuration function ************************************************/
-void HASH_Init(HASH_InitTypeDef* HASH_InitStruct);
-void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct);
-void HASH_Reset(void);
-
-/* HASH Message Digest generation functions ***********************************/
-void HASH_DataIn(uint32_t Data);
-uint8_t HASH_GetInFIFOWordsNbr(void);
-void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber);
-void HASH_StartDigest(void);
-void HASH_AutoStartDigest(FunctionalState NewState);
-void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest);
-
-/* HASH Context swapping functions ********************************************/
-void HASH_SaveContext(HASH_Context* HASH_ContextSave);
-void HASH_RestoreContext(HASH_Context* HASH_ContextRestore);
-
-/* HASH DMA interface function ************************************************/
-void HASH_DMACmd(FunctionalState NewState);
-
-/* HASH Interrupts and flags management functions *****************************/
-void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState);
-FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG);
-void HASH_ClearFlag(uint32_t HASH_FLAG);
-ITStatus HASH_GetITStatus(uint32_t HASH_IT);
-void HASH_ClearITPendingBit(uint32_t HASH_IT);
-
-/* High Level SHA1 functions **************************************************/
-ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]);
-ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen,
-                      uint8_t *Input, uint32_t Ilen,
-                      uint8_t Output[20]);
-
-/* High Level MD5 functions ***************************************************/
-ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]);
-ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen,
-                     uint8_t *Input, uint32_t Ilen,
-                     uint8_t Output[16]);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_HASH_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h

@@ -1,709 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_i2c.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the I2C firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************  
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_I2C_H
-#define __STM32F4xx_I2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup I2C
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  I2C Init structure definition  
-  */
-
-typedef struct
-{
-  uint32_t I2C_ClockSpeed;          /*!< Specifies the clock frequency.
-                                         This parameter must be set to a value lower than 400kHz */
-
-  uint16_t I2C_Mode;                /*!< Specifies the I2C mode.
-                                         This parameter can be a value of @ref I2C_mode */
-
-  uint16_t I2C_DutyCycle;           /*!< Specifies the I2C fast mode duty cycle.
-                                         This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
-
-  uint16_t I2C_OwnAddress1;         /*!< Specifies the first device own address.
-                                         This parameter can be a 7-bit or 10-bit address. */
-
-  uint16_t I2C_Ack;                 /*!< Enables or disables the acknowledgement.
-                                         This parameter can be a value of @ref I2C_acknowledgement */
-
-  uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
-                                         This parameter can be a value of @ref I2C_acknowledged_address */
-}I2C_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-
-/** @defgroup I2C_Exported_Constants
-  * @{
-  */
-#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
-                                   ((PERIPH) == I2C2) || \
-                                   ((PERIPH) == I2C3))
-/** @defgroup I2C_Digital_Filter
-  * @{
-  */
-
-#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000F)
-/**
-  * @}
-  */
-
-
-/** @defgroup I2C_mode 
-  * @{
-  */
-
-#define I2C_Mode_I2C                    ((uint16_t)0x0000)
-#define I2C_Mode_SMBusDevice            ((uint16_t)0x0002)  
-#define I2C_Mode_SMBusHost              ((uint16_t)0x000A)
-#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
-                           ((MODE) == I2C_Mode_SMBusDevice) || \
-                           ((MODE) == I2C_Mode_SMBusHost))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_duty_cycle_in_fast_mode 
-  * @{
-  */
-
-#define I2C_DutyCycle_16_9              ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
-#define I2C_DutyCycle_2                 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
-                                  ((CYCLE) == I2C_DutyCycle_2))
-/**
-  * @}
-  */ 
-
-/** @defgroup I2C_acknowledgement
-  * @{
-  */
-
-#define I2C_Ack_Enable                  ((uint16_t)0x0400)
-#define I2C_Ack_Disable                 ((uint16_t)0x0000)
-#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
-                                 ((STATE) == I2C_Ack_Disable))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_transfer_direction 
-  * @{
-  */
-
-#define  I2C_Direction_Transmitter      ((uint8_t)0x00)
-#define  I2C_Direction_Receiver         ((uint8_t)0x01)
-#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
-                                     ((DIRECTION) == I2C_Direction_Receiver))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_acknowledged_address 
-  * @{
-  */
-
-#define I2C_AcknowledgedAddress_7bit    ((uint16_t)0x4000)
-#define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)
-#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
-                                             ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
-/**
-  * @}
-  */ 
-
-/** @defgroup I2C_registers 
-  * @{
-  */
-
-#define I2C_Register_CR1                ((uint8_t)0x00)
-#define I2C_Register_CR2                ((uint8_t)0x04)
-#define I2C_Register_OAR1               ((uint8_t)0x08)
-#define I2C_Register_OAR2               ((uint8_t)0x0C)
-#define I2C_Register_DR                 ((uint8_t)0x10)
-#define I2C_Register_SR1                ((uint8_t)0x14)
-#define I2C_Register_SR2                ((uint8_t)0x18)
-#define I2C_Register_CCR                ((uint8_t)0x1C)
-#define I2C_Register_TRISE              ((uint8_t)0x20)
-#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
-                                   ((REGISTER) == I2C_Register_CR2) || \
-                                   ((REGISTER) == I2C_Register_OAR1) || \
-                                   ((REGISTER) == I2C_Register_OAR2) || \
-                                   ((REGISTER) == I2C_Register_DR) || \
-                                   ((REGISTER) == I2C_Register_SR1) || \
-                                   ((REGISTER) == I2C_Register_SR2) || \
-                                   ((REGISTER) == I2C_Register_CCR) || \
-                                   ((REGISTER) == I2C_Register_TRISE))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_NACK_position 
-  * @{
-  */
-
-#define I2C_NACKPosition_Next           ((uint16_t)0x0800)
-#define I2C_NACKPosition_Current        ((uint16_t)0xF7FF)
-#define IS_I2C_NACK_POSITION(POSITION)  (((POSITION) == I2C_NACKPosition_Next) || \
-                                         ((POSITION) == I2C_NACKPosition_Current))
-/**
-  * @}
-  */ 
-
-/** @defgroup I2C_SMBus_alert_pin_level 
-  * @{
-  */
-
-#define I2C_SMBusAlert_Low              ((uint16_t)0x2000)
-#define I2C_SMBusAlert_High             ((uint16_t)0xDFFF)
-#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
-                                   ((ALERT) == I2C_SMBusAlert_High))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_PEC_position 
-  * @{
-  */
-
-#define I2C_PECPosition_Next            ((uint16_t)0x0800)
-#define I2C_PECPosition_Current         ((uint16_t)0xF7FF)
-#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
-                                       ((POSITION) == I2C_PECPosition_Current))
-/**
-  * @}
-  */ 
-
-/** @defgroup I2C_interrupts_definition 
-  * @{
-  */
-
-#define I2C_IT_BUF                      ((uint16_t)0x0400)
-#define I2C_IT_EVT                      ((uint16_t)0x0200)
-#define I2C_IT_ERR                      ((uint16_t)0x0100)
-#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
-/**
-  * @}
-  */ 
-
-/** @defgroup I2C_interrupts_definition 
-  * @{
-  */
-
-#define I2C_IT_SMBALERT                 ((uint32_t)0x01008000)
-#define I2C_IT_TIMEOUT                  ((uint32_t)0x01004000)
-#define I2C_IT_PECERR                   ((uint32_t)0x01001000)
-#define I2C_IT_OVR                      ((uint32_t)0x01000800)
-#define I2C_IT_AF                       ((uint32_t)0x01000400)
-#define I2C_IT_ARLO                     ((uint32_t)0x01000200)
-#define I2C_IT_BERR                     ((uint32_t)0x01000100)
-#define I2C_IT_TXE                      ((uint32_t)0x06000080)
-#define I2C_IT_RXNE                     ((uint32_t)0x06000040)
-#define I2C_IT_STOPF                    ((uint32_t)0x02000010)
-#define I2C_IT_ADD10                    ((uint32_t)0x02000008)
-#define I2C_IT_BTF                      ((uint32_t)0x02000004)
-#define I2C_IT_ADDR                     ((uint32_t)0x02000002)
-#define I2C_IT_SB                       ((uint32_t)0x02000001)
-
-#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
-
-#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
-                           ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
-                           ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
-                           ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
-                           ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
-                           ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
-                           ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_flags_definition 
-  * @{
-  */
-
-/** 
-  * @brief  SR2 register flags  
-  */
-
-#define I2C_FLAG_DUALF                  ((uint32_t)0x00800000)
-#define I2C_FLAG_SMBHOST                ((uint32_t)0x00400000)
-#define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00200000)
-#define I2C_FLAG_GENCALL                ((uint32_t)0x00100000)
-#define I2C_FLAG_TRA                    ((uint32_t)0x00040000)
-#define I2C_FLAG_BUSY                   ((uint32_t)0x00020000)
-#define I2C_FLAG_MSL                    ((uint32_t)0x00010000)
-
-/** 
-  * @brief  SR1 register flags  
-  */
-
-#define I2C_FLAG_SMBALERT               ((uint32_t)0x10008000)
-#define I2C_FLAG_TIMEOUT                ((uint32_t)0x10004000)
-#define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)
-#define I2C_FLAG_OVR                    ((uint32_t)0x10000800)
-#define I2C_FLAG_AF                     ((uint32_t)0x10000400)
-#define I2C_FLAG_ARLO                   ((uint32_t)0x10000200)
-#define I2C_FLAG_BERR                   ((uint32_t)0x10000100)
-#define I2C_FLAG_TXE                    ((uint32_t)0x10000080)
-#define I2C_FLAG_RXNE                   ((uint32_t)0x10000040)
-#define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)
-#define I2C_FLAG_ADD10                  ((uint32_t)0x10000008)
-#define I2C_FLAG_BTF                    ((uint32_t)0x10000004)
-#define I2C_FLAG_ADDR                   ((uint32_t)0x10000002)
-#define I2C_FLAG_SB                     ((uint32_t)0x10000001)
-
-#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
-
-#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
-                               ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
-                               ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
-                               ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
-                               ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
-                               ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
-                               ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
-                               ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
-                               ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
-                               ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
-                               ((FLAG) == I2C_FLAG_SB))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Events 
-  * @{
-  */
-
-/**
- ===============================================================================
-               I2C Master Events (Events grouped in order of communication)
- ===============================================================================
- */
-
-/** 
-  * @brief  Communication start
-  * 
-  * After sending the START condition (I2C_GenerateSTART() function) the master 
-  * has to wait for this event. It means that the Start condition has been correctly 
-  * released on the I2C bus (the bus is free, no other devices is communicating).
-  * 
-  */
-/* --EV5 */
-#define  I2C_EVENT_MASTER_MODE_SELECT                      ((uint32_t)0x00030001)  /* BUSY, MSL and SB flag */
-
-/** 
-  * @brief  Address Acknowledge
-  * 
-  * After checking on EV5 (start condition correctly released on the bus), the 
-  * master sends the address of the slave(s) with which it will communicate 
-  * (I2C_Send7bitAddress() function, it also determines the direction of the communication: 
-  * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges 
-  * his address. If an acknowledge is sent on the bus, one of the following events will 
-  * be set:
-  * 
-  *  1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED 
-  *     event is set.
-  *  
-  *  2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED 
-  *     is set
-  *  
-  *  3) In case of 10-Bit addressing mode, the master (just after generating the START 
-  *  and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() 
-  *  function). Then master should wait on EV9. It means that the 10-bit addressing 
-  *  header has been correctly sent on the bus. Then master should send the second part of 
-  *  the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master 
-  *  should wait for event EV6. 
-  *     
-  */
-
-/* --EV6 */
-#define  I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED        ((uint32_t)0x00070082)  /* BUSY, MSL, ADDR, TXE and TRA flags */
-#define  I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED           ((uint32_t)0x00030002)  /* BUSY, MSL and ADDR flags */
-/* --EV9 */
-#define  I2C_EVENT_MASTER_MODE_ADDRESS10                   ((uint32_t)0x00030008)  /* BUSY, MSL and ADD10 flags */
-
-/** 
-  * @brief Communication events
-  * 
-  * If a communication is established (START condition generated and slave address 
-  * acknowledged) then the master has to check on one of the following events for 
-  * communication procedures:
-  *  
-  * 1) Master Receiver mode: The master has to wait on the event EV7 then to read 
-  *    the data received from the slave (I2C_ReceiveData() function).
-  * 
-  * 2) Master Transmitter mode: The master has to send data (I2C_SendData() 
-  *    function) then to wait on event EV8 or EV8_2.
-  *    These two events are similar: 
-  *     - EV8 means that the data has been written in the data register and is 
-  *       being shifted out.
-  *     - EV8_2 means that the data has been physically shifted out and output 
-  *       on the bus.
-  *     In most cases, using EV8 is sufficient for the application.
-  *     Using EV8_2 leads to a slower communication but ensure more reliable test.
-  *     EV8_2 is also more suitable than EV8 for testing on the last data transmission 
-  *     (before Stop condition generation).
-  *     
-  *  @note In case the  user software does not guarantee that this event EV7 is 
-  *        managed before the current byte end of transfer, then user may check on EV7 
-  *        and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
-  *        In this case the communication may be slower.
-  * 
-  */
-
-/* Master RECEIVER mode -----------------------------*/ 
-/* --EV7 */
-#define  I2C_EVENT_MASTER_BYTE_RECEIVED                    ((uint32_t)0x00030040)  /* BUSY, MSL and RXNE flags */
-
-/* Master TRANSMITTER mode --------------------------*/
-/* --EV8 */
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTING                 ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
-/* --EV8_2 */
-#define  I2C_EVENT_MASTER_BYTE_TRANSMITTED                 ((uint32_t)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */
-
-
-/**
- ===============================================================================
-               I2C Slave Events (Events grouped in order of communication)
- ===============================================================================
- */
-
-
-/** 
-  * @brief  Communication start events
-  * 
-  * Wait on one of these events at the start of the communication. It means that 
-  * the I2C peripheral detected a Start condition on the bus (generated by master 
-  * device) followed by the peripheral address. The peripheral generates an ACK 
-  * condition on the bus (if the acknowledge feature is enabled through function 
-  * I2C_AcknowledgeConfig()) and the events listed above are set :
-  *  
-  * 1) In normal case (only one address managed by the slave), when the address 
-  *   sent by the master matches the own address of the peripheral (configured by 
-  *   I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set 
-  *   (where XXX could be TRANSMITTER or RECEIVER).
-  *    
-  * 2) In case the address sent by the master matches the second address of the 
-  *   peripheral (configured by the function I2C_OwnAddress2Config() and enabled 
-  *   by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED 
-  *   (where XXX could be TRANSMITTER or RECEIVER) are set.
-  *   
-  * 3) In case the address sent by the master is General Call (address 0x00) and 
-  *   if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) 
-  *   the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.   
-  * 
-  */
-
-/* --EV1  (all the events below are variants of EV1) */   
-/* 1) Case of One Single Address managed by the slave */
-#define  I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED          ((uint32_t)0x00020002) /* BUSY and ADDR flags */
-#define  I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED       ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
-
-/* 2) Case of Dual address managed by the slave */
-#define  I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED    ((uint32_t)0x00820000)  /* DUALF and BUSY flags */
-#define  I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */
-
-/* 3) Case of General Call enabled for the slave */
-#define  I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED        ((uint32_t)0x00120000)  /* GENCALL and BUSY flags */
-
-/** 
-  * @brief  Communication events
-  * 
-  * Wait on one of these events when EV1 has already been checked and: 
-  * 
-  * - Slave RECEIVER mode:
-  *     - EV2: When the application is expecting a data byte to be received. 
-  *     - EV4: When the application is expecting the end of the communication: master 
-  *       sends a stop condition and data transmission is stopped.
-  *    
-  * - Slave Transmitter mode:
-  *    - EV3: When a byte has been transmitted by the slave and the application is expecting 
-  *      the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
-  *      I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be 
-  *      used when the user software doesn't guarantee the EV3 is managed before the
-  *      current byte end of transfer.
-  *    - EV3_2: When the master sends a NACK in order to tell slave that data transmission 
-  *      shall end (before sending the STOP condition). In this case slave has to stop sending 
-  *      data bytes and expect a Stop condition on the bus.
-  *      
-  *  @note In case the  user software does not guarantee that the event EV2 is 
-  *        managed before the current byte end of transfer, then user may check on EV2 
-  *        and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
-  *        In this case the communication may be slower.
-  *
-  */
-
-/* Slave RECEIVER mode --------------------------*/ 
-/* --EV2 */
-#define  I2C_EVENT_SLAVE_BYTE_RECEIVED                     ((uint32_t)0x00020040)  /* BUSY and RXNE flags */
-/* --EV4  */
-#define  I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010)  /* STOPF flag */
-
-/* Slave TRANSMITTER mode -----------------------*/
-/* --EV3 */
-#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTED                  ((uint32_t)0x00060084)  /* TRA, BUSY, TXE and BTF flags */
-#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTING                 ((uint32_t)0x00060080)  /* TRA, BUSY and TXE flags */
-/* --EV3_2 */
-#define  I2C_EVENT_SLAVE_ACK_FAILURE                       ((uint32_t)0x00000400)  /* AF flag */
-
-/*
- ===============================================================================
-                          End of Events Description
- ===============================================================================
- */
-
-#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
-                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
-                             ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
-                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
-                             ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
-                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
-                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
-                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
-                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
-                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
-                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
-                             ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
-                             ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
-                             ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
-                             ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
-                             ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
-                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
-                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
-                             ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
-                             ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_own_address1 
-  * @{
-  */
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_clock_speed 
-  * @{
-  */
-
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/ 
-
-/*  Function used to set the I2C configuration to the default reset state *****/
-void I2C_DeInit(I2C_TypeDef* I2Cx);
-
-/* Initialization and Configuration functions *********************************/
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter);
-void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
-void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
-void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
-void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-
-/* Data transfers functions ***************************************************/ 
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
-
-/* PEC management functions ***************************************************/ 
-void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
-
-/* DMA transfers management functions *****************************************/
-void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-
-/* Interrupts, events and flags management functions **************************/
-uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
-
-/* 
- ===============================================================================
-                          I2C State Monitoring Functions
- ===============================================================================
-  This I2C driver provides three different ways for I2C state monitoring
-  depending on the application requirements and constraints:
-         
-   
-     1. Basic state monitoring (Using I2C_CheckEvent() function)
-     -----------------------------------------------------------
-        It compares the status registers (SR1 and SR2) content to a given event
-        (can be the combination of one or more flags).
-        It returns SUCCESS if the current status includes the given flags 
-        and returns ERROR if one or more flags are missing in the current status.
-
-          - When to use
-             - This function is suitable for most applications as well as for startup 
-               activity since the events are fully described in the product reference 
-               manual (RM0090).
-             - It is also suitable for users who need to define their own events.
-
-          - Limitations
-             - If an error occurs (ie. error flags are set besides to the monitored 
-               flags), the I2C_CheckEvent() function may return SUCCESS despite 
-               the communication hold or corrupted real state. 
-               In this case, it is advised to use error interrupts to monitor 
-               the error events and handle them in the interrupt IRQ handler.
-         
-     Note 
-         For error management, it is advised to use the following functions:
-           - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
-           - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
-             Where x is the peripheral instance (I2C1, I2C2 ...)
-           - I2C_GetFlagStatus() or I2C_GetITStatus()  to be called into the 
-             I2Cx_ER_IRQHandler() function in order to determine which error occurred.
-           - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() 
-             and/or I2C_GenerateStop() in order to clear the error flag and source 
-             and return to correct  communication status.
-             
- 
-     2. Advanced state monitoring (Using the function I2C_GetLastEvent())
-     -------------------------------------------------------------------- 
-        Using the function I2C_GetLastEvent() which returns the image of both status 
-        registers in a single word (uint32_t) (Status Register 2 value is shifted left 
-        by 16 bits and concatenated to Status Register 1).
-
-          - When to use
-             - This function is suitable for the same applications above but it 
-               allows to overcome the mentioned limitation of I2C_GetFlagStatus() 
-               function.
-             - The returned value could be compared to events already defined in 
-               this file or to custom values defined by user.
-               This function is suitable when multiple flags are monitored at the 
-               same time.
-             - At the opposite of I2C_CheckEvent() function, this function allows 
-               user to choose when an event is accepted (when all events flags are 
-               set and no other flags are set or just when the needed flags are set 
-               like I2C_CheckEvent() function.
-
-          - Limitations
-             - User may need to define his own events.
-             - Same remark concerning the error management is applicable for this 
-               function if user decides to check only regular communication flags 
-               (and ignores error flags).
-      
- 
-     3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
-     -----------------------------------------------------------------------
-     
-      Using the function I2C_GetFlagStatus() which simply returns the status of 
-      one single flag (ie. I2C_FLAG_RXNE ...). 
-
-          - When to use
-             - This function could be used for specific applications or in debug 
-               phase.
-             - It is suitable when only one flag checking is needed (most I2C 
-               events are monitored through multiple flags).
-          - Limitations: 
-             - When calling this function, the Status register is accessed. 
-               Some flags are cleared when the status register is accessed. 
-               So checking the status of one Flag, may clear other ones.
-             - Function may need to be called twice or more in order to monitor 
-               one single event.           
- */
-
-/*
- ===============================================================================
-                          1. Basic state monitoring
- ===============================================================================
- */
-ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
-/*
- ===============================================================================
-                          2. Advanced state monitoring
- ===============================================================================
- */
-uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
-/*
- ===============================================================================
-                          3. Flag-based state monitoring
- ===============================================================================
- */
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-
-
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_I2C_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h

@@ -1,131 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_iwdg.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the IWDG 
-  *          firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_IWDG_H
-#define __STM32F4xx_IWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup IWDG
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup IWDG_Exported_Constants
-  * @{
-  */
-  
-/** @defgroup IWDG_WriteAccess
-  * @{
-  */
-#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
-#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
-#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
-                                      ((ACCESS) == IWDG_WriteAccess_Disable))
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_prescaler 
-  * @{
-  */
-#define IWDG_Prescaler_4            ((uint8_t)0x00)
-#define IWDG_Prescaler_8            ((uint8_t)0x01)
-#define IWDG_Prescaler_16           ((uint8_t)0x02)
-#define IWDG_Prescaler_32           ((uint8_t)0x03)
-#define IWDG_Prescaler_64           ((uint8_t)0x04)
-#define IWDG_Prescaler_128          ((uint8_t)0x05)
-#define IWDG_Prescaler_256          ((uint8_t)0x06)
-#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4)  || \
-                                      ((PRESCALER) == IWDG_Prescaler_8)  || \
-                                      ((PRESCALER) == IWDG_Prescaler_16) || \
-                                      ((PRESCALER) == IWDG_Prescaler_32) || \
-                                      ((PRESCALER) == IWDG_Prescaler_64) || \
-                                      ((PRESCALER) == IWDG_Prescaler_128)|| \
-                                      ((PRESCALER) == IWDG_Prescaler_256))
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Flag 
-  * @{
-  */
-#define IWDG_FLAG_PVU               ((uint16_t)0x0001)
-#define IWDG_FLAG_RVU               ((uint16_t)0x0002)
-#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
-#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Prescaler and Counter configuration functions ******************************/
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
-void IWDG_SetReload(uint16_t Reload);
-void IWDG_ReloadCounter(void);
-
-/* IWDG activation function ***************************************************/
-void IWDG_Enable(void);
-
-/* Flag management function ***************************************************/
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_IWDG_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_lptim.h

@@ -1,386 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_lptim.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the LPTIM
-  *          firmware library
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4XX_LPTIM_H
-#define __STM32F4XX_LPTIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup LPTIM
-  * @{
-  */
-#if defined(STM32F410xx) || defined(STM32F413_423xx)
-/* Exported types ------------------------------------------------------------*/
-/**
-  * @brief   LPTIM Init structure definition
-  * @note
-  */
-typedef struct
-{
-  uint32_t LPTIM_ClockSource;          /*!< Selects the clock source.
-                                       This parameter can be a value of @ref LPTIM_Clock_Source */
-
-  uint32_t LPTIM_Prescaler;            /*!< Specifies the timer clock Prescaler.
-                                       This parameter can be a value of @ref LPTIM_Clock_Prescaler */
-
-  uint32_t LPTIM_Waveform;             /*!< Selects the output shape.
-                                       This parameter can be a value of @ref LPTIM_Waveform_Shape */
-
-  uint32_t LPTIM_OutputPolarity;       /*!< Specifies the LPTIM Output pin polarity.
-                                       This parameter can be a value of @ref LPTIM_Output_Polarity */
-}LPTIM_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup LPTIM_Exported_Constants
-  * @{
-  */
-
-#define IS_LPTIM_ALL_PERIPH(PERIPH)                  ((PERIPH) == LPTIM1)
-
-/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
-  * @{
-  */
-
-#define LPTIM_ClockSource_APBClock_LPosc     ((uint32_t)0x00000000)
-#define LPTIM_ClockSource_ULPTIM             ((uint32_t)0x00000001)
-#define IS_LPTIM_CLOCK_SOURCE(SOURCE)        (((SOURCE) == LPTIM_ClockSource_ULPTIM) || \
-                                              ((SOURCE) == LPTIM_ClockSource_APBClock_LPosc))
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
-  * @{
-  */
-#define LPTIM_Prescaler_DIV1                 ((uint32_t)0x00000000)
-#define LPTIM_Prescaler_DIV2                 ((uint32_t)0x00000200)
-#define LPTIM_Prescaler_DIV4                 ((uint32_t)0x00000400)
-#define LPTIM_Prescaler_DIV8                 ((uint32_t)0x00000600)
-#define LPTIM_Prescaler_DIV16                ((uint32_t)0x00000800)
-#define LPTIM_Prescaler_DIV32                ((uint32_t)0x00000A00)
-#define LPTIM_Prescaler_DIV64                ((uint32_t)0x00000C00)
-#define LPTIM_Prescaler_DIV128               ((uint32_t)0x00000E00)
-#define IS_LPTIM_CLOCK_PRESCALER(PRESCALER) (((PRESCALER) == LPTIM_Prescaler_DIV1) || \
-                                             ((PRESCALER) == LPTIM_Prescaler_DIV2) || \
-                                             ((PRESCALER) == LPTIM_Prescaler_DIV4) || \
-                                             ((PRESCALER) == LPTIM_Prescaler_DIV8) || \
-                                             ((PRESCALER) == LPTIM_Prescaler_DIV16) || \
-                                             ((PRESCALER) == LPTIM_Prescaler_DIV32) || \
-                                             ((PRESCALER) == LPTIM_Prescaler_DIV64) || \
-                                             ((PRESCALER) == LPTIM_Prescaler_DIV128))  
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Waveform_Shape LPTIM Waveform Shape
-  * @{
-  */
-#define LPTIM_Waveform_PWM_OnePulse          ((uint32_t)0x00000000)
-#define LPTIM_Waveform_SetOnce               ((uint32_t)0x00100000)
-#define IS_LPTIM_WAVEFORM(WAVE)             (((WAVE) == LPTIM_Waveform_SetOnce) || \
-                                            ((WAVE) == LPTIM_Waveform_PWM_OnePulse))
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
-  * @{
-  */
-#define LPTIM_OutputPolarity_High            ((uint32_t)0x00000000)
-#define LPTIM_OutputPolarity_Low             ((uint32_t)0x00200000)
-#define IS_LPTIM_OUTPUT_POLARITY(POLARITY)   (((POLARITY) == LPTIM_OutputPolarity_Low ) || \
-                                             ((POLARITY) == LPTIM_OutputPolarity_High))
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
-  * @{
-  */
-#define LPTIM_ClockPolarity_RisingEdge        ((uint32_t)0x00000000)
-#define LPTIM_ClockPolarity_FallingEdge       ((uint32_t)0x00000002)
-#define LPTIM_ClockPolarity_BothEdges         ((uint32_t)0x00000004)
-#define IS_LPTIM_CLOCK_POLARITY(POLARITY)     (((POLARITY) == LPTIM_ClockPolarity_RisingEdge ) || \
-                                             ((POLARITY) == LPTIM_ClockPolarity_FallingEdge ) || \
-                                             ((POLARITY) == LPTIM_ClockPolarity_BothEdges))
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_External_Trigger_Source LPTIM External Trigger Source
-  * @{
-  */
-#define LPTIM_ExtTRGSource_0          ((uint32_t)0x00000000)
-#define LPTIM_ExtTRGSource_1          ((uint32_t)0x00002000)
-#define LPTIM_ExtTRGSource_2          ((uint32_t)0x00004000)
-#define LPTIM_ExtTRGSource_3          ((uint32_t)0x00006000)
-#define LPTIM_ExtTRGSource_4          ((uint32_t)0x00008000)
-#define LPTIM_ExtTRGSource_5          ((uint32_t)0x0000A000)
-#define LPTIM_ExtTRGSource_6          ((uint32_t)0x0000C000)
-#define LPTIM_ExtTRGSource_7          ((uint32_t)0x0000E000)
-#define IS_LPTIM_EXT_TRG_SOURCE(TRIG)         (((TRIG) == LPTIM_ExtTRGSource_0) || \
-                                               ((TRIG) == LPTIM_ExtTRGSource_1) || \
-                                               ((TRIG) == LPTIM_ExtTRGSource_2) || \
-                                               ((TRIG) == LPTIM_ExtTRGSource_3) || \
-                                               ((TRIG) == LPTIM_ExtTRGSource_4) || \
-                                               ((TRIG) == LPTIM_ExtTRGSource_5) || \
-                                               ((TRIG) == LPTIM_ExtTRGSource_6) || \
-                                               ((TRIG) == LPTIM_ExtTRGSource_7))
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
-  * @{
-  */
-#define LPTIM_ExtTRGPolarity_RisingEdge       ((uint32_t)0x00020000)
-#define LPTIM_ExtTRGPolarity_FallingEdge      ((uint32_t)0x00040000)
-#define LPTIM_ExtTRGPolarity_BothEdges        ((uint32_t)0x00060000)
-#define IS_LPTIM_EXT_TRG_POLARITY(POLAR)      (((POLAR) == LPTIM_ExtTRGPolarity_RisingEdge) || \
-                                               ((POLAR) == LPTIM_ExtTRGPolarity_FallingEdge) || \
-                                               ((POLAR) == LPTIM_ExtTRGPolarity_BothEdges))
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
-  * @{
-  */
-#define LPTIM_ClockSampleTime_DirectTransistion  ((uint32_t)0x00000000)
-#define LPTIM_ClockSampleTime_2Transistions      ((uint32_t)0x00000008)
-#define LPTIM_ClockSampleTime_4Transistions      ((uint32_t)0x00000010)
-#define LPTIM_ClockSampleTime_8Transistions      ((uint32_t)0x00000018)
-#define IS_LPTIM_CLOCK_SAMPLE_TIME(SAMPLETIME)   (((SAMPLETIME) == LPTIM_ClockSampleTime_DirectTransistion) || \
-                                                  ((SAMPLETIME) == LPTIM_ClockSampleTime_2Transistions) || \
-                                                  ((SAMPLETIME) == LPTIM_ClockSampleTime_4Transistions) || \
-                                                  ((SAMPLETIME) == LPTIM_ClockSampleTime_8Transistions))
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
-  * @{
-  */
-#define LPTIM_TrigSampleTime_DirectTransistion   ((uint32_t)0x00000000)
-#define LPTIM_TrigSampleTime_2Transistions       ((uint32_t)0x00000040)
-#define LPTIM_TrigSampleTime_4Transistions       ((uint32_t)0x00000080)
-#define LPTIM_TrigSampleTime_8Transistions       ((uint32_t)0x000000C0)
-#define IS_LPTIM_TRIG_SAMPLE_TIME(SAMPLETIME)    (((SAMPLETIME) == LPTIM_TrigSampleTime_DirectTransistion) || \
-                                                  ((SAMPLETIME) == LPTIM_TrigSampleTime_2Transistions) || \
-                                                  ((SAMPLETIME) == LPTIM_TrigSampleTime_4Transistions) || \
-                                                  ((SAMPLETIME) == LPTIM_TrigSampleTime_8Transistions))
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Operating_Mode LPTIM Operating Mode
-  * @{
-  */
-#define LPTIM_Mode_Continuous                    ((uint32_t)0x00000004)
-#define LPTIM_Mode_Single                        ((uint32_t)0x00000002)
-#define IS_LPTIM_MODE(MODE)                      (((MODE) == LPTIM_Mode_Continuous) || \
-                                                  ((MODE) == LPTIM_Mode_Single))
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Updating_Register LPTIM Updating Register
-  * @{
-  */
-#define LPTIM_Update_Immediate                  ((uint32_t)0x00000000)
-#define LPTIM_Update_EndOfPeriod                ((uint32_t)0x00400000)
-#define IS_LPTIM_UPDATE(UPDATE)                 (((UPDATE) == LPTIM_Update_Immediate) || \
-                                                ((UPDATE) == LPTIM_Update_EndOfPeriod))
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
-  * @{
-  */
-#define LPTIM_IT_DOWN                            LPTIM_IER_DOWNIE
-#define LPTIM_IT_UP                              LPTIM_IER_UPIE
-#define LPTIM_IT_ARROK                           LPTIM_IER_ARROKIE
-#define LPTIM_IT_CMPOK                           LPTIM_IER_CMPOKIE
-#define LPTIM_IT_EXTTRIG                         LPTIM_IER_EXTTRIGIE
-#define LPTIM_IT_ARRM                            LPTIM_IER_ARRMIE
-#define LPTIM_IT_CMPM                            LPTIM_IER_CMPMIE
-#define IS_LPTIM_IT(IT)                          (((IT) == LPTIM_IT_DOWN) || \
-                                                  ((IT) == LPTIM_IT_UP) || \
-                                                  ((IT) == LPTIM_IT_ARROK) || \
-                                                  ((IT) == LPTIM_IT_CMPOK) || \
-                                                  ((IT) == LPTIM_IT_EXTTRIG) || \
-                                                  ((IT) == LPTIM_IT_ARRM) || \
-                                                  ((IT) == LPTIM_IT_CMPM))
-
-#define IS_LPTIM_GET_IT(IT)                      (((IT) == LPTIM_IT_DOWN) || \
-                                                  ((IT) == LPTIM_IT_UP) || \
-                                                  ((IT) == LPTIM_IT_ARROK) || \
-                                                  ((IT) == LPTIM_IT_CMPOK) || \
-                                                  ((IT) == LPTIM_IT_EXTTRIG) || \
-                                                  ((IT) == LPTIM_IT_ARRM) || \
-                                                  ((IT) == LPTIM_IT_CMPM))
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Flag_Definition LPTIM Flag Definition
-  * @{
-  */
-#define LPTIM_FLAG_DOWN                          LPTIM_ISR_DOWN
-#define LPTIM_FLAG_UP                            LPTIM_ISR_UP
-#define LPTIM_FLAG_ARROK                         LPTIM_ISR_ARROK
-#define LPTIM_FLAG_CMPOK                         LPTIM_ISR_CMPOK
-#define LPTIM_FLAG_EXTTRIG                       LPTIM_ISR_EXTTRIG
-#define LPTIM_FLAG_ARRM                          LPTIM_ISR_ARRM
-#define LPTIM_FLAG_CMPM                          LPTIM_ISR_CMPM
-#define IS_LPTIM_GET_FLAG(FLAG)                 (((FLAG) == LPTIM_FLAG_DOWN) || \
-                                                 ((FLAG) == LPTIM_FLAG_UP) || \
-                                                 ((FLAG) == LPTIM_FLAG_ARROK) || \
-                                                 ((FLAG) == LPTIM_FLAG_CMPOK) || \
-                                                 ((FLAG) == LPTIM_FLAG_EXTTRIG) || \
-                                                 ((FLAG) == LPTIM_FLAG_ARRM) || \
-                                                 ((FLAG) == LPTIM_FLAG_CMPM))
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Clear_Flag_Definition LPTIM Clear Flag Definition
-  * @{
-  */
-#define LPTIM_CLEAR_DOWN                        LPTIM_ICR_DOWNCF
-#define LPTIM_CLEAR_UP                          LPTIM_ICR_UPCF
-#define LPTIM_CLEAR_ARROK                       LPTIM_ICR_ARROKCF
-#define LPTIM_CLEAR_CMPOK                       LPTIM_ICR_CMPOKCF
-#define LPTIM_CLEAR_EXTTRIG                     LPTIM_ICR_EXTTRIGCF
-#define LPTIM_CLEAR_ARRM                        LPTIM_ICR_ARRMCF
-#define LPTIM_CLEAR_CMPM                        LPTIM_ICR_CMPMCF
-#define IS_LPTIM_CLEAR_FLAG(CLEARF)              (((CLEARF) == LPTIM_CLEAR_DOWN) || \
-                                                  ((CLEARF) == LPTIM_CLEAR_UP) || \
-                                                  ((CLEARF) == LPTIM_CLEAR_ARROK) || \
-                                                  ((CLEARF) == LPTIM_CLEAR_CMPOK) || \
-                                                  ((CLEARF) == LPTIM_CLEAR_EXTTRIG) || \
-                                                  ((CLEARF) == LPTIM_CLEAR_ARRM ) || \
-                                                  ((CLEARF) == LPTIM_CLEAR_CMPM))
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Autorelaod_Value LPTIM Autorelaod Value
-  * @{
-  */
-#define IS_LPTIM_AUTORELOAD(AUTORELOAD)         ((AUTORELOAD) <= 0x0000FFFF)
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Compare_Value LPTIM Compare Value
-  * @{
-  */
-#define IS_LPTIM_COMPARE(COMPARE)               ((COMPARE) <= 0x0000FFFF)
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Option_Register_Definition LPTIM Option Register Definition
-  * @{
-  */
-#define LPTIM_OP_PAD_AF                          ((uint32_t)0x00000000)
-#define LPTIM_OP_PAD_PA4                         LPTIM_OR_OR_0
-#define LPTIM_OP_PAD_PB9                         LPTIM_OR_OR_1
-#define LPTIM_OP_TIM_DAC                         LPTIM_OR_OR
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Initialization functions ***************************************************/
-void LPTIM_DeInit(LPTIM_TypeDef* LPTIMx);
-void LPTIM_Init(LPTIM_TypeDef* LPTIMx, LPTIM_InitTypeDef* LPTIM_InitStruct);
-void LPTIM_StructInit(LPTIM_InitTypeDef* LPTIM_InitStruct);
-
-/* Configuration functions ****************************************************/
-void LPTIM_Cmd(LPTIM_TypeDef* LPTIMx, FunctionalState NewState);
-void LPTIM_SelectClockSource(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_ClockSource);
-void LPTIM_SelectULPTIMClockPolarity(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_ClockPolarity);
-void LPTIM_ConfigPrescaler(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Prescaler);
-void LPTIM_ConfigExternalTrigger(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_ExtTRGSource, uint32_t LPTIM_ExtTRGPolarity);
-void LPTIM_SelectSoftwareStart(LPTIM_TypeDef* LPTIMx);
-void LPTIM_ConfigTriggerGlitchFilter(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_TrigSampleTime);
-void LPTIM_ConfigClockGlitchFilter(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_ClockSampleTime);
-void LPTIM_SelectOperatingMode(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Mode);
-void LPTIM_TimoutCmd(LPTIM_TypeDef* LPTIMx, FunctionalState NewState);
-void LPTIM_ConfigWaveform(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Waveform);
-void LPTIM_ConfigUpdate(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Update);
-void LPTIM_SetAutoreloadValue(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Autoreload);
-void LPTIM_SetCompareValue(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_Compare);
-void LPTIM_SelectCounterMode(LPTIM_TypeDef* LPTIMx, FunctionalState NewState);
-void LPTIM_SelectEncoderMode(LPTIM_TypeDef* LPTIMx, FunctionalState NewState);
-void LPTIM_RemapConfig(LPTIM_TypeDef* LPTIMx,uint32_t LPTIM_OPTR);
-uint32_t LPTIM_GetCounterValue(LPTIM_TypeDef* LPTIMx);
-uint32_t LPTIM_GetAutoreloadValue(LPTIM_TypeDef* LPTIMx); 
-uint32_t LPTIM_GetCompareValue(LPTIM_TypeDef* LPTIMx);
-
-/* Interrupts and flags management functions **********************************/
-void LPTIM_ITConfig(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_IT, FunctionalState NewState);
-FlagStatus LPTIM_GetFlagStatus(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_FLAG);
-void LPTIM_ClearFlag(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_CLEARF);
-ITStatus LPTIM_GetITStatus(LPTIM_TypeDef* LPTIMx, uint32_t LPTIM_IT);
-
-#endif /* STM32F410xx || STM32F413_423xx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_LPTIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h

@@ -1,503 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_ltdc.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the LTDC firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LTDC_H
-#define __STM32F4xx_LTDC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup LTDC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
- 
-/** 
-  * @brief  LTDC Init structure definition  
-  */
-
-typedef struct
-{
-  uint32_t LTDC_HSPolarity;                 /*!< configures the horizontal synchronization polarity.
-                                                 This parameter can be one value of @ref LTDC_HSPolarity */
-
-  uint32_t LTDC_VSPolarity;                 /*!< configures the vertical synchronization polarity.
-                                                 This parameter can be one value of @ref LTDC_VSPolarity */
-
-  uint32_t LTDC_DEPolarity;                 /*!< configures the data enable polarity. This parameter can
-                                                 be one of value of @ref LTDC_DEPolarity */
-
-  uint32_t LTDC_PCPolarity;                 /*!< configures the pixel clock polarity. This parameter can
-                                                 be one of value of @ref LTDC_PCPolarity */
-
-  uint32_t LTDC_HorizontalSync;             /*!< configures the number of Horizontal synchronization 
-                                                 width. This parameter must range from 0x000 to 0xFFF. */
-
-  uint32_t LTDC_VerticalSync;               /*!< configures the number of Vertical synchronization 
-                                                 height. This parameter must range from 0x000 to 0x7FF. */
-
-  uint32_t LTDC_AccumulatedHBP;             /*!< configures the accumulated horizontal back porch width.
-                                                 This parameter must range from LTDC_HorizontalSync to 0xFFF. */
-
-  uint32_t LTDC_AccumulatedVBP;             /*!< configures the accumulated vertical back porch height.
-                                                 This parameter must range from LTDC_VerticalSync to 0x7FF. */
-            
-  uint32_t LTDC_AccumulatedActiveW;         /*!< configures the accumulated active width. This parameter 
-                                                 must range from LTDC_AccumulatedHBP to 0xFFF. */
-
-  uint32_t LTDC_AccumulatedActiveH;         /*!< configures the accumulated active height. This parameter 
-                                                 must range from LTDC_AccumulatedVBP to 0x7FF. */
-
-  uint32_t LTDC_TotalWidth;                 /*!< configures the total width. This parameter 
-                                                 must range from LTDC_AccumulatedActiveW to 0xFFF. */
-
-  uint32_t LTDC_TotalHeigh;                 /*!< configures the total height. This parameter 
-                                                 must range from LTDC_AccumulatedActiveH to 0x7FF. */
-            
-  uint32_t LTDC_BackgroundRedValue;         /*!< configures the background red value.
-                                                 This parameter must range from 0x00 to 0xFF. */
-
-  uint32_t LTDC_BackgroundGreenValue;       /*!< configures the background green value.
-                                                 This parameter must range from 0x00 to 0xFF. */ 
-
-   uint32_t LTDC_BackgroundBlueValue;       /*!< configures the background blue value.
-                                                 This parameter must range from 0x00 to 0xFF. */
-} LTDC_InitTypeDef;
-
-/** 
-  * @brief  LTDC Layer structure definition  
-  */
-
-typedef struct
-{
-  uint32_t LTDC_HorizontalStart;            /*!< Configures the Window Horizontal Start Position.
-                                                 This parameter must range from 0x000 to 0xFFF. */
-            
-  uint32_t LTDC_HorizontalStop;             /*!< Configures the Window Horizontal Stop Position.
-                                                 This parameter must range from 0x0000 to 0xFFFF. */
-  
-  uint32_t LTDC_VerticalStart;              /*!< Configures the Window vertical Start Position.
-                                                 This parameter must range from 0x000 to 0xFFF. */
-
-  uint32_t LTDC_VerticalStop;               /*!< Configures the Window vaertical Stop Position.
-                                                 This parameter must range from 0x0000 to 0xFFFF. */
-  
-  uint32_t LTDC_PixelFormat;                /*!< Specifies the pixel format. This parameter can be 
-                                                 one of value of @ref LTDC_Pixelformat */
-
-  uint32_t LTDC_ConstantAlpha;              /*!< Specifies the constant alpha used for blending.
-                                                 This parameter must range from 0x00 to 0xFF. */
-
-  uint32_t LTDC_DefaultColorBlue;           /*!< Configures the default blue value.
-                                                 This parameter must range from 0x00 to 0xFF. */
-
-  uint32_t LTDC_DefaultColorGreen;          /*!< Configures the default green value.
-                                                 This parameter must range from 0x00 to 0xFF. */
-            
-  uint32_t LTDC_DefaultColorRed;            /*!< Configures the default red value.
-                                                 This parameter must range from 0x00 to 0xFF. */
-
-  uint32_t LTDC_DefaultColorAlpha;          /*!< Configures the default alpha value.
-                                                 This parameter must range from 0x00 to 0xFF. */
-
-  uint32_t LTDC_BlendingFactor_1;           /*!< Select the blending factor 1. This parameter 
-                                                 can be one of value of @ref LTDC_BlendingFactor1 */
-
-  uint32_t LTDC_BlendingFactor_2;           /*!< Select the blending factor 2. This parameter 
-                                                 can be one of value of @ref LTDC_BlendingFactor2 */
-            
-  uint32_t LTDC_CFBStartAdress;             /*!< Configures the color frame buffer address */
-
-  uint32_t LTDC_CFBLineLength;              /*!< Configures the color frame buffer line length. 
-                                                 This parameter must range from 0x0000 to 0x1FFF. */
-
-  uint32_t LTDC_CFBPitch;                   /*!< Configures the color frame buffer pitch in bytes.
-                                                 This parameter must range from 0x0000 to 0x1FFF. */
-                                                 
-  uint32_t LTDC_CFBLineNumber;              /*!< Specifies the number of line in frame buffer. 
-                                                 This parameter must range from 0x000 to 0x7FF. */
-} LTDC_Layer_InitTypeDef;
-
-/** 
-  * @brief  LTDC Position structure definition  
-  */
-typedef struct
-{
-  uint32_t LTDC_POSX;                         /*!<  Current X Position */
-  uint32_t LTDC_POSY;                         /*!<  Current Y Position */
-} LTDC_PosTypeDef;
-
-/** 
-  * @brief  LTDC RGB structure definition  
-  */
-typedef struct
-{
-  uint32_t LTDC_BlueWidth;                        /*!< Blue width */
-  uint32_t LTDC_GreenWidth;                       /*!< Green width */
-  uint32_t LTDC_RedWidth;                         /*!< Red width */
-} LTDC_RGBTypeDef;
-
-/** 
-  * @brief  LTDC Color Keying structure definition  
-  */
-typedef struct
-{
-  uint32_t LTDC_ColorKeyBlue;               /*!< Configures the color key blue value. 
-                                                 This parameter must range from 0x00 to 0xFF. */
-
-  uint32_t LTDC_ColorKeyGreen;              /*!< Configures the color key green value. 
-                                                 This parameter must range from 0x00 to 0xFF. */
-            
-  uint32_t LTDC_ColorKeyRed;                /*!< Configures the color key red value. 
-                                                 This parameter must range from 0x00 to 0xFF. */
-} LTDC_ColorKeying_InitTypeDef;
-
-/** 
-  * @brief  LTDC CLUT structure definition  
-  */
-typedef struct
-{
-  uint32_t LTDC_CLUTAdress;                 /*!< Configures the CLUT address.
-                                                 This parameter must range from 0x00 to 0xFF. */
-
-  uint32_t LTDC_BlueValue;                  /*!< Configures the blue value. 
-                                                 This parameter must range from 0x00 to 0xFF. */
-                                                 
-  uint32_t LTDC_GreenValue;                 /*!< Configures the green value. 
-                                                 This parameter must range from 0x00 to 0xFF. */
-
-  uint32_t LTDC_RedValue;                   /*!< Configures the red value.
-                                                 This parameter must range from 0x00 to 0xFF. */
-} LTDC_CLUT_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup LTDC_Exported_Constants
-  * @{
-  */
-  
-/** @defgroup LTDC_SYNC 
-  * @{
-  */
-
-#define LTDC_HorizontalSYNC               ((uint32_t)0x00000FFF)
-#define LTDC_VerticalSYNC                 ((uint32_t)0x000007FF)
-
-#define IS_LTDC_HSYNC(HSYNC) ((HSYNC) <= LTDC_HorizontalSYNC)
-#define IS_LTDC_VSYNC(VSYNC) ((VSYNC) <= LTDC_VerticalSYNC)
-#define IS_LTDC_AHBP(AHBP)  ((AHBP) <= LTDC_HorizontalSYNC)
-#define IS_LTDC_AVBP(AVBP) ((AVBP) <= LTDC_VerticalSYNC)
-#define IS_LTDC_AAW(AAW)   ((AAW) <= LTDC_HorizontalSYNC)
-#define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VerticalSYNC)
-#define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HorizontalSYNC)
-#define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VerticalSYNC)
-/**
-  * @}
-  */
-
-/** @defgroup LTDC_HSPolarity 
-  * @{
-  */
-#define LTDC_HSPolarity_AL                ((uint32_t)0x00000000)                /*!< Horizontal Synchronization is active low. */
-#define LTDC_HSPolarity_AH                LTDC_GCR_HSPOL                        /*!< Horizontal Synchronization is active high. */
-
-#define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPolarity_AL) || \
-                              ((HSPOL) == LTDC_HSPolarity_AH))
-/**
-  * @}
-  */
-
-/** @defgroup LTDC_VSPolarity 
-  * @{
-  */
-#define LTDC_VSPolarity_AL                ((uint32_t)0x00000000)                /*!< Vertical Synchronization is active low. */
-#define LTDC_VSPolarity_AH                LTDC_GCR_VSPOL                        /*!< Vertical Synchronization is active high. */
-
-#define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPolarity_AL) || \
-                              ((VSPOL) == LTDC_VSPolarity_AH))  
-/**
-  * @}
-  */
-
-/** @defgroup LTDC_DEPolarity 
-  * @{
-  */
-#define LTDC_DEPolarity_AL                ((uint32_t)0x00000000)                /*!< Data Enable, is active low. */
-#define LTDC_DEPolarity_AH                LTDC_GCR_DEPOL                        /*!< Data Enable, is active high. */
-
-#define IS_LTDC_DEPOL(DEPOL) (((DEPOL) ==  LTDC_VSPolarity_AL) || \
-                              ((DEPOL) ==  LTDC_DEPolarity_AH))
-/**
-  * @}
-  */
-
-/** @defgroup LTDC_PCPolarity 
-  * @{
-  */
-#define LTDC_PCPolarity_IPC               ((uint32_t)0x00000000)                /*!< input pixel clock. */
-#define LTDC_PCPolarity_IIPC              LTDC_GCR_PCPOL                        /*!< inverted input pixel clock. */
-
-#define IS_LTDC_PCPOL(PCPOL) (((PCPOL) ==  LTDC_PCPolarity_IPC) || \
-                              ((PCPOL) ==  LTDC_PCPolarity_IIPC))
-/**
-  * @}
-  */
-
-/** @defgroup LTDC_Reload 
-  * @{
-  */
-#define LTDC_IMReload                     LTDC_SRCR_IMR                         /*!< Immediately Reload. */
-#define LTDC_VBReload                     LTDC_SRCR_VBR                         /*!< Vertical Blanking Reload. */
-
-#define IS_LTDC_RELOAD(RELOAD) (((RELOAD) == LTDC_IMReload) || \
-                                ((RELOAD) == LTDC_VBReload))
-/**
-  * @}
-  */
-
-/** @defgroup LTDC_Back_Color
-  * @{
-  */
-#define LTDC_Back_Color                   ((uint32_t)0x000000FF)
-
-#define IS_LTDC_BackBlueValue(BBLUE)    ((BBLUE) <= LTDC_Back_Color)
-#define IS_LTDC_BackGreenValue(BGREEN)  ((BGREEN) <= LTDC_Back_Color)
-#define IS_LTDC_BackRedValue(BRED)      ((BRED) <= LTDC_Back_Color) 
-/**
-  * @}
-  */
-
-/** @defgroup LTDC_Position 
-  * @{
-  */
-#define LTDC_POS_CY                       LTDC_CPSR_CYPOS
-#define LTDC_POS_CX                       LTDC_CPSR_CXPOS
-
-#define IS_LTDC_GET_POS(POS) (((POS) <= LTDC_POS_CY))
-/**
-  * @}
-  */
-
-/** @defgroup LTDC_LIPosition 
-  * @{
-  */
-#define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF)
-/**
-  * @}
-  */
-
-/** @defgroup LTDC_CurrentStatus 
-  * @{
-  */
-#define LTDC_CD_VDES                     LTDC_CDSR_VDES
-#define LTDC_CD_HDES                     LTDC_CDSR_HDES
-#define LTDC_CD_VSYNC                    LTDC_CDSR_VSYNCS
-#define LTDC_CD_HSYNC                    LTDC_CDSR_HSYNCS
-
-#define IS_LTDC_GET_CD(CD) (((CD) == LTDC_CD_VDES) || ((CD) == LTDC_CD_HDES) || \
-                              ((CD) == LTDC_CD_VSYNC) || ((CD) == LTDC_CD_HSYNC))
-/**
-  * @}
-  */
-
-/** @defgroup LTDC_Interrupts 
-  * @{
-  */
-#define LTDC_IT_LI                      LTDC_IER_LIE
-#define LTDC_IT_FU                      LTDC_IER_FUIE
-#define LTDC_IT_TERR                    LTDC_IER_TERRIE
-#define LTDC_IT_RR                      LTDC_IER_RRIE
-
-#define IS_LTDC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF0) == 0x00) && ((IT) != 0x00))
-
-/**
-  * @}
-  */
-
-/** @defgroup LTDC_Flag 
-  * @{
-  */
-#define LTDC_FLAG_LI                     LTDC_ISR_LIF
-#define LTDC_FLAG_FU                     LTDC_ISR_FUIF
-#define LTDC_FLAG_TERR                   LTDC_ISR_TERRIF
-#define LTDC_FLAG_RR                     LTDC_ISR_RRIF
-
-#define IS_LTDC_FLAG(FLAG) (((FLAG) == LTDC_FLAG_LI) || ((FLAG) == LTDC_FLAG_FU) || \
-                               ((FLAG) == LTDC_FLAG_TERR) || ((FLAG) == LTDC_FLAG_RR))
-/**
-  * @}
-  */
-
-/** @defgroup LTDC_Pixelformat 
-  * @{
-  */
-#define LTDC_Pixelformat_ARGB8888                  ((uint32_t)0x00000000)
-#define LTDC_Pixelformat_RGB888                    ((uint32_t)0x00000001)
-#define LTDC_Pixelformat_RGB565                    ((uint32_t)0x00000002)
-#define LTDC_Pixelformat_ARGB1555                  ((uint32_t)0x00000003)
-#define LTDC_Pixelformat_ARGB4444                  ((uint32_t)0x00000004)
-#define LTDC_Pixelformat_L8                        ((uint32_t)0x00000005)
-#define LTDC_Pixelformat_AL44                      ((uint32_t)0x00000006)
-#define LTDC_Pixelformat_AL88                      ((uint32_t)0x00000007)
-
-#define IS_LTDC_Pixelformat(Pixelformat) (((Pixelformat) == LTDC_Pixelformat_ARGB8888) || ((Pixelformat) == LTDC_Pixelformat_RGB888)   || \
-                        ((Pixelformat) == LTDC_Pixelformat_RGB565)   || ((Pixelformat) == LTDC_Pixelformat_ARGB1555) || \
-                        ((Pixelformat) == LTDC_Pixelformat_ARGB4444) || ((Pixelformat) == LTDC_Pixelformat_L8)       || \
-                        ((Pixelformat) == LTDC_Pixelformat_AL44)     || ((Pixelformat) == LTDC_Pixelformat_AL88))
-
-/**
-  * @}
-  */
-
-/** @defgroup LTDC_BlendingFactor1 
-  * @{
-  */
-#define LTDC_BlendingFactor1_CA                       ((uint32_t)0x00000400)
-#define LTDC_BlendingFactor1_PAxCA                    ((uint32_t)0x00000600)
-
-#define IS_LTDC_BlendingFactor1(BlendingFactor1) (((BlendingFactor1) == LTDC_BlendingFactor1_CA) || ((BlendingFactor1) == LTDC_BlendingFactor1_PAxCA))
-/**
-  * @}
-  */
-
-/** @defgroup LTDC_BlendingFactor2
-  * @{
-  */
-#define LTDC_BlendingFactor2_CA                       ((uint32_t)0x00000005)
-#define LTDC_BlendingFactor2_PAxCA                    ((uint32_t)0x00000007)
-
-#define IS_LTDC_BlendingFactor2(BlendingFactor2) (((BlendingFactor2) == LTDC_BlendingFactor2_CA) || ((BlendingFactor2) == LTDC_BlendingFactor2_PAxCA))
-/**
-  * @}
-  */
-
-/** @defgroup LTDC_LAYER_Config
-  * @{
-  */
-#define LTDC_STOPPosition                 ((uint32_t)0x0000FFFF)
-#define LTDC_STARTPosition                ((uint32_t)0x00000FFF)
-
-#define LTDC_DefaultColorConfig           ((uint32_t)0x000000FF)
-#define LTDC_ColorFrameBuffer             ((uint32_t)0x00001FFF)
-#define LTDC_LineNumber                   ((uint32_t)0x000007FF)
-
-#define IS_LTDC_HCONFIGST(HCONFIGST) ((HCONFIGST) <= LTDC_STARTPosition)
-#define IS_LTDC_HCONFIGSP(HCONFIGSP) ((HCONFIGSP) <= LTDC_STOPPosition)
-#define IS_LTDC_VCONFIGST(VCONFIGST)  ((VCONFIGST) <= LTDC_STARTPosition)
-#define IS_LTDC_VCONFIGSP(VCONFIGSP) ((VCONFIGSP) <= LTDC_STOPPosition)
-
-#define IS_LTDC_DEFAULTCOLOR(DEFAULTCOLOR) ((DEFAULTCOLOR) <= LTDC_DefaultColorConfig)
-
-#define IS_LTDC_CFBP(CFBP) ((CFBP) <= LTDC_ColorFrameBuffer)
-#define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_ColorFrameBuffer)
-
-#define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LineNumber)
-/**
-  * @}
-  */
-
-/** @defgroup LTDC_colorkeying_Config
-  * @{
-  */
-#define LTDC_colorkeyingConfig            ((uint32_t)0x000000FF)
-
-#define IS_LTDC_CKEYING(CKEYING) ((CKEYING) <= LTDC_colorkeyingConfig)
-/**
-  * @}
-  */
-
-/** @defgroup LTDC_CLUT_Config
-  * @{
-  */
-
-#define LTDC_CLUTWR                       ((uint32_t)0x000000FF)
-
-#define IS_LTDC_CLUTWR(CLUTWR)  ((CLUTWR) <= LTDC_CLUTWR)
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/*  Function used to set the LTDC configuration to the default reset state *****/
-void LTDC_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void LTDC_Init(LTDC_InitTypeDef* LTDC_InitStruct);
-void LTDC_StructInit(LTDC_InitTypeDef* LTDC_InitStruct);
-void LTDC_Cmd(FunctionalState NewState);
-void LTDC_DitherCmd(FunctionalState NewState);
-LTDC_RGBTypeDef LTDC_GetRGBWidth(void);
-void LTDC_RGBStructInit(LTDC_RGBTypeDef* LTDC_RGB_InitStruct);
-void LTDC_LIPConfig(uint32_t LTDC_LIPositionConfig);
-void LTDC_ReloadConfig(uint32_t LTDC_Reload);
-void LTDC_LayerInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_Layer_InitTypeDef* LTDC_Layer_InitStruct);
-void LTDC_LayerStructInit(LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct);
-void LTDC_LayerCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState);
-LTDC_PosTypeDef LTDC_GetPosStatus(void);
-void LTDC_PosStructInit(LTDC_PosTypeDef* LTDC_Pos_InitStruct);
-FlagStatus LTDC_GetCDStatus(uint32_t LTDC_CD);
-void LTDC_ColorKeyingConfig(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct, FunctionalState NewState);
-void LTDC_ColorKeyingStructInit(LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct);
-void LTDC_CLUTCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState);
-void LTDC_CLUTInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct);
-void LTDC_CLUTStructInit(LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct);
-void LTDC_LayerPosition(LTDC_Layer_TypeDef* LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY);
-void LTDC_LayerAlpha(LTDC_Layer_TypeDef* LTDC_Layerx, uint8_t ConstantAlpha);
-void LTDC_LayerAddress(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Address);
-void LTDC_LayerSize(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Width, uint32_t Height);
-void LTDC_LayerPixelFormat(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t PixelFormat);
-
-/* Interrupts and flags management functions **********************************/
-void LTDC_ITConfig(uint32_t LTDC_IT, FunctionalState NewState);
-FlagStatus LTDC_GetFlagStatus(uint32_t LTDC_FLAG);
-void LTDC_ClearFlag(uint32_t LTDC_FLAG);
-ITStatus LTDC_GetITStatus(uint32_t LTDC_IT);
-void LTDC_ClearITPendingBit(uint32_t LTDC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_LTDC_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h

@@ -1,245 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_pwr.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the PWR firmware 
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_PWR_H
-#define __STM32F4xx_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup PWR
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Constants
-  * @{
-  */ 
-
-/** @defgroup PWR_PVD_detection_level 
-  * @{
-  */ 
-#define PWR_PVDLevel_0                  PWR_CR_PLS_LEV0
-#define PWR_PVDLevel_1                  PWR_CR_PLS_LEV1
-#define PWR_PVDLevel_2                  PWR_CR_PLS_LEV2
-#define PWR_PVDLevel_3                  PWR_CR_PLS_LEV3
-#define PWR_PVDLevel_4                  PWR_CR_PLS_LEV4
-#define PWR_PVDLevel_5                  PWR_CR_PLS_LEV5
-#define PWR_PVDLevel_6                  PWR_CR_PLS_LEV6
-#define PWR_PVDLevel_7                  PWR_CR_PLS_LEV7
-
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
-                                 ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
-                                 ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
-                                 ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
-/**
-  * @}
-  */
-
-  
-/** @defgroup PWR_Regulator_state_in_STOP_mode 
-  * @{
-  */
-#define PWR_MainRegulator_ON                        ((uint32_t)0x00000000)
-#define PWR_LowPowerRegulator_ON                    PWR_CR_LPDS
-
-/* --- PWR_Legacy ---*/
-#define PWR_Regulator_ON                            PWR_MainRegulator_ON
-#define PWR_Regulator_LowPower                      PWR_LowPowerRegulator_ON
-
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MainRegulator_ON) || \
-                                     ((REGULATOR) == PWR_LowPowerRegulator_ON))
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Regulator_state_in_UnderDrive_mode 
-  * @{
-  */
-#define PWR_MainRegulator_UnderDrive_ON               PWR_CR_MRUDS
-#define PWR_LowPowerRegulator_UnderDrive_ON           ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
-
-#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MainRegulator_UnderDrive_ON) || \
-                                                ((REGULATOR) == PWR_LowPowerRegulator_UnderDrive_ON))
-
-/**
-  * @}
-  */
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
-/** @defgroup PWR_Wake_Up_Pin
-  * @{
-  */
-#define PWR_WakeUp_Pin1           ((uint32_t)0x00)
-#define PWR_WakeUp_Pin2           ((uint32_t)0x01)
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
-#define PWR_WakeUp_Pin3           ((uint32_t)0x02)
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
-
-#if defined(STM32F446xx)
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUp_Pin1) || \
-                                ((PIN) == PWR_WakeUp_Pin2))
-#else /* STM32F410xx || STM32F412xG */
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUp_Pin1) || ((PIN) == PWR_WakeUp_Pin2) || \
-                                ((PIN) == PWR_WakeUp_Pin3)) 
-#endif /* STM32F446xx */
-/**
-  * @}
-  */    
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
-
-/** @defgroup PWR_STOP_mode_entry 
-  * @{
-  */
-#define PWR_STOPEntry_WFI               ((uint8_t)0x01)
-#define PWR_STOPEntry_WFE               ((uint8_t)0x02)
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Regulator_Voltage_Scale 
-  * @{
-  */
-#define PWR_Regulator_Voltage_Scale1    ((uint32_t)0x0000C000)
-#define PWR_Regulator_Voltage_Scale2    ((uint32_t)0x00008000)
-#define PWR_Regulator_Voltage_Scale3    ((uint32_t)0x00004000)
-#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || \
-                                           ((VOLTAGE) == PWR_Regulator_Voltage_Scale2) || \
-                                           ((VOLTAGE) == PWR_Regulator_Voltage_Scale3))
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Flag 
-  * @{
-  */
-#define PWR_FLAG_WU                     PWR_CSR_WUF
-#define PWR_FLAG_SB                     PWR_CSR_SBF
-#define PWR_FLAG_PVDO                   PWR_CSR_PVDO
-#define PWR_FLAG_BRR                    PWR_CSR_BRR
-#define PWR_FLAG_VOSRDY                 PWR_CSR_VOSRDY
-#define PWR_FLAG_ODRDY                  PWR_CSR_ODRDY
-#define PWR_FLAG_ODSWRDY                PWR_CSR_ODSWRDY
-#define PWR_FLAG_UDRDY                  PWR_CSR_UDSWRDY
-
-/* --- FLAG Legacy ---*/
-#define PWR_FLAG_REGRDY                  PWR_FLAG_VOSRDY               
-
-#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
-                               ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \
-                               ((FLAG) == PWR_FLAG_VOSRDY) || ((FLAG) == PWR_FLAG_ODRDY) || \
-                               ((FLAG) == PWR_FLAG_ODSWRDY) || ((FLAG) == PWR_FLAG_UDRDY))
-
-
-#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
-                                 ((FLAG) == PWR_FLAG_UDRDY))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/ 
-
-/* Function used to set the PWR configuration to the default reset state ******/ 
-void PWR_DeInit(void);
-
-/* Backup Domain Access function **********************************************/ 
-void PWR_BackupAccessCmd(FunctionalState NewState);
-
-/* PVD configuration functions ************************************************/ 
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
-void PWR_PVDCmd(FunctionalState NewState);
-
-/* WakeUp pins configuration functions ****************************************/
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
-void PWR_WakeUpPinCmd(FunctionalState NewState);
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
-#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) ||defined(STM32F446xx)
-void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPinx, FunctionalState NewState);
-#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
-/* Main and Backup Regulators configuration functions *************************/ 
-void PWR_BackupRegulatorCmd(FunctionalState NewState);
-void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage);
-void PWR_OverDriveCmd(FunctionalState NewState);
-void PWR_OverDriveSWCmd(FunctionalState NewState);
-void PWR_UnderDriveCmd(FunctionalState NewState);
-
-#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
-void PWR_MainRegulatorUnderDriveCmd(FunctionalState NewState);
-void PWR_LowRegulatorUnderDriveCmd(FunctionalState NewState);
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx */
-
-#if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) || defined(STM32F413_423xx)
-void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState);
-void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState);
-#endif /* STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F413_423xx */
-
-/* FLASH Power Down configuration functions ***********************************/ 
-void PWR_FlashPowerDownCmd(FunctionalState NewState);
-
-/* Low Power modes configuration functions ************************************/ 
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
-void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
-void PWR_EnterSTANDBYMode(void);
-
-/* Flags management functions *************************************************/ 
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
-void PWR_ClearFlag(uint32_t PWR_FLAG);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_PWR_H */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_qspi.h

@@ -1,493 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_qspi.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the QSPI 
-  *          firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4XX_QUADSPI_H
-#define __STM32F4XX_QUADSPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup QSPI
-  * @{
-  */
-#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  QSPI Communication Configuration Init structure definition  
-  */
-
-typedef struct
-{
-  
-  uint32_t QSPI_ComConfig_FMode;            /* Specifies the Functional Mode
-                                          This parameter can be a value of @ref QSPI_ComConfig_Functional_Mode*/  
-	
-  uint32_t QSPI_ComConfig_DDRMode;          /* Specifies the Double Data Rate Mode
-                                          This parameter can be a value of @ref QSPI_ComConfig_DoubleDataRateMode*/
-	
-  uint32_t QSPI_ComConfig_DHHC;            /* Specifies the Delay Half Hclk Cycle
-                                          This parameter can be a value of @ref QSPI_ComConfig_DelayHalfHclkCycle*/
-  
-  uint32_t QSPI_ComConfig_SIOOMode;         /* Specifies the Send Instruction Only Once Mode
-                                          This parameter can be a value of @ref QSPI_ComConfig_SendInstructionOnlyOnceMode*/
-  
-  uint32_t QSPI_ComConfig_DMode;            /* Specifies the Data Mode
-                                          This parameter can be a value of @ref QSPI_ComConfig_DataMode*/
-  
-  uint32_t QSPI_ComConfig_DummyCycles;      /* Specifies the Number of Dummy Cycles.
-                                           This parameter can be a number between 0x00 and 0x1F */             
-
-  uint32_t QSPI_ComConfig_ABSize;           /* Specifies the Alternate Bytes Size
-                                          This parameter can be a value of @ref QSPI_ComConfig_AlternateBytesSize*/ 
-
-  uint32_t QSPI_ComConfig_ABMode;           /* Specifies the Alternate Bytes Mode
-                                          This parameter can be a value of @ref QSPI_ComConfig_AlternateBytesMode*/     
- 
-  uint32_t QSPI_ComConfig_ADSize;           /* Specifies the Address Size
-                                          This parameter can be a value of @ref QSPI_ComConfig_AddressSize*/
-
-  uint32_t QSPI_ComConfig_ADMode;           /* Specifies the Address Mode
-                                          This parameter can be a value of @ref QSPI_ComConfig_AddressMode*/
-  
-  uint32_t QSPI_ComConfig_IMode;            /* Specifies the Instruction Mode
-                                          This parameter can be a value of @ref QSPI_ComConfig_InstructionMode*/
-
-  uint32_t QSPI_ComConfig_Ins;      /* Specifies the Instruction Mode
-                                          This parameter can be a value of @ref QSPI_ComConfig_Instruction*/
-  
-}QSPI_ComConfig_InitTypeDef;
-
-/** 
-  * @brief  QSPI Init structure definition  
-  */
-
-typedef struct
-{
-  uint32_t QSPI_SShift;    /* Specifies the Sample Shift
-                              This parameter can be a value of @ref QSPI_Sample_Shift*/
-
-  uint32_t QSPI_Prescaler; /* Specifies the prescaler value used to divide the QSPI clock.
-                              This parameter can be a number between 0x00 and 0xFF */ 
-
-  uint32_t QSPI_CKMode;    /* Specifies the Clock Mode
-                              This parameter can be a value of @ref QSPI_Clock_Mode*/
-
-  uint32_t QSPI_CSHTime;   /* Specifies the Chip Select High Time
-                              This parameter can be a value of @ref QSPI_ChipSelectHighTime*/   
- 
-  uint32_t QSPI_FSize;     /* Specifies the Flash Size.
-                               QSPI_FSize+1 is effectively the number of address bits required to address the flash memory.
-                               The flash capacity can be up to 4GB (addressed using 32 bits) in indirect mode, but the
-                               addressable space in memory-mapped mode is limited to 512MB
-                               This parameter can be a number between 0x00 and 0x1F */
-  uint32_t QSPI_FSelect;   /* Specifies the Flash which will be used,
-                                 This parameter can be a value of @ref QSPI_Fash_Select*/
-  uint32_t QSPI_DFlash;    /* Specifies the Dual Flash Mode State
-                                 This parameter can be a value of @ref QSPI_Dual_Flash*/
-}QSPI_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup QSPI_Exported_Constants
-  * @{
-  */
-
-/** @defgroup QSPI_Sample_Shift 
-  * @{
-  */
-#define QSPI_SShift_NoShift                        ((uint32_t)0x00000000)
-#define QSPI_SShift_HalfCycleShift                 ((uint32_t)QUADSPI_CR_SSHIFT)
-#define IS_QSPI_SSHIFT(SSHIFT)      (((SSHIFT) == QSPI_SShift_NoShift) ||  ((SSHIFT) == QSPI_SShift_HalfCycleShift))
-/* Legacy Defines */
-#define QUADSPI_CR_SSHIFT_0    QUADSPI_CR_SSHIFT
-/**
-  * @}
-  */
-  
-/** @defgroup QSPI_Prescaler 
-  * @{
-  */
-#define IS_QSPI_PRESCALER(PRESCALER) (((PRESCALER) <= 0xFF))
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_Clock_Mode 
-  * @{
-  */
-#define QSPI_CKMode_Mode0           ((uint32_t)0x00000000)
-#define QSPI_CKMode_Mode3           ((uint32_t)QUADSPI_DCR_CKMODE)
-#define IS_QSPI_CKMODE(CKMode)      (((CKMode) == QSPI_CKMode_Mode0) || ((CKMode) == QSPI_CKMode_Mode3))
-/**
-  * @}
-  */
-  
-/** @defgroup QSPI_ChipSelectHighTime 
-  * @{
-  */
-#define QSPI_CSHTime_1Cycle           ((uint32_t)0x00000000)
-#define QSPI_CSHTime_2Cycle           ((uint32_t)QUADSPI_DCR_CSHT_0)
-#define QSPI_CSHTime_3Cycle           ((uint32_t)QUADSPI_DCR_CSHT_1)
-#define QSPI_CSHTime_4Cycle           ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1)
-#define QSPI_CSHTime_5Cycle           ((uint32_t)QUADSPI_DCR_CSHT_2)
-#define QSPI_CSHTime_6Cycle           ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0)
-#define QSPI_CSHTime_7Cycle           ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1)
-#define QSPI_CSHTime_8Cycle           ((uint32_t)QUADSPI_DCR_CSHT)
-#define IS_QSPI_CSHTIME(CSHTIME)    (((CSHTIME) == QSPI_CSHTime_1Cycle) || \
-                                     ((CSHTIME) == QSPI_CSHTime_2Cycle) || \
-                                     ((CSHTIME) == QSPI_CSHTime_3Cycle) || \
-                                     ((CSHTIME) == QSPI_CSHTime_4Cycle) || \
-                                     ((CSHTIME) == QSPI_CSHTime_5Cycle) || \
-                                     ((CSHTIME) == QSPI_CSHTime_6Cycle) || \
-                                     ((CSHTIME) == QSPI_CSHTime_7Cycle) || \
-                                     ((CSHTIME) == QSPI_CSHTime_8Cycle))
-/**
-  * @}
-  */
-  
-/** @defgroup QSPI_Flash_Size 
-  * @{
-  */
-#define IS_QSPI_FSIZE(FSIZE)         (((FSIZE) <= 0x1F))
-/**
-  * @}
-  */
-	
-/** @defgroup QSPI_Fash_Select 
-  * @{
-  */
-#define QSPI_FSelect_1           ((uint32_t)0x00000000)
-#define QSPI_FSelect_2           ((uint32_t)QUADSPI_CR_FSEL)
-#define IS_QSPI_FSEL(FLA)    (((FLA) == QSPI_FSelect_1) || ((FLA) == QSPI_FSelect_2))
-/**
-  * @}
-  */
-	
-/** @defgroup QSPI_Dual_Flash 
-  * @{
-  */
-#define QSPI_DFlash_Disable           ((uint32_t)0x00000000)
-#define QSPI_DFlash_Enable            ((uint32_t)QUADSPI_CR_DFM)
-#define IS_QSPI_DFM(FLA)    (((FLA) == QSPI_DFlash_Enable) || ((FLA) == QSPI_DFlash_Disable))
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_ComConfig_Functional_Mode 
-  * @{
-  */  
-#define QSPI_ComConfig_FMode_Indirect_Write     ((uint32_t)0x00000000)
-#define QSPI_ComConfig_FMode_Indirect_Read      ((uint32_t)QUADSPI_CCR_FMODE_0)
-#define QSPI_ComConfig_FMode_Auto_Polling       ((uint32_t)QUADSPI_CCR_FMODE_1)
-#define QSPI_ComConfig_FMode_Memory_Mapped      ((uint32_t)QUADSPI_CCR_FMODE)
-#define IS_QSPI_FMODE(FMODE)                  (((FMODE) == QSPI_ComConfig_FMode_Indirect_Write) || \
-                                               ((FMODE) == QSPI_ComConfig_FMode_Indirect_Read) || \
-                                               ((FMODE) == QSPI_ComConfig_FMode_Auto_Polling) || \
-                                               ((FMODE) == QSPI_ComConfig_FMode_Memory_Mapped))
-/**
-  * @}
-  */
-	
-/** @defgroup QSPI_ComConfig_DoubleDataRateMode 
-  * @{
-  */
-#define QSPI_ComConfig_DDRMode_Disable           ((uint32_t)0x00000000)
-#define QSPI_ComConfig_DDRMode_Enable            ((uint32_t)QUADSPI_CCR_DDRM)
-#define IS_QSPI_DDRMODE(DDRMODE)    (((DDRMODE) == QSPI_ComConfig_DDRMode_Disable) || \
-                                     ((DDRMODE) == QSPI_ComConfig_DDRMode_Enable))
-/**
-  * @}
-  */
-	
-/** @defgroup QSPI_ComConfig_DelayHalfHclkCycle 
-  * @{
-  */
-#define QSPI_ComConfig_DHHC_Disable           ((uint32_t)0x00000000)
-#define QSPI_ComConfig_DHHC_Enable            ((uint32_t)QUADSPI_CCR_DHHC)
-#define IS_QSPI_DHHC(DHHC)          (((DHHC) == QSPI_ComConfig_DHHC_Disable) || \
-                                     ((DHHC) == QSPI_ComConfig_DHHC_Enable))
-/**
-  * @}
-  */
-  
-/** @defgroup QSPI_ComConfig_SendInstructionOnlyOnceMode 
-  * @{
-  */
-#define QSPI_ComConfig_SIOOMode_Disable           ((uint32_t)0x00000000)
-#define QSPI_ComConfig_SIOOMode_Enable            ((uint32_t)QUADSPI_CCR_SIOO)
-#define IS_QSPI_SIOOMODE(SIOOMODE)    (((SIOOMODE) == QSPI_ComConfig_SIOOMode_Disable) || \
-                                       ((SIOOMODE) == QSPI_ComConfig_SIOOMode_Enable))
-/**
-  * @}
-  */  
-
-/** @defgroup QSPI_ComConfig_DataMode 
-  * @{
-  */
-#define QSPI_ComConfig_DMode_NoData          ((uint32_t)0x00000000)
-#define QSPI_ComConfig_DMode_1Line           ((uint32_t)QUADSPI_CCR_DMODE_0)
-#define QSPI_ComConfig_DMode_2Line           ((uint32_t)QUADSPI_CCR_DMODE_1)
-#define QSPI_ComConfig_DMode_4Line           ((uint32_t)QUADSPI_CCR_DMODE)
-#define IS_QSPI_DMODE(DMODE)        (((DMODE) == QSPI_ComConfig_DMode_NoData) || \
-                                     ((DMODE) == QSPI_ComConfig_DMode_1Line) || \
-                                     ((DMODE) == QSPI_ComConfig_DMode_2Line) || \
-                                     ((DMODE) == QSPI_ComConfig_DMode_4Line))
-/**
-  * @}
-  */
-  
-/** @defgroup QSPI_ComConfig_AlternateBytesSize 
-  * @{
-  */
-#define QSPI_ComConfig_ABSize_8bit            ((uint32_t)0x00000000)
-#define QSPI_ComConfig_ABSize_16bit           ((uint32_t)QUADSPI_CCR_ABSIZE_0)
-#define QSPI_ComConfig_ABSize_24bit           ((uint32_t)QUADSPI_CCR_ABSIZE_1)
-#define QSPI_ComConfig_ABSize_32bit           ((uint32_t)QUADSPI_CCR_ABSIZE)
-#define IS_QSPI_ABSIZE(ABSIZE)      (((ABSIZE) == QSPI_ComConfig_ABSize_8bit) || \
-                                     ((ABSIZE) == QSPI_ComConfig_ABSize_16bit) || \
-                                     ((ABSIZE) == QSPI_ComConfig_ABSize_24bit) || \
-                                     ((ABSIZE) == QSPI_ComConfig_ABSize_32bit))
-/**
-  * @}
-  */
-  
-/** @defgroup QSPI_ComConfig_AlternateBytesMode 
-  * @{
-  */
-#define QSPI_ComConfig_ABMode_NoAlternateByte          ((uint32_t)0x00000000)
-#define QSPI_ComConfig_ABMode_1Line                    ((uint32_t)QUADSPI_CCR_ABMODE_0)
-#define QSPI_ComConfig_ABMode_2Line                    ((uint32_t)QUADSPI_CCR_ABMODE_1)
-#define QSPI_ComConfig_ABMode_4Line                    ((uint32_t)QUADSPI_CCR_ABMODE)
-#define IS_QSPI_ABMODE(ABMODE)      (((ABMODE) == QSPI_ComConfig_ABMode_NoAlternateByte) || \
-                                     ((ABMODE) == QSPI_ComConfig_ABMode_1Line) || \
-                                     ((ABMODE) == QSPI_ComConfig_ABMode_2Line) || \
-                                     ((ABMODE) == QSPI_ComConfig_ABMode_4Line))
-/**
-  * @}
-  */
-  
-/** @defgroup QSPI_ComConfig_AddressSize 
-  * @{
-  */
-#define QSPI_ComConfig_ADSize_8bit            ((uint32_t)0x00000000)
-#define QSPI_ComConfig_ADSize_16bit           ((uint32_t)QUADSPI_CCR_ADSIZE_0)
-#define QSPI_ComConfig_ADSize_24bit           ((uint32_t)QUADSPI_CCR_ADSIZE_1)
-#define QSPI_ComConfig_ADSize_32bit           ((uint32_t)QUADSPI_CCR_ADSIZE)
-#define IS_QSPI_ADSIZE(ADSIZE)      (((ADSIZE) == QSPI_ComConfig_ADSize_8bit) || \
-                                     ((ADSIZE) == QSPI_ComConfig_ADSize_16bit) || \
-                                     ((ADSIZE) == QSPI_ComConfig_ADSize_24bit) || \
-                                     ((ADSIZE) == QSPI_ComConfig_ADSize_32bit))
-/**
-  * @}
-  */
-  
-/** @defgroup QSPI_ComConfig_AddressMode 
-  * @{
-  */
-#define QSPI_ComConfig_ADMode_NoAddress          ((uint32_t)0x00000000)
-#define QSPI_ComConfig_ADMode_1Line              ((uint32_t)QUADSPI_CCR_ADMODE_0)
-#define QSPI_ComConfig_ADMode_2Line              ((uint32_t)QUADSPI_CCR_ADMODE_1)
-#define QSPI_ComConfig_ADMode_4Line              ((uint32_t)QUADSPI_CCR_ADMODE)
-#define IS_QSPI_ADMODE(ADMODE)        (((ADMODE) == QSPI_ComConfig_ADMode_NoAddress) || \
-                                       ((ADMODE) == QSPI_ComConfig_ADMode_1Line) || \
-                                       ((ADMODE) == QSPI_ComConfig_ADMode_2Line) || \
-                                       ((ADMODE) == QSPI_ComConfig_ADMode_4Line))
-/**
-  * @}
-  */  
-  
-/** @defgroup QSPI_ComConfig_InstructionMode 
-  * @{
-  */
-#define QSPI_ComConfig_IMode_NoInstruction          ((uint32_t)0x00000000)
-#define QSPI_ComConfig_IMode_1Line                  ((uint32_t)QUADSPI_CCR_IMODE_0)
-#define QSPI_ComConfig_IMode_2Line                  ((uint32_t)QUADSPI_CCR_IMODE_1)
-#define QSPI_ComConfig_IMode_4Line                  ((uint32_t)QUADSPI_CCR_IMODE)
-#define IS_QSPI_IMODE(IMODE)        (((IMODE) == QSPI_ComConfig_IMode_NoInstruction) || \
-                                     ((IMODE) == QSPI_ComConfig_IMode_1Line) || \
-                                     ((IMODE) == QSPI_ComConfig_IMode_2Line) || \
-                                     ((IMODE) == QSPI_ComConfig_IMode_4Line))
-/**
-  * @}
-  */
-
-/** @defgroup QSPI_ComConfig_Instruction 
-  * @{
-  */
-#define IS_QSPI_INSTRUCTION(INSTRUCTION)           ((INSTRUCTION) <= 0xFF) 
-/**
-  * @}
-  */ 
-
-/** @defgroup QSPI_InterruptsDefinition 
-  * @{
-  */
-#define QSPI_IT_TO                (uint32_t)(QUADSPI_CR_TOIE | QUADSPI_SR_TOF)
-#define QSPI_IT_SM                (uint32_t)(QUADSPI_CR_SMIE | QUADSPI_SR_SMF)
-#define QSPI_IT_FT                (uint32_t)(QUADSPI_CR_FTIE | QUADSPI_SR_FTF)
-#define QSPI_IT_TC                (uint32_t)(QUADSPI_CR_TCIE | QUADSPI_SR_TCF)
-#define QSPI_IT_TE                (uint32_t)(QUADSPI_CR_TEIE | QUADSPI_SR_TEF)
-#define IS_QSPI_IT(IT)   ((((IT) & 0xFFE0FFE0) == 0) && ((IT) != 0))
-#define IS_QSPI_CLEAR_IT(IT)   ((((IT) & 0xFFE4FFE4) == 0) && ((IT) != 0))  
-/**
-  * @}
-  */
-  
-/** @defgroup QSPI_FlagsDefinition 
-  * @{
-  */
-#define QSPI_FLAG_TO                  QUADSPI_SR_TOF
-#define QSPI_FLAG_SM                  QUADSPI_SR_SMF
-#define QSPI_FLAG_FT                  QUADSPI_SR_FTF
-#define QSPI_FLAG_TC                  QUADSPI_SR_TCF
-#define QSPI_FLAG_TE                  QUADSPI_SR_TEF
-#define QSPI_FLAG_BUSY                QUADSPI_SR_BUSY
-#define IS_QSPI_GET_FLAG(FLAG)   (((FLAG) == QSPI_FLAG_TO) || ((FLAG) == QSPI_FLAG_SM) || \
-                                  ((FLAG) == QSPI_FLAG_FT) || ((FLAG) == QSPI_FLAG_TC) || \
-                                  ((FLAG) == QSPI_FLAG_TE) || ((FLAG) == QSPI_FLAG_BUSY))
-#define IS_QSPI_CLEAR_FLAG(FLAG)  (((FLAG) == QSPI_FLAG_TO) || ((FLAG) == QSPI_FLAG_SM) || \
-                                  ((FLAG) == QSPI_FLAG_TC) ||  ((FLAG) == QSPI_FLAG_TE))
-
-/**
-  * @}
-  */
-  
-/** @defgroup QSPI_Polling_Match_Mode 
-  * @{
-  */
-#define QSPI_PMM_AND                 ((uint32_t)0x00000000)
-#define QSPI_PMM_OR                  ((uint32_t)QUADSPI_CR_PMM)
-#define IS_QSPI_PMM(PMM)      (((PMM) == QSPI_PMM_AND) || ((PMM) == QSPI_PMM_OR)) 
-/**
-  * @}
-  */
-  
-/** @defgroup QSPI_Polling_Interval 
-  * @{
-  */
-#define IS_QSPI_PIR(PIR)                 ((PIR) <= QUADSPI_PIR_INTERVAL) 
-/**
-  * @}
-  */
-  
-/** @defgroup QSPI_Timeout 
-  * @{
-  */
-#define IS_QSPI_TIMEOUT(TIMEOUT)         ((TIMEOUT) <= QUADSPI_LPTR_TIMEOUT) 
-/**
-  * @}
-  */
-  
-/** @defgroup QSPI_DummyCycle 
-  * @{
-  */
-#define IS_QSPI_DCY(DCY)                 ((DCY) <= 0x1F) 
-/**
-  * @}
-  */
-  
-/** @defgroup QSPI_FIFOThreshold 
-  * @{
-  */
-#define IS_QSPI_FIFOTHRESHOLD(FIFOTHRESHOLD)        ((FIFOTHRESHOLD) <= 0x0F) 
-/**
-  * @}
-  */  
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Initialization and Configuration functions *********************************/
-void QSPI_DeInit(void);
-void QSPI_Init(QSPI_InitTypeDef* QSPI_InitStruct);
-void QSPI_StructInit(QSPI_InitTypeDef* QSPI_InitStruct);
-void QSPI_ComConfig_Init(QSPI_ComConfig_InitTypeDef* QSPI_ComConfig_InitStruct);
-void QSPI_ComConfig_StructInit(QSPI_ComConfig_InitTypeDef* QSPI_ComConfig_InitStruct);
-void QSPI_Cmd(FunctionalState NewState);
-void QSPI_AutoPollingMode_Config(uint32_t QSPI_Match, uint32_t QSPI_Mask , uint32_t QSPI_Match_Mode);
-void QSPI_AutoPollingMode_SetInterval(uint32_t QSPI_Interval);
-void QSPI_MemoryMappedMode_SetTimeout(uint32_t QSPI_Timeout);
-void QSPI_SetAddress(uint32_t QSPI_Address);
-void QSPI_SetAlternateByte(uint32_t QSPI_AlternateByte);
-void QSPI_SetFIFOThreshold(uint32_t QSPI_FIFOThreshold);
-void QSPI_SetDataLength(uint32_t QSPI_DataLength);
-void QSPI_TimeoutCounterCmd(FunctionalState NewState);
-void QSPI_AutoPollingModeStopCmd(FunctionalState NewState);
-void QSPI_AbortRequest(void);
-void QSPI_DualFlashMode_Cmd(FunctionalState NewState);
-
-/* Data transfers functions ***************************************************/
-void     QSPI_SendData8(uint8_t Data);
-void     QSPI_SendData16(uint16_t Data);
-void     QSPI_SendData32(uint32_t Data);
-uint8_t  QSPI_ReceiveData8(void);
-uint16_t QSPI_ReceiveData16(void);
-uint32_t QSPI_ReceiveData32(void);
-
-/* DMA transfers management functions *****************************************/
-void QSPI_DMACmd(FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void       QSPI_ITConfig(uint32_t QSPI_IT, FunctionalState NewState);
-uint32_t   QSPI_GetFIFOLevel(void);
-FlagStatus QSPI_GetFlagStatus(uint32_t QSPI_FLAG);
-void       QSPI_ClearFlag(uint32_t QSPI_FLAG);
-ITStatus   QSPI_GetITStatus(uint32_t QSPI_IT);
-void       QSPI_ClearITPendingBit(uint32_t QSPI_IT);
-uint32_t   QSPI_GetFMode(void);
-
-#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4XX_QUADSPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h

@@ -1,121 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_rng.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the Random 
-  *          Number Generator(RNG) firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_RNG_H
-#define __STM32F4xx_RNG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup RNG
-  * @{
-  */ 
-#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/ 
-
-/** @defgroup RNG_Exported_Constants
-  * @{
-  */
-  
-/** @defgroup RNG_flags_definition  
-  * @{
-  */ 
-#define RNG_FLAG_DRDY               ((uint8_t)0x0001) /*!< Data ready */
-#define RNG_FLAG_CECS               ((uint8_t)0x0002) /*!< Clock error current status */
-#define RNG_FLAG_SECS               ((uint8_t)0x0004) /*!< Seed error current status */
-
-#define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \
-                                   ((RNG_FLAG) == RNG_FLAG_CECS) || \
-                                   ((RNG_FLAG) == RNG_FLAG_SECS))
-#define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \
-                                    ((RNG_FLAG) == RNG_FLAG_SECS))
-/**
-  * @}
-  */ 
-
-/** @defgroup RNG_interrupts_definition   
-  * @{
-  */  
-#define RNG_IT_CEI                  ((uint8_t)0x20) /*!< Clock error interrupt */
-#define RNG_IT_SEI                  ((uint8_t)0x40) /*!< Seed error interrupt */
-
-#define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00))
-#define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI))
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/ 
-
-/*  Function used to set the RNG configuration to the default reset state *****/ 
-void RNG_DeInit(void);
-
-/* Configuration function *****************************************************/
-void RNG_Cmd(FunctionalState NewState);
-
-/* Get 32 bit Random number function ******************************************/
-uint32_t RNG_GetRandomNumber(void);
-
-/* Interrupts and flags management functions **********************************/
-void RNG_ITConfig(FunctionalState NewState);
-FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG);
-void RNG_ClearFlag(uint8_t RNG_FLAG);
-ITStatus RNG_GetITStatus(uint8_t RNG_IT);
-void RNG_ClearITPendingBit(uint8_t RNG_IT);
-#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F429_439xx || STM32F469_479xx */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_RNG_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

targets/cortex-m4_stm32f429ig_fire-challenger_iar/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h

@@ -1,888 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_rtc.h
-  * @author  MCD Application Team
-  * @version V1.8.0
-  * @date    04-November-2016
-  * @brief   This file contains all the functions prototypes for the RTC firmware
-  *          library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
-  *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-  * You may not use this file except in compliance with the License.
-  * You may obtain a copy of the License at:
-  *
-  *        http://www.st.com/software_license_agreement_liberty_v2
-  *
-  * Unless required by applicable law or agreed to in writing, software 
-  * distributed under the License is distributed on an "AS IS" BASIS, 
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-  * See the License for the specific language governing permissions and
-  * limitations under the License.
-  *
-  ****************************************************************************** 
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_RTC_H
-#define __STM32F4xx_RTC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
-  * @{
-  */
-
-/** @addtogroup RTC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  RTC Init structures definition  
-  */ 
-typedef struct
-{
-  uint32_t RTC_HourFormat;   /*!< Specifies the RTC Hour Format.
-                             This parameter can be a value of @ref RTC_Hour_Formats */
-  
-  uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
-                             This parameter must be set to a value lower than 0x7F */
-  
-  uint32_t RTC_SynchPrediv;  /*!< Specifies the RTC Synchronous Predivider value.
-                             This parameter must be set to a value lower than 0x7FFF */
-}RTC_InitTypeDef;
-
-/** 
-  * @brief  RTC Time structure definition  
-  */
-typedef struct
-{
-  uint8_t RTC_Hours;    /*!< Specifies the RTC Time Hour.
-                        This parameter must be set to a value in the 0-12 range
-                        if the RTC_HourFormat_12 is selected or 0-23 range if
-                        the RTC_HourFormat_24 is selected. */
-
-  uint8_t RTC_Minutes;  /*!< Specifies the RTC Time Minutes.
-                        This parameter must be set to a value in the 0-59 range. */
-  
-  uint8_t RTC_Seconds;  /*!< Specifies the RTC Time Seconds.
-                        This parameter must be set to a value in the 0-59 range. */
-
-  uint8_t RTC_H12;      /*!< Specifies the RTC AM/PM Time.
-                        This parameter can be a value of @ref RTC_AM_PM_Definitions */
-}RTC_TimeTypeDef; 
-
-/** 
-  * @brief  RTC Date structure definition  
-  */
-typedef struct
-{
-  uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
-                        This parameter can be a value of @ref RTC_WeekDay_Definitions */
-  
-  uint8_t RTC_Month;   /*!< Specifies the RTC Date Month (in BCD format).
-                        This parameter can be a value of @ref RTC_Month_Date_Definitions */
-
-  uint8_t RTC_Date;     /*!< Specifies the RTC Date.
-                        This parameter must be set to a value in the 1-31 range. */
-  
-  uint8_t RTC_Year;     /*!< Specifies the RTC Date Year.
-                        This parameter must be set to a value in the 0-99 range. */
-}RTC_DateTypeDef;
-
-/** 
-  * @brief  RTC Alarm structure definition  
-  */
-typedef struct
-{
-  RTC_TimeTypeDef RTC_AlarmTime;     /*!< Specifies the RTC Alarm Time members. */
-
-  uint32_t RTC_AlarmMask;            /*!< Specifies the RTC Alarm Masks.
-                                     This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-
-  uint32_t RTC_AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
-                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-  
-  uint8_t RTC_AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
-                                     If the Alarm Date is selected, this parameter
-                                     must be set to a value in the 1-31 range.
-                                     If the Alarm WeekDay is selected, this 
-                                     parameter can be a value of @ref RTC_WeekDay_Definitions */
-}RTC_AlarmTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RTC_Exported_Constants
-  * @{
-  */ 
-
-
-/** @defgroup RTC_Hour_Formats 
-  * @{
-  */ 
-#define RTC_HourFormat_24              ((uint32_t)0x00000000)
-#define RTC_HourFormat_12              ((uint32_t)0x00000040)
-#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HourFormat_12) || \
-                                        ((FORMAT) == RTC_HourFormat_24))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Asynchronous_Predivider 
-  * @{
-  */ 
-#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7F)
- 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup RTC_Synchronous_Predivider 
-  * @{
-  */ 
-#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= 0x7FFF)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Time_Definitions 
-  * @{
-  */ 
-#define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0) && ((HOUR) <= 12))
-#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23)
-#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59)
-#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_AM_PM_Definitions 
-  * @{
-  */ 
-#define RTC_H12_AM                     ((uint8_t)0x00)
-#define RTC_H12_PM                     ((uint8_t)0x40)
-#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Year_Date_Definitions 
-  * @{
-  */ 
-#define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Month_Date_Definitions 
-  * @{
-  */ 
-
-/* Coded in BCD format */
-#define RTC_Month_January              ((uint8_t)0x01)
-#define RTC_Month_February             ((uint8_t)0x02)
-#define RTC_Month_March                ((uint8_t)0x03)
-#define RTC_Month_April                ((uint8_t)0x04)
-#define RTC_Month_May                  ((uint8_t)0x05)
-#define RTC_Month_June                 ((uint8_t)0x06)
-#define RTC_Month_July                 ((uint8_t)0x07)
-#define RTC_Month_August               ((uint8_t)0x08)
-#define RTC_Month_September            ((uint8_t)0x09)
-#define RTC_Month_October              ((uint8_t)0x10)
-#define RTC_Month_November             ((uint8_t)0x11)
-#define RTC_Month_December             ((uint8_t)0x12)
-#define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1) && ((MONTH) <= 12))
-#define IS_RTC_DATE(DATE)              (((DATE) >= 1) && ((DATE) <= 31))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_WeekDay_Definitions 
-  * @{
-  */ 
-  
-#define RTC_Weekday_Monday             ((uint8_t)0x01)
-#define RTC_Weekday_Tuesday            ((uint8_t)0x02)
-#define RTC_Weekday_Wednesday          ((uint8_t)0x03)
-#define RTC_Weekday_Thursday           ((uint8_t)0x04)
-#define RTC_Weekday_Friday             ((uint8_t)0x05)
-#define RTC_Weekday_Saturday           ((uint8_t)0x06)
-#define RTC_Weekday_Sunday             ((uint8_t)0x07)
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
-                                 ((WEEKDAY) == RTC_Weekday_Tuesday) || \
-                                 ((WEEKDAY) == RTC_Weekday_Wednesday) || \
-                                 ((WEEKDAY) == RTC_Weekday_Thursday) || \
-                                 ((WEEKDAY) == RTC_Weekday_Friday) || \
-                                 ((WEEKDAY) == RTC_Weekday_Saturday) || \
-                                 ((WEEKDAY) == RTC_Weekday_Sunday))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup RTC_Alarm_Definitions
-  * @{
-  */ 
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
-                                                    ((WEEKDAY) == RTC_Weekday_Tuesday) || \
-                                                    ((WEEKDAY) == RTC_Weekday_Wednesday) || \
-                                                    ((WEEKDAY) == RTC_Weekday_Thursday) || \
-                                                    ((WEEKDAY) == RTC_Weekday_Friday) || \
-                                                    ((WEEKDAY) == RTC_Weekday_Saturday) || \
-                                                    ((WEEKDAY) == RTC_Weekday_Sunday))
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions 
-  * @{
-  */ 
-#define RTC_AlarmDateWeekDaySel_Date      ((uint32_t)0x00000000)
-#define RTC_AlarmDateWeekDaySel_WeekDay   ((uint32_t)0x40000000)
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
-                                            ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
-
-/**
-  * @}
-  */ 
-
-
-/** @defgroup RTC_AlarmMask_Definitions 
-  * @{
-  */ 
-#define RTC_AlarmMask_None                ((uint32_t)0x00000000)
-#define RTC_AlarmMask_DateWeekDay         ((uint32_t)0x80000000)
-#define RTC_AlarmMask_Hours               ((uint32_t)0x00800000)
-#define RTC_AlarmMask_Minutes             ((uint32_t)0x00008000)
-#define RTC_AlarmMask_Seconds             ((uint32_t)0x00000080)
-#define RTC_AlarmMask_All                 ((uint32_t)0x80808080)
-#define IS_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Alarms_Definitions 
-  * @{
-  */ 
-#define RTC_Alarm_A                       ((uint32_t)0x00000100)
-#define RTC_Alarm_B                       ((uint32_t)0x00000200)
-#define IS_RTC_ALARM(ALARM)     (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
-#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
-
-/**
-  * @}
-  */ 
-
-  /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
-  * @{
-  */ 
-#define RTC_AlarmSubSecondMask_All         ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. 
-                                                                       There is no comparison on sub seconds 
-                                                                       for Alarm */
-#define RTC_AlarmSubSecondMask_SS14_1      ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm 
-                                                                       comparison. Only SS[0] is compared. */
-#define RTC_AlarmSubSecondMask_SS14_2      ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm 
-                                                                       comparison. Only SS[1:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_3      ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm 
-                                                                       comparison. Only SS[2:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_4      ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm 
-                                                                       comparison. Only SS[3:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_5      ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm 
-                                                                       comparison. Only SS[4:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_6      ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm 
-                                                                       comparison. Only SS[5:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_7      ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm 
-                                                                       comparison. Only SS[6:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_8      ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm 
-                                                                       comparison. Only SS[7:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_9      ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm 
-                                                                       comparison. Only SS[8:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_10     ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm 
-                                                                       comparison. Only SS[9:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_11     ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm 
-                                                                       comparison. Only SS[10:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_12     ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm 
-                                                                       comparison.Only SS[11:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_13     ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm 
-                                                                       comparison. Only SS[12:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14        ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm 
-                                                                       comparison.Only SS[13:0] are compared */
-#define RTC_AlarmSubSecondMask_None        ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match 
-                                                                       to activate alarm. */
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_AlarmSubSecondMask_All) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
-                                              ((MASK) == RTC_AlarmSubSecondMask_None))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Alarm_Sub_Seconds_Value
-  * @{
-  */ 
-
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Wakeup_Timer_Definitions 
-  * @{
-  */ 
-#define RTC_WakeUpClock_RTCCLK_Div16        ((uint32_t)0x00000000)
-#define RTC_WakeUpClock_RTCCLK_Div8         ((uint32_t)0x00000001)
-#define RTC_WakeUpClock_RTCCLK_Div4         ((uint32_t)0x00000002)
-#define RTC_WakeUpClock_RTCCLK_Div2         ((uint32_t)0x00000003)
-#define RTC_WakeUpClock_CK_SPRE_16bits      ((uint32_t)0x00000004)
-#define RTC_WakeUpClock_CK_SPRE_17bits      ((uint32_t)0x00000006)
-#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
-                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
-                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
-                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
-                                    ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
-                                    ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
-#define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFF)
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Time_Stamp_Edges_definitions 
-  * @{
-  */ 
-#define RTC_TimeStampEdge_Rising          ((uint32_t)0x00000000)
-#define RTC_TimeStampEdge_Falling         ((uint32_t)0x00000008)
-#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
-                                     ((EDGE) == RTC_TimeStampEdge_Falling))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Output_selection_Definitions 
-  * @{
-  */ 
-#define RTC_Output_Disable             ((uint32_t)0x00000000)
-#define RTC_Output_AlarmA              ((uint32_t)0x00200000)
-#define RTC_Output_AlarmB              ((uint32_t)0x00400000)
-#define RTC_Output_WakeUp              ((uint32_t)0x00600000)
- 
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
-                               ((OUTPUT) == RTC_Output_AlarmA) || \
-                               ((OUTPUT) == RTC_Output_AlarmB) || \
-                               ((OUTPUT) == RTC_Output_WakeUp))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Output_Polarity_Definitions 
-  * @{
-  */ 
-#define RTC_OutputPolarity_High           ((uint32_t)0x00000000)
-#define RTC_OutputPolarity_Low            ((uint32_t)0x00100000)
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
-                                ((POL) == RTC_OutputPolarity_Low))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup RTC_Digital_Calibration_Definitions 
-  * @{
-  */ 
-#define RTC_CalibSign_Positive            ((uint32_t)0x00000000) 
-#define RTC_CalibSign_Negative            ((uint32_t)0x00000080)
-#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
-                                 ((SIGN) == RTC_CalibSign_Negative))
-#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
-
-/**
-  * @}
-  */ 
-
- /** @defgroup RTC_Calib_Output_selection_Definitions 
-  * @{
-  */ 
-#define RTC_CalibOutput_512Hz            ((uint32_t)0x00000000) 
-#define RTC_CalibOutput_1Hz              ((uint32_t)0x00080000)
-#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CalibOutput_512Hz) || \
-                                      ((OUTPUT) == RTC_CalibOutput_1Hz))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Smooth_calib_period_Definitions 
-  * @{
-  */ 
-#define RTC_SmoothCalibPeriod_32sec   ((uint32_t)0x00000000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation
-                                                             period is 32s,  else 2exp20 RTCCLK seconds */
-#define RTC_SmoothCalibPeriod_16sec   ((uint32_t)0x00002000) /*!<  if RTCCLK = 32768 Hz, Smooth calibration 
-                                                             period is 16s, else 2exp19 RTCCLK seconds */
-#define RTC_SmoothCalibPeriod_8sec    ((uint32_t)0x00004000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation 
-                                                             period is 8s, else 2exp18 RTCCLK seconds */
-#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
-                                             ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
-                                             ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
-                                          
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions 
-  * @{
-  */ 
-#define RTC_SmoothCalibPlusPulses_Set    ((uint32_t)0x00008000) /*!<  The number of RTCCLK pulses added  
-                                                                during a X -second window = Y - CALM[8:0]. 
-                                                                 with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SmoothCalibPlusPulses_Reset  ((uint32_t)0x00000000) /*!<  The number of RTCCLK pulses subbstited
-                                                                 during a 32-second window =   CALM[8:0]. */
-#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
-                                         ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions 
-  * @{
-  */ 
-#define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_DayLightSaving_Definitions 
-  * @{
-  */ 
-#define RTC_DayLightSaving_SUB1H   ((uint32_t)0x00020000)
-#define RTC_DayLightSaving_ADD1H   ((uint32_t)0x00010000)
-#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
-                                      ((SAVE) == RTC_DayLightSaving_ADD1H))
-
-#define RTC_StoreOperation_Reset        ((uint32_t)0x00000000)
-#define RTC_StoreOperation_Set          ((uint32_t)0x00040000)
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
-                                           ((OPERATION) == RTC_StoreOperation_Set))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Tamper_Trigger_Definitions 
-  * @{
-  */ 
-#define RTC_TamperTrigger_RisingEdge            ((uint32_t)0x00000000)
-#define RTC_TamperTrigger_FallingEdge           ((uint32_t)0x00000001)
-#define RTC_TamperTrigger_LowLevel              ((uint32_t)0x00000000)
-#define RTC_TamperTrigger_HighLevel             ((uint32_t)0x00000001)
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
-                                        ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
-                                        ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
-                                        ((TRIGGER) == RTC_TamperTrigger_HighLevel)) 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Tamper_Filter_Definitions 
-  * @{
-  */ 
-#define RTC_TamperFilter_Disable   ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
-
-#define RTC_TamperFilter_2Sample   ((uint32_t)0x00000800) /*!< Tamper is activated after 2 
-                                                          consecutive samples at the active level */
-#define RTC_TamperFilter_4Sample   ((uint32_t)0x00001000) /*!< Tamper is activated after 4 
-                                                          consecutive samples at the active level */
-#define RTC_TamperFilter_8Sample   ((uint32_t)0x00001800) /*!< Tamper is activated after 8 
-                                                          consecutive samples at the active level. */
-#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
-                                      ((FILTER) == RTC_TamperFilter_2Sample) || \
-                                      ((FILTER) == RTC_TamperFilter_4Sample) || \
-                                      ((FILTER) == RTC_TamperFilter_8Sample))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions 
-  * @{
-  */ 
-#define RTC_TamperSamplingFreq_RTCCLK_Div32768  ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
-                                                                           with a frequency =  RTCCLK / 32768 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div16384  ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
-                                                                            with a frequency =  RTCCLK / 16384 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div8192   ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
-                                                                           with a frequency =  RTCCLK / 8192  */
-#define RTC_TamperSamplingFreq_RTCCLK_Div4096   ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
-                                                                           with a frequency =  RTCCLK / 4096  */
-#define RTC_TamperSamplingFreq_RTCCLK_Div2048   ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
-                                                                           with a frequency =  RTCCLK / 2048  */
-#define RTC_TamperSamplingFreq_RTCCLK_Div1024   ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
-                                                                           with a frequency =  RTCCLK / 1024  */
-#define RTC_TamperSamplingFreq_RTCCLK_Div512    ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
-                                                                           with a frequency =  RTCCLK / 512   */
-#define RTC_TamperSamplingFreq_RTCCLK_Div256    ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
-                                                                           with a frequency =  RTCCLK / 256   */
-#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
-                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
-                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
-                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
-                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
-                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
-                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
-                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
-
-/**
-  * @}
-  */
-
-  /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions 
-  * @{
-  */ 
-#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before 
-                                                                         sampling during 1 RTCCLK cycle */
-#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before 
-                                                                         sampling during 2 RTCCLK cycles */
-#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before 
-                                                                         sampling during 4 RTCCLK cycles */
-#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before 
-                                                                         sampling during 8 RTCCLK cycles */
-
-#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
-                                                    ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
-                                                    ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
-                                                    ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Tamper_Pins_Definitions 
-  * @{
-  */ 
-#define RTC_Tamper_1 RTC_TAFCR_TAMP1E
-#define RTC_Tamper_2 RTC_TAFCR_TAMP2E
-#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1) || ((TAMPER) == RTC_Tamper_2))
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Tamper_Pin_Selection 
-  * @{
-  */ 
-#define RTC_TamperPin_Default       ((uint32_t)0x00000000)
-#define RTC_TamperPin_Pos1          ((uint32_t)0x00010000)
-#define IS_RTC_TAMPER_PIN(PIN)      (((PIN) == RTC_TamperPin_Default) || \
-                                    ((PIN) == RTC_TamperPin_Pos1))
-/* Legacy Defines */
-#define RTC_TamperPin_PC13           RTC_TamperPin_Default
-#define RTC_TamperPin_PI8            RTC_TamperPin_Pos1
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_TimeStamp_Pin_Selection 
-  * @{
-  */ 
-#define RTC_TimeStampPin_PC13              ((uint32_t)0x00000000)
-#define RTC_TimeStampPin_PI8               ((uint32_t)0x00020000)
-#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \
-                                   ((PIN) == RTC_TimeStampPin_PI8))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Output_Type_ALARM_OUT 
-  * @{
-  */ 
-#define RTC_OutputType_OpenDrain           ((uint32_t)0x00000000)
-#define RTC_OutputType_PushPull            ((uint32_t)0x00040000)
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
-                                  ((TYPE) == RTC_OutputType_PushPull))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Add_1_Second_Parameter_Definitions
-  * @{
-  */ 
-#define RTC_ShiftAdd1S_Reset      ((uint32_t)0x00000000)
-#define RTC_ShiftAdd1S_Set        ((uint32_t)0x80000000)
-#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
-                                 ((SEL) == RTC_ShiftAdd1S_Set))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Substract_Fraction_Of_Second_Value
-  * @{
-  */ 
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Backup_Registers_Definitions 
-  * @{
-  */
-
-#define RTC_BKP_DR0                       ((uint32_t)0x00000000)
-#define RTC_BKP_DR1                       ((uint32_t)0x00000001)
-#define RTC_BKP_DR2                       ((uint32_t)0x00000002)
-#define RTC_BKP_DR3                       ((uint32_t)0x00000003)
-#define RTC_BKP_DR4                       ((uint32_t)0x00000004)
-#define RTC_BKP_DR5                       ((uint32_t)0x00000005)
-#define RTC_BKP_DR6                       ((uint32_t)0x00000006)
-#define RTC_BKP_DR7                       ((uint32_t)0x00000007)
-#define RTC_BKP_DR8                       ((uint32_t)0x00000008)
-#define RTC_BKP_DR9                       ((uint32_t)0x00000009)
-#define RTC_BKP_DR10                      ((uint32_t)0x0000000A)
-#define RTC_BKP_DR11                      ((uint32_t)0x0000000B)
-#define RTC_BKP_DR12                      ((uint32_t)0x0000000C)
-#define RTC_BKP_DR13                      ((uint32_t)0x0000000D)
-#define RTC_BKP_DR14                      ((uint32_t)0x0000000E)
-#define RTC_BKP_DR15                      ((uint32_t)0x0000000F)
-#define RTC_BKP_DR16                      ((uint32_t)0x00000010)
-#define RTC_BKP_DR17                      ((uint32_t)0x00000011)
-#define RTC_BKP_DR18                      ((uint32_t)0x00000012)
-#define RTC_BKP_DR19                      ((uint32_t)0x00000013)
-#define IS_RTC_BKP(BKP)                   (((BKP) == RTC_BKP_DR0) || \
-                                           ((BKP) == RTC_BKP_DR1) || \
-                                           ((BKP) == RTC_BKP_DR2) || \
-                                           ((BKP) == RTC_BKP_DR3) || \
-                                           ((BKP) == RTC_BKP_DR4) || \
-                                           ((BKP) == RTC_BKP_DR5) || \
-                                           ((BKP) == RTC_BKP_DR6) || \
-                                           ((BKP) == RTC_BKP_DR7) || \
-                                           ((BKP) == RTC_BKP_DR8) || \
-                                           ((BKP) == RTC_BKP_DR9) || \
-                                           ((BKP) == RTC_BKP_DR10) || \
-                                           ((BKP) == RTC_BKP_DR11) || \
-                                           ((BKP) == RTC_BKP_DR12) || \
-                                           ((BKP) == RTC_BKP_DR13) || \
-                                           ((BKP) == RTC_BKP_DR14) || \
-                                           ((BKP) == RTC_BKP_DR15) || \
-                                           ((BKP) == RTC_BKP_DR16) || \
-                                           ((BKP) == RTC_BKP_DR17) || \
-                                           ((BKP) == RTC_BKP_DR18) || \
-                                           ((BKP) == RTC_BKP_DR19))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Input_parameter_format_definitions 
-  * @{
-  */ 
-#define RTC_Format_BIN                    ((uint32_t)0x000000000)
-#define RTC_Format_BCD                    ((uint32_t)0x000000001)
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Flags_Definitions 
-  * @{
-  */ 
-#define RTC_FLAG_RECALPF                  ((uint32_t)0x00010000)
-#define RTC_FLAG_TAMP1F                   ((uint32_t)0x00002000)
-#define RTC_FLAG_TAMP2F                   ((uint32_t)0x00004000) 
-#define RTC_FLAG_TSOVF                    ((uint32_t)0x00001000)
-#define RTC_FLAG_TSF                      ((uint32_t)0x00000800)
-#define RTC_FLAG_WUTF                     ((uint32_t)0x00000400)
-#define RTC_FLAG_ALRBF                    ((uint32_t)0x00000200)
-#define RTC_FLAG_ALRAF                    ((uint32_t)0x00000100)
-#define RTC_FLAG_INITF                    ((uint32_t)0x00000040)
-#define RTC_FLAG_RSF                      ((uint32_t)0x00000020)
-#define RTC_FLAG_INITS                    ((uint32_t)0x00000010)
-#define RTC_FLAG_SHPF                     ((uint32_t)0x00000008)
-#define RTC_FLAG_WUTWF                    ((uint32_t)0x00000004)
-#define RTC_FLAG_ALRBWF                   ((uint32_t)0x00000002)
-#define RTC_FLAG_ALRAWF                   ((uint32_t)0x00000001)
-#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
-                               ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
-                               ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
-                               ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
-                               ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
-                               ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \
-                                ((FLAG) == RTC_FLAG_TAMP2F) ||((FLAG) == RTC_FLAG_SHPF))
-#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Interrupts_Definitions 
-  * @{
-  */ 
-#define RTC_IT_TS                         ((uint32_t)0x00008000)
-#define RTC_IT_WUT                        ((uint32_t)0x00004000)
-#define RTC_IT_ALRB                       ((uint32_t)0x00002000)
-#define RTC_IT_ALRA                       ((uint32_t)0x00001000)
-#define RTC_IT_TAMP                       ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
-#define RTC_IT_TAMP1                      ((uint32_t)0x00020000)
-#define RTC_IT_TAMP2                      ((uint32_t)0x00040000)
-
-#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
-#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \
-                           ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \
-                           ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2))
-#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF90FFF) == (uint32_t)RESET))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Legacy 
-  * @{
-  */ 
-#define RTC_DigitalCalibConfig  RTC_CoarseCalibConfig
-#define RTC_DigitalCalibCmd     RTC_CoarseCalibCmd
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/ 
-
-/*  Function used to set the RTC configuration to the default reset state *****/
-ErrorStatus RTC_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
-void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
-void RTC_WriteProtectionCmd(FunctionalState NewState);
-ErrorStatus RTC_EnterInitMode(void);
-void RTC_ExitInitMode(void);
-ErrorStatus RTC_WaitForSynchro(void);
-ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
-void RTC_BypassShadowCmd(FunctionalState NewState);
-
-/* Time and Date configuration functions **************************************/
-ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
-void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
-void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
-uint32_t RTC_GetSubSecond(void);
-ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
-void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
-void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
-
-/* Alarms (Alarm A and Alarm B) configuration functions  **********************/
-void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
-void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
-void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
-ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
-void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
-uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
-
-/* WakeUp Timer configuration functions ***************************************/
-void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);
-void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
-uint32_t RTC_GetWakeUpCounter(void);
-ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
-
-/* Daylight Saving configuration functions ************************************/
-void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
-uint32_t RTC_GetStoreOperation(void);
-
-/* Output pin Configuration function ******************************************/
-void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
-
-/* Digital Calibration configuration functions *********************************/
-ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value);
-ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState);
-void RTC_CalibOutputCmd(FunctionalState NewState);
-void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
-ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, 
-                                  uint32_t RTC_SmoothCalibPlusPulses,
-                                  uint32_t RTC_SmouthCalibMinusPulsesValue);
-
-/* TimeStamp configuration functions ******************************************/
-void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
-void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
-                                      RTC_DateTypeDef* RTC_StampDateStruct);
-uint32_t RTC_GetTimeStampSubSecond(void);
-
-/* Tampers configuration functions ********************************************/
-void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
-void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
-void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
-void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
-void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
-void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
-void RTC_TamperPullUpCmd(FunctionalState NewState);
-
-/* Backup Data Registers configuration functions ******************************/
-void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
-uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
-
-/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
-   functions ******************************************************************/
-void RTC_TamperPinSelection(uint32_t RTC_TamperPin);
-void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin);
-void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
-
-/* RTC_Shift_control_synchonisation_functions *********************************/
-ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
-
-/* Interrupts and flags management functions **********************************/
-void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
-FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
-void RTC_ClearFlag(uint32_t RTC_FLAG);
-ITStatus RTC_GetITStatus(uint32_t RTC_IT);
-void RTC_ClearITPendingBit(uint32_t RTC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_RTC_H */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/