commit
d5b90399b7
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@ -39,7 +39,8 @@ module_group("arch") {
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"$board_cpu" == "cortex-m4" || "$board_cpu" == "cortex-m7" ||
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"$board_cpu" == "cortex-m33" || "$board_cpu" == "cortex-m55") {
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modules += [ "arm" ]
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} else if ("$board_cpu" == "ck802" || "$board_cpu" == "e802") {
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} else if ("$board_cpu" == "ck802" || "$board_cpu" == "e802" ||
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"$board_cpu" == "ck804ef") {
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modules += [ "csky" ]
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} else if ("$board_cpu" == "") {
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if ("$board_arch" == "rv32imac" || "$board_arch" == "rv32imafdc") {
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@ -59,13 +59,33 @@ typedef struct TagTskContext {
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UINT32 R12;
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UINT32 R13;
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UINT32 R15;
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#ifdef CPU_CK804
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UINT32 R16;
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UINT32 R17;
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UINT32 R18;
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UINT32 R19;
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UINT32 R20;
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UINT32 R21;
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UINT32 R22;
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UINT32 R23;
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UINT32 R24;
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UINT32 R25;
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UINT32 R26;
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UINT32 R27;
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UINT32 R28;
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UINT32 R29;
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UINT32 R30;
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UINT32 R31;
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#endif
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UINT32 EPSR;
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UINT32 EPC;
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} TaskContext;
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VOID HalStartToRun(VOID);
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VOID HalTaskContextSwitch(VOID);
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#ifndef CPU_CK804
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VOID HalIrqEndCheckNeedSched(VOID);
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#endif
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#ifdef __cplusplus
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#if __cplusplus
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@ -82,7 +82,7 @@ typedef VOID (**HWI_VECTOR_FUNC)(VOID);
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* @ingroup los_arch_interrupt
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* Count of interrupts.
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*/
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extern UINT32 g_intCount;
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extern volatile UINT32 g_intCount;
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/* *
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* @ingroup los_arch_interrupt
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@ -38,7 +38,9 @@
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#include "los_interrupt.h"
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#include "los_debug.h"
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#ifndef CPU_CK804
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STATIC UINT32 g_sysNeedSched = FALSE;
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#endif
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/* ****************************************************************************
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Function : ArchInit
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@ -93,8 +95,29 @@ LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VO
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context->R11 = 0x11111111L;
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context->R12 = 0x12121212L;
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context->R13 = 0x13131313L;
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#ifdef CPU_CK804
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context->R15 = (UINT32)ArchSysExit;
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context->R16 = 0x16161616L;
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context->R17 = 0x17171717L;
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context->R18 = 0x18181818L;
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context->R19 = 0x19191919L;
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context->R20 = 0x20202020L;
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context->R21 = 0x21212121L;
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context->R22 = 0x22222222L;
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context->R23 = 0x23232323L;
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context->R24 = 0x24242424L;
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context->R25 = 0x25252525L;
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context->R26 = 0x26262626L;
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context->R27 = 0x27272727L;
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context->R28 = 0x28282828L;
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context->R29 = 0x29292929L;
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context->R30 = 0x30303030L;
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context->R31 = 0x31313131L;
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context->EPSR = 0x80000340L;
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#else
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context->R15 = (UINT32)ArchSysExit;
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context->EPSR = 0xe0000144L;
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#endif
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context->EPC = (UINT32)OsTaskEntry;
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return (VOID *)context;
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}
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@ -107,6 +130,7 @@ LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
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return LOS_OK; /* never return */
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}
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#ifndef CPU_CK804
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VOID HalIrqEndCheckNeedSched(VOID)
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{
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if (g_sysNeedSched && g_taskScheduled && LOS_CHECK_SCHEDULE) {
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@ -132,3 +156,10 @@ VOID ArchTaskSchedule(VOID)
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LOS_IntRestore(intSave);
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return;
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}
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#else
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VOID ArchTaskSchedule(VOID)
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{
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HalTaskContextSwitch();
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}
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#endif
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@ -32,6 +32,89 @@
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#define OS_TASK_STATUS_RUNNING 0x0010
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#define VIC_TSPDR 0XE000EC08
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#ifdef CPU_CK804
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.section .text
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.align 2
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.type HalStartToRun, %function
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.global HalStartToRun
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HalStartToRun:
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lrw r1, g_losTask
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lrw r2, g_losTask + 4
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ldw r0, (r2)
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st.w r0, (r1)
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st.w r0, (r2)
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ldw sp, (r0)
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ldw r0, (sp, 128)
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mtcr r0, epc
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ldw r0, (sp, 124)
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mtcr r0, epsr
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ldw r15, (sp, 56)
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ldm r0-r13, (sp)
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addi sp, 60
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ldm r16-r31, (sp)
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addi sp, 72
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rte
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.align 2
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.type HalTaskContextSwitch, %function
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.global HalTaskContextSwitch
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HalTaskContextSwitch:
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lrw r0, VIC_TSPDR
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bgeni r1, 0
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stw r1, (r0)
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nop
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nop
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nop
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rts
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.align 2
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.type tspend_handler, %function
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.global tspend_handler
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tspend_handler:
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subi sp, 132
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stm r0-r13, (sp)
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stw r15, (sp, 56)
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addi r0, sp, 60
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stm r16-r31, (r0)
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mfcr r1, epsr
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stw r1, (sp, 124)
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mfcr r1, epc
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stw r1, (sp, 128)
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jbsr OsSchedTaskSwitch
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bez r0, ret_con
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lrw r2, g_losTask
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ldw r0, (r2)
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stw sp, (r0)
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lrw r3, g_losTask + 4
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ldw r0, (r3)
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stw r0, (r2)
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ldw sp, (r0)
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ret_con:
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ldw r0, (sp, 128)
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mtcr r0, epc
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ldw r0, (sp, 124)
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mtcr r0, epsr
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ldw r15, (sp, 56)
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ldm r0-r13, (sp)
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addi sp, 60
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ldm r16-r31, (sp)
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addi sp, 72
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rte
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#else
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.section .text
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.align 2
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.type HalStartToRun, %function
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@ -87,3 +170,4 @@ HalTaskContextSwitch:
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rte
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#endif
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@ -32,6 +32,57 @@
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.import HalExcHandleEntry
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.extern g_trapStackBase
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#ifdef CPU_CK804
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.section .text
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.align 2
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.global HandleEntry
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HandleEntry:
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mov r10, sp
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lrw r14, g_trapStackBase
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stm r0-r15, (sp)
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stw r10, (sp, 56)
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addi r0, sp, 64
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stm r16-r31, (r0)
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mfcr r0, epsr
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stw r0, (sp, 128)
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mfcr r0, epc
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stw r0, (sp, 132)
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mov r0, sp
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mfcr r1, epc
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mov sp, r10
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lrw r2, HalExcHandleEntry
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jmp r2
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.section .text
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.align 2
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.global IrqEntry
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IrqEntry:
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psrset ee
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subi sp, 136
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stm r0-r15, (sp)
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addi r0, sp, 64
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stm r16-r31, (r0)
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mfcr r0, epsr
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stw r0, (sp, 128)
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mfcr r0, epc
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stw r0, (sp, 132)
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jbsr HalInterrupt
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ldw r0, (sp, 132)
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mtcr r0, epc
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ldw r0, (sp, 128)
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bseti r0, r0, 6
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mtcr r0, epsr
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ldm r0-r15, (sp)
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addi sp, 64
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ldm r16-r31, (sp)
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addi sp, 72
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rte
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#else
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.section .text
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.align 2
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.global HandleEntry
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ldm r0-r15, (sp)
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addi sp, 72
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rte
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#endif
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@ -52,13 +52,12 @@
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#define MASK_8_BITS 0xFF
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#define MASK_32_BITS 0xFFFFFFFF
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#define BYTES_OF_128_INT 4
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#define TIM_INT_NUM 1
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#define OS_USER_HWI_MIN 0
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#define OS_USER_HWI_MAX (LOSCFG_PLATFORM_HWI_LIMIT - 1)
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#define HWI_ALIGNSIZE 0x400
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UINT32 g_intCount = 0;
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UINT32 volatile g_intCount = 0;
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CHAR g_trapStackBase[OS_TRAP_STACK_SIZE];
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VIC_TYPE *VIC_REG = (VIC_TYPE *)VIC_REG_BASE;
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intSave = LOS_IntLock();
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g_intCount--;
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#ifndef CPU_CK804
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HalIrqEndCheckNeedSched();
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#endif
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LOS_IntRestore(intSave);
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}
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@ -586,6 +587,10 @@ WEAK VOID __stack_chk_fail(VOID)
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__builtin_return_address(0));
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}
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WEAK void HalHwiHandleReInit(UINT32 hwiFormAddr)
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{
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}
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/* ****************************************************************************
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Function : HalHwiInit
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Description : initialization of the hardware interrupt
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for (i = OS_SYS_VECTOR_CNT; i < (LOSCFG_PLATFORM_HWI_LIMIT + OS_SYS_VECTOR_CNT); i++) {
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g_hwiForm[i] = (HWI_PROC_FUNC)IrqEntry;
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}
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HalHwiHandleReInit((UINT32)&g_hwiForm);
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HalSetVbr((UINT32)&g_hwiForm);
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for (int i = 0; i < BYTES_OF_128_INT; i++) {
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@ -50,7 +50,11 @@ typedef struct {
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#define CORETIM_SOURCE (1UL << 2)
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#define CORETIM_MODE (1UL << 16)
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#ifdef CPU_CK804
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#define TIM_INT_NUM 25
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#else
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#define TIM_INT_NUM 1
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#endif
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STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
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STATIC UINT64 SysTickReload(UINT64 nextResponseTime);
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Loading…
Reference in New Issue