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!587 fix: cortex-m55栈优化 

Merge pull request !587 from Harylee/m55
This commit is contained in:
openharmony_ci 2022-02-10 13:37:30 +00:00 committed by Gitee
parent d1d412255c 59e9c6ed73
commit a68323683d
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GPG Key ID: 173E9B9CA92EEF8F
4 changed files with 79 additions and 89 deletions
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19
arch/arm/cortex-m55/gcc/NTZ/los_arch_context.h
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@ -41,6 +41,16 @@ extern "C" {
#endif /* __cplusplus */ #endif /* __cplusplus */
typedef struct TagTskContext { typedef struct TagTskContext {
UINT32 uwEXCLR;
UINT32 uwR4;
UINT32 uwR5;
UINT32 uwR6;
UINT32 uwR7;
UINT32 uwR8;
UINT32 uwR9;
UINT32 uwR10;
UINT32 uwR11;
UINT32 uwPriMask;
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined(__FPU_USED) && (__FPU_USED == 1U))) (defined(__FPU_USED) && (__FPU_USED == 1U)))
UINT32 S16; UINT32 S16;
@ -60,15 +70,6 @@ typedef struct TagTskContext {
UINT32 S30; UINT32 S30;
UINT32 S31; UINT32 S31;
#endif #endif
UINT32 uwR4;
UINT32 uwR5;
UINT32 uwR6;
UINT32 uwR7;
UINT32 uwR8;
UINT32 uwR9;
UINT32 uwR10;
UINT32 uwR11;
UINT32 uwPriMask;
UINT32 uwR0; UINT32 uwR0;
UINT32 uwR1; UINT32 uwR1;
UINT32 uwR2; UINT32 uwR2;

4
arch/arm/cortex-m55/gcc/NTZ/los_context.c
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@ -112,8 +112,10 @@ LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VO
context->S15 = 0xAA00000F; context->S15 = 0xAA00000F;
context->FPSCR = 0x00000000; context->FPSCR = 0x00000000;
context->NO_NAME = 0xAA000011; context->NO_NAME = 0xAA000011;
context->uwEXCLR = 0xFFFFFFEDL;
#else
context->uwEXCLR = 0xFFFFFFFDL;
#endif #endif
context->uwR4 = 0x04040404L; context->uwR4 = 0x04040404L;
context->uwR5 = 0x05050505L; context->uwR5 = 0x05050505L;
context->uwR6 = 0x06060606L; context->uwR6 = 0x06060606L;

41
arch/arm/cortex-m55/gcc/NTZ/los_dispatch.S
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@ -33,13 +33,10 @@
.fpu vfpv3-d16-fp16 .fpu vfpv3-d16-fp16
.thumb .thumb
.equ OS_FPU_CPACR, 0xE000ED88
.equ OS_FPU_CPACR_ENABLE, 0x00F00000
.equ OS_NVIC_INT_CTRL, 0xE000ED04 .equ OS_NVIC_INT_CTRL, 0xE000ED04
.equ OS_NVIC_SYSPRI3, 0xE000ED20 .equ OS_NVIC_SYSPRI3, 0xE000ED20
.equ OS_NVIC_PENDSV_PRI, 0xF0F00000 .equ OS_NVIC_PENDSV_PRI, 0xF0F00000
.equ OS_NVIC_PENDSVSET, 0x10000000 .equ OS_NVIC_PENDSVSET, 0x10000000
.equ OS_TASK_STATUS_RUNNING, 0x0010
.section .text .section .text
.thumb .thumb
@ -70,13 +67,12 @@ HalStartToRun:
ldr r0, [r1, #4] ldr r0, [r1, #4]
ldr r12, [r0] ldr r12, [r0]
ldr.w r1, =OS_FPU_CPACR ldr r2, [r12]
ldr r1, [r1] tst r2, #0x10
and r1, r1, #OS_FPU_CPACR_ENABLE it ne
cmp r1, #OS_FPU_CPACR_ENABLE
bne __DisabledFPU bne __DisabledFPU
add r12, r12, #100 add r12, r12, #104
ldmfd r12!, {r0-r7} ldmfd r12!, {r0-r7}
add r12, r12, #72 add r12, r12, #72
msr psp, r12 msr psp, r12
@ -88,7 +84,7 @@ HalStartToRun:
bx r6 bx r6
__DisabledFPU: __DisabledFPU:
add r12, r12, #36 add r12, r12, #40
ldmfd r12!, {r0-r7} ldmfd r12!, {r0-r7}
msr psp, r12 msr psp, r12
@ -167,16 +163,12 @@ HalTaskSwitch:
TaskContextSwitch: TaskContextSwitch:
mov lr, r0 mov lr, r0
mrs r0, psp mrs r0, psp
stmfd r0!, {r4-r12} tst lr, #0x10
it eq
vstmdbeq r0!, {d8-d15}
mov r3, lr
stmfd r0!, {r3-r12}
ldr.w r3, =OS_FPU_CPACR
ldr r3, [r3]
and r3, r3, #OS_FPU_CPACR_ENABLE
cmp r3, #OS_FPU_CPACR_ENABLE
bne __DisabledFPU1
vstmdb r0!, {d8-d15}
__DisabledFPU1:
ldr r5, =g_losTask ldr r5, =g_losTask
ldr r6, [r5] ldr r6, [r5]
str r0, [r6] str r0, [r6]
@ -186,15 +178,10 @@ __DisabledFPU1:
ldr r1, [r0] ldr r1, [r0]
SignalContextRestore: SignalContextRestore:
ldr.w r3, =OS_FPU_CPACR ldmfd r1!, {r3-r12}
ldr r3, [r3] tst r3, #0x10
and r3, r3, #OS_FPU_CPACR_ENABLE it eq
cmp r3, #OS_FPU_CPACR_ENABLE vldmiaeq r1!, {d8-d15}
bne __DisabledFPU2
VLDMIA r1!, {d8-d15}
__DisabledFPU2:
ldmfd r1!, {r4-r12}
msr psp, r1 msr psp, r1
msr PRIMASK, r12 msr PRIMASK, r12

34
arch/arm/cortex-m55/gcc/NTZ/los_exc.S
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@ -56,13 +56,13 @@
.equ FLAG_HWI_ACTIVE, 0x20000 .equ FLAG_HWI_ACTIVE, 0x20000
.equ FLAG_NO_FLOAT, 0x10000000 .equ FLAG_NO_FLOAT, 0x10000000
.equ OS_NVIC_FSR , 0xE000ED28 //include BusFault/MemFault/UsageFault State Register .equ OS_NVIC_FSR, 0xE000ED28 //include BusFault/MemFault/UsageFault State Register
.equ OS_NVIC_HFSR , 0xE000ED2C //HardFault State Register .equ OS_NVIC_HFSR, 0xE000ED2C //HardFault State Register
.equ OS_NVIC_BFAR , 0xE000ED38 .equ OS_NVIC_BFAR, 0xE000ED38
.equ OS_NVIC_MMAR , 0xE000ED34 .equ OS_NVIC_MMAR, 0xE000ED34
.equ OS_NVIC_ACT_BASE , 0xE000E300 .equ OS_NVIC_ACT_BASE, 0xE000E300
.equ OS_NVIC_SHCSRS , 0xE000ED24 .equ OS_NVIC_SHCSRS, 0xE000ED24
.equ OS_NVIC_SHCSR_MASK , 0xC00 .equ OS_NVIC_SHCSR_MASK, 0xC00
.type HalExcNMI, %function .type HalExcNMI, %function
.global HalExcNMI .global HalExcNMI
@ -88,7 +88,7 @@ HalExcHardFault:
TST R2, #0x80000000 TST R2, #0x80000000
BNE osExcDispatch // DEBUGEVT BNE osExcDispatch // DEBUGEVT
AND R0, R0 , #0x000000FF AND R0, R0, #0x000000FF
MOV R1, #HF_VECTBL MOV R1, #HF_VECTBL
ORR R0, R0, R1, LSL #0x8 ORR R0, R0, R1, LSL #0x8
TST R2, #0x00000002 TST R2, #0x00000002
@ -106,7 +106,7 @@ HalExcHardFault:
TST R2, #0x80 // MMARVALID TST R2, #0x80 // MMARVALID
BNE _HFMemFault // MemFault BNE _HFMemFault // MemFault
MOV R12,#0 MOV R12, #0
B osHFExcCommonBMU B osHFExcCommonBMU
.fnend .fnend
@ -141,7 +141,7 @@ osHFExcCommonBMU:
ADD R3, R3, R2 ADD R3, R3, R2
LDRB R2, [R3] LDRB R2, [R3]
ORR R0, R0, R2, LSL #0x8 ORR R0, R0, R2, LSL #0x8
ORR R0, R0 ,R12 ORR R0, R0, R12
B osExcDispatch B osExcDispatch
.fnend .fnend
@ -183,7 +183,7 @@ HalExcBusFault:
_ExcBusNoADDR: _ExcBusNoADDR:
.fnstart .fnstart
.cantunwind .cantunwind
MOV R12,#0 MOV R12, #0
B osExcCommonBMU B osExcCommonBMU
.fnend .fnend
@ -210,7 +210,7 @@ HalExcMemFault:
_ExcMemNoADDR: _ExcMemNoADDR:
.fnstart .fnstart
.cantunwind .cantunwind
MOV R12,#0 MOV R12, #0
B osExcCommonBMU B osExcCommonBMU
.fnend .fnend
@ -248,7 +248,7 @@ osExcDispatch:
.fnstart .fnstart
.cantunwind .cantunwind
LDR R2, =OS_NVIC_ACT_BASE LDR R2, =OS_NVIC_ACT_BASE
MOV R12, #8 // R12 is hwi check loop counter MOV R12, #16 // R12 is hwi check loop counter
.fnend .fnend
.type _hwiActiveCheck, %function .type _hwiActiveCheck, %function
@ -308,10 +308,10 @@ _hwiActiveCheckNext:
/*NMI interrupt excption*/ /*NMI interrupt excption*/
LDR R2, =OS_NVIC_SHCSRS LDR R2, =OS_NVIC_SHCSRS
LDRH R2,[R2] LDRH R2, [R2]
LDR R3,=OS_NVIC_SHCSR_MASK LDR R3, =OS_NVIC_SHCSR_MASK
AND R2, R2,R3 AND R2, R2, R3
CMP R2,#0 CMP R2, #0
BNE _ExcInMSP BNE _ExcInMSP
// exc occured in Task or Init or exc // exc occured in Task or Init or exc
// reserved for register info from task stack // reserved for register info from task stack