diff --git a/arch/arm/cortex-m55/gcc/NTZ/los_arch_context.h b/arch/arm/cortex-m55/gcc/NTZ/los_arch_context.h index 8e61631f..4caf6de5 100755 --- a/arch/arm/cortex-m55/gcc/NTZ/los_arch_context.h +++ b/arch/arm/cortex-m55/gcc/NTZ/los_arch_context.h @@ -41,6 +41,16 @@ extern "C" { #endif /* __cplusplus */ typedef struct TagTskContext { + UINT32 uwEXCLR; + UINT32 uwR4; + UINT32 uwR5; + UINT32 uwR6; + UINT32 uwR7; + UINT32 uwR8; + UINT32 uwR9; + UINT32 uwR10; + UINT32 uwR11; + UINT32 uwPriMask; #if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ (defined(__FPU_USED) && (__FPU_USED == 1U))) UINT32 S16; @@ -60,15 +70,6 @@ typedef struct TagTskContext { UINT32 S30; UINT32 S31; #endif - UINT32 uwR4; - UINT32 uwR5; - UINT32 uwR6; - UINT32 uwR7; - UINT32 uwR8; - UINT32 uwR9; - UINT32 uwR10; - UINT32 uwR11; - UINT32 uwPriMask; UINT32 uwR0; UINT32 uwR1; UINT32 uwR2; diff --git a/arch/arm/cortex-m55/gcc/NTZ/los_context.c b/arch/arm/cortex-m55/gcc/NTZ/los_context.c index 34f38ba6..a920c676 100755 --- a/arch/arm/cortex-m55/gcc/NTZ/los_context.c +++ b/arch/arm/cortex-m55/gcc/NTZ/los_context.c @@ -112,8 +112,10 @@ LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VO context->S15 = 0xAA00000F; context->FPSCR = 0x00000000; context->NO_NAME = 0xAA000011; + context->uwEXCLR = 0xFFFFFFEDL; +#else + context->uwEXCLR = 0xFFFFFFFDL; #endif - context->uwR4 = 0x04040404L; context->uwR5 = 0x05050505L; context->uwR6 = 0x06060606L; diff --git a/arch/arm/cortex-m55/gcc/NTZ/los_dispatch.S b/arch/arm/cortex-m55/gcc/NTZ/los_dispatch.S index 8f3952a5..b8afd980 100755 --- a/arch/arm/cortex-m55/gcc/NTZ/los_dispatch.S +++ b/arch/arm/cortex-m55/gcc/NTZ/los_dispatch.S @@ -33,13 +33,10 @@ .fpu vfpv3-d16-fp16 .thumb -.equ OS_FPU_CPACR, 0xE000ED88 -.equ OS_FPU_CPACR_ENABLE, 0x00F00000 .equ OS_NVIC_INT_CTRL, 0xE000ED04 .equ OS_NVIC_SYSPRI3, 0xE000ED20 .equ OS_NVIC_PENDSV_PRI, 0xF0F00000 .equ OS_NVIC_PENDSVSET, 0x10000000 -.equ OS_TASK_STATUS_RUNNING, 0x0010 .section .text .thumb @@ -70,13 +67,12 @@ HalStartToRun: ldr r0, [r1, #4] ldr r12, [r0] - ldr.w r1, =OS_FPU_CPACR - ldr r1, [r1] - and r1, r1, #OS_FPU_CPACR_ENABLE - cmp r1, #OS_FPU_CPACR_ENABLE + ldr r2, [r12] + tst r2, #0x10 + it ne bne __DisabledFPU - add r12, r12, #100 + add r12, r12, #104 ldmfd r12!, {r0-r7} add r12, r12, #72 msr psp, r12 @@ -88,7 +84,7 @@ HalStartToRun: bx r6 __DisabledFPU: - add r12, r12, #36 + add r12, r12, #40 ldmfd r12!, {r0-r7} msr psp, r12 @@ -165,38 +161,29 @@ HalTaskSwitch: bx lr TaskContextSwitch: - mov lr, r0 - mrs r0, psp - stmfd r0!, {r4-r12} + mov lr, r0 + mrs r0, psp + tst lr, #0x10 + it eq + vstmdbeq r0!, {d8-d15} + mov r3, lr + stmfd r0!, {r3-r12} - ldr.w r3, =OS_FPU_CPACR - ldr r3, [r3] - and r3, r3, #OS_FPU_CPACR_ENABLE - cmp r3, #OS_FPU_CPACR_ENABLE - bne __DisabledFPU1 - vstmdb r0!, {d8-d15} + ldr r5, =g_losTask + ldr r6, [r5] + str r0, [r6] -__DisabledFPU1: - ldr r5, =g_losTask - ldr r6, [r5] - str r0, [r6] - - ldr r0, [r5, #4] - str r0, [r5] - ldr r1, [r0] + ldr r0, [r5, #4] + str r0, [r5] + ldr r1, [r0] SignalContextRestore: - ldr.w r3, =OS_FPU_CPACR - ldr r3, [r3] - and r3, r3, #OS_FPU_CPACR_ENABLE - cmp r3, #OS_FPU_CPACR_ENABLE - bne __DisabledFPU2 - VLDMIA r1!, {d8-d15} + ldmfd r1!, {r3-r12} + tst r3, #0x10 + it eq + vldmiaeq r1!, {d8-d15} + msr psp, r1 + msr PRIMASK, r12 -__DisabledFPU2: - ldmfd r1!, {r4-r12} - msr psp, r1 - msr PRIMASK, r12 - - bx lr + bx lr .fnend diff --git a/arch/arm/cortex-m55/gcc/NTZ/los_exc.S b/arch/arm/cortex-m55/gcc/NTZ/los_exc.S index 976b78e1..2668ddac 100755 --- a/arch/arm/cortex-m55/gcc/NTZ/los_exc.S +++ b/arch/arm/cortex-m55/gcc/NTZ/los_exc.S @@ -56,13 +56,13 @@ .equ FLAG_HWI_ACTIVE, 0x20000 .equ FLAG_NO_FLOAT, 0x10000000 -.equ OS_NVIC_FSR , 0xE000ED28 //include BusFault/MemFault/UsageFault State Register -.equ OS_NVIC_HFSR , 0xE000ED2C //HardFault State Register -.equ OS_NVIC_BFAR , 0xE000ED38 -.equ OS_NVIC_MMAR , 0xE000ED34 -.equ OS_NVIC_ACT_BASE , 0xE000E300 -.equ OS_NVIC_SHCSRS , 0xE000ED24 -.equ OS_NVIC_SHCSR_MASK , 0xC00 +.equ OS_NVIC_FSR, 0xE000ED28 //include BusFault/MemFault/UsageFault State Register +.equ OS_NVIC_HFSR, 0xE000ED2C //HardFault State Register +.equ OS_NVIC_BFAR, 0xE000ED38 +.equ OS_NVIC_MMAR, 0xE000ED34 +.equ OS_NVIC_ACT_BASE, 0xE000E300 +.equ OS_NVIC_SHCSRS, 0xE000ED24 +.equ OS_NVIC_SHCSR_MASK, 0xC00 .type HalExcNMI, %function .global HalExcNMI @@ -71,7 +71,7 @@ HalExcNMI: .cantunwind MOV R0, #OS_EXC_CAUSE_NMI MOV R1, #0 - B osExcDispatch + B osExcDispatch .fnend .type HalExcHardFault, %function @@ -88,7 +88,7 @@ HalExcHardFault: TST R2, #0x80000000 BNE osExcDispatch // DEBUGEVT - AND R0, R0 , #0x000000FF + AND R0, R0, #0x000000FF MOV R1, #HF_VECTBL ORR R0, R0, R1, LSL #0x8 TST R2, #0x00000002 @@ -106,7 +106,7 @@ HalExcHardFault: TST R2, #0x80 // MMARVALID BNE _HFMemFault // MemFault - MOV R12,#0 + MOV R12, #0 B osHFExcCommonBMU .fnend @@ -141,7 +141,7 @@ osHFExcCommonBMU: ADD R3, R3, R2 LDRB R2, [R3] ORR R0, R0, R2, LSL #0x8 - ORR R0, R0 ,R12 + ORR R0, R0, R12 B osExcDispatch .fnend @@ -183,7 +183,7 @@ HalExcBusFault: _ExcBusNoADDR: .fnstart .cantunwind - MOV R12,#0 + MOV R12, #0 B osExcCommonBMU .fnend @@ -210,7 +210,7 @@ HalExcMemFault: _ExcMemNoADDR: .fnstart .cantunwind - MOV R12,#0 + MOV R12, #0 B osExcCommonBMU .fnend @@ -222,7 +222,7 @@ HalExcUsageFault: LDR R0, =OS_NVIC_FSR LDR R0, [R0] - MOVW R1, #0x030F + MOVW R1, #0x030F LSL R1, R1, #16 AND R0, R0, R1 MOV R12, #0 @@ -248,7 +248,7 @@ osExcDispatch: .fnstart .cantunwind LDR R2, =OS_NVIC_ACT_BASE - MOV R12, #8 // R12 is hwi check loop counter + MOV R12, #16 // R12 is hwi check loop counter .fnend .type _hwiActiveCheck, %function @@ -277,8 +277,8 @@ _ExcInMSP: BNE _NoFloatInMsp ADD R3, R13, #104 PUSH {R3} - MRS R12, PRIMASK // store message-->exc: disable int? - PUSH {R4-R12} // store message-->exc: {R4-R12} + MRS R12, PRIMASK // store message-->exc: disable int? + PUSH {R4-R12} // store message-->exc: {R4-R12} VPUSH {D8-D15} B _handleEntry .fnend @@ -291,8 +291,8 @@ _NoFloatInMsp: ADD R3, R13, #32 PUSH {R3} // save IRQ SP // store message-->exc: MSP(R13) - MRS R12, PRIMASK // store message-->exc: disable int? - PUSH {R4-R12} // store message-->exc: {R4-R12} + MRS R12, PRIMASK // store message-->exc: disable int? + PUSH {R4-R12} // store message-->exc: {R4-R12} ORR R0, R0, #FLAG_NO_FLOAT B _handleEntry .fnend @@ -308,42 +308,42 @@ _hwiActiveCheckNext: /*NMI interrupt excption*/ LDR R2, =OS_NVIC_SHCSRS - LDRH R2,[R2] - LDR R3,=OS_NVIC_SHCSR_MASK - AND R2, R2,R3 - CMP R2,#0 + LDRH R2, [R2] + LDR R3, =OS_NVIC_SHCSR_MASK + AND R2, R2, R3 + CMP R2, #0 BNE _ExcInMSP // exc occured in Task or Init or exc // reserved for register info from task stack - LDR R2, =g_taskScheduled - LDR R2, [R2] - TST R2, #1 // OS_FLG_BGD_ACTIVE - BEQ _ExcInMSP // if exc occured in Init then branch + LDR R2, =g_taskScheduled + LDR R2, [R2] + TST R2, #1 // OS_FLG_BGD_ACTIVE + BEQ _ExcInMSP // if exc occured in Init then branch - CMP LR, #0xFFFFFFED //auto push floating registers + CMP LR, #0xFFFFFFED //auto push floating registers BNE _NoFloatInPsp // exc occured in Task - MOV R2, R13 - SUB R13, #96 // add 8 Bytes reg(for STMFD) + MOV R2, R13 + SUB R13, #96 // add 8 Bytes reg(for STMFD) - MRS R3, PSP + MRS R3, PSP ADD R12, R3, #104 - PUSH {R12} // save task SP + PUSH {R12} // save task SP MRS R12, PRIMASK - PUSH {R4-R12} + PUSH {R4-R12} VPUSH {D8-D15} // copy auto saved task register - LDMFD R3!, {R4-R11} // R4-R11 store PSP reg(auto push when exc in task) + LDMFD R3!, {R4-R11} // R4-R11 store PSP reg(auto push when exc in task) VLDMIA R3!, {D8-D15} VSTMDB R2!, {D8-D15} - STMFD R2!, {R4-R11} - B _handleEntry + STMFD R2!, {R4-R11} + B _handleEntry .fnend .type _NoFloatInPsp, %function @@ -351,15 +351,15 @@ _hwiActiveCheckNext: _NoFloatInPsp: .fnstart .cantunwind - MOV R2, R13 // no auto push floating registers + MOV R2, R13 // no auto push floating registers SUB R13, #32 // add 8 Bytes reg(for STMFD) - MRS R3, PSP + MRS R3, PSP ADD R12, R3, #32 PUSH {R12} // save task SP MRS R12, PRIMASK - PUSH {R4-R12} + PUSH {R4-R12} LDMFD R3, {R4-R11} // R4-R11 store PSP reg(auto push when exc in task) STMFD R2!, {R4-R11} @@ -371,10 +371,10 @@ _NoFloatInPsp: _handleEntry: .fnstart .cantunwind - MOV R3, R13 // R13:the 4th param + MOV R3, R13 // R13:the 4th param CPSID I CPSID F - B HalExcHandleEntry + B HalExcHandleEntry NOP .fnend