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!481 fix：修复Fault异常模块中FPU宏等问题 

Merge pull request !481 from kenneth/cherry-pick-1640158227
This commit is contained in:
openharmony_ci 2021-12-23 07:17:18 +00:00 committed by Gitee
parent 314102c234 7a6242549f
commit 5acd9b36ff
9 changed files with 9 additions and 30 deletions
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2
kernel/arch/arm/cortex-m3/keil/los_exc.S
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@ -195,7 +195,7 @@ _hwiActiveCheck
RBIT R2, R3 RBIT R2, R3
CLZ R2, R2 CLZ R2, R2
AND R12, R12, #1 AND R12, R12, #1
ADD R2, R2, R12, LSL #5 ; calculate R2 (hwi number) as uwPid ADD R2, R2, R12, LSL #5 ; calculate R2 (hwi number) as pid
_ExcInMSP _ExcInMSP
CMP LR, #0xFFFFFFE9 CMP LR, #0xFFFFFFE9

8
kernel/arch/arm/cortex-m33/gcc/NTZ/los_exc.S
View File

@ -268,7 +268,7 @@ _hwiActiveCheck:
RBIT R2, R3 RBIT R2, R3
CLZ R2, R2 CLZ R2, R2
AND R12, R12, #1 AND R12, R12, #1
ADD R2, R2, R12, LSL #5 // calculate R2 (hwi number) as uwPid ADD R2, R2, R12, LSL #5 // calculate R2 (hwi number) as pid
.fnend .fnend
.type _ExcInMSP, %function .type _ExcInMSP, %function
@ -282,10 +282,7 @@ _ExcInMSP:
PUSH {R3} PUSH {R3}
MRS R12, PRIMASK // store message-->exc: disable int? MRS R12, PRIMASK // store message-->exc: disable int?
PUSH {R4-R12} // store message-->exc: {R4-R12} PUSH {R4-R12} // store message-->exc: {R4-R12}
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined(__FPU_USED) && (__FPU_USED == 1U)))
VPUSH {D8-D15} VPUSH {D8-D15}
#endif
B _handleEntry B _handleEntry
.fnend .fnend
@ -341,10 +338,7 @@ _hwiActiveCheckNext:
MRS R12, PRIMASK MRS R12, PRIMASK
PUSH {R4-R12} PUSH {R4-R12}
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined(__FPU_USED) && (__FPU_USED == 1U)))
VPUSH {D8-D15} VPUSH {D8-D15}
#endif
// copy auto saved task register // copy auto saved task register

8
kernel/arch/arm/cortex-m33/gcc/TZ/non_secure/los_exc.S
View File

@ -252,7 +252,7 @@ _hwiActiveCheck:
RBIT R2, R3 RBIT R2, R3
CLZ R2, R2 CLZ R2, R2
AND R12, R12, #1 AND R12, R12, #1
ADD R2, R2, R12, LSL #5 // calculate R2 (hwi number) as uwPid ADD R2, R2, R12, LSL #5 // calculate R2 (hwi number) as pid
.fnend .fnend
.type _ExcInMSP, %function .type _ExcInMSP, %function
@ -266,10 +266,7 @@ _ExcInMSP:
PUSH {R3} PUSH {R3}
MRS R12, PRIMASK // store message-->exc: disable int? MRS R12, PRIMASK // store message-->exc: disable int?
PUSH {R4-R12} // store message-->exc: {R4-R12} PUSH {R4-R12} // store message-->exc: {R4-R12}
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined(__FPU_USED) && (__FPU_USED == 1U)))
VPUSH {D8-D15} VPUSH {D8-D15}
#endif
B _handleEntry B _handleEntry
.fnend .fnend
@ -325,10 +322,7 @@ _hwiActiveCheckNext:
MRS R12, PRIMASK MRS R12, PRIMASK
PUSH {R4-R12} PUSH {R4-R12}
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined(__FPU_USED) && (__FPU_USED == 1U)))
VPUSH {D8-D15} VPUSH {D8-D15}
#endif
// copy auto saved task register // copy auto saved task register

8
kernel/arch/arm/cortex-m33/gcc/los_exc.S
View File

@ -268,7 +268,7 @@ _hwiActiveCheck:
RBIT R2, R3 RBIT R2, R3
CLZ R2, R2 CLZ R2, R2
AND R12, R12, #1 AND R12, R12, #1
ADD R2, R2, R12, LSL #5 // calculate R2 (hwi number) as uwPid ADD R2, R2, R12, LSL #5 // calculate R2 (hwi number) as pid
.fnend .fnend
.type _ExcInMSP, %function .type _ExcInMSP, %function
@ -282,10 +282,7 @@ _ExcInMSP:
PUSH {R3} PUSH {R3}
MRS R12, PRIMASK // store message-->exc: disable int? MRS R12, PRIMASK // store message-->exc: disable int?
PUSH {R4-R12} // store message-->exc: {R4-R12} PUSH {R4-R12} // store message-->exc: {R4-R12}
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined(__FPU_USED) && (__FPU_USED == 1U)))
VPUSH {D8-D15} VPUSH {D8-D15}
#endif
B _handleEntry B _handleEntry
.fnend .fnend
@ -341,10 +338,7 @@ _hwiActiveCheckNext:
MRS R12, PRIMASK MRS R12, PRIMASK
PUSH {R4-R12} PUSH {R4-R12}
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined(__FPU_USED) && (__FPU_USED == 1U)))
VPUSH {D8-D15} VPUSH {D8-D15}
#endif
// copy auto saved task register // copy auto saved task register

2
kernel/arch/arm/cortex-m33/iar/TZ/non_secure/los_exc.S
View File

@ -184,7 +184,7 @@ _hwiActiveCheck
RBIT R2, R3 RBIT R2, R3
CLZ R2, R2 CLZ R2, R2
AND R12, R12, #1 AND R12, R12, #1
ADD R2, R2, R12, LSL #5 ; calculate R2 (hwi number) as uwPid ADD R2, R2, R12, LSL #5 ; calculate R2 (hwi number) as pid
_ExcInMSP _ExcInMSP
CMP LR, #0xFFFFFFE9 CMP LR, #0xFFFFFFE9

2
kernel/arch/arm/cortex-m4/gcc/los_exc.S
View File

@ -267,7 +267,7 @@ _hwiActiveCheck:
RBIT R2, R3 RBIT R2, R3
CLZ R2, R2 CLZ R2, R2
AND R12, R12, #1 AND R12, R12, #1
ADD R2, R2, R12, LSL #5 // calculate R2 (hwi number) as uwPid ADD R2, R2, R12, LSL #5 // calculate R2 (hwi number) as pid
.fnend .fnend
.type _ExcInMSP, %function .type _ExcInMSP, %function

2
kernel/arch/arm/cortex-m4/iar/los_exc.S
View File

@ -195,7 +195,7 @@ _hwiActiveCheck
RBIT R2, R3 RBIT R2, R3
CLZ R2, R2 CLZ R2, R2
AND R12, R12, #1 AND R12, R12, #1
ADD R2, R2, R12, LSL #5 ; calculate R2 (hwi number) as uwPid ADD R2, R2, R12, LSL #5 ; calculate R2 (hwi number) as pid
_ExcInMSP _ExcInMSP
CMP LR, #0xFFFFFFE9 CMP LR, #0xFFFFFFE9

5
kernel/arch/arm/cortex-m7/gcc/los_exc.S
View File

@ -268,7 +268,7 @@ _hwiActiveCheck:
RBIT R2, R3 RBIT R2, R3
CLZ R2, R2 CLZ R2, R2
AND R12, R12, #1 AND R12, R12, #1
ADD R2, R2, R12, LSL #5 // calculate R2 (hwi number) as uwPid ADD R2, R2, R12, LSL #5 // calculate R2 (hwi number) as pid
.fnend .fnend
.type _ExcInMSP, %function .type _ExcInMSP, %function
@ -282,10 +282,7 @@ _ExcInMSP:
PUSH {R3} PUSH {R3}
MRS R12, PRIMASK // store message-->exc: disable int? MRS R12, PRIMASK // store message-->exc: disable int?
PUSH {R4-R12} // store message-->exc: {R4-R12} PUSH {R4-R12} // store message-->exc: {R4-R12}
#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined(__FPU_USED) && (__FPU_USED == 1U)))
VPUSH {D8-D15} VPUSH {D8-D15}
#endif
B _handleEntry B _handleEntry
.fnend .fnend

2
kernel/arch/arm/cortex-m7/iar/los_exc.S
View File

@ -195,7 +195,7 @@ _hwiActiveCheck
RBIT R2, R3 RBIT R2, R3
CLZ R2, R2 CLZ R2, R2
AND R12, R12, #1 AND R12, R12, #1
ADD R2, R2, R12, LSL #5 ; calculate R2 (hwi number) as uwPid ADD R2, R2, R12, LSL #5 ; calculate R2 (hwi number) as pid
_ExcInMSP _ExcInMSP
CMP LR, #0xFFFFFFE9 CMP LR, #0xFFFFFFE9