xuos-web/docs/doc/processor/aiit-arm64.md

aiit-arm64

综述

AIIT-ARM64

XiUOS最新分支支持stm32f407-st-discovery开发板，该开发板作为一种标准的板子，支持各种上层组件和应用程序。

硬件特点

• Core: Arm® 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator) allowing 0-wait state execution from Flash memory, frequency up to 168 MHz, memory protection unit, 210 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
• Memories

1. Up to 1 Mbyte of Flash memory

2. Up to 192+4 Kbytes of SRAM including 64-Kbyte of CCM (core coupled memory) data RAM

3. Up to 192+4 Kbytes of SRAM including 64-Kbyte of CCM (core coupled memory) data RAM

4. 512 bytes of OTP memory

5. Flexible static memory controller supporting Compact Flash, SRAM, PSRAM, NOR and NAND memories

+ LCD parallel interface, 8080/6800 modes + Clock, reset and supply management

1. 1.8 V to 3.6 V application supply and I/Os

2. POR, PDR, PVD and BOR

3. 4-to-26 MHz crystal oscillator

4. Internal 16 MHz factory-trimmed RC (1% accuracy)

5. 32 kHz oscillator for RTC with calibration

6. Internal 32 kHz RC with calibration

+ Low-power operation

1. Sleep, Stop and Standby modes

2. V_BAT supply for RTC, 20×32 bit backup registers + optional 4 KB backup SRAM

+ 3×12-bit, 2.4 MSPS A/D converters: up to 24 channels and 7.2 MSPS in triple interleaved mode + 2×12-bit D/A converters + General-purpose DMA: 16-stream DMA controller with FIFOs and burst support + Up to 17 timers: up to twelve 16-bit and two 32-bit timers up to 168 MHz, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input + Debug mode

1. Serial wire debug (SWD) & JTAG interfaces

2. Cortex-M4 Embedded Trace Macrocell™

+ Up to 140 I/O ports with interrupt capability

1. Up to 136 fast I/Os up to 84 MHz

2. Up to 138 5 V-tolerant I/Os

+ Up to 15 communication interfaces

1. Up to 3 × I²C interfaces (SMBus/PMBus)

2. Up to 4 USARTs/2 UARTs (10.5 Mbit/s, ISO 7816 interface, LIN, IrDA, modem control)

3. Up to 3 SPIs (42 Mbits/s), 2 with muxed full-duplex I2S to achieve audio class accuracy via internal audio PLL or external clock

4. 2 × CAN interfaces (2.0B Active)

5. SDIO interface

+ Advanced connectivity

1. USB 2.0 full-speed device/host/OTG controller with on-chip PHY

2. USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI

3. 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII

+ 8- to 14-bit parallel camera interface up to 54 Mbytes/s + True random number generator + CRC calculation unit + 96-bit unique ID + RTC: subsecond accuracy, hardware calendar

支持的功能