modify the dir under processor

docs/.vuepress/sidebar.js

@@ -8,7 +8,8 @@ const sidebar = {
     '/doc/kernel/synchron',
     '/doc/kernel/threadcommunication',
     '/doc/kernel/int',
-    '/doc/kernel/tmr'
+    '/doc/kernel/tmr',
+    '/doc/kernel/task'
   ],
   'component': [
     '/doc/component/fs',
@@ -65,8 +66,8 @@ const sidebar = {
   ],
   'processor': [
     '/doc/processor/riscv',
-    '/doc/processor/riscv_sk',
+    '/doc/processor/arm',
-    '/doc/processor/riscv_fpga'
+    '/doc/processor/riscv_sfcore'
   ],
   'selfterminal': [
     '/doc/selfterminal/aiit-arm',

docs/doc/processor/README.md

@@ -4,7 +4,7 @@
 
 - [RISC-V](/doc/processor/riscv.md)
 
-- [RISC-V软核](/doc/processor/riscv_sk.md)
+- [ARM](/doc/processor/arm.md)
 
-- [ARM+contex M系列](/doc/processor/riscv_fpga.md)
+- [RISC-V软核](/doc/processor/riscv_sfcore.md)
 

docs/doc/processor/arm.md

@@ -0,0 +1 @@
+# ARM

docs/doc/processor/riscv.md

@@ -1 +1 @@
-# riscv
+# RISC-V

docs/doc/processor/riscv_fpga.md

@@ -1 +0,0 @@
-# riscv+fpga

docs/doc/processor/riscv_sfcore.md

@@ -0,0 +1 @@
+# RISC-V 软核

docs/doc/processor/riscv_sk.md

@@ -1 +0,0 @@
-# riscv_软核