1、modify the 'link.lds' file accroding to sdk;2、add irq enable and disable function

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/arch_interrupt.h

@@ -22,6 +22,14 @@
 int32_t ArchEnableHwIrq(uint32_t irq_num);
 int32_t ArchDisableHwIrq(uint32_t irq_num);
 
+//! @brief
+typedef enum {
+    CPU_0,
+    CPU_1,
+    CPU_2,
+    CPU_3,
+} cpuid_e;
+
 struct ExceptionStackRegister
 {
 	uint32_t r0;

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/boot.S

@@ -1,18 +1,8 @@
-
-@ .equ Mode_USR,        0x10
-@ .equ Mode_FIQ,        0x11
-@ .equ Mode_IRQ,        0x12
-@ .equ Mode_SVC,        0x13
-@ .equ Mode_ABT,        0x17
-@ .equ Mode_UND,        0x1B
-@ .equ Mode_SYS,        0x1F
 #include <asm_defines.h>
 
-@ .equ I_BIT,           0x80            @ when I bit is set, IRQ is disabled
-@ .equ F_BIT,           0x40            @ when F bit is set, FIQ is disabled
-
-.equ STACK_SIZE,     0x00000100
+.global ExceptionVectors
 
+.section ".startup","ax"
 .globl _reset
 
 _reset:
@@ -30,7 +20,6 @@ _reset:
     bic     r0, #(1 << 0)           /* mmu */
     mcr     p15, 0, r0, c1, c0, 0
     
-
     ldr     r0, =stack_top
 
     @  Set the startup stack for svc
@@ -39,26 +28,38 @@ _reset:
     @  Enter Undefined Instruction Mode and set its Stack Pointer
     msr     cpsr_c, #MODE_UND|I_BIT|F_BIT
     mov     sp, r0
-    sub     r0, r0, #STACK_SIZE
+    sub     r0, r0, #EXCEPTION_STACK_SIZE
 
     @  Enter Abort Mode and set its Stack Pointer
     msr     cpsr_c, #MODE_ABT|I_BIT|F_BIT
     mov     sp, r0
-    sub     r0, r0, #STACK_SIZE
+    sub     r0, r0, #EXCEPTION_STACK_SIZE
 
     @  Enter FIQ Mode and set its Stack Pointer
     msr     cpsr_c, #MODE_FIQ|I_BIT|F_BIT
     mov     sp, r0
-    sub     r0, r0, #STACK_SIZE
+    sub     r0, r0, #EXCEPTION_STACK_SIZE
 
     @  Enter IRQ Mode and set its Stack Pointer
     msr     cpsr_c, #MODE_IRQ|I_BIT|F_BIT
     mov     sp, r0
-    sub     r0, r0, #STACK_SIZE
+    sub     r0, r0, #EXCEPTION_STACK_SIZE
 
     /* come back to SVC mode */
     msr     cpsr_c, #MODE_SVC|I_BIT|F_BIT
 
+    /*
+     * copy the vector table into the RAM vectors
+     * this assumes that the RAM vectors size is divisible by 3 words (12 bytes)
+     */
+    ldr     r1,=__ram_vectors_start
+    ldr     r2,=__ram_vectors_end
+    ldr     r3,=ExceptionVectors
+1:  cmp     r1,r2
+    ldmlt   r3!,{r4,r5,r6}
+    stmlt   r1!,{r4,r5,r6}
+    blt     1b
+
     /* clear .bss */
     mov     r0, #0                  /* get a zero */
     ldr     r1,=__bss_start           /* bss start  */

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/exception.S

@@ -1,6 +1,6 @@
 #include <asm_defines.h>
 
-.section .vectors, "ax"
+.section .text.vectors, "ax"
 .code 32
 
 .globl ExceptionVectors

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv7-a/cortex-a9/interrupt.c

@@ -3,24 +3,43 @@
 #include <stddef.h>
 #include <isr.h>
 
-unsigned long __attribute__((naked)) DisableLocalInterrupt()
+uint32_t DisableLocalInterrupt(void)
 {
-
+    uint32_t intSave;
+    __asm__ __volatile__(
+        "mrs    %0, cpsr      \n"
+        "cpsid  if              "
+        : "=r"(intSave)
+        :
+        : "memory");
+    return intSave;
 }
 
-void __attribute__((naked)) EnableLocalInterrupt(unsigned long level)
+void EnableLocalInterrupt(unsigned long level)
 {
-
+    uint32_t intSave;
+    __asm__ __volatile__(
+        "mrs    %0, cpsr      \n"
+        "cpsie  if              "
+        : "=r"(intSave)
+        :
+        : "memory");
+    return;
 }
 
 int32_t ArchEnableHwIrq(uint32_t irq_num)
 {
-
+    // gic_set_irq_priority(irq_num, priority);
+    gic_set_irq_security(irq_num, false);    // set IRQ as non-secure
+    // gic_set_cpu_target(irq_num, CPU_0, true);
+    gic_enable_irq(irq_num, true);
     return 0;
 }
 
 int32_t ArchDisableHwIrq(uint32_t irq_num)
 {
+    gic_enable_irq(irq_num, false);
+    // gic_set_cpu_target(irq_num, CPU_0, false);
     return 0;
 }