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This commit is contained in:
songyanguang 2025-01-21 10:16:39 +08:00
parent e0fb6dc926
commit e98cffed83
4 changed files with 3 additions and 6 deletions
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2
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S
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@ -118,5 +118,5 @@ relocate_enable_mmu:
j .Lsecondary_park
debug_string_start: .ascii "XiZi boot start\n\0"
debug_string_start: .ascii "XiZi jh7110 boot start\n\0"

4
Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c
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@ -32,7 +32,7 @@ void plic_enable_irq(int cpu, int hwirq, int enable)
int hart = CPU_TO_HART(cpu);
unsigned int reg = PLIC_MENABLE(hart) + 4 * (hwirq / 32);
printk("plic_enable_irq hwirq=%d\n", hwirq);
// printk("plic_enable_irq hwirq=%d\n", hwirq);
#if 0
if (enable) {
writel(readl(reg) | hwirq_mask, reg);
@ -50,7 +50,7 @@ int plic_init(void)
int i;
int hwirq;
printk("plic_init boot_cpu_hartid=%lu\n", boot_cpu_hartid);
// printk("plic_init boot_cpu_hartid=%lu\n", boot_cpu_hartid);
#if 0
for (i = 0; i < MAX_CPUS; i++) {
writel(0, PLIC_MTHRESHOLD(CPU_TO_HART(i)));

2
Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c
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@ -50,10 +50,8 @@ void load_pgdir(uintptr_t pgdir_paddr)
struct ICacheDone* p_icache_done = AchieveResource(&right_group.icache_driver_tag);
struct DCacheDone* p_dcache_done = AchieveResource(&right_group.dcache_driver_tag);
printk("load_pgdir pgdir_paddr=%08lx\n", pgdir_paddr);
csr_write(CSR_SATP, PFN_DOWN(pgdir_paddr) | SATP_MODE);
__asm__ __volatile__ ("sfence.vma" : : : "memory");
printf_early("load_pgdir pgdir_paddr=%08lx ok\n", pgdir_paddr);
p_icache_done->invalidateall();
p_dcache_done->flushall();

1
Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c
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@ -55,7 +55,6 @@ static bool _new_pgdir(struct TopLevelPageDirectory* pgdir)
static bool _map_pages(uintptr_t* pgdir, uintptr_t vaddr, uintptr_t paddr, intptr_t len, uintptr_t attr)
{
DEBUG_PRINTF("_map_pages pgdir=%08lx, vaddr=%08lx, paddr=%08lx, len=%08lx, attr==%08lx\n", pgdir, vaddr, paddr, len, attr);
assert(len >= 0);
vaddr = ALIGNDOWN(vaddr, LEVEL4_PTE_SIZE);
paddr = ALIGNDOWN(paddr, LEVEL4_PTE_SIZE);