From e98cffed83757b66aa1f8cafbafe9f44cb93b6b5 Mon Sep 17 00:00:00 2001
From: songyanguang <345810377@qq.com>
Date: Tue, 21 Jan 2025 10:16:39 +0800
Subject: [PATCH] Modify log

---
 .../hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S    | 2 +-
 .../XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c      | 4 ++--
 Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c        | 2 --
 Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c      | 1 -
 4 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S
index 089df000e..f9ba432d3 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S
@@ -118,5 +118,5 @@ relocate_enable_mmu:
 	j .Lsecondary_park
 
 
-debug_string_start:  .ascii "XiZi boot start\n\0"
+debug_string_start:  .ascii "XiZi jh7110 boot start\n\0"
 
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c
index af02658f7..aa3546ee5 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c
@@ -32,7 +32,7 @@ void plic_enable_irq(int cpu, int hwirq, int enable)
     int hart = CPU_TO_HART(cpu);
     unsigned int reg = PLIC_MENABLE(hart) + 4 * (hwirq / 32);
 
-    printk("plic_enable_irq hwirq=%d\n", hwirq);
+//    printk("plic_enable_irq hwirq=%d\n", hwirq);
 #if 0
     if (enable) {
         writel(readl(reg) | hwirq_mask, reg);
@@ -50,7 +50,7 @@ int plic_init(void)
     int i;
     int hwirq;
 
-    printk("plic_init boot_cpu_hartid=%lu\n", boot_cpu_hartid);
+//    printk("plic_init boot_cpu_hartid=%lu\n", boot_cpu_hartid);
 #if 0
     for (i = 0; i < MAX_CPUS; i++) {
         writel(0, PLIC_MTHRESHOLD(CPU_TO_HART(i)));
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c
index 508c88296..cb5849baa 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c
@@ -50,10 +50,8 @@ void load_pgdir(uintptr_t pgdir_paddr)
     struct ICacheDone* p_icache_done = AchieveResource(&right_group.icache_driver_tag);
     struct DCacheDone* p_dcache_done = AchieveResource(&right_group.dcache_driver_tag);
 
-    printk("load_pgdir pgdir_paddr=%08lx\n", pgdir_paddr);
     csr_write(CSR_SATP, PFN_DOWN(pgdir_paddr) | SATP_MODE);
 	__asm__ __volatile__ ("sfence.vma" : : : "memory");
-    printf_early("load_pgdir pgdir_paddr=%08lx ok\n", pgdir_paddr);
 
     p_icache_done->invalidateall();
     p_dcache_done->flushall();
diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c
index bfc173b36..68adee8fa 100644
--- a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c
+++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c
@@ -55,7 +55,6 @@ static bool _new_pgdir(struct TopLevelPageDirectory* pgdir)
 
 static bool _map_pages(uintptr_t* pgdir, uintptr_t vaddr, uintptr_t paddr, intptr_t len, uintptr_t attr)
 {
-    DEBUG_PRINTF("_map_pages pgdir=%08lx, vaddr=%08lx, paddr=%08lx, len=%08lx, attr==%08lx\n", pgdir, vaddr, paddr, len, attr);
     assert(len >= 0);
     vaddr = ALIGNDOWN(vaddr, LEVEL4_PTE_SIZE);
     paddr = ALIGNDOWN(paddr, LEVEL4_PTE_SIZE);