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Modify riscv csr

This commit is contained in:
songyanguang 2025-01-22 09:42:33 +08:00
parent 0d05dab7b3
commit ca35c72d02
2 changed files with 2 additions and 16 deletions
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3
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/csr.h
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@ -6,11 +6,12 @@
#ifndef _ASM_RISCV_CSR_H
#define _ASM_RISCV_CSR_H
#include "autoconf.h"
#include <asm/asm.h>
#include <asm/const.h>
#define CONFIG_64BIT 1
/* Status register flags */
#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
#define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */

15
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/autoconf.h
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@ -1,15 +0,0 @@
#ifndef _AUTOCONF_H
#define _AUTOCONF_H
#define CONFIG_64BIT 1
#define CONFIG_MMU 1
#define CONFIG_PHYS_ADDR_T_64BIT 1
#define CONFIG_PAGE_OFFSET 0xffffffe000000000
#define CONFIG_VA_BITS 39
#define THREAD_SIZE (512 << 2)
#define KERNEL_MAP_VIRT_ADDR 0 /* offsetof(struct kernel_mapping, virt_addr) */
#define TASK_TI_CPU 32 /* offsetof(struct task_struct, thread_info.cpu) */
#endif /* _AUTOCONF_H */