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Merge branch 'jh7110_debug' into prepare_for_master

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songyanguang
2025-01-24 17:52:12 +08:00
parent dca3e93959 3e70ccddce
commit b3aae320fe
97 changed files with 5617 additions and 31 deletions
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Ubiquitous/XiZi_AIoT/hardkernel/arch/Makefile
+5
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@@ -1,3 +1,8 @@
ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), )
SRC_DIR := arm
endif
ifneq ($(findstring $(BOARD), jh7110), )
SRC_DIR := riscv
endif
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/Makefile
+5
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@@ -0,0 +1,5 @@
ifneq ($(findstring $(BOARD), jh7110), )
SRC_DIR := rv64gc
endif
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/Makefile
+4
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@@ -0,0 +1,4 @@
SRC_DIR := preboot_for_$(BOARD)
SRC_FILES := context_switch.S core.c
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/context_switch.S
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@@ -0,0 +1,69 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file context_switch.S
* @brief task context switch functions
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024.4.10
*/
/*************************************************
File name: context_switch.S
Description: task context switch functions
Others:
History:
*************************************************/
/*
* Integer register context switch
* The callee-saved registers must be saved and restored.
*
* a0: previous thread_struct (must be preserved across the switch)
* a1: next thread_struct
*
*/
.global context_switch
context_switch:
sd ra, 0(a0)
sd sp, 8(a0)
sd s0, 16(a0)
sd s1, 24(a0)
sd s2, 32(a0)
sd s3, 40(a0)
sd s4, 48(a0)
sd s5, 56(a0)
sd s6, 64(a0)
sd s7, 72(a0)
sd s8, 80(a0)
sd s9, 88(a0)
sd s10, 96(a0)
sd s11, 104(a0)
ld ra, 0(a1)
ld sp, 8(a1)
ld s0, 16(a1)
ld s1, 24(a1)
ld s2, 32(a1)
ld s3, 40(a1)
ld s4, 48(a1)
ld s5, 56(a1)
ld s6, 64(a1)
ld s7, 72(a1)
ld s8, 80(a1)
ld s9, 88(a1)
ld s10, 96(a1)
ld s11, 104(a1)
mv tp, a1
ret
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.c
+74
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@@ -0,0 +1,74 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file core.c
* @brief spl boot function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024.04.23
*/
/*************************************************
File name: core.c
Description: cortex-a9 core function, include cpu registers operations、core boot
Others:
History:
1. Date: 2024-04-23
Author: AIIT XUOS Lab
Modification:
1. first version
*************************************************/
/*********cortex-a55 general register************
EL0 | EL1 | EL2 | EL3
x0;
x1;
x2;
x3;
x4;
x5;
x6;
x7;
x8;
x9;
x10;
x11;
x12;
x13;
x14;
x15;
x16;
x17;
x18;
x19;
x20;
x21;
x22;
x23;
x24;
x25;
x26;
x27;
x28;
x29;
x30;
*********cortex-a55 special register************
XZR
PC
SP_EL0 SP_EL1 SP_EL2 SP_EL3
SPSR_EL1 SPSR_EL2 SPSR_EL3
ELR_EL1 ELR_EL2 ELR_EL3
************************************************/
#include "core.h"
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h
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@@ -0,0 +1,220 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file core.h
* @brief cortex-a55 core function
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024.04.11
*/
/*************************************************
File name: core.h
Description: cortex-a55 core function
Others:
History:
Author: AIIT XUOS Lab
Modification:
*************************************************/
#pragma once
// Interrupt control bits
#define NO_INT 0x80 // disable IRQ.
#define DIS_INT 0xc0 // disable both IRQ and FIQ.
#define MODE_STACK_SIZE 0x1000
//! @name SPSR fields
//@{
#define SPSR_EL1_N (1 << 31) //!< Negative
#define SPSR_EL1_Z (1 << 30) //!< Zero
#define SPSR_EL1_C (1 << 29) //!< Carry
#define SPSR_EL1_V (1 << 28) //!< Overflow
#define SPSR_EL1_SS (1 << 21) //!< Software Step
#define SPSR_EL1_IL (1 << 20) //!< Illegal Exception
#define SPSR_EL1_D (1 << 9) //!< Debug mask
#define SPSR_EL1_A (1 << 8) //!< SError mask
#define SPSR_EL1_I (1 << 7) //!< IRQ mask
#define SPSR_EL1_F (1 << 6) //!< FIQ mask
#define SPSR_EL1_M (1 << 4) //!< Execution state 0=64-bit 1=32-bit
#define SPSR_EL1_MODE (0x7) //!< Current processor mode
//@}
//! @name Interrupt enable bits in SPSR
//@{
#define I_BIT 0x80 //!< When I bit is set, IRQ is disabled
#define F_BIT 0x40 //!< When F bit is set, FIQ is disabled
//@}
// ARM Modes t indicates selecting sp_el0 pointer, h indicates selecting sp_eln pointer
#define SPSR_MODE_MASK 0x0f
#define ARM_MODE_EL0_t 0x00
#define ARM_MODE_EL1_t 0x04
#define ARM_MODE_EL1_h 0x05
#define ARM_MODE_EL2_t 0x08
#define ARM_MODE_EL2_h 0x09
#define ARM_MODE_EL3_t 0x0c
#define ARM_MODE_EL3_h 0x0d
#ifndef __ASSEMBLER__
#include <stdint.h>
#include <string.h>
#include "cortex.h"
#include "asm/csr.h"
#define NR_CPU 1 // maximum number of CPUs
struct __riscv_d_ext_state {
uint64_t f[32];
uint32_t fcsr;
};
/* Refer to struct thread_struct in Linux */
/* CPU-specific state of a task */
struct context {
/* Callee-saved registers */
unsigned long ra;
unsigned long sp; /* Kernel mode stack */
unsigned long s[12]; /* s[0]: frame pointer */
struct __riscv_d_ext_state fstate;
unsigned long bad_cause;
};
/// @brief init task context, set return address to trap return
/// @param ctx
extern void task_prepare_enter(void);
__attribute__((__always_inline__)) static inline void arch_init_context(struct context* ctx)
{
memset(ctx, 0, sizeof(*ctx));
ctx->ra = (uintptr_t)(task_prepare_enter);
}
__attribute__((__always_inline__)) static inline void arch_context_set_sp(struct context* ctx, unsigned long sp)
{
ctx->sp = sp;
}
/* Refer to struct pt_regs in Linux */
struct trapframe {
unsigned long epc;
unsigned long ra;
unsigned long sp;
unsigned long gp;
unsigned long tp;
unsigned long t0;
unsigned long t1;
unsigned long t2;
unsigned long s0;
unsigned long s1;
unsigned long a0;
unsigned long a1;
unsigned long a2;
unsigned long a3;
unsigned long a4;
unsigned long a5;
unsigned long a6;
unsigned long a7;
unsigned long s2;
unsigned long s3;
unsigned long s4;
unsigned long s5;
unsigned long s6;
unsigned long s7;
unsigned long s8;
unsigned long s9;
unsigned long s10;
unsigned long s11;
unsigned long t3;
unsigned long t4;
unsigned long t5;
unsigned long t6;
/* Supervisor/Machine CSRs */
unsigned long status;
unsigned long badaddr;
unsigned long cause;
/* a0 value before the syscall */
unsigned long orig_a0;
};
/// @brief init task trapframe
/// @param tf
/// @param sp
/// @param pc
__attribute__((__always_inline__)) static inline void arch_init_trapframe(struct trapframe* tf, uintptr_t sp, uintptr_t pc)
{
memset(tf, 0, sizeof(*tf));
tf->sp = sp;
tf->epc = pc;
tf->status = SR_PIE;
}
/// @brief set pc and sp to trapframe
/// @param tf
/// @param sp
/// @param pc
__attribute__((__always_inline__)) static inline void arch_trapframe_set_sp_pc(struct trapframe* tf, uintptr_t sp, uintptr_t pc)
{
tf->sp = sp;
tf->epc = pc;
}
/// @brief set params of main(int argc, char** argv) to trapframe (argc, argv)
/// @param tf
/// @param argc
/// @param argv
__attribute__((__always_inline__)) static inline void arch_set_main_params(struct trapframe* tf, int argc, uintptr_t argv)
{
tf->a0 = (uint64_t)argc;
tf->a1 = (uint64_t)argv;
}
/// @brief retrieve params to trapframe (up to max number of 6) and pass it to syscall()
/// @param sys_num
/// @param param1
/// @param param2
/// @param param3
/// @param param4
/// @param param5
/// @return
extern int syscall(int sys_num, uintptr_t param1, uintptr_t param2, uintptr_t param3, uintptr_t param4);
__attribute__((__always_inline__)) static inline int arch_syscall(struct trapframe* tf, int* syscall_num)
{
// call syscall
*syscall_num = tf->a7;
return syscall(*syscall_num, tf->a0, tf->a1, tf->a2, tf->a3);
}
/// @brief set return reg to trapframe
/// @param tf
/// @param ret
__attribute__((__always_inline__)) static inline void arch_set_return(struct trapframe* tf, int ret)
{
tf->a0 = (uint64_t)ret;
}
// TODO: refer to jh7110 Linux
struct thread_info {
unsigned long flags; /* low level flags */
long preempt_count; /* 0=>preemptible, <0=>BUG */
long kernel_sp; /* Kernel stack pointer */
long user_sp; /* User stack pointer */
long cpu;
};
void cpu_start_secondary(uint8_t cpu_id);
void start_smp_cache_broadcast(int cpu_id);
#endif
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/asm-offsets.h
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#ifndef __ASM_OFFSETS_H__
#define __ASM_OFFSETS_H__
#define PT_SIZE 288 /* sizeof(struct pt_regs) */
#define PT_EPC 0 /* offsetof(struct pt_regs, epc) */
#define PT_RA 8 /* offsetof(struct pt_regs, ra) */
#define PT_FP 64 /* offsetof(struct pt_regs, s0) */
#define PT_S0 64 /* offsetof(struct pt_regs, s0) */
#define PT_S1 72 /* offsetof(struct pt_regs, s1) */
#define PT_S2 144 /* offsetof(struct pt_regs, s2) */
#define PT_S3 152 /* offsetof(struct pt_regs, s3) */
#define PT_S4 160 /* offsetof(struct pt_regs, s4) */
#define PT_S5 168 /* offsetof(struct pt_regs, s5) */
#define PT_S6 176 /* offsetof(struct pt_regs, s6) */
#define PT_S7 184 /* offsetof(struct pt_regs, s7) */
#define PT_S8 192 /* offsetof(struct pt_regs, s8) */
#define PT_S9 200 /* offsetof(struct pt_regs, s9) */
#define PT_S10 208 /* offsetof(struct pt_regs, s10) */
#define PT_S11 216 /* offsetof(struct pt_regs, s11) */
#define PT_SP 16 /* offsetof(struct pt_regs, sp) */
#define PT_TP 32 /* offsetof(struct pt_regs, tp) */
#define PT_A0 80 /* offsetof(struct pt_regs, a0) */
#define PT_A1 88 /* offsetof(struct pt_regs, a1) */
#define PT_A2 96 /* offsetof(struct pt_regs, a2) */
#define PT_A3 104 /* offsetof(struct pt_regs, a3) */
#define PT_A4 112 /* offsetof(struct pt_regs, a4) */
#define PT_A5 120 /* offsetof(struct pt_regs, a5) */
#define PT_A6 128 /* offsetof(struct pt_regs, a6) */
#define PT_A7 136 /* offsetof(struct pt_regs, a7) */
#define PT_T0 40 /* offsetof(struct pt_regs, t0) */
#define PT_T1 48 /* offsetof(struct pt_regs, t1) */
#define PT_T2 56 /* offsetof(struct pt_regs, t2) */
#define PT_T3 224 /* offsetof(struct pt_regs, t3) */
#define PT_T4 232 /* offsetof(struct pt_regs, t4) */
#define PT_T5 240 /* offsetof(struct pt_regs, t5) */
#define PT_T6 248 /* offsetof(struct pt_regs, t6) */
#define PT_GP 24 /* offsetof(struct pt_regs, gp) */
#define PT_ORIG_A0 280 /* offsetof(struct pt_regs, orig_a0) */
#define PT_STATUS 256 /* offsetof(struct pt_regs, status) */
#define PT_BADADDR 264 /* offsetof(struct pt_regs, badaddr) */
#define PT_CAUSE 272 /* offsetof(struct pt_regs, cause) */
#define PT_SIZE_ON_STACK 288 /* ALIGN(sizeof(struct pt_regs), STACK_ALIGN) */
#endif
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/asm.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2015 Regents of the University of California
*/
#ifndef _ASM_RISCV_ASM_H
#define _ASM_RISCV_ASM_H
//#define __ASSEMBLY__
#ifdef __ASSEMBLY__
#define __ASM_STR(x) x
#else
#define __ASM_STR(x) #x
#endif
#define REG_L ld
#define REG_S sd
#define REG_SC sc.d
#define REG_ASM .dword
#define SZREG 8
#define LGREG 3
#define RISCV_PTR .dword
#define RISCV_SZPTR 8
#define RISCV_LGPTR 3
#define RISCV_INT __ASM_STR(.word)
#define RISCV_SZINT __ASM_STR(4)
#define RISCV_LGINT __ASM_STR(2)
#define RISCV_SHORT __ASM_STR(.half)
#define RISCV_SZSHORT __ASM_STR(2)
#define RISCV_LGSHORT __ASM_STR(1)
#endif /* _ASM_RISCV_ASM_H */
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/const.h
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/* const.h: Macros for dealing with constants. */
#ifndef _UAPI_LINUX_CONST_H
#define _UAPI_LINUX_CONST_H
/* Some constant macros are used in both assembler and
* C code. Therefore we cannot annotate them always with
* 'UL' and other type specifiers unilaterally. We
* use the following macros to deal with this.
*
* Similarly, _AT() will cast an expression with a type in C, but
* leave it unchanged in asm.
*/
//#ifdef __ASSEMBLY__
#if 0
#define _AC(X,Y) X
#define _AT(T,X) X
#else
#define __AC(X,Y) (X##Y)
#define _AC(X,Y) __AC(X,Y)
#define _AT(T,X) ((T)(X))
#endif
#define _UL(x) (_AC(x, UL))
#define _ULL(x) (_AC(x, ULL))
#define UL(x) (_UL(x))
#define ULL(x) (_ULL(x))
#define _BITUL(x) (_UL(1) << (x))
#define _BITULL(x) (_ULL(1) << (x))
#define __ALIGN_KERNEL(x, a) __ALIGN_KERNEL_MASK(x, (typeof(x))(a) - 1)
#define __ALIGN_KERNEL_MASK(x, mask) (((x) + (mask)) & ~(mask))
#define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
#endif /* _UAPI_LINUX_CONST_H */
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/csr.h
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2015 Regents of the University of California
*/
#ifndef _ASM_RISCV_CSR_H
#define _ASM_RISCV_CSR_H
#include <asm/asm.h>
#include <asm/const.h>
#define CONFIG_64BIT 1
/* Status register flags */
#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
#define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */
#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
#define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */
#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
#define SR_MPP _AC(0x00001800, UL) /* Previously Machine */
#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
#define SR_FS_OFF _AC(0x00000000, UL)
#define SR_FS_INITIAL _AC(0x00002000, UL)
#define SR_FS_CLEAN _AC(0x00004000, UL)
#define SR_FS_DIRTY _AC(0x00006000, UL)
#define SR_XS _AC(0x00018000, UL) /* Extension Status */
#define SR_XS_OFF _AC(0x00000000, UL)
#define SR_XS_INITIAL _AC(0x00008000, UL)
#define SR_XS_CLEAN _AC(0x00010000, UL)
#define SR_XS_DIRTY _AC(0x00018000, UL)
#ifndef CONFIG_64BIT
#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */
#else
#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */
#endif
/* SATP flags */
#ifndef CONFIG_64BIT
#define SATP_PPN _AC(0x003FFFFF, UL)
#define SATP_MODE_32 _AC(0x80000000, UL)
#define SATP_MODE SATP_MODE_32
#define SATP_ASID_BITS 9
#define SATP_ASID_SHIFT 22
#define SATP_ASID_MASK _AC(0x1FF, UL)
#else
#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
#define SATP_MODE_39 _AC(0x8000000000000000, UL)
#define SATP_MODE SATP_MODE_39
#define SATP_ASID_BITS 16
#define SATP_ASID_SHIFT 44
#define SATP_ASID_MASK _AC(0xFFFF, UL)
#endif
/* Exception cause high bit - is an interrupt if set */
#define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
/* Interrupt causes (minus the high bit) */
#define IRQ_S_SOFT 1
#define IRQ_M_SOFT 3
#define IRQ_S_TIMER 5
#define IRQ_M_TIMER 7
#define IRQ_S_EXT 9
#define IRQ_M_EXT 11
#define IRQ_PMU_OVF 13
/* Exception causes */
#define EXC_INST_MISALIGNED 0
#define EXC_INST_ACCESS 1
#define EXC_BREAKPOINT 3
#define EXC_LOAD_ACCESS 5
#define EXC_STORE_ACCESS 7
#define EXC_SYSCALL 8
#define EXC_INST_PAGE_FAULT 12
#define EXC_LOAD_PAGE_FAULT 13
#define EXC_STORE_PAGE_FAULT 15
/* PMP configuration */
#define PMP_R 0x01
#define PMP_W 0x02
#define PMP_X 0x04
#define PMP_A 0x18
#define PMP_A_TOR 0x08
#define PMP_A_NA4 0x10
#define PMP_A_NAPOT 0x18
#define PMP_L 0x80
/* symbolic CSR names: */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
#define CSR_INSTRET 0xc02
#define CSR_HPMCOUNTER3 0xc03
#define CSR_HPMCOUNTER4 0xc04
#define CSR_HPMCOUNTER5 0xc05
#define CSR_HPMCOUNTER6 0xc06
#define CSR_HPMCOUNTER7 0xc07
#define CSR_HPMCOUNTER8 0xc08
#define CSR_HPMCOUNTER9 0xc09
#define CSR_HPMCOUNTER10 0xc0a
#define CSR_HPMCOUNTER11 0xc0b
#define CSR_HPMCOUNTER12 0xc0c
#define CSR_HPMCOUNTER13 0xc0d
#define CSR_HPMCOUNTER14 0xc0e
#define CSR_HPMCOUNTER15 0xc0f
#define CSR_HPMCOUNTER16 0xc10
#define CSR_HPMCOUNTER17 0xc11
#define CSR_HPMCOUNTER18 0xc12
#define CSR_HPMCOUNTER19 0xc13
#define CSR_HPMCOUNTER20 0xc14
#define CSR_HPMCOUNTER21 0xc15
#define CSR_HPMCOUNTER22 0xc16
#define CSR_HPMCOUNTER23 0xc17
#define CSR_HPMCOUNTER24 0xc18
#define CSR_HPMCOUNTER25 0xc19
#define CSR_HPMCOUNTER26 0xc1a
#define CSR_HPMCOUNTER27 0xc1b
#define CSR_HPMCOUNTER28 0xc1c
#define CSR_HPMCOUNTER29 0xc1d
#define CSR_HPMCOUNTER30 0xc1e
#define CSR_HPMCOUNTER31 0xc1f
#define CSR_CYCLEH 0xc80
#define CSR_TIMEH 0xc81
#define CSR_INSTRETH 0xc82
#define CSR_HPMCOUNTER3H 0xc83
#define CSR_HPMCOUNTER4H 0xc84
#define CSR_HPMCOUNTER5H 0xc85
#define CSR_HPMCOUNTER6H 0xc86
#define CSR_HPMCOUNTER7H 0xc87
#define CSR_HPMCOUNTER8H 0xc88
#define CSR_HPMCOUNTER9H 0xc89
#define CSR_HPMCOUNTER10H 0xc8a
#define CSR_HPMCOUNTER11H 0xc8b
#define CSR_HPMCOUNTER12H 0xc8c
#define CSR_HPMCOUNTER13H 0xc8d
#define CSR_HPMCOUNTER14H 0xc8e
#define CSR_HPMCOUNTER15H 0xc8f
#define CSR_HPMCOUNTER16H 0xc90
#define CSR_HPMCOUNTER17H 0xc91
#define CSR_HPMCOUNTER18H 0xc92
#define CSR_HPMCOUNTER19H 0xc93
#define CSR_HPMCOUNTER20H 0xc94
#define CSR_HPMCOUNTER21H 0xc95
#define CSR_HPMCOUNTER22H 0xc96
#define CSR_HPMCOUNTER23H 0xc97
#define CSR_HPMCOUNTER24H 0xc98
#define CSR_HPMCOUNTER25H 0xc99
#define CSR_HPMCOUNTER26H 0xc9a
#define CSR_HPMCOUNTER27H 0xc9b
#define CSR_HPMCOUNTER28H 0xc9c
#define CSR_HPMCOUNTER29H 0xc9d
#define CSR_HPMCOUNTER30H 0xc9e
#define CSR_HPMCOUNTER31H 0xc9f
#define CSR_SSCOUNTOVF 0xda0
#define CSR_SSTATUS 0x100
#define CSR_SIE 0x104
#define CSR_STVEC 0x105
#define CSR_SCOUNTEREN 0x106
#define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141
#define CSR_SCAUSE 0x142
#define CSR_STVAL 0x143
#define CSR_SIP 0x144
#define CSR_SATP 0x180
#define CSR_MSTATUS 0x300
#define CSR_MISA 0x301
#define CSR_MIE 0x304
#define CSR_MTVEC 0x305
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPADDR0 0x3b0
#define CSR_MVENDORID 0xf11
#define CSR_MARCHID 0xf12
#define CSR_MIMPID 0xf13
#define CSR_MHARTID 0xf14
#ifdef CONFIG_RISCV_M_MODE
# define CSR_STATUS CSR_MSTATUS
# define CSR_IE CSR_MIE
# define CSR_TVEC CSR_MTVEC
# define CSR_SCRATCH CSR_MSCRATCH
# define CSR_EPC CSR_MEPC
# define CSR_CAUSE CSR_MCAUSE
# define CSR_TVAL CSR_MTVAL
# define CSR_IP CSR_MIP
# define SR_IE SR_MIE
# define SR_PIE SR_MPIE
# define SR_PP SR_MPP
# define RV_IRQ_SOFT IRQ_M_SOFT
# define RV_IRQ_TIMER IRQ_M_TIMER
# define RV_IRQ_EXT IRQ_M_EXT
#else /* CONFIG_RISCV_M_MODE */
# define CSR_STATUS CSR_SSTATUS
# define CSR_IE CSR_SIE
# define CSR_TVEC CSR_STVEC
# define CSR_SCRATCH CSR_SSCRATCH
# define CSR_EPC CSR_SEPC
# define CSR_CAUSE CSR_SCAUSE
# define CSR_TVAL CSR_STVAL
# define CSR_IP CSR_SIP
# define SR_IE SR_SIE
# define SR_PIE SR_SPIE
# define SR_PP SR_SPP
# define RV_IRQ_SOFT IRQ_S_SOFT
# define RV_IRQ_TIMER IRQ_S_TIMER
# define RV_IRQ_EXT IRQ_S_EXT
# define RV_IRQ_PMU IRQ_PMU_OVF
# define SIP_LCOFIP (_AC(0x1, UL) << IRQ_PMU_OVF)
#endif /* !CONFIG_RISCV_M_MODE */
/* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
#define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT)
#define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER)
#define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT)
#ifndef __ASSEMBLY__
#define csr_swap(csr, val) \
({ \
unsigned long __v = (unsigned long)(val); \
__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
: "=r" (__v) : "rK" (__v) \
: "memory"); \
__v; \
})
#define csr_read(csr) \
({ \
register unsigned long __v; \
__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
: "=r" (__v) : \
: "memory"); \
__v; \
})
#define csr_write(csr, val) \
({ \
unsigned long __v = (unsigned long)(val); \
__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
: : "rK" (__v) \
: "memory"); \
})
#define csr_read_set(csr, val) \
({ \
unsigned long __v = (unsigned long)(val); \
__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
: "=r" (__v) : "rK" (__v) \
: "memory"); \
__v; \
})
#define csr_set(csr, val) \
({ \
unsigned long __v = (unsigned long)(val); \
__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \
: : "rK" (__v) \
: "memory"); \
})
#define csr_read_clear(csr, val) \
({ \
unsigned long __v = (unsigned long)(val); \
__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
: "=r" (__v) : "rK" (__v) \
: "memory"); \
__v; \
})
#define csr_clear(csr, val) \
({ \
unsigned long __v = (unsigned long)(val); \
__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \
: : "rK" (__v) \
: "memory"); \
})
#endif /* __ASSEMBLY__ */
#endif /* _ASM_RISCV_CSR_H */
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/mmio.h
+177
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h
* which was based on arch/arm/include/io.h
*
* Copyright (C) 1996-2000 Russell King
* Copyright (C) 2012 ARM Ltd.
* Copyright (C) 2014 Regents of the University of California
*/
#ifndef _ASM_RISCV_MMIO_H
#define _ASM_RISCV_MMIO_H
//#include <linux/types.h>
//#include <asm/mmiowb.h>
#include "asm/const.h"
#include <stdint.h>
#define CONFIG_64BIT 1
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
typedef uint64_t u64;
typedef uint32_t __le32;
#ifndef __iomem
#define __iomem
#endif
#ifndef asm
#define asm __asm__
#endif
#define __force
#define cpu_to_le32(x) (x)
#define le16_to_cpu(x) (x)
#define le32_to_cpu(x) (x)
#define le64_to_cpu(x) (x)
/* Generic IO read/write. These perform native-endian accesses. */
#define __raw_writeb __raw_writeb
static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
{
asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr));
}
#define __raw_writew __raw_writew
static inline void __raw_writew(u16 val, volatile void __iomem *addr)
{
asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr));
}
#define __raw_writel __raw_writel
static inline void __raw_writel(u32 val, volatile void __iomem *addr)
{
asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr));
}
#ifdef CONFIG_64BIT
#define __raw_writeq __raw_writeq
static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
{
asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr));
}
#endif
#define __raw_readb __raw_readb
static inline u8 __raw_readb(const volatile void __iomem *addr)
{
u8 val;
asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr));
return val;
}
#define __raw_readw __raw_readw
static inline u16 __raw_readw(const volatile void __iomem *addr)
{
u16 val;
asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr));
return val;
}
#define __raw_readl __raw_readl
static inline u32 __raw_readl(const volatile void __iomem *addr)
{
u32 val;
asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr));
return val;
}
#ifdef CONFIG_64BIT
#define __raw_readq __raw_readq
static inline u64 __raw_readq(const volatile void __iomem *addr)
{
u64 val;
asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr));
return val;
}
#endif
/*
* Unordered I/O memory access primitives. These are even more relaxed than
* the relaxed versions, as they don't even order accesses between successive
* operations to the I/O regions.
*/
#define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; })
#define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
#define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
#define writeb_cpu(v, c) ((void)__raw_writeb((v), (c)))
#define writew_cpu(v, c) ((void)__raw_writew((__force u16)cpu_to_le16(v), (c)))
#define writel_cpu(v, c) ((void)__raw_writel((__force u32)cpu_to_le32(v), (c)))
#ifdef CONFIG_64BIT
#define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
#define writeq_cpu(v, c) ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c)))
#endif
/*
* Relaxed I/O memory access primitives. These follow the Device memory
* ordering rules but do not guarantee any ordering relative to Normal memory
* accesses. These are defined to order the indicated access (either a read or
* write) with all other I/O memory accesses. Since the platform specification
* defines that all I/O regions are strongly ordered on channel 2, no explicit
* fences are required to enforce this ordering.
*/
/* FIXME: These are now the same as asm-generic */
#define __io_rbr() do {} while (0)
#define __io_rar() do {} while (0)
#define __io_rbw() do {} while (0)
#define __io_raw() do {} while (0)
#define readb_relaxed(c) ({ u8 __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; })
#define readw_relaxed(c) ({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; })
#define readl_relaxed(c) ({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; })
#define writeb_relaxed(v, c) ({ __io_rbw(); writeb_cpu((v), (c)); __io_raw(); })
#define writew_relaxed(v, c) ({ __io_rbw(); writew_cpu((v), (c)); __io_raw(); })
#define writel_relaxed(v, c) ({ __io_rbw(); writel_cpu((v), (c)); __io_raw(); })
#ifdef CONFIG_64BIT
#define readq_relaxed(c) ({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; })
#define writeq_relaxed(v, c) ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); })
#endif
/*
* I/O memory access primitives. Reads are ordered relative to any
* following Normal memory access. Writes are ordered relative to any prior
* Normal memory access. The memory barriers here are necessary as RISC-V
* doesn't define any ordering between the memory space and the I/O space.
*/
#define __io_br() do {} while (0)
#define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory")
#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory")
//#define __io_aw() mmiowb_set_pending()
#define __io_aw() do {} while (0)
#define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; })
#define readw(c) ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; })
#define readl(c) ({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(__v); __v; })
#define writeb(v, c) ({ __io_bw(); writeb_cpu((v), (c)); __io_aw(); })
#define writew(v, c) ({ __io_bw(); writew_cpu((v), (c)); __io_aw(); })
#define writel(v, c) ({ __io_bw(); writel_cpu((v), (c)); __io_aw(); })
#ifdef CONFIG_64BIT
#define readq(c) ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(__v); __v; })
#define writeq(v, c) ({ __io_bw(); writeq_cpu((v), (c)); __io_aw(); })
#endif
#endif /* _ASM_RISCV_MMIO_H */
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable-bits.h
+52
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2012 Regents of the University of California
*/
#ifndef _ASM_RISCV_PGTABLE_BITS_H
#define _ASM_RISCV_PGTABLE_BITS_H
#include <asm/const.h>
#define BIT(nr) (UL(1) << (nr))
/*
* PTE format:
* | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
* PFN reserved for SW D A G U X W R V
*/
#define _PAGE_ACCESSED_OFFSET 6
#define _PAGE_PRESENT (1 << 0)
#define _PAGE_READ (1 << 1) /* Readable */
#define _PAGE_WRITE (1 << 2) /* Writable */
#define _PAGE_EXEC (1 << 3) /* Executable */
#define _PAGE_USER (1 << 4) /* User */
#define _PAGE_GLOBAL (1 << 5) /* Global */
#define _PAGE_ACCESSED (1 << 6) /* Set by hardware on any access */
#define _PAGE_DIRTY (1 << 7) /* Set by hardware on any write */
#define _PAGE_SOFT (1 << 8) /* Reserved for software */
#define _PAGE_SPECIAL _PAGE_SOFT
#define _PAGE_TABLE _PAGE_PRESENT
/*
* _PAGE_PROT_NONE is set on not-present pages (and ignored by the hardware) to
* distinguish them from swapped out pages
*/
#define _PAGE_PROT_NONE _PAGE_READ
#define _PAGE_PFN_SHIFT 10
/* Set of bits to preserve across pte_modify() */
#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
_PAGE_WRITE | _PAGE_EXEC | \
_PAGE_USER | _PAGE_GLOBAL))
/*
* when all of R/W/X are zero, the PTE is a pointer to the next level
* of the page table; otherwise, it is a leaf PTE.
*/
#define _PAGE_LEAF (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)
#endif /* _ASM_RISCV_PGTABLE_BITS_H */
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/Makefile
+6
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SRC_FILES := boot.S \
xizi_smp.S \
smp.c \
cortex.S
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S
+120
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@@ -0,0 +1,120 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#include <asm/csr.h>
#include "memlayout.h"
.section ".text", "ax"
.globl _boot_start
_boot_start:
mv s0, a0
call _debug_uart_init_early
la a0, debug_string_start
call _debug_uart_printascii
mv a0, s0
j _start_kernel
_start_kernel:
/* Mask all interrupts */
csrw CSR_IE, zero
csrw CSR_IP, zero
/* Clear BSS for flat non-ELF images */
la a3, __bss_start
la a4, __bss_stop
ble a4, a3, clear_bss_done
clear_bss:
sd zero, (a3)
add a3, a3, RISCV_SZPTR
blt a3, a4, clear_bss
clear_bss_done:
li a0, 1
la a2, boot_cpu_hartid
sd a0, (a2)
la sp, stacks_top
/* Initialize page tables and relocate to virtual addresses */
call setup_vm_early
la a0, early_pg_dir
call relocate_enable_mmu
la sp, stacks_top
call _debug_uart_init
/* Restore C environment */
la tp, init_thread_info
sw zero, 32(tp)
/* Start the kernel */
tail main
relocate_enable_mmu:
/* Relocate return address */
la a1, kernel_map
ld a1, 0(a1)
la a2, _start
sub a1, a1, a2
add ra, ra, a1
/* Point stvec to virtual address of intruction after satp write */
la a2, 1f
add a2, a2, a1
csrw CSR_TVEC, a2
/* Compute satp for kernel page tables, but don't load it yet */
srl a2, a0, PAGE_SHIFT
li a1, SATP_MODE
or a2, a2, a1
/*
* Load trampoline page directory, which will cause us to trap to
* stvec if VA != PA, or simply fall through if VA == PA. We need a
* full fence here because setup_vm() just wrote these PTEs and we need
* to ensure the new translations are in use.
*/
la a0, trampoline_pg_dir
srl a0, a0, PAGE_SHIFT
or a0, a0, a1
sfence.vma
csrw CSR_SATP, a0
1:
/* Set trap vector to spin forever to help debug */
la a0, .Lsecondary_park
csrw CSR_TVEC, a0
/*
* Switch to kernel page tables. A full fence is necessary in order to
* avoid using the trampoline translations, which are only correct for
* the first superpage. Fetching the fence is guarnteed to work
* because that first superpage is translated the same way.
*/
csrw CSR_SATP, a2
sfence.vma
ret
.Lsecondary_park:
/* We lack SMP support or have too many harts, so park this hart */
wfi
j .Lsecondary_park
debug_string_start: .ascii "XiZi jh7110 boot start\n\0"
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk
+13
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export CROSS_COMPILE ?= riscv64-unknown-elf-
export ARCH = riscv
export KBUILD_CFLAGS := -Wall -Wundef -Wno-trigraphs -fno-strict-aliasing -fno-common -fshort-wchar -fno-PIE -Werror=implicit-function-declaration -Werror=implicit-int -Werror=return-type -Wno-format-security -std=gnu89 -Wno-sign-compare -fno-asynchronous-unwind-tables -fno-delete-null-pointer-checks -fno-stack-protector -Wno-main -fomit-frame-pointer -Wvla -Wno-pointer-sign -Wno-array-bounds -fno-strict-overflow -fno-stack-check -Werror=date-time
export KBUILD_AFLAGS :=
export CHECKFLAGS += -D__riscv -D__riscv_xlen=64
export DEVICE :=
export CFLAGS := $(KBUILD_CFLAGS) $(KBUILD_AFLAGS) $(CHECKFLAGS) -std=c11 -mcmodel=medany
export LFLAGS := -T $(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds
export CXXFLAGS :=
export DEFINES :=
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/cortex.S
+36
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/*!
* @file cortex.s
* @brief This file contains cortexA55 functions
*
*/
/*************************************************
File name: cortex.S
Description: This file contains cortexA9 functions
Others:
History:
1. Date: 2024-05-08
Author: AIIT XUOS Lab
Modification:
1. No modifications
*************************************************/
.section ".text","ax"
.global cpu_get_current
# int cpu_get_current(void)@
# get current CPU ID
.func cpu_get_current
cpu_get_current:
li a0, 0
ret
.endfunc
.global psci_call
psci_call:
ret
# ------------------------------------------------------------
# End of cortexA55.s
# ------------------------------------------------------------
.end
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/cortex.h
+241
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/*
* Copyright (c) 2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file cortex.h
* @brief some cortex A55 core functions
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024.04.24
*/
/*************************************************
File name: cortex.h
Description: some cortex A55 core functions
Others:
History:
Author: AIIT XUOS Lab
Modification:
1. No modifications
*************************************************/
#if !defined(__CORTEX_A55_H__)
#define __CORTEX_A55_H__
#include <stdbool.h>
#include <stdint.h>
#include <stdlib.h>
//! @name Instruction macros
//@{
//#define NOP() __asm__ volatile("nop\n\t")
//#define WFI() __asm__ volatile("wfi\n\t")
//#define WFE() __asm__ volatile("wfe\n\t")
//#define SEV() __asm__ volatile("sev\n\t")
//#define DMB() __asm__ volatile("dmb ish\n\t")
//#define DSB() __asm__ volatile("dsb ish\n\t")
//#define ISB() __asm__ volatile("isb\n\t")
#define NOP() __asm__ volatile("nop\n\t")
#define WFI() __asm__ volatile("nop\n\t")
#define WFE() __asm__ volatile("nop\n\t")
#define SEV() __asm__ volatile("nop\n\t")
#define DMB() __asm__ volatile("nop\n\t")
#define DSB() __asm__ volatile("nop\n\t")
#define ISB() __asm__ volatile("nop\n\t")
#define _ARM_MRS(coproc, opcode1, Rt, CRn, CRm, opcode2) \
__asm__ volatile("mrc p" #coproc ", " #opcode1 ", %[output], c" #CRn ", c" #CRm ", " #opcode2 "\n" : [output] "=r"(Rt))
#define _ARM_MSR(coproc, opcode1, Rt, CRn, CRm, opcode2) \
__asm__ volatile("mcr p" #coproc ", " #opcode1 ", %[input], c" #CRn ", c" #CRm ", " #opcode2 "\n" ::[input] "r"(Rt))
// #define WriteReg(value, address) (*(volatile unsigned int*)(address) = (value))
// #define ReadReg(address) (*(volatile unsigned int*)(address))
#if defined(__cplusplus)
extern "C" {
#endif
//! @name Misc
//@{
//! @brief Enable or disable the IRQ and FIQ state.
bool arm_set_interrupt_state(bool enable);
//! @brief Get current CPU ID.
int cpu_get_current(void);
//! @brief Enable the NEON MPE.
void enable_neon_fpu(void);
//! @brief Disable aborts on unaligned accesses.
void disable_strict_align_check(void);
//! @brief Get base address of private perpherial space.
//!
//! @return The address of the ARM CPU's private peripherals.
// uint32_t get_arm_private_peripheral_base(void);
//@}
//! @name Data cache operations
//@{
//! @brief Check if dcache is enabled or disabled.
int arm_dcache_state_query();
//! @brief Enables data cache at any available cache level.
//!
//! Works only if MMU is enabled!
void arm_dcache_enable();
//! @brief Disables the data cache at any available cache level.
void arm_dcache_disable();
//! @brief Invalidates the entire data cache.
void arm_dcache_invalidate();
//! @brief Invalidate a line of data cache.
void arm_dcache_invalidate_line(const void* addr);
//! @brief Invalidate a number of lines of data cache.
//!
//! Number of lines depends on length parameter and size of line.
//! Size of line for A9 L1 cache is 32B.
void arm_dcache_invalidate_mlines(const void* addr, size_t length);
//! @brief Flush (clean) all lines of cache (all sets in all ways).
void arm_dcache_flush();
//! @brief Flush (clean) one line of cache.
void arm_dcache_flush_line(const void* addr);
// @brief Flush (clean) multiple lines of cache.
//!
//! Number of lines depends on length parameter and size of line.
void arm_dcache_flush_mlines(const void* addr, size_t length);
//@}
//! @name Instrution cache operations
//@{
//! @brief Check if icache is enabled or disabled.
int arm_icache_state_query();
//! @brief Enables instruction cache at any available cache level.
//!
//! Works without enabled MMU too!
void arm_icache_enable();
//! @brief Disables the instruction cache at any available cache level.
void arm_icache_disable();
//! @brief Invalidates the entire instruction cache.
void arm_icache_invalidate();
//! @brief Invalidates the entire instruction cache inner shareable.
void arm_icache_invalidate_is();
//! @brief Invalidate a line of the instruction cache.
void arm_icache_invalidate_line(const void* addr);
//! @brief Invalidate a number of lines of instruction cache.
//!
//! Number of lines depends on length parameter and size of line.
void arm_icache_invalidate_mlines(const void* addr, size_t length);
//@}
//! @name TLB operations
//@{
//! @brief Invalidate entire unified TLB.
void arm_unified_tlb_invalidate(void);
//! @brief Invalidate entire unified TLB Inner Shareable.
void arm_unified_tlb_invalidate_is(void);
//@}
//! @name Branch predictor operations
//@{
//! @brief Enable branch prediction.
void arm_branch_prediction_enable(void);
//! @brief Disable branch prediction.
void arm_branch_prediction_disable(void);
//! @brief Invalidate entire branch predictor array.
void arm_branch_target_cache_invalidate(void);
//! @brief Invalidate entire branch predictor array Inner Shareable
void arm_branch_target_cache_invalidate_is(void);
//@}
//! @name SCU
//@{
//! @brief Enables the SCU.
void scu_enable(void);
//! @brief Set this CPU as participating in SMP.
void scu_join_smp(void);
//! @brief Set this CPU as not participating in SMP.
void scu_leave_smp(void);
//! @brief Determine which CPUs are participating in SMP.
//!
//! The return value is 1 bit per core:
//! - bit 0 - CPU 0
//! - bit 1 - CPU 1
//! - etc...
unsigned int scu_get_cpus_in_smp(void);
//! @brief Enable the broadcasting of cache & TLB maintenance operations.
//!
//! When enabled AND in SMP, broadcast all "inner sharable"
//! cache and TLM maintenance operations to other SMP cores
void scu_enable_maintenance_broadcast(void);
//! @brief Disable the broadcasting of cache & TLB maintenance operations.
void scu_disable_maintenance_broadcast(void);
//! @brief Invalidates the SCU copy of the tag rams for the specified core.
//!
//! Typically only done at start-up.
//! Possible flow:
//! - Invalidate L1 caches
//! - Invalidate SCU copy of TAG RAMs
//! - Join SMP
//!
//! @param cpu 0x0=CPU 0, 0x1=CPU 1, etc...
//! @param ways The ways to invalidate. Pass 0xf to invalidate all ways.
void scu_secure_invalidate(unsigned int cpu, unsigned int ways);
//@}
#if defined(__cplusplus)
}
#endif
#endif //__CORTEX_A55_H__
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds
+135
View File
@@ -0,0 +1,135 @@
/*
* Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file jh7110.lds
* @brief
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024.10.10
*/
OUTPUT_ARCH(riscv)
OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv")
ENTRY( _boot_start )
MEMORY {
vir_ddr3 (rwx) : ORIGIN = (0 - 0x80000000), LENGTH = 1024M
phy_ddr3 (rwx) : ORIGIN = 0x40200000, LENGTH = 1024M
}
BOOT_STACK_SIZE = 0x4000;
SECTIONS
{
. = ORIGIN(vir_ddr3);
_start = .;
_boot_start = .;
.start_sec : {
_start_image_addr = .;
boot.o(.text)
ns16550.o(.text .text.*)
mmu_init.o(.text .text.*)
boot.o(.rodata .rodata.*)
ns16550.o(.rodata .rodata.*)
mmu_init.o(.rodata .rodata.*)
boot.o(.data .data.*)
ns16550.o(.data .data.*)
mmu_init.o(.data .data.*)
PROVIDE(boot_start_addr = .);
boot.o(.bss .bss.* COMMON)
ns16550.o(.bss .bss.* COMMON)
mmu_init.o(.bss .bss.* COMMON)
. = ALIGN(0x1000);
PROVIDE(stacks_start = .);
. += BOOT_STACK_SIZE;
PROVIDE(stacks_end = .);
PROVIDE(stacks_top = .);
PROVIDE(boot_end_addr = .);
}
.text : {
. = ALIGN(0x1000);
*(.text .text.*)
}
.data : {
. = ALIGN(0x1000);
*(.data .data.*)
. = ALIGN(0x1000);
PROVIDE(_binary_fs_img_start = .);
*(.rawdata_fs_img*)
PROVIDE(_binary_fs_img_end = .);
. = ALIGN(0x1000);
PROVIDE(_binary_init_start = .);
*(.rawdata_init*)
PROVIDE(_binary_init_end = .);
. = ALIGN(0x1000);
PROVIDE(_binary_default_fs_start = .);
*(.rawdata_memfs*)
PROVIDE(_binary_default_fs_end = .);
PROVIDE(__init_array_start = .);
PROVIDE(__init_array_end = .);
}
.sdata : {
. = ALIGN(0x1000);
__global_pointer$ = . + 0x800;
*(.sdata*)
}
.bss : {
. = ALIGN(0x1000);
PROVIDE(kernel_data_begin = .);
PROVIDE(__bss_start = .);
*(.bss .bss.* COMMON)
. = ALIGN(0x1000);
PROVIDE(__bss_end = .);
PROVIDE(kernel_data_end = .);
__bss_stop = .;
}
. = ALIGN(0x1000);
_image_size = . - _start;
. = ALIGN((1 << 21));
_edata = .;
_end = .;
}
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/smp.c
+86
View File
@@ -0,0 +1,86 @@
/*
* Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @file smp.c
* @brief start multicore
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024.04.10
*/
/*************************************************
File name: smp.c
Description:
Others:
History:
Author: AIIT XUOS Lab
Modification:
1. No modifications
*************************************************/
#include <stdint.h>
unsigned long boot_cpu_hartid;
#define PSCI_CPUON 0xc4000003
struct xizi_smccc_res {
unsigned long a0;
unsigned long a1;
unsigned long a2;
unsigned long a3;
};
extern void _boot_start();
extern void __print();
extern void __xizi_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2,
unsigned long a3, unsigned long a4, unsigned long a5,
unsigned long a6, unsigned long a7, struct xizi_smccc_res* res);
static struct xizi_smccc_res __invoke_sip_fn_smc(unsigned long function_id,
unsigned long arg0,
unsigned long arg1,
unsigned long arg2)
{
struct xizi_smccc_res res;
__xizi_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res);
return res;
}
void cpu_start_secondary(uint8_t cpu_id)
{
__invoke_sip_fn_smc(PSCI_CPUON, cpu_id, (uintptr_t)0xa00000, 0);
}
void start_smp_cache_broadcast(int cpu_id)
{
return;
}
Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/xizi_smp.S
+17
View File
@@ -0,0 +1,17 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
.global __xizi_smccc_smc
.func __xizi_smccc_smc
__xizi_smccc_smc:
1: ret
.endfunc
Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/Makefile
Vendored
+5
View File
@@ -1,3 +1,8 @@
ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), )
SRC_DIR := arm
endif
ifneq ($(findstring $(BOARD), jh7110), )
SRC_DIR := riscv
endif
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/Makefile
Vendored
+5
View File
@@ -0,0 +1,5 @@
ifneq ($(findstring $(BOARD), jh7110), )
SRC_DIR := rv64gc
endif
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/Makefile
Vendored
+3
View File
@@ -0,0 +1,3 @@
SRC_FILES := l1_cache.c cache.S
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/cache.S
Vendored
+184
View File
@@ -0,0 +1,184 @@
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* This file is based on sample code from ARMv8 ARM.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#define ASM_NL ;
#define SYMBOL_NAME(X) X
// #define SYMBOL_NAME_LABEL(X) X##:
#define SYMBOL_NAME_LABEL(X) X:
#ifndef __ALIGN
#define __ALIGN .align 4
#endif
#ifndef __ALIGN_STR
#define __ALIGN_STR ".align 4"
#endif
#define ALIGN __ALIGN
#define ALIGN_STR __ALIGN_STR
#define LENTRY(name) \
ALIGN ASM_NL \
SYMBOL_NAME_LABEL(name)
#define ENTRY(name) \
.globl SYMBOL_NAME(name) ASM_NL \
LENTRY(name)
#define WEAK(name) \
.weak SYMBOL_NAME(name) ASM_NL \
LENTRY(name)
#define END(name) \
.size name, .-name
#define ENDPROC(name) \
.type name STT_FUNC ASM_NL \
END(name)
#define CR_M (1 << 0) /* MMU enable */
#define CR_A (1 << 1) /* Alignment abort enable */
#define CR_C (1 << 2) /* Dcache enable */
#define CR_SA (1 << 3) /* Stack Alignment Check Enable */
#define CR_I (1 << 12) /* Icache enable */
#define CR_WXN (1 << 19) /* Write Permision Imply XN */
#define CR_EE (1 << 25) /* Exception (Big) Endian */
.macro switch_el, xreg, el3_label, el2_label, el1_label
nop
.endm
/*
* void __asm_dcache_level(level)
* flush or invalidate one level cache.
*
* x0: cache level
* x1: 0 clean & invalidate, 1 invalidate only
* x2~x9: clobbered
*/
ENTRY(__asm_dcache_level)
nop
loop_set:
nop
loop_way:
nop
ret
ENDPROC(__asm_dcache_level)
/*
* void __asm_flush_dcache_all(int invalidate_only)
*
* x0: 0 clean & invalidate, 1 invalidate only
*
* flush or invalidate all data cache by SET/WAY.
*/
ENTRY(__asm_dcache_all)
nop
ret
ENDPROC(__asm_dcache_all)
ENTRY(__asm_flush_dcache_all)
j __asm_dcache_all
ENDPROC(__asm_flush_dcache_all)
ENTRY(__asm_invalidate_dcache_all)
j __asm_dcache_all
ENDPROC(__asm_invalidate_dcache_all)
/*
* void __asm_flush_dcache_range(start, end)
*
* clean & invalidate data cache in the range
*
* x0: start address
* x1: end address
*/
ENTRY(__asm_flush_dcache_range)
nop
ret
ENDPROC(__asm_flush_dcache_range)
/*
* void __asm_invalidate_dcache_range(start, end)
*
* invalidate data cache in the range
*
* x0: start address
* x1: end address
*/
ENTRY(__asm_invalidate_dcache_range)
nop
ret
ENDPROC(__asm_invalidate_dcache_range)
/*
* void __asm_invalidate_icache_all(void)
*
* invalidate all tlb entries.
*/
ENTRY(__asm_invalidate_icache_all)
nop
ret
ENDPROC(__asm_invalidate_icache_all)
ENTRY(__asm_invalidate_l3_dcache)
nop
ret
ENDPROC(__asm_invalidate_l3_dcache)
.weak __asm_invalidate_l3_dcache
ENTRY(__asm_flush_l3_dcache)
nop
ret
ENDPROC(__asm_flush_l3_dcache)
.weak __asm_flush_l3_dcache
ENTRY(__asm_invalidate_l3_icache)
nop
ret
ENDPROC(__asm_invalidate_l3_icache)
.weak __asm_invalidate_l3_icache
/*
* void __asm_switch_ttbr(ulong new_ttbr)
*
* Safely switches to a new page table.
*/
ENTRY(__asm_switch_ttbr)
nop
ret
ENDPROC(__asm_switch_ttbr)
ENTRY(__asm_invalidate_tlb_all)
ret
ENDPROC(__asm_invalidate_tlb_all)
Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/l1_cache.c
Vendored
+81
View File
@@ -0,0 +1,81 @@
/**
* @file: l1_cache.c
* @brief: the general management of L1 cache
* @version: 1.0
* @author: AIIT XUOS Lab
* @date: 2024/04/23
*
*/
/*************************************************
File name: l1_cache.c
Description: the general management of L1 cache
Others:
History:
Author: AIIT XUOS Lab
Modification:
1. implement the l1 cache operations
2. function names are modified to apply softkernel developement
3. function implementations are from modifications of imx6 SDK package
*************************************************/
#include "l1_cache.h"
extern void __asm_flush_dcache_all();
extern void __asm_flush_l3_dcache();
extern void __asm_invalidate_icache_all();
extern void __asm_invalidate_l3_icache();
void InvalidateL1Dcache(uintptr_t start, uintptr_t end)
{
}
void InvalidateL1DcacheAll(void)
{
}
void CleanL1Dcache(uintptr_t start, uintptr_t end)
{
}
void CleanL1DcacheAll(void)
{
}
void FlushL1Dcache(uintptr_t start, uintptr_t end)
{
}
void FlushL1DcacheAll(void)
{
}
void InvalidateL1IcacheAll()
{
}
void InvalidateL1Icache(uintptr_t start, uintptr_t end)
{
}
void EnableL1Dcache()
{
}
void DisableL1Dcache()
{
}
void EnableL1Icache()
{
}
void DisableL1Icache()
{
}
Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/l1_cache.h
Vendored
+76
View File
@@ -0,0 +1,76 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file: l1_cache.h
* @brief: the general management of L1 cache
* @version: 1.0
* @author: AIIT XUOS Lab
* @date: 2024/4/23
*
*/
/*************************************************
File name: l1_cache.h
Description: the general management of L1 cache
Others:
History:
Author: AIIT XUOS Lab
Modification:
1、define the l1 cache operations
*************************************************/
#include "core.h"
#include <stdint.h>
/*
* L1 Cache Operation:
*
* IVAC -Invalidate by Virtual Address, to Point of Coherency AArch32Equivalent :DCIMVAC
*
* ISW -Invalidate by Set/Way AArch32Equivalent :DCISW
*
*CVAC -Clean by Virtual Address to Point of Coherency AArch32Equivalent :DCCMVAC
*
*CSW -Clean by Set/Way AArch32Equivalent :DCCSW
*
*CVAU -Clean by Virtual Address to Point of Unification AArch32Equivalent :DCCMVAU
*
*CIVAC -Clean and invalidate data cache line by VA to PoC. AArch32Equivalent :DCCIMVAC
*
*ISW -Clean and invalidate data cache line by Set/Way. AArch32Equivalent :DCCISW
*/
#define SCTLR_EL1_ICACHE_ENABLE (1 << 12) //!< Instruction cache enable
#define SCTLR_EL1_DCACHE_ENABLE (1 << 2) //!< Data cache enable
void InvalidateL1Dcache(uintptr_t start, uintptr_t end);
void InvalidateL1DcacheAll(void);
void CleanL1Dcache(uintptr_t start, uintptr_t end);
void CleanL1DcacheAll(void);
void FlushL1Dcache(uintptr_t start, uintptr_t end);
void FlushL1DcacheAll(void);
void InvalidateL1IcacheAll(void);
void InvalidateL1Icache(uintptr_t start, uintptr_t end);
void EnableL1Icache(void);
void DisableL1Icache();
void EnableL1Dcache();
void DisableL1Dcache();
Ubiquitous/XiZi_AIoT/hardkernel/clock/Makefile
+6 -1
View File
@@ -1,3 +1,8 @@
SRC_DIR:= arm
ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), )
SRC_DIR := arm
endif
ifneq ($(findstring $(BOARD), jh7110), )
SRC_DIR := riscv
endif
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/Makefile
+5
View File
@@ -0,0 +1,5 @@
ifneq ($(findstring $(BOARD), jh7110), )
SRC_DIR := rv64gc
endif
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/Makefile
+4
View File
@@ -0,0 +1,4 @@
SRC_DIR := $(BOARD)
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/Makefile
+4
View File
@@ -0,0 +1,4 @@
SRC_FILES := clock.c timer-clint.c
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clint.h
+8
View File
@@ -0,0 +1,8 @@
#ifndef _ASM_RISCV_CLINT_H
#define _ASM_RISCV_CLINT_H
#include <asm/mmio.h>
int clint_timer_init(void);
#endif
Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clock.c
+84
View File
@@ -0,0 +1,84 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
#include "actracer.h"
#include "core.h"
#include "clock_common_op.h"
#include "clint.h"
//TODO:
static void enable_timer()
{
;
}
static void disable_timer()
{
;
}
static void reload_timer()
{
// interval 1ms
;
}
void _sys_clock_init()
{
clint_timer_init();
disable_timer();
reload_timer();
enable_timer();
}
static uint32_t _get_clock_int()
{
return 30;
}
static uint64_t _get_tick()
{
return 0;
}
static uint64_t _get_second()
{
return 0;
}
static bool _is_timer_expired()
{
return true;
}
static void _clear_clock_intr()
{
disable_timer();
reload_timer();
enable_timer();
}
static struct XiziClockDriver hardkernel_clock_driver = {
.sys_clock_init = _sys_clock_init,
.get_clock_int = _get_clock_int,
.get_tick = _get_tick,
.get_second = _get_second,
.is_timer_expired = _is_timer_expired,
.clear_clock_intr = _clear_clock_intr,
};
struct XiziClockDriver* hardkernel_clock_init(struct TraceTag* hardkernel_tag)
{
hardkernel_clock_driver.sys_clock_init();
return &hardkernel_clock_driver;
}
Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/timer-clint.c
+9
View File
@@ -0,0 +1,9 @@
#include "clint.h"
// Refer to linux/drivers/clocksource/timer-clint.c
// TODO:
int clint_timer_init(void)
{
return 0;
}
Ubiquitous/XiZi_AIoT/hardkernel/intr/Makefile
+6
View File
@@ -1,4 +1,10 @@
ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), )
SRC_DIR := arm
endif
ifneq ($(findstring $(BOARD), jh7110), )
SRC_DIR := riscv
endif
SRC_FILES := spinlock.c
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/Makefile
+5
View File
@@ -0,0 +1,5 @@
ifneq ($(findstring $(BOARD), jh7110), )
SRC_DIR := rv64gc
endif
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile
+4
View File
@@ -0,0 +1,4 @@
SRC_FILES := trampoline.S $(BOARD)/trap_common.c $(BOARD)/trap.c $(BOARD)/plic.c error_debug.c hard_spinlock.S
SRC_FILES += $(BOARD)/
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/error_debug.c
+65
View File
@@ -0,0 +1,65 @@
/* Copyright (c) 2006-2018 Frans Kaashoek, Robert Morris, Russ Cox,
* Massachusetts Institute of Technology
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/**
* @file error_debug.c
* @brief handle program abort
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024.4.25
*/
/*************************************************
File name: error_debug.c
Description: handle program abort
Others:
History:
Author: AIIT XUOS Lab
Modification:
1. Take only armv8 abort reason part(_abort_reason).
2. Modify iabort and dabort handler(in dabort_handler() and iabort_handler())
*************************************************/
#include <stddef.h>
#include <stdint.h>
#include "assert.h"
#include "core.h"
#include "log.h"
#include "multicores.h"
#include "task.h"
#include "trap_common.h"
void dump_tf(struct trapframe* tf)
{
}
void dabort_reason(struct trapframe* r)
{
return;
}
void iabort_reason(struct trapframe* r)
{
return;
}
Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S
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/*
* Copyright (c) 2013, Freescale Semiconductor, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Portions Copyright (c) 2011-2012 ARM Ltd. All rights reserved.
*/
/**
* @file hard_spinlock.S
* @brief spinlock implementation
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024.04.11
*/
/*************************************************
File name: hard_spinlock.S
Description: spinlock implementation
Others:
History:
Author: AIIT XUOS Lab
Modification:
*************************************************/
// .arch armv8-a
.section ".text","ax"
.global cpu_get_current
#define UNLOCKED 0xFF
// int spinlock_lock(spinlock_t * lock, uint64_t timeout)
.global _spinlock_lock
.func _spinlock_lock
_spinlock_lock:
mv s0, a0
li a0, 0 # cpu_get_current
mv a1, a0
mv a0, s0
li a2, UNLOCKED
1:
lr.w a3, (a0)
bne a3, a2, 1b
sc.w a4, a1, (a0)
bnez a4, 1b
ret
.endfunc
// void spinlock_unlock(spinlock_t * lock)
.global _spinlock_unlock
.func _spinlock_unlock
_spinlock_unlock:
mv s0, a0
li a0, 0 # cpu_get_current
mv a1, a0
mv a0, s0
li a2, UNLOCKED
lw a3, (a0)
bne a3, a1, 1f
sw a2, (a0)
li a0, 0
ret
1:
li a0, -1
ret
.endfunc
.end
Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/irq_numbers.h
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/**
* @file irq_numbers.c
* @brief irq numbers
* @version 3.0
* @author AIIT XUOS Lab
* @date 2023.08.25
*/
/*************************************************
File name: irq_numbers.c
Description: irq numbers
Others:
History:
1. Date: 2023-08-28
Author: AIIT XUOS Lab
Modification:
1. Add HW_NR_IRQS
*************************************************/
#if !defined(__IRQ_NUMBERS_H__)
#define __IRQ_NUMBERS_H__
#define HW_NR_IRQS NR_OK1028_INTRS
////////////////////////////////////////////////////////////////////////////////
// Definitions
////////////////////////////////////////////////////////////////////////////////
//! @brief i.MX6 interrupt numbers.
//!
//! This enumeration lists the numbers for all of the interrupts available on the i.MX6 series.
//! Use these numbers when specifying an interrupt to the GIC.
//!
//! The first 16 interrupts are special in that they are reserved for software interrupts generated
//! by the SWI instruction.
enum _ls_interrupts {
SW_INTERRUPT_0 = 0, //!< Software interrupt 0.
SW_INTERRUPT_1 = 1, //!< Software interrupt 1.
SW_INTERRUPT_2 = 2, //!< Software interrupt 2.
SW_INTERRUPT_3 = 3, //!< Software interrupt 3.
SW_INTERRUPT_4 = 4, //!< Software interrupt 4.
SW_INTERRUPT_5 = 5, //!< Software interrupt 5.
SW_INTERRUPT_6 = 6, //!< Software interrupt 6.
SW_INTERRUPT_7 = 7, //!< Software interrupt 7.
SW_INTERRUPT_8 = 8, //!< Software interrupt 8.
SW_INTERRUPT_9 = 9, //!< Software interrupt 9.
SW_INTERRUPT_10 = 10, //!< Software interrupt 10.
SW_INTERRUPT_11 = 11, //!< Software interrupt 11.
SW_INTERRUPT_12 = 12, //!< Software interrupt 12.
SW_INTERRUPT_13 = 13, //!< Software interrupt 13.
SW_INTERRUPT_14 = 14, //!< Software interrupt 14.
SW_INTERRUPT_15 = 15, //!< Software interrupt 15.
RSVD_INTERRUPT_16 = 16, //!< Reserved.
RSVD_INTERRUPT_17 = 17, //!< Reserved.
RSVD_INTERRUPT_18 = 18, //!< Reserved.
RSVD_INTERRUPT_19 = 19, //!< Reserved.
RSVD_INTERRUPT_20 = 20, //!< Reserved.
RSVD_INTERRUPT_21 = 21, //!< Reserved.
LS_INT_DEBUG_CC = 22, //!<(cluster-internal) COMMIRQ - Debug communications channel
LS_INT_PMU = 23, //!<(cluster-internal) PMUIRQ - Perfmon*
LS_INT_CTI = 24, //!<(cluster-internal) CTIIRQ - Cross-trigger interface*
LS_INT_VMI = 25, //!<(cluster-internal) VCPUMNTIRQ -Virtual maintenance interface*
LS_INT_WDOG = 28, //!< Watchdog timer
LS_INT_SEC_PHY_TIMER = 29, //!<(cluster-internal) CNTPSIRQ - EL1 Secure physical timer event*
LS_INT_NON_SEC_PHY_TIMER = 30, //!<(cluster-internal) CNTPNSIRQ - EL1 Non-secure physical timer event*
RSVD_INTERRUPT_31 = 31, //!< Reserved.
RSVD_INTERRUPT_32 = 32, //!< Reserved.
RSVD_INTERRUPT_33 = 33, //!< Reserved.
RSVD_INTERRUPT_34 = 34, //!< Reserved.
RSVD_INTERRUPT_35 = 35, //!< Reserved.
RSVD_INTERRUPT_36 = 36, //!< Reserved.
RSVD_INTERRUPT_37 = 37, //!< Reserved.
RSVD_INTERRUPT_38 = 38, //!< Reserved.
RSVD_INTERRUPT_39 = 39, //!< Reserved.
RSVD_INTERRUPT_40 = 40, //!< Reserved.
RSVD_INTERRUPT_41 = 41, //!< Reserved.
RSVD_INTERRUPT_42 = 42, //!< Reserved.
LS_INT_DUART1 = 64, // Logical OR of DUART1 interrupt requests.
LS_INT_I2C1_2 = 66, //!< I2C1 and I2C2 ORed
LS_INT_I2C3_4 = 67, //!< I2C3 and I2C4 ORed
LS_INT_GPIO1_2 = 68, //!< GPIO1 and GPIO2 ORed
LS_INT_GPIO3 = 69, //!< GPIO3
LS_INT_FLETIMER1 = 76, //!< ORed all Flextimer 1 interrupt signals
LS_INT_FLETIMER2 = 77, //!< ORed all Flextimer 2 interrupt signals
LS_INT_FLETIMER3 = 78, //!< ORed all Flextimer 3 interrupt signals
LS_INT_FLETIMER4 = 79, //!< ORed all Flextimer 4 interrupt signals
LS_INT_I2C5_6 = 106, //!< I2C5 and I2C6 ORed
LS_INT_I2C7_8 = 107, //!< I2C7 and I2C8 ORed
LS_INT_USB3_1 = 112, //!< USB1 ORed INT
LS_INT_USB3_2 = 113, //!< USB2 ORed INT
LS_INT_LPUART1 = 264, //!< LPUART1 interrupt request.
LS_INT_LPUART2 = 265, //!< LPUART1 interrupt request.
LS_INT_LPUART3 = 266, //!< LPUART1 interrupt request.
LS_INT_LPUART4 = 267, //!< LPUART1 interrupt request.
LS_INT_LPUART5 = 268, //!< LPUART1 interrupt request.
LS_INT_LPUART6 = 269, //!< LPUART1 interrupt request.
NR_OK1028_INTRS,
};
#endif //__IRQ_NUMBERS_H__
Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c
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/*
* This driver implements a version of the RISC-V PLIC with the actual layout
* specified in chapter 8 of the SiFive U5 Coreplex Series Manual:
*
* https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
*
*/
#include "asm/csr.h"
#include "printf.h"
#include "plic.h"
#include "asm/mmio.h"
#include "ptrace.h"
extern unsigned long boot_cpu_hartid;
#define MAX_CPUS 4
#define MAX_PLIC_IRQS 136
#define CPU_TO_HART(cpu) ((2 * cpu) + 2)
//TODO: to debug
void plic_set_priority(int hwirq, int pro)
{
#if 0
unsigned int reg = PLIC_PRIORITY(hwirq);
writel(pro, reg);
#endif
}
//TODO: to debug
void plic_enable_irq(int cpu, int hwirq, int enable)
{
#if 0
unsigned int hwirq_mask = 1 << (hwirq % 32);
int hart = CPU_TO_HART(cpu);
unsigned int reg = PLIC_MENABLE(hart) + 4 * (hwirq / 32);
// printk("plic_enable_irq hwirq=%d\n", hwirq);
if (enable) {
writel(readl(reg) | hwirq_mask, reg);
}
else {
writel(readl(reg) & ~hwirq_mask, reg);
}
#endif
}
//TODO: to debug
//Refer to linux/drivers/irqchip/irq-sifive-plic.c
int plic_init(void)
{
#if 0
int i;
int hwirq;
// printk("plic_init boot_cpu_hartid=%lu\n", boot_cpu_hartid);
for (i = 0; i < MAX_CPUS; i++) {
writel(0, PLIC_MTHRESHOLD(CPU_TO_HART(i)));
for (hwirq = 1; hwirq <= MAX_PLIC_IRQS; hwirq++) {
plic_enable_irq(i, hwirq, 0);
plic_set_priority(hwirq, 1);
}
}
csr_set(CSR_IE, IE_EIE);
#endif
return 0;
}
void plic_handle_irq(struct pt_regs *regs)
{
#if 0
int hwirq;
int hart = CPU_TO_HART(0);
unsigned int claim_reg = PLIC_MCLAIM(hart);
csr_clear(CSR_IE, IE_EIE);
//TODO
csr_set(CSR_IE, IE_EIE);
#endif
}
void plic_init_hart(uint32_t cpu_id)
{
;
}
uint32_t plic_read_irq_ack(void)
{
return 0;
}
void plic_write_end_of_irq(uint32_t x)
{
;
}
void intr_on(void)
{
;
}
void intr_off(void)
{
;
}
Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h
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#ifndef _RISCV_PLIC_H
#define _RISCV_PLIC_H
#include "memlayout.h"
#include "ptrace.h"
#include <stdint.h>
#define PLIC_BASE PLIC_VIRTMEM_BASE
#define PLIC_PRIORITY(hwirq) (PLIC_BASE + (hwirq) * 4)
#define PLIC_PENDING(hwirq) (PLIC_BASE + 0x1000 + ((hwirq) / 32) * 4)
#define PLIC_MENABLE(hart) (PLIC_BASE + 0x2000 + (hart) * 0x80)
#define PLIC_MTHRESHOLD(hart) (PLIC_BASE + 0x200000 + (hart) * 0x1000)
#define PLIC_MCLAIM(hart) (PLIC_BASE + 0x200004 + (hart) * 0x1000)
int plic_init(void);
void plic_enable_irq(int cpu, int hwirq, int enable);
void plic_handle_irq(struct pt_regs *regs);
void plic_init_hart(uint32_t cpu_id);
uint32_t plic_read_irq_ack(void);
void plic_write_end_of_irq(uint32_t x);
void intr_on(void);
void intr_off(void);
#endif /* _RISCV_PLIC_H */
Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c
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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file trap.c
* @brief trap interface of hardkernel
* @version 1.0
* @author AIIT XUOS Lab
* @date 2023.05.06
*/
/*************************************************
File name: trap.c
Description: trap interface of hardkernel
Others:
History:
Author: AIIT XUOS Lab
Modification:
1. first version
*************************************************/
#include <stdint.h>
#include "assert.h"
#include "core.h"
#include "multicores.h"
#include "syscall.h"
#include "task.h"
#include "mmu.h"
#include "asm/csr.h"
#include "ptrace.h"
#include "plic.h"
extern void dabort_handler(struct trapframe* r);
extern void iabort_handler(struct trapframe* r);
void kernel_abort_handler(struct trapframe* tf)
{
uint64_t ec = tf->cause;
switch (ec) {
case 0:
case 1:
case 2:
case 12:
iabort_handler(tf);
break;
case 4:
case 5:
case 6:
case 7:
case 13:
case 15:
dabort_handler(tf);
break;
default: {
ERROR("tf->cause: %016lx\n", tf->cause);
ERROR("Current Task: %s.\n", cur_cpu()->task->name);
panic("Unimplemented Error Occured.\n");
}
}
panic("Return from abort handler.\n");
}
void kernel_intr_handler(struct trapframe* tf)
{
panic("Intr at kernel mode should never happen by design.\n");
}
extern void context_switch(struct context*, struct context*);
void syscall_arch_handler(struct trapframe* tf)
{
uint64_t ec = tf->cause;
switch (ec) {
case EXC_SYSCALL:
software_irq_dispatch(tf);
break;
default: {
ERROR("USYSCALL: unexpected\n");
ERROR("tf->cause: %016lx\n", tf->cause);
extern void dump_tf(struct trapframe * tf);
dump_tf(tf);
// kill error task
xizi_enter_kernel();
assert(cur_cpu()->task != NULL);
ERROR("Error Task: %s\n", cur_cpu()->task->name);
sys_exit(cur_cpu()->task);
context_switch(cur_cpu()->task->thread_context.context, &cur_cpu()->scheduler);
panic("dabort end should never be reashed.\n");
}
}
}
extern void handle_exception(void);
void trap_init(void)
{
csr_write(stvec, handle_exception);
csr_write(sie, 0);
__asm__ volatile("csrw sscratch, zero" : : : "memory");
#if 0
printk("trap_init test\n");
__asm__ volatile("ebreak");
printk("trap_init test ok\n");
#endif
}
void trap_set_exception_vector(uint64_t new_tbl_base)
{
csr_write(stvec, new_tbl_base);
}
static void do_trap_error(struct pt_regs *regs, const char *str)
{
printk("Oops: %s\n", str);
printk("sstatus: 0x%016lx, sbadaddr: 0x%016lx, scause: 0x%016lx\n",
regs->status, regs->badaddr, regs->cause);
panic("Fatal exception\n");
}
#define DO_ERROR_INFO(name) \
static int name(struct pt_regs *regs, const char *str) \
{ \
do_trap_error(regs, str); \
return 0; \
}
DO_ERROR_INFO(do_trap_unknown);
DO_ERROR_INFO(do_trap_insn_misaligned);
DO_ERROR_INFO(do_trap_insn_fault);
DO_ERROR_INFO(do_trap_insn_illegal);
DO_ERROR_INFO(do_trap_load_misaligned);
DO_ERROR_INFO(do_trap_load_fault);
DO_ERROR_INFO(do_trap_store_misaligned);
DO_ERROR_INFO(do_trap_store_fault);
DO_ERROR_INFO(do_trap_ecall_u);
DO_ERROR_INFO(do_trap_ecall_s);
DO_ERROR_INFO(do_trap_break);
DO_ERROR_INFO(do_page_fault);
struct fault_info {
int (*fn)(struct pt_regs *regs, const char *name);
const char *name;
};
static struct fault_info fault_inf[] = {
{do_trap_insn_misaligned, "Instruction address misaligned"},
{do_trap_insn_fault, "Instruction access fault"},
{do_trap_insn_illegal, "Illegal instruction"},
{do_trap_break, "Breakpoint"},
{do_trap_load_misaligned, "Load address misaligned"},
{do_trap_load_fault, "Load access fault"},
{do_trap_store_misaligned, "Store/AMO address misaligned"},
{do_trap_store_fault, "Store/AMO access fault"},
{do_trap_ecall_u, "Environment call from U-mode"},
{do_trap_ecall_s, "Environment call from S-mode"},
{do_trap_unknown, "unknown 10"},
{do_trap_unknown, "unknown 11"},
{do_page_fault, "Instruction page fault"},
{do_page_fault, "Load page fault"},
{do_trap_unknown, "unknown 14"},
{do_page_fault, "Store/AMO page fault"},
};
struct fault_info * ec_to_fault_info(unsigned long scause)
{
struct fault_info *inf;
if (scause >= (sizeof(fault_inf)/sizeof(fault_inf[0]))) {
printk("The cause is out of range Exception Code, scause=0x%lx\n", scause);
panic("Fatal exception\n");
}
inf = &fault_inf[scause];
return inf;
}
void handle_irq(struct pt_regs *regs, unsigned long scause)
{
switch (scause & ~CAUSE_IRQ_FLAG) {
case IRQ_S_TIMER:
//handle_timer_irq();
break;
case IRQ_S_EXT:
plic_handle_irq(regs);
break;
case IRQ_S_SOFT:
// TODO
break;
default:
panic("unexpected interrupt cause\n");
}
}
void do_exception(struct pt_regs *regs, unsigned long scause)
{
const struct fault_info *inf;
printk("%s, scause: 0x%lx\n", __func__, scause);
if (scause & CAUSE_IRQ_FLAG) {
intr_irq_dispatch((struct trapframe *)regs);
}
else {
inf = ec_to_fault_info(scause);
if (!inf->fn(regs, inf->name)) {
return;
}
}
}
#define INIT_THREAD_INFO \
{ \
.flags = 0, \
.preempt_count = 1, \
}
struct thread_info init_thread_info = INIT_THREAD_INFO;
Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c
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/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file trap_common.c
* @brief trap interface of hardkernel
* @version 1.0
* @author AIIT XUOS Lab
* @date 2023.05.06
*/
/*************************************************
File name: trap_common.c
Description: trap interface of hardkernel
Others:
History:
Author: AIIT XUOS Lab
Modification:
1. first version
*************************************************/
#include <string.h>
#include "core.h"
#include "cortex.h"
#include "trap_common.h"
#include "log.h"
#include "multicores.h"
#include "plic.h"
static struct XiziTrapDriver xizi_trap_driver;
extern void trap_init(void);
extern void trap_set_exception_vector(uint64_t new_tbl_base);
void panic(char* s)
{
KPrintf("panic: %s\n", s);
for (;;)
;
}
static void _sys_irq_init(int cpu_id)
{
// primary core init intr
if (cpu_id == 0) {
plic_init();
}
plic_init_hart(cpu_id);
}
static void _sys_trap_init(int cpu_id)
{
if (cpu_id == 0) {
trap_init();
}
_sys_irq_init(cpu_id);
}
static void _cpu_irq_enable(void)
{
intr_on();
}
static void _cpu_irq_disable(void)
{
intr_off();
}
static void _single_irq_enable(int irq, int cpu, int prio)
{
plic_enable_irq(cpu, irq, 1);
}
static void _single_irq_disable(int irq, int cpu)
{
plic_enable_irq(cpu, irq, 0);
}
static inline uintptr_t* _switch_hw_irqtbl(uintptr_t* new_tbl_base)
{
trap_set_exception_vector((uintptr_t)new_tbl_base);
return NULL;
}
static void _bind_irq_handler(int irq, irq_handler_t handler)
{
xizi_trap_driver.sw_irqtbl[irq].handler = handler;
}
static uint32_t _hw_before_irq()
{
uint32_t iar = plic_read_irq_ack();
return iar;
}
static uint32_t _hw_cur_int_num(uint32_t int_info)
{
return int_info & 0x3FF;
}
static void _hw_after_irq(uint32_t int_info)
{
plic_write_end_of_irq(int_info);
}
int _cur_cpu_id()
{
return cpu_get_current();
}
static struct XiziTrapDriver xizi_trap_driver = {
.sys_irq_init = _sys_trap_init,
.cur_cpu_id = _cur_cpu_id,
.cpu_irq_enable = _cpu_irq_enable,
.cpu_irq_disable = _cpu_irq_disable,
.single_irq_enable = _single_irq_enable,
.single_irq_disable = _single_irq_disable,
.switch_hw_irqtbl = _switch_hw_irqtbl,
.bind_irq_handler = _bind_irq_handler,
.hw_before_irq = _hw_before_irq,
.hw_cur_int_num = _hw_cur_int_num,
.hw_after_irq = _hw_after_irq,
};
struct XiziTrapDriver* hardkernel_intr_init(struct TraceTag* hardkernel_tag)
{
xizi_trap_driver.sys_irq_init(0);
xizi_trap_driver.cpu_irq_disable();
return &xizi_trap_driver;
}
Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/ptrace.h
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#ifndef _ASM_RISCV_PTRACE_H
#define _ASM_RISCV_PTRACE_H
struct pt_regs {
unsigned long epc;
unsigned long ra;
unsigned long sp;
unsigned long gp;
unsigned long tp;
unsigned long t0;
unsigned long t1;
unsigned long t2;
unsigned long s0;
unsigned long s1;
unsigned long a0;
unsigned long a1;
unsigned long a2;
unsigned long a3;
unsigned long a4;
unsigned long a5;
unsigned long a6;
unsigned long a7;
unsigned long s2;
unsigned long s3;
unsigned long s4;
unsigned long s5;
unsigned long s6;
unsigned long s7;
unsigned long s8;
unsigned long s9;
unsigned long s10;
unsigned long s11;
unsigned long t3;
unsigned long t4;
unsigned long t5;
unsigned long t6;
/* Supervisor/Machine CSRs */
unsigned long status;
unsigned long badaddr;
unsigned long cause;
/* a0 value before the syscall */
unsigned long orig_a0;
};
#define REG_FMT "%016lx"
#define user_mode(regs) (((regs)->status & SR_PP) == 0)
//#define MAX_REG_OFFSET offsetof(struct pt_regs, orig_a0)
/* Helpers for working with the instruction pointer */
static inline unsigned long instruction_pointer(struct pt_regs *regs)
{
return regs->epc;
}
static inline void instruction_pointer_set(struct pt_regs *regs,
unsigned long val)
{
regs->epc = val;
}
#define profile_pc(regs) instruction_pointer(regs)
/* Helpers for working with the user stack pointer */
static inline unsigned long user_stack_pointer(struct pt_regs *regs)
{
return regs->sp;
}
static inline void user_stack_pointer_set(struct pt_regs *regs,
unsigned long val)
{
regs->sp = val;
}
/* Valid only for Kernel mode traps. */
static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
{
return regs->sp;
}
/* Helpers for working with the frame pointer */
static inline unsigned long frame_pointer(struct pt_regs *regs)
{
return regs->s0;
}
static inline void frame_pointer_set(struct pt_regs *regs,
unsigned long val)
{
regs->s0 = val;
}
static inline unsigned long regs_return_value(struct pt_regs *regs)
{
return regs->a0;
}
static inline void regs_set_return_value(struct pt_regs *regs,
unsigned long val)
{
regs->a0 = val;
}
#endif /* _ASM_RISCV_PTRACE_H */
Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S
+270
View File
@@ -0,0 +1,270 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file trampoline.S
* @brief trap in and out code
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024-04-22
*/
/*************************************************
File name: trampoline.S
Description: trap in and out code
Others:
History:
1. Date: 2024-04-22
Author: AIIT XUOS Lab
Modification:
1. first version
*************************************************/
#include "asm/csr.h"
#include "asm/asm-offsets.h"
.align 4
.global handle_exception
handle_exception:
# Here tp is struct thread_info
csrrw tp, CSR_SCRATCH, tp
bnez tp, _save_context
_restore_kernel_tpsp:
csrr tp, CSR_SCRATCH
REG_S sp, 16(tp)
_save_context:
REG_S sp, 24(tp)
REG_L sp, 16(tp)
# Here sp is struct trapframe
addi sp, sp, -(PT_SIZE_ON_STACK)
REG_S x1, PT_RA(sp)
REG_S x3, PT_GP(sp)
REG_S x5, PT_T0(sp)
REG_S x6, PT_T1(sp)
REG_S x7, PT_T2(sp)
REG_S x8, PT_S0(sp)
REG_S x9, PT_S1(sp)
REG_S x10, PT_A0(sp)
REG_S x11, PT_A1(sp)
REG_S x12, PT_A2(sp)
REG_S x13, PT_A3(sp)
REG_S x14, PT_A4(sp)
REG_S x15, PT_A5(sp)
REG_S x16, PT_A6(sp)
REG_S x17, PT_A7(sp)
REG_S x18, PT_S2(sp)
REG_S x19, PT_S3(sp)
REG_S x20, PT_S4(sp)
REG_S x21, PT_S5(sp)
REG_S x22, PT_S6(sp)
REG_S x23, PT_S7(sp)
REG_S x24, PT_S8(sp)
REG_S x25, PT_S9(sp)
REG_S x26, PT_S10(sp)
REG_S x27, PT_S11(sp)
REG_S x28, PT_T3(sp)
REG_S x29, PT_T4(sp)
REG_S x30, PT_T5(sp)
REG_S x31, PT_T6(sp)
/*
* Disable user-mode memory access as it should only be set in the
* actual user copy routines.
*
* Disable the FPU to detect illegal usage of floating point in kernel
* space.
*/
li t0, SR_SUM | SR_FS
REG_L s0, 24(tp)
csrrc s1, CSR_STATUS, t0
csrr s2, CSR_EPC
csrr s3, CSR_TVAL
csrr s4, CSR_CAUSE
csrr s5, CSR_SCRATCH
REG_S s0, PT_SP(sp)
REG_S s1, PT_STATUS(sp)
REG_S s2, PT_EPC(sp)
REG_S s3, PT_BADADDR(sp)
REG_S s4, PT_CAUSE(sp)
REG_S s5, PT_TP(sp)
/*
* Set the scratch register to 0, so that if a recursive exception
* occurs, the exception vector knows it came from the kernel
*/
csrw CSR_SCRATCH, x0
/* Load the global pointer */
.option push
.option norelax
la gp, __global_pointer$
.option pop
/*
* MSB of cause differentiates between
* interrupts and exceptions
*/
bge s4, zero, 1f
la ra, ret_from_exception
/* Handle interrupts */
move a0, sp /* pt_regs */
//la a1, handle_arch_irq
la a1, intr_irq_dispatch
REG_L a1, (a1)
jr a1
1:
/*
* Exceptions run with interrupts enabled or disabled depending on the
* state of SR_PIE in m/sstatus.
*/
andi t0, s1, SR_PIE
beqz t0, 1f
/* kprobes, entered via ebreak, must have interrupts disabled. */
li t0, EXC_BREAKPOINT
beq s4, t0, 1f
csrs CSR_STATUS, SR_IE
1:
la ra, ret_from_exception
/* Handle syscalls */
li t0, EXC_SYSCALL
beq s4, t0, handle_syscall
mv a0, sp
mv a1, s4
tail do_exception
handle_syscall:
/* save the initial A0 value (needed in signal handlers) */
REG_S a0, PT_ORIG_A0(sp)
/*
* Advance SEPC to avoid executing the original
* scall instruction on sret
*/
addi s2, s2, 0x4
REG_S s2, PT_EPC(sp)
/* Trace syscalls, but only if requested by the user. */
j handle_syscall_trace_enter
ret
/* Slow paths for ptrace. */
handle_syscall_trace_enter:
csrr s0, satp
la a0, riscv_kernel_satp
ld a0, 0(a0)
csrw satp, a0
sfence.vma
move a0, sp
//call do_syscall_trace_enter
call syscall_arch_handler
move t0, a0
REG_L a0, PT_A0(sp)
REG_L a1, PT_A1(sp)
REG_L a2, PT_A2(sp)
REG_L a3, PT_A3(sp)
REG_L a4, PT_A4(sp)
REG_L a5, PT_A5(sp)
REG_L a6, PT_A6(sp)
REG_L a7, PT_A7(sp)
//bnez t0, ret_from_syscall_rejected
//j check_syscall_nr
handle_syscall_trace_exit:
move a0, sp
//call do_syscall_trace_exit
csrw satp, s0
sfence.vma
j ret_from_exception
ret_from_exception:
REG_L s0, PT_STATUS(sp)
csrc CSR_STATUS, SR_IE
andi s0, s0, SR_SPP
bnez s0, resume_kernel
resume_userspace:
/* Save unwound kernel stack pointer in thread_info */
addi s0, sp, PT_SIZE_ON_STACK
REG_S s0, 16(tp)
/*
* Save TP into the scratch register , so we can find the kernel data
* structures again.
*/
csrw CSR_SCRATCH, tp
restore_all:
REG_L a0, PT_STATUS(sp)
REG_L a2, PT_EPC(sp)
REG_SC x0, a2, PT_EPC(sp)
csrw CSR_STATUS, a0
csrw CSR_EPC, a2
REG_L x1, PT_RA(sp)
REG_L x3, PT_GP(sp)
REG_L x4, PT_TP(sp)
REG_L x5, PT_T0(sp)
REG_L x6, PT_T1(sp)
REG_L x7, PT_T2(sp)
REG_L x8, PT_S0(sp)
REG_L x9, PT_S1(sp)
REG_L x10, PT_A0(sp)
REG_L x11, PT_A1(sp)
REG_L x12, PT_A2(sp)
REG_L x13, PT_A3(sp)
REG_L x14, PT_A4(sp)
REG_L x15, PT_A5(sp)
REG_L x16, PT_A6(sp)
REG_L x17, PT_A7(sp)
REG_L x18, PT_S2(sp)
REG_L x19, PT_S3(sp)
REG_L x20, PT_S4(sp)
REG_L x21, PT_S5(sp)
REG_L x22, PT_S6(sp)
REG_L x23, PT_S7(sp)
REG_L x24, PT_S8(sp)
REG_L x25, PT_S9(sp)
REG_L x26, PT_S10(sp)
REG_L x27, PT_S11(sp)
REG_L x28, PT_T3(sp)
REG_L x29, PT_T4(sp)
REG_L x30, PT_T5(sp)
REG_L x31, PT_T6(sp)
REG_L x2, PT_SP(sp)
sret
resume_kernel:
j restore_all
.global task_prepare_enter
task_prepare_enter:
call xizi_leave_kernel
j ret_from_exception
Ubiquitous/XiZi_AIoT/hardkernel/mmu/Makefile
+5
View File
@@ -1,4 +1,9 @@
ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), )
SRC_DIR := arm
endif
ifneq ($(findstring $(BOARD), jh7110), )
SRC_DIR := riscv
endif
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/Makefile
+4
View File
@@ -1 +1,5 @@
ifneq ($(findstring $(BOARD), jh7110), )
SRC_DIR := rv64gc
endif
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/Makefile
+4
View File
@@ -0,0 +1,4 @@
SRC_FILES := mmu_init.c mmu.c pagetable_attr.c
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/mmu.h
+79
View File
@@ -0,0 +1,79 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file mmu.h
* @brief mmu related configure and registers
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024-04-26
*/
/*************************************************
File name: mmu.h
Description: mmu related configure and registers
Others:
History:
Author: AIIT XUOS Lab
Modification:
1. first version
*************************************************/
#pragma once
#include <stdint.h>
#include "memlayout.h"
// #define TCR_SH1_INNER (0b11 << 28)
// #define TCR_ORGN1_IRGN1_WRITEBACK_WRITEALLOC ((0b01 << 26) | (0b01 << 24))
// #define TCR_SH0_INNER (0b11 << 12)
// #define TCR_ORGN0_IRGN0_WRITEBACK_WRITEALLOC ((0b01 << 10) | (0b01 << 8))
#define TCR_IPS (0 << 0)
#define TCR_TG1_4K (0b10 << 30)
#define TCR_TOSZ (0b11001 << 0)
#define TCR_T1SZ (0b11001 << 16)
#define TCR_TG0_4K (0 << 14)
#define TCR_VALUE \
(TCR_IPS | TCR_TG1_4K | TCR_TG0_4K | TCR_TOSZ | TCR_T1SZ)
enum AccessPermission {
AccessPermission_NoAccess = 0,
AccessPermission_KernelOnly = 1, // EL1
AccessPermission_Reserved = 2,
AccessPermission_KernelUser = 3, // EL1&EL0
};
void GetDevPteAttr(uintptr_t* attr);
void GetUsrPteAttr(uintptr_t* attr);
void GetUsrDevPteAttr(uintptr_t* attr);
void GetKernPteAttr(uintptr_t* attr);
void GetPdeAttr(uintptr_t* attr);
/*
Enable MMU, cache, write buffer, etc.
*/
//#define SCTLR_R(val) __asm__ volatile("mrs %0, sctlr_el1" : "=r"(val)::"memory")
//#define SCTLR_W(val) __asm__ volatile("msr sctlr_el1, %0" ::"r"(val) : "memory")
#define SCTLR_R(val) 0
#define SCTLR_W(val) 0
/*
Read and write mmu pagetable register base addr
*/
#ifndef __ASSEMBLER__
#include <stdint.h>
__attribute__((always_inline)) static inline uint64_t v2p(void* a) { return ((uint64_t)(a)) - KERN_MEM_BASE; }
__attribute__((always_inline)) static inline void* p2v(uint64_t a) { return (void*)((a) + KERN_MEM_BASE); }
#endif
Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h
+98
View File
@@ -0,0 +1,98 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file memlayout.h
* @brief virtual memory and physical memory layout
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024-10-31
*/
/*************************************************
File name: memlayout.h
Description: virtual memory and physical memory layout
Others:
History:
Author: AIIT XUOS Lab
Modification:
1. first version
*************************************************/
#pragma once
// Memory layout
// clang-format off
#define ARCH_BIT 64
/* physical memory layout */
#define PHY_MEM_BASE (0x0000000040200000ULL)
#define PHY_USER_FREEMEM_BASE (0x0000000080000000ULL)
#define PHY_USER_FREEMEM_TOP (0x0000000200000000ULL)
#define PHY_MEM_STOP (0x0000000200000000ULL)
/* PTE-PAGE_SIZE */
#define LEVEL4_PTE_SHIFT 12
#define LEVEL4_PTE_SIZE (1 << LEVEL4_PTE_SHIFT)
/* PDE-SECTION_SIZE */
#define LEVEL3_PDE_SHIFT 21
#define LEVEL3_PDE_SIZE (1 << LEVEL3_PDE_SHIFT)
#define LEVEL2_PDE_SHIFT 30
#define LEVEL2_PDE_SIZE (1 << LEVEL2_PDE_SHIFT)
#define LEVEL1_PTE_SHIFT 39
#define NUM_LEVEL2_PDE (1 << (LEVEL1_PTE_SHIFT - LEVEL2_PDE_SHIFT))
#define NUM_LEVEL3_PDE (1 << (LEVEL2_PDE_SHIFT - LEVEL3_PDE_SHIFT)) // how many PDE in a PT
#define NUM_LEVEL4_PTE (1 << (LEVEL3_PDE_SHIFT - LEVEL4_PTE_SHIFT)) // how many PTE in a PT
#define NUM_TOPLEVEL_PDE NUM_LEVEL2_PDE
#define PAGE_SHIFT LEVEL4_PTE_SHIFT
#define PAGE_SIZE LEVEL4_PTE_SIZE
#define MAX_NR_FREE_PAGES ((PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT)
/* Deivce memory layout */
#define DEV_PHYMEM_BASE (0x0000000010000000ULL)
#define DEV_VRTMEM_BASE ((0 - 0x0000004000000000ULL) + DEV_PHYMEM_BASE)
#define DEV_MEM_SIZE (0x0000000030040000ULL)
/* User memory layout */
#define USER_STACK_SIZE PAGE_SIZE
#define USER_MEM_BASE (0x0000000000000000ULL)
#define USER_MEM_TOP (0x0000004000000000ULL)
#define USER_IPC_SPACE_BASE (0x0000003000000000ULL)
#define USER_IPC_USE_ALLOCATOR_WATERMARK (0x0000003000010000ULL)
#define USER_IPC_SPACE_TOP (USER_IPC_SPACE_BASE + 0x10000000ULL)
/* Kernel memory layout */
#define KERN_MEM_BASE ((0 - 0x0000002000000000ULL) + PHY_MEM_BASE) // First kernel virtual address
#define KERN_OFFSET (KERN_MEM_BASE - PHY_MEM_BASE)
/* Leave 2GB for kernel and BPF at the end of the address space */
#define KERNEL_LINK_ADDR (0 - 0x80000000ULL)
#define KERNEL_LINK_OFFSET (KERNEL_LINK_ADDR - PHY_MEM_BASE)
/* PLIC (platform-level interrupt controller) memory layout */
#define PLIC_PHYMEM_BASE (0x0C000000ULL)
#define PLIC_MEM_SIZE (0x00400000ULL)
#define PLIC_VIRTMEM_BASE ((0 - 0x0000003000000000ULL) + PLIC_PHYMEM_BASE)
#define V2P(a) (((uint64_t)(a)) - KERN_OFFSET)
#define P2V(a) ((void *)(((char *)(a)) + KERN_OFFSET))
#define V2P_WO(x) ((x) - KERN_OFFSET) // same as V2P, but without casts
#define P2V_WO(x) ((x) + KERN_OFFSET) // same as P2V, but without casts
#define V2P_LINK(a) (((uint64_t)(a)) - KERNEL_LINK_OFFSET)
#define P2V_LINK(a) ((a) + KERNEL_LINK_OFFSET)
Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c
+98
View File
@@ -0,0 +1,98 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file mmu.c
* @brief mmu operations
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024.04.26
*/
/*************************************************
File name: mmu.c
Description: mmu operations
Others:
History:
Author: AIIT XUOS Lab
Modification:
1. first version
*************************************************/
#include <string.h>
#include "mmu.h"
#include "cache_common_ope.h"
#include "mmu_common.h"
#include "trap_common.h"
#include "asm/csr.h"
#include "printf.h"
// extern struct MmuCommonDone mmu_common_done;
static struct MmuDriverRightGroup right_group;
void load_pgdir(uintptr_t pgdir_paddr)
{
/* get cache driver */
struct ICacheDone* p_icache_done = AchieveResource(&right_group.icache_driver_tag);
struct DCacheDone* p_dcache_done = AchieveResource(&right_group.dcache_driver_tag);
csr_write(CSR_SATP, (pgdir_paddr >> PAGE_SHIFT) | SATP_MODE);
__asm__ __volatile__ ("sfence.vma" : : : "memory");
p_icache_done->invalidateall();
p_dcache_done->flushall();
}
__attribute__((always_inline)) inline static void _tlb_flush(uintptr_t va)
{
;
}
static void tlb_flush_range(uintptr_t vstart, int len)
{
uintptr_t vaddr = vstart;
uintptr_t vend = vaddr + len;
for (; vaddr < vend; vaddr += PAGE_SIZE) {
_tlb_flush(vaddr);
}
}
static void tlb_flush_all()
{
;
}
static struct MmuCommonDone mmu_common_done = {
.MmuDevPteAttr = GetDevPteAttr,
.MmuPdeAttr = GetPdeAttr,
.MmuUsrPteAttr = GetUsrPteAttr,
.MmuUsrDevPteAttr = GetUsrDevPteAttr,
.MmuKernPteAttr = GetKernPteAttr,
.LoadPgdir = load_pgdir,
.TlbFlushAll = tlb_flush_all,
.TlbFlush = tlb_flush_range,
};
struct MmuCommonDone* hardkernel_mmu_init(struct TraceTag* hardkernel_tag, char* icache_name, char* dcache_name)
{
/* init right group for mmu driver */
AchieveResourceTag(&right_group.icache_driver_tag, hardkernel_tag, icache_name);
AchieveResourceTag(&right_group.dcache_driver_tag, hardkernel_tag, dcache_name);
return &mmu_common_done;
}
Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c
+243
View File
@@ -0,0 +1,243 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file
* @brief
* @version 1.0
* @author AIIT XUOS Lab
* @date 2024.12.02
*/
/*************************************************
File name: mmu_init.c
Description:
Others:
History:
Author: AIIT XUOS Lab
Modification:
1. first version
*************************************************/
#include <stdint.h>
#include <string.h>
#include <stdbool.h>
#include "memlayout.h"
#include <asm/pgtable-bits.h>
#define PTRS_PER_PGD NUM_LEVEL2_PDE
#define PTRS_PER_PMD NUM_LEVEL3_PDE
#define PGDIR_SHIFT LEVEL2_PDE_SHIFT
#define PGDIR_SIZE (1 << PGDIR_SHIFT)
#define PMD_SHIFT LEVEL3_PDE_SHIFT
#define PMD_SIZE (1 << PMD_SHIFT)
#define _PAGE_KERNEL (_PAGE_READ \
| _PAGE_WRITE \
| _PAGE_PRESENT \
| _PAGE_ACCESSED \
| _PAGE_DIRTY \
| _PAGE_GLOBAL)
#define PFN_PD(x, prot) (((x) << _PAGE_PFN_SHIFT) | (prot))
#define _PD_PFN(x) ((x) >> _PAGE_PFN_SHIFT)
#define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
#define PFN_PHYS(x) ((x) << PAGE_SHIFT)
#define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
#define pmd_index(a) (((a) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
extern char _start[];
extern char _end[];
struct kernel_mapping {
unsigned long virt_addr;
uintptr_t phys_addr;
uintptr_t size;
/* Offset between linear mapping virtual address and kernel load address */
unsigned long va_pa_offset;
/* Offset between kernel mapping virtual address and kernel load address */
unsigned long va_kernel_pa_offset;
unsigned long va_kernel_xip_pa_offset;
};
typedef uint64_t phys_addr_t;
struct kernel_mapping kernel_map;
uintptr_t trampoline_pg_dir[PTRS_PER_PGD] __attribute__((aligned(PAGE_SIZE)));
uintptr_t early_pg_dir[PTRS_PER_PGD] __attribute__((aligned(PAGE_SIZE)));
static uintptr_t trampoline_pmd[PTRS_PER_PMD] __attribute__((aligned(PAGE_SIZE)));
static uintptr_t early_pmd[PTRS_PER_PMD] __attribute__((aligned(PAGE_SIZE)));
static uintptr_t early_uart_pmd[PTRS_PER_PMD] __attribute__((aligned(PAGE_SIZE)));
static uintptr_t early_pmd_free[((PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) >> PGDIR_SHIFT) + 1][PTRS_PER_PMD] __attribute__((aligned(PAGE_SIZE)));
static uintptr_t early_plic_pmd[PTRS_PER_PMD] __attribute__((aligned(PAGE_SIZE)));
static uintptr_t *get_pmd_virt_early(phys_addr_t pa)
{
/* Before MMU is enabled */
return (uintptr_t *)((uintptr_t)pa);
}
static phys_addr_t alloc_pmd_early(uintptr_t va)
{
return (uintptr_t)early_pmd;
}
static void create_pmd_mapping_early(uintptr_t *pmdp,
uintptr_t va, phys_addr_t pa,
phys_addr_t sz, uintptr_t prot)
{
uintptr_t pmd_idx = pmd_index(va);
if (sz == PMD_SIZE) {
if ((pmdp[pmd_idx]) == 0)
pmdp[pmd_idx] = (PFN_PD(PFN_DOWN(pa), prot));
return;
}
}
static void create_pgd_mapping_early(uintptr_t *pgdp,
uintptr_t va, phys_addr_t pa,
phys_addr_t sz, uintptr_t prot)
{
uintptr_t *nextp;
phys_addr_t next_phys;
uintptr_t pgd_idx = pgd_index(va);
if (sz == PGDIR_SIZE) {
if ((pgdp[pgd_idx]) == 0)
pgdp[pgd_idx] = (PFN_PD(PFN_DOWN(pa), prot));
return;
}
if ((pgdp[pgd_idx]) == 0) {
next_phys = alloc_pmd_early(va);
pgdp[pgd_idx] = (PFN_PD(PFN_DOWN(next_phys), _PAGE_TABLE));
nextp = get_pmd_virt_early(next_phys);
memset(nextp, 0, PAGE_SIZE);
} else {
next_phys = PFN_PHYS(_PD_PFN((pgdp[pgd_idx])));
nextp = get_pmd_virt_early(next_phys);
}
create_pmd_mapping_early(nextp, va, pa, sz, prot);
}
static void create_kernel_page_table_early(uintptr_t *pgdir, bool early)
{
uintptr_t va, end_va;
end_va = kernel_map.virt_addr + kernel_map.size;
for (va = kernel_map.virt_addr; va < end_va; va += PMD_SIZE) {
create_pgd_mapping_early(pgdir, va,
kernel_map.phys_addr + (va - kernel_map.virt_addr),
PMD_SIZE,
(_PAGE_KERNEL | _PAGE_EXEC));
}
}
static void create_kernel_pgd_mapping_free_early(uintptr_t *pgdp,
uintptr_t va, phys_addr_t pa,
phys_addr_t sz, uintptr_t prot)
{
uintptr_t *nextp;
phys_addr_t next_phys;
uintptr_t pgd_idx = pgd_index(va);
uintptr_t start_pgd_idx = pgd_index(kernel_map.virt_addr);
if ((pgdp[pgd_idx]) == 0) {
next_phys = (uintptr_t)early_pmd_free[pgd_idx - start_pgd_idx];
pgdp[pgd_idx] = (PFN_PD(PFN_DOWN(next_phys), _PAGE_TABLE));
nextp = get_pmd_virt_early(next_phys);
memset(nextp, 0, PAGE_SIZE);
} else {
next_phys = PFN_PHYS(_PD_PFN((pgdp[pgd_idx])));
nextp = get_pmd_virt_early(next_phys);
}
create_pmd_mapping_early(nextp, va, pa, sz, prot);
}
static void create_kernel_page_table_free_early(uintptr_t *pgdir, bool early)
{
uintptr_t va, end_va;
end_va = KERN_MEM_BASE + (PHY_USER_FREEMEM_BASE - PHY_MEM_BASE);
for (va = KERN_MEM_BASE + kernel_map.size; va < end_va; va += PMD_SIZE) {
create_kernel_pgd_mapping_free_early(pgdir, va,
kernel_map.phys_addr + (va - KERN_MEM_BASE),
PMD_SIZE,
_PAGE_KERNEL);
}
}
static void create_plic_page_table_early(uintptr_t *pgdir, bool early)
{
uintptr_t va;
uintptr_t pa;
for (va = PLIC_VIRTMEM_BASE; va < PLIC_VIRTMEM_BASE + PLIC_MEM_SIZE; va += PMD_SIZE) {
pa = va - PLIC_VIRTMEM_BASE + PLIC_PHYMEM_BASE;
create_pgd_mapping_early(pgdir, va, (uintptr_t)early_plic_pmd, PGDIR_SIZE, _PAGE_TABLE);
create_pmd_mapping_early(early_plic_pmd, va, pa, PMD_SIZE, _PAGE_KERNEL);
}
}
/*
* setup_vm_early() is called from boot.S with MMU-off.
*
* Following requirements should be honoured for setup_vm() to work
* correctly:
* 1) It should use PC-relative addressing for accessing kernel symbols.
* To achieve this we always use GCC cmodel=medany.
* 2) The compiler instrumentation for FTRACE will not work for setup_vm()
* so disable compiler instrumentation when FTRACE is enabled.
*/
void setup_vm_early(void)
{
kernel_map.virt_addr = KERNEL_LINK_ADDR;
kernel_map.phys_addr = (uintptr_t)(&_start);
kernel_map.size = (uintptr_t)(&_end) - kernel_map.phys_addr;
kernel_map.va_pa_offset = KERN_OFFSET - kernel_map.phys_addr;
kernel_map.va_kernel_pa_offset = kernel_map.virt_addr - kernel_map.phys_addr;
/* Setup trampoline PGD and PMD */
create_pgd_mapping_early(trampoline_pg_dir, kernel_map.virt_addr, (uintptr_t)trampoline_pmd, PGDIR_SIZE, _PAGE_TABLE);
create_pmd_mapping_early(trampoline_pmd, kernel_map.virt_addr, kernel_map.phys_addr, PMD_SIZE, (_PAGE_KERNEL | _PAGE_EXEC));
/*
* Setup early PGD covering entire kernel which will allow
* us to reach paging_init(). We map all memory banks later
* in setup_vm_final() below.
*/
create_kernel_page_table_early(early_pg_dir, true);
/* Setup uart PGD and PMD */
create_pgd_mapping_early(early_pg_dir, DEV_VRTMEM_BASE, (uintptr_t)early_uart_pmd, PGDIR_SIZE, _PAGE_TABLE);
create_pmd_mapping_early(early_uart_pmd, DEV_VRTMEM_BASE, DEV_PHYMEM_BASE, PMD_SIZE, _PAGE_KERNEL);
/* Setup kernel free PGD and PMD */
create_kernel_page_table_free_early(early_pg_dir, true);
/* Setup PLIC PGD and PMD */
create_plic_page_table_early(early_pg_dir, true);
}
Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/pagetable_attr.c
+65
View File
@@ -0,0 +1,65 @@
/*
* Copyright (c) 2020 AIIT XUOS Lab
* XiUOS is licensed under Mulan PSL v2.
* You can use this software according to the terms and conditions of the Mulan PSL v2.
* You may obtain a copy of Mulan PSL v2 at:
* http://license.coscl.org.cn/MulanPSL2
* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
* See the Mulan PSL v2 for more details.
*/
/**
* @file pagetable_attr.c
* @brief mmu entry attributes
* @version 1.
* @author AIIT XUOS Lab
* @date 2023.04.26
*/
/*************************************************
File name: pagetable_attr.c
Description: mmu entry attributes
Others:
History:
Author: AIIT XUOS Lab
Modification:
1. first version
*************************************************/
#include "mmu.h"
#include "mmu_common.h"
#include "asm/pgtable-bits.h"
#define _PAGE_KERNEL (_PAGE_READ \
| _PAGE_WRITE \
| _PAGE_PRESENT \
| _PAGE_ACCESSED \
| _PAGE_DIRTY \
| _PAGE_GLOBAL)
void GetUsrPteAttr(uintptr_t* attr)
{
*attr = _PAGE_KERNEL | _PAGE_USER | _PAGE_EXEC;
}
void GetUsrDevPteAttr(uintptr_t* attr)
{
*attr = _PAGE_KERNEL | _PAGE_USER;
}
void GetDevPteAttr(uintptr_t* attr)
{
*attr = _PAGE_KERNEL;
}
void GetKernPteAttr(uintptr_t* attr)
{
*attr = _PAGE_KERNEL | _PAGE_EXEC;
}
void GetPdeAttr(uintptr_t* attr)
{
*attr = _PAGE_PRESENT;
}
Ubiquitous/XiZi_AIoT/hardkernel/uart/Makefile
+6
View File
@@ -1,4 +1,10 @@
ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), )
SRC_DIR := arm
endif
ifneq ($(findstring $(BOARD), jh7110), )
SRC_DIR := riscv
endif
SRC_FILES := uart_common_ope.c
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h
+4 -1
View File
@@ -50,6 +50,8 @@ extern "C" {
#define KPrintf printf_
#define printf printf_
int printf_(const char* format, ...);
int printf_early(const char* format, ...);
#define printk printf_
/**
* Tiny sprintf implementation
@@ -99,4 +101,5 @@ int fctprintf(void (*out)(char character, void* arg), void* arg, const char* for
}
#endif
#endif // _PRINTF_H_
#endif // _PRINTF_H_
Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/Makefile
+5
View File
@@ -0,0 +1,5 @@
ifneq ($(findstring $(BOARD), jh7110), )
SRC_DIR := rv64gc
endif
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/Makefile
+3
View File
@@ -0,0 +1,3 @@
SRC_DIR := uart_io_for_$(BOARD)
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/Makefile
+3
View File
@@ -0,0 +1,3 @@
SRC_FILES := uart.c ns16550.c
include $(KERNEL_ROOT)/compiler.mk
Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h
+219
View File
@@ -0,0 +1,219 @@
/*
* NS16550 Serial Port
* originally from linux source (arch/powerpc/boot/ns16550.h)
*
* Cleanup and unification
* (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
*
* modified slightly to
* have addresses as offsets from CONFIG_SYS_ISA_BASE
* added a few more definitions
* added prototypes for ns16550.c
* reduced no of com ports to 2
* modifications (c) Rob Taylor, Flying Pig Systems. 2000.
*
* added support for port on 64-bit bus
* by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
*/
/*
* Note that the following macro magic uses the fact that the compiler
* will not allocate storage for arrays of size 0
*/
#ifndef __ns16550_h
#define __ns16550_h
#include <stdint.h>
/*
* For driver model we always use one byte per register, and sort out the
* differences in the driver
*/
#define CONFIG_SYS_NS16550_REG_SIZE (-1)
#define UART_REG(x) \
unsigned char x; \
unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
/**
* struct ns16550_plat - information about a NS16550 port
*
* @base: Base register address
* @reg_width: IO accesses size of registers (in bytes, 1 or 4)
* @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...)
* @reg_offset: Offset to start of registers (normally 0)
* @clock: UART base clock speed in Hz
* @fcr: Offset of FCR register (normally UART_FCR_DEFVAL)
*/
struct ns16550_plat {
unsigned long base;
int reg_width;
int reg_shift;
int reg_offset;
int clock;
uint32_t fcr;
};
struct ns16550 {
UART_REG(rbr); /* 0 */
UART_REG(ier); /* 1 */
UART_REG(fcr); /* 2 */
UART_REG(lcr); /* 3 */
UART_REG(mcr); /* 4 */
UART_REG(lsr); /* 5 */
UART_REG(msr); /* 6 */
UART_REG(spr); /* 7 */
#ifdef CONFIG_SOC_DA8XX
UART_REG(reg8); /* 8 */
UART_REG(reg9); /* 9 */
UART_REG(revid1); /* A */
UART_REG(revid2); /* B */
UART_REG(pwr_mgmt); /* C */
UART_REG(mdr1); /* D */
#else
UART_REG(mdr1); /* 8 */
UART_REG(reg9); /* 9 */
UART_REG(regA); /* A */
UART_REG(regB); /* B */
UART_REG(regC); /* C */
UART_REG(regD); /* D */
UART_REG(regE); /* E */
UART_REG(uasr); /* F */
UART_REG(scr); /* 10*/
UART_REG(ssr); /* 11*/
#endif
struct ns16550_plat *plat;
};
#define thr rbr
#define iir fcr
#define dll rbr
#define dlm ier
/*
* These are the definitions for the FIFO Control Register
*/
#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
/* Ingenic JZ47xx specific UART-enable bit. */
#define UART_FCR_UME 0x10
/* Clear & enable FIFOs */
#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \
UART_FCR_RXSR | \
UART_FCR_TXSR)
/*
* These are the definitions for the Modem Control Register
*/
#define UART_MCR_DTR 0x01 /* DTR */
#define UART_MCR_RTS 0x02 /* RTS */
#define UART_MCR_OUT1 0x04 /* Out 1 */
#define UART_MCR_OUT2 0x08 /* Out 2 */
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */
#define UART_MCR_DMA_EN 0x04
#define UART_MCR_TX_DFR 0x08
/*
* These are the definitions for the Line Control Register
*
* Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
* UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
*/
#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
#define UART_LCR_PEN 0x08 /* Parity eneble */
#define UART_LCR_EPS 0x10 /* Even Parity Select */
#define UART_LCR_STKP 0x20 /* Stick Parity */
#define UART_LCR_SBRK 0x40 /* Set Break */
#define UART_LCR_BKSE 0x80 /* Bank select enable */
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
/*
* These are the definitions for the Line Status Register
*/
#define UART_LSR_DR 0x01 /* Data ready */
#define UART_LSR_OE 0x02 /* Overrun */
#define UART_LSR_PE 0x04 /* Parity error */
#define UART_LSR_FE 0x08 /* Framing error */
#define UART_LSR_BI 0x10 /* Break */
#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
#define UART_LSR_TEMT 0x40 /* Xmitter empty */
#define UART_LSR_ERR 0x80 /* Error */
#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
#define UART_MSR_RI 0x40 /* Ring Indicator */
#define UART_MSR_DSR 0x20 /* Data Set Ready */
#define UART_MSR_CTS 0x10 /* Clear to Send */
#define UART_MSR_DDCD 0x08 /* Delta DCD */
#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
#define UART_MSR_DDSR 0x02 /* Delta DSR */
#define UART_MSR_DCTS 0x01 /* Delta CTS */
/*
* These are the definitions for the Interrupt Identification Register
*/
#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
#define UART_IIR_MSI 0x00 /* Modem status interrupt */
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
/*
* These are the definitions for the Interrupt Enable Register
*/
#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
/* useful defaults for LCR */
#define UART_LCR_8N1 0x03
void ns16550_init(struct ns16550 *com_port, int baud_divisor);
void ns16550_putc(struct ns16550 *com_port, char c);
char ns16550_getc(struct ns16550 *com_port);
int ns16550_tstc(struct ns16550 *com_port);
void ns16550_reinit(struct ns16550 *com_port, int baud_divisor);
/**
* ns16550_calc_divisor() - calculate the divisor given clock and baud rate
*
* Given the UART input clock and required baudrate, calculate the divisor
* that should be used.
*
* @port: UART port
* @clock: UART input clock speed in Hz
* @baudrate: Required baud rate
* @return baud rate divisor that should be used
*/
int ns16550_calc_divisor(struct ns16550 *port, int clock, int baudrate);
void _debug_uart_init(void);
void _debug_uart_putc(int ch);
int _debug_uart_getc(void);
void _debug_uart_printascii(const char *str);
void _debug_uart_init_early(void);
#endif /* __ns16550_h */
Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/uart.h
+29
View File
@@ -0,0 +1,29 @@
#pragma once
#include "memlayout.h"
#include "mmio_access.h"
#define UART0_BASE (0x09000000ULL)
#define UART0_REG(reg) ((volatile uint32_t*)(MMIO_P2V_WO(UART0_BASE + reg)))
// the UART control registers.
// pl011
#define DR 0x00
#define FR 0x18
#define FR_RXFE (1 << 4) // recieve fifo empty
#define FR_TXFF (1 << 5) // transmit fifo full
#define FR_RXFF (1 << 6) // recieve fifo full
#define FR_TXFE (1 << 7) // transmit fifo empty
#define IBRD 0x24
#define FBRD 0x28
#define LCRH 0x2c
#define LCRH_FEN (1 << 4)
#define LCRH_WLEN_8BIT (3 << 5)
#define CR 0x30
#define IMSC 0x38
#define INT_RX_ENABLE (1 << 4)
#define INT_TX_ENABLE (1 << 5)
#define ICR 0x44
#define UART_READ_REG(reg) (*(UART0_REG(reg)))
#define UART_WRITE_REG(reg, v) (*(UART0_REG(reg)) = (v))
Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c
+217
View File
@@ -0,0 +1,217 @@
/*
* COM1 NS16550 support
* originally from linux source (arch/powerpc/boot/ns16550.c)
* modified to use CONFIG_SYS_ISA_MEM and new defines
*/
#include "ns16550.h"
#include "mmio_access.h"
struct ns16550 g_ns16550_com_port = {0};
struct ns16550_plat g_ns16550_plat = {0};
unsigned long g_ns16550_uart_base = {0};
#define CONFIG_SYS_NS16550_UART_BASE 0x10000000
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_NS16550_CLK 24000000
#define CONFIG_SYS_NS16550_UART_BASE_VIRT MMIO_P2V_WO(CONFIG_SYS_NS16550_UART_BASE)
#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */
#define UART_MCRVAL (UART_MCR_DTR | \
UART_MCR_RTS) /* RTS/DTR */
#ifndef CONFIG_SYS_NS16550_IER
#define CONFIG_SYS_NS16550_IER 0x00
#endif /* CONFIG_SYS_NS16550_IER */
#define CONFIG_SYS_NS16550_PORT_MAPPED
#define readb(addr) \
({ unsigned char __v = (*(volatile unsigned char *)(addr)); __v; })
#define writeb(b, addr) (void)((*(volatile unsigned char *)(addr)) = (b))
static inline void serial_out_shift(void *addr, int shift, int value)
{
writeb(value, addr);
}
static inline int serial_in_shift(void *addr, int shift)
{
return readb(addr);
}
static void ns16550_writeb(struct ns16550 *port, int offset, int value)
{
struct ns16550_plat *plat = port->plat;
unsigned char *addr;
offset *= 1 << plat->reg_shift;
addr = (unsigned char *)plat->base + offset + plat->reg_offset;
serial_out_shift(addr, plat->reg_shift, value);
}
static int ns16550_readb(struct ns16550 *port, int offset)
{
struct ns16550_plat *plat = port->plat;
unsigned char *addr;
offset *= 1 << plat->reg_shift;
addr = (unsigned char *)plat->base + offset + plat->reg_offset;
return serial_in_shift(addr, plat->reg_shift);
}
static uint32_t ns16550_getfcr(struct ns16550 *port)
{
struct ns16550_plat *plat = port->plat;
return plat->fcr;
}
/* We can clean these up once everything is moved to driver model */
#define serial_out(value, addr) \
ns16550_writeb(com_port, \
(unsigned char *)addr - (unsigned char *)com_port, value)
#define serial_in(addr) \
ns16550_readb(com_port, \
(unsigned char *)addr - (unsigned char *)com_port)
/* Divide positive dividend by positive divisor and round to closest integer. */
#define DIV_ROUND_CLOSEST(x, divisor) \
(((x) + ((divisor) / 2)) / (divisor))
int ns16550_calc_divisor(struct ns16550 *port, int clock, int baudrate)
{
const unsigned int mode_x_div = 16;
return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
}
static void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor)
{
/* to keep serial format, read lcr before writing BKSE */
int lcr_val = serial_in(&com_port->lcr) & ~UART_LCR_BKSE;
serial_out(UART_LCR_BKSE | lcr_val, &com_port->lcr);
serial_out(baud_divisor & 0xff, &com_port->dll);
serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
serial_out(lcr_val, &com_port->lcr);
}
void ns16550_init(struct ns16550 *com_port, int baud_divisor)
{
while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT))
;
serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
serial_out(UART_MCRVAL, &com_port->mcr);
serial_out(ns16550_getfcr(com_port), &com_port->fcr);
/* initialize serial config to 8N1 before writing baudrate */
serial_out(UART_LCRVAL, &com_port->lcr);
if (baud_divisor != -1)
ns16550_setbrg(com_port, baud_divisor);
}
void ns16550_putc(struct ns16550 *com_port, char c)
{
while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0)
;
serial_out(c, &com_port->thr);
}
char ns16550_getc(struct ns16550 *com_port)
{
while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0)
;
return serial_in(&com_port->rbr);
}
int ns16550_tstc(struct ns16550 *com_port)
{
return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0;
}
static void ns16550_plat_init(void)
{
struct ns16550_plat *plat = &g_ns16550_plat;
/* refer jh7110 u-boot/arch/riscv/dts/jh7110.dtsi */
plat->base = g_ns16550_uart_base;
plat->reg_offset = 0;
plat->reg_shift = 2;
plat->reg_width = 4;
plat->clock = CONFIG_SYS_NS16550_CLK;
plat->fcr = UART_FCR_DEFVAL;
}
static void ns16550_serial_init(void)
{
struct ns16550_plat *plat = &g_ns16550_plat;
struct ns16550 *com_port = &g_ns16550_com_port;
ns16550_plat_init();
com_port->plat = plat;
ns16550_init(com_port, -1);
}
static void ns16550_serial_setbrg(int baudrate)
{
struct ns16550 *const com_port = &g_ns16550_com_port;
struct ns16550_plat *plat = com_port->plat;
int clock_divisor;
clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate);
ns16550_setbrg(com_port, clock_divisor);
}
void _debug_uart_init(void)
{
int baudrate = CONFIG_BAUDRATE;
g_ns16550_uart_base = CONFIG_SYS_NS16550_UART_BASE_VIRT;
ns16550_serial_init();
ns16550_serial_setbrg(baudrate);
// _debug_uart_printascii("_debug_uart_init success.\n");
}
void _debug_uart_init_early(void)
{
int baudrate = CONFIG_BAUDRATE;
g_ns16550_uart_base = CONFIG_SYS_NS16550_UART_BASE;
ns16550_serial_init();
ns16550_serial_setbrg(baudrate);
// _debug_uart_printascii("_debug_uart_init_early success.\n");
}
void _debug_uart_putc(int ch)
{
struct ns16550* com_port = &g_ns16550_com_port;
if (ch == '\n')
ns16550_putc(com_port, '\r');
ns16550_putc(com_port, ch);
}
int _debug_uart_getc(void)
{
struct ns16550* com_port = &g_ns16550_com_port;
return ns16550_getc(com_port);
}
static void _printch(int ch)
{
if (ch == '\n')
_debug_uart_putc('\r');
_debug_uart_putc(ch);
}
void _debug_uart_printascii(const char *str)
{
while (*str)
_printch(*str++);
}
Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/uart.c
+45
View File
@@ -0,0 +1,45 @@
//
// low-level driver routines for pl011 UART.
//
#include "uart.h"
#include "actracer.h"
#include "ns16550.h"
#include "uart_common_ope.h"
// the UART control registers are memory-mapped
// at address UART0. this macro returns the
// address of one of the registers.
void uartinit(void)
{
_debug_uart_init();
}
void uartputc(uint8_t c)
{
_debug_uart_putc((int)c);
}
static uint8_t uartgetc(void)
{
return (uint8_t)_debug_uart_getc();
}
static uint32_t UartGetIrqnum()
{
return 0;
}
static struct XiziSerialDriver hardkernel_serial_driver = {
.sys_serial_init = uartinit,
.get_serial_irqnum = UartGetIrqnum,
.putc = uartputc,
.getc = uartgetc,
};
struct XiziSerialDriver* hardkernel_uart_init(struct TraceTag* hardkernel_tag)
{
hardkernel_serial_driver.sys_serial_init();
return &hardkernel_serial_driver;
}
Ubiquitous/XiZi_AIoT/hardkernel/uart/uart_common_ope.c
+24 -1
View File
@@ -895,4 +895,27 @@ int fctprintf(void (*out)(char character, void* arg), void* arg, const char* for
const int ret = _vsnprintf(_out_fct, (char*)(uintptr_t)&out_fct_wrap, (size_t)-1, format, va);
va_end(va);
return ret;
}
}
///////////////////////////////////////////////////////////////////////////////
__attribute__((weak)) void _debug_uart_putc(int ch) {}
static inline void _out_char_early(char character, void* buffer, size_t idx, size_t maxlen)
{
(void)buffer;
(void)idx;
(void)maxlen;
if (character) {
_debug_uart_putc(character);
}
}
int printf_early(const char* format, ...)
{
va_list va;
va_start(va, format);
char buffer[1];
const int ret = _vsnprintf(_out_char_early, buffer, (size_t)-1, format, va);
va_end(va);
return ret;
}