From bac1ec5b717377f8866ebcd7c0a6994f2a5c734d Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 15 Oct 2024 10:35:00 +0800 Subject: [PATCH 01/54] Add xiuos jh7110 code can be compiled. --- Ubiquitous/XiZi_AIoT/.config | 18 -- Ubiquitous/XiZi_AIoT/Makefile | 8 +- Ubiquitous/XiZi_AIoT/hardkernel/arch/Makefile | 5 + .../XiZi_AIoT/hardkernel/arch/riscv/Makefile | 5 + .../hardkernel/arch/riscv/rv64gc/Makefile | 4 + .../arch/riscv/rv64gc/context_switch.S | 30 ++ .../hardkernel/arch/riscv/rv64gc/core.c | 74 +++++ .../hardkernel/arch/riscv/rv64gc/core.h | 218 +++++++++++++++ .../riscv/rv64gc/preboot_for_jh7110/Makefile | 6 + .../riscv/rv64gc/preboot_for_jh7110/boot.S | 34 +++ .../riscv/rv64gc/preboot_for_jh7110/config.mk | 17 ++ .../riscv/rv64gc/preboot_for_jh7110/cortex.S | 34 +++ .../preboot_for_jh7110/include/cortex.h | 241 ++++++++++++++++ .../preboot_for_jh7110/include/registers.h | 110 ++++++++ .../rv64gc/preboot_for_jh7110/jh7110.lds | 136 +++++++++ .../riscv/rv64gc/preboot_for_jh7110/smp.c | 84 ++++++ .../rv64gc/preboot_for_jh7110/xizi_smp.S | 17 ++ .../XiZi_AIoT/hardkernel/cache/L1/Makefile | 5 + .../hardkernel/cache/L1/riscv/Makefile | 5 + .../hardkernel/cache/L1/riscv/rv64gc/Makefile | 3 + .../hardkernel/cache/L1/riscv/rv64gc/cache.S | 184 +++++++++++++ .../cache/L1/riscv/rv64gc/l1_cache.c | 81 ++++++ .../cache/L1/riscv/rv64gc/l1_cache.h | 76 +++++ .../XiZi_AIoT/hardkernel/clock/Makefile | 7 +- .../XiZi_AIoT/hardkernel/clock/riscv/Makefile | 5 + .../hardkernel/clock/riscv/rv64gc/Makefile | 4 + .../hardkernel/clock/riscv/rv64gc/clock.c | 95 +++++++ .../clock/riscv/rv64gc/jh7110/Makefile | 4 + .../clock/riscv/rv64gc/jh7110/clock.c | 95 +++++++ .../rv64gc/jh7110/include/generic_timer.h | 54 ++++ Ubiquitous/XiZi_AIoT/hardkernel/intr/Makefile | 6 + .../XiZi_AIoT/hardkernel/intr/riscv/Makefile | 5 + .../hardkernel/intr/riscv/rv64gc/Makefile | 9 + .../intr/riscv/rv64gc/error_debug.c | 67 +++++ .../intr/riscv/rv64gc/gicv3/Makefile | 3 + .../intr/riscv/rv64gc/gicv3/gicv3.c | 260 ++++++++++++++++++ .../riscv/rv64gc/gicv3/gicv3_common_opa.h | 140 ++++++++++ .../intr/riscv/rv64gc/gicv3/gicv3_registers.h | 59 ++++ .../intr/riscv/rv64gc/hard_spinlock.S | 72 +++++ .../riscv/rv64gc/jh7110/exception_registers.h | 68 +++++ .../intr/riscv/rv64gc/jh7110/irq_numbers.h | 110 ++++++++ .../intr/riscv/rv64gc/jh7110/trap.c | 121 ++++++++ .../intr/riscv/rv64gc/jh7110/trap_common.c | 137 +++++++++ .../hardkernel/intr/riscv/rv64gc/trampoline.S | 112 ++++++++ Ubiquitous/XiZi_AIoT/hardkernel/mmu/Makefile | 5 + .../XiZi_AIoT/hardkernel/mmu/riscv/Makefile | 4 + .../hardkernel/mmu/riscv/rv64gc/Makefile | 3 + .../hardkernel/mmu/riscv/rv64gc/bootmmu.c | 148 ++++++++++ .../hardkernel/mmu/riscv/rv64gc/include/mmu.h | 118 ++++++++ .../mmu/riscv/rv64gc/jh7110/memlayout.h | 85 ++++++ .../hardkernel/mmu/riscv/rv64gc/mmu.c | 93 +++++++ .../mmu/riscv/rv64gc/pagetable_attr.c | 80 ++++++ Ubiquitous/XiZi_AIoT/hardkernel/uart/Makefile | 6 + .../XiZi_AIoT/hardkernel/uart/riscv/Makefile | 5 + .../hardkernel/uart/riscv/rv64gc/Makefile | 3 + .../riscv/rv64gc/uart_io_for_jh7110/Makefile | 3 + .../uart_io_for_jh7110/include/ns16550.h | 198 +++++++++++++ .../rv64gc/uart_io_for_jh7110/include/uart.h | 29 ++ .../riscv/rv64gc/uart_io_for_jh7110/ns16550.c | 111 ++++++++ .../riscv/rv64gc/uart_io_for_jh7110/uart.c | 45 +++ Ubiquitous/XiZi_AIoT/path_kernel.mk | 15 + Ubiquitous/XiZi_AIoT/softkernel/load_apps.S | 6 +- .../XiZi_AIoT/softkernel/memory/Makefile | 3 + 63 files changed, 3764 insertions(+), 24 deletions(-) delete mode 100644 Ubiquitous/XiZi_AIoT/.config create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/context_switch.S create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/cortex.S create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/cortex.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/registers.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/smp.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/xizi_smp.S create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/cache.S create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/l1_cache.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/l1_cache.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/clock.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clock.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/include/generic_timer.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/error_debug.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_common_opa.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_registers.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/exception_registers.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/irq_numbers.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/mmu.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/pagetable_attr.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/uart.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/uart.c diff --git a/Ubiquitous/XiZi_AIoT/.config b/Ubiquitous/XiZi_AIoT/.config deleted file mode 100644 index a40a1d2b4..000000000 --- a/Ubiquitous/XiZi_AIoT/.config +++ /dev/null @@ -1,18 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# XiZi_AIoT Project Configuration -# -CONFIG_BOARD_IMX6Q_SABRELITE=y -CONFIG_ARCH_ARM=y - -# -# imx6q sabrelite feature -# - -# -# Lib -# -CONFIG_LIB=y -CONFIG_LIB_POSIX=y -CONFIG_LIB_NEWLIB=y -# CONFIG_LIB_MUSLLIB is not set diff --git a/Ubiquitous/XiZi_AIoT/Makefile b/Ubiquitous/XiZi_AIoT/Makefile index 4bc6e3b00..c78e94350 100755 --- a/Ubiquitous/XiZi_AIoT/Makefile +++ b/Ubiquitous/XiZi_AIoT/Makefile @@ -3,7 +3,7 @@ MAKEFLAGS += --no-print-directory .PHONY:all clean distclean show_info menuconfig .PHONY:COMPILE_APP COMPILE_KERNEL -riscv_support := +riscv_support := jh7110 arm_support += imx6q-sabrelite zynq7000-zc702 3568 emulator_support += support := $(riscv_support) $(arm_support) $(emulator_support) @@ -37,13 +37,17 @@ endif ifneq ($(findstring $(BOARD), 3568), ) include $(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a55/preboot_for_$(BOARD)/config.mk endif +ifneq ($(findstring $(BOARD), jh7110), ) +include $(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/preboot_for_$(BOARD)/config.mk +endif export BSP_BUILD_DIR := $(KERNEL_ROOT) export HOSTTOOLS_DIR ?= $(KERNEL_ROOT)/services/tools/hosttools export CONFIG2H_EXE ?= $(HOSTTOOLS_DIR)/xsconfig.sh export CPPPATHS export SRC_APP_DIR := ../../APP_Framework -export SRC_KERNEL_DIR := hardkernel kernel_actracer services softkernel +# export SRC_KERNEL_DIR := hardkernel kernel_actracer services softkernel +export SRC_KERNEL_DIR := hardkernel kernel_actracer softkernel export SRC_DIR := $(SRC_KERNEL_DIR) export LIBCC diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/Makefile index 2765b4d99..4972e6661 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/Makefile @@ -1,3 +1,8 @@ +ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), ) SRC_DIR := arm +endif +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := riscv +endif include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/Makefile new file mode 100644 index 000000000..dd587adc4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/Makefile @@ -0,0 +1,5 @@ +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := rv64gc +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/Makefile new file mode 100644 index 000000000..f4cbabfc4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/Makefile @@ -0,0 +1,4 @@ +SRC_DIR := preboot_for_$(BOARD) +SRC_FILES := context_switch.S core.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/context_switch.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/context_switch.S new file mode 100644 index 000000000..681c13524 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/context_switch.S @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file context_switch.S + * @brief task context switch functions + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.4.10 + */ + +/************************************************* +File name: context_switch.S +Description: task context switch functions +Others: +History: +*************************************************/ +.global context_switch + +context_switch: + nop + ret \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.c b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.c new file mode 100644 index 000000000..e677d92d6 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file core.c + * @brief spl boot function + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.23 + */ + +/************************************************* +File name: core.c +Description: cortex-a9 core function, include cpu registers operations、core boot +Others: +History: +1. Date: 2024-04-23 +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ + +/*********cortex-a55 general register************ + EL0 | EL1 | EL2 | EL3 + + x0; + x1; + x2; + x3; + x4; + x5; + x6; + x7; + x8; + x9; + x10; + x11; + x12; + x13; + x14; + x15; + x16; + x17; + x18; + x19; + x20; + x21; + x22; + x23; + x24; + x25; + x26; + x27; + x28; + x29; + x30; +*********cortex-a55 special register************ + XZR + PC + SP_EL0 SP_EL1 SP_EL2 SP_EL3 + SPSR_EL1 SPSR_EL2 SPSR_EL3 + ELR_EL1 ELR_EL2 ELR_EL3 +************************************************/ + +#include "core.h" \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h new file mode 100644 index 000000000..9267f1f04 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file core.h + * @brief cortex-a55 core function + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.11 + */ + +/************************************************* +File name: core.h +Description: cortex-a55 core function +Others: +History: +Author: AIIT XUOS Lab +Modification: +*************************************************/ + +#pragma once + +// Interrupt control bits +#define NO_INT 0x80 // disable IRQ. +#define DIS_INT 0xc0 // disable both IRQ and FIQ. + +#define MODE_STACK_SIZE 0x1000 + +//! @name SPSR fields +//@{ +#define SPSR_EL1_N (1 << 31) //!< Negative +#define SPSR_EL1_Z (1 << 30) //!< Zero +#define SPSR_EL1_C (1 << 29) //!< Carry +#define SPSR_EL1_V (1 << 28) //!< Overflow +#define SPSR_EL1_SS (1 << 21) //!< Software Step +#define SPSR_EL1_IL (1 << 20) //!< Illegal Exception +#define SPSR_EL1_D (1 << 9) //!< Debug mask +#define SPSR_EL1_A (1 << 8) //!< SError mask +#define SPSR_EL1_I (1 << 7) //!< IRQ mask +#define SPSR_EL1_F (1 << 6) //!< FIQ mask +#define SPSR_EL1_M (1 << 4) //!< Execution state 0=64-bit 1=32-bit +#define SPSR_EL1_MODE (0x7) //!< Current processor mode +//@} + +//! @name Interrupt enable bits in SPSR +//@{ +#define I_BIT 0x80 //!< When I bit is set, IRQ is disabled +#define F_BIT 0x40 //!< When F bit is set, FIQ is disabled +//@} + +// ARM Modes t indicates selecting sp_el0 pointer, h indicates selecting sp_eln pointer +#define SPSR_MODE_MASK 0x0f +#define ARM_MODE_EL0_t 0x00 +#define ARM_MODE_EL1_t 0x04 +#define ARM_MODE_EL1_h 0x05 +#define ARM_MODE_EL2_t 0x08 +#define ARM_MODE_EL2_h 0x09 +#define ARM_MODE_EL3_t 0x0c +#define ARM_MODE_EL3_h 0x0d + +#ifndef __ASSEMBLER__ +#include +#include + +#include "cortex.h" + +#define NR_CPU 4 // maximum number of CPUs + +__attribute__((always_inline)) static inline uint64_t EL0_mode() // Set ARM mode to EL0 +{ + uint64_t val = 0; + + return val; +} + +__attribute__((always_inline, optimize("O0"))) static inline void cpu_into_low_power() +{ + WFE(); +} + +__attribute__((always_inline, optimize("O0"))) static inline void cpu_leave_low_power() +{ + SEV(); +} + +struct context { + uint64_t sp; + + /* callee register */ + uint64_t x18; + uint64_t x19; + uint64_t x20; + uint64_t x21; + uint64_t x22; + uint64_t x23; + uint64_t x24; + uint64_t x25; + uint64_t x26; + uint64_t x27; + uint64_t x28; + uint64_t x29; + uint64_t x30; +}; + +/// @brief init task context, set return address to trap return +/// @param ctx +extern void task_prepare_enter(void); +__attribute__((__always_inline__)) static inline void arch_init_context(struct context* ctx) +{ + memset(ctx, 0, sizeof(*ctx)); + ctx->x30 = (uintptr_t)(task_prepare_enter + 4); +} + +struct trapframe { + uint64_t x0; + uint64_t x1; + uint64_t x2; + uint64_t x3; + uint64_t x4; + uint64_t x5; + uint64_t x6; + uint64_t x7; + uint64_t x8; + uint64_t x9; + uint64_t x10; + uint64_t x11; + uint64_t x12; + uint64_t x13; + uint64_t x14; + uint64_t x15; + uint64_t x16; + uint64_t x17; + uint64_t x18; + uint64_t x19; + uint64_t x20; + uint64_t x21; + uint64_t x22; + uint64_t x23; + uint64_t x24; + uint64_t x25; + uint64_t x26; + uint64_t x27; + uint64_t x28; + uint64_t x29; + uint64_t x30; + uint64_t pc; + uint64_t spsr; + uint64_t sp; +}; + +/// @brief init task trapframe +/// @param tf +/// @param sp +/// @param pc +__attribute__((__always_inline__)) static inline void arch_init_trapframe(struct trapframe* tf, uintptr_t sp, uintptr_t pc) +{ + memset(tf, 0, sizeof(*tf)); + tf->sp = sp; + tf->spsr = EL0_mode(); + tf->pc = pc; +} + +/// @brief set pc and sp to trapframe +/// @param tf +/// @param sp +/// @param pc +__attribute__((__always_inline__)) static inline void arch_trapframe_set_sp_pc(struct trapframe* tf, uintptr_t sp, uintptr_t pc) +{ + tf->sp = sp; + tf->pc = pc; +} + +/// @brief set params of main(int argc, char** argv) to trapframe (argc, argv) +/// @param tf +/// @param argc +/// @param argv +__attribute__((__always_inline__)) static inline void arch_set_main_params(struct trapframe* tf, int argc, uintptr_t argv) +{ + tf->x0 = (uint64_t)argc; + tf->x1 = (uint64_t)argv; +} + +/// @brief retrieve params to trapframe (up to max number of 6) and pass it to syscall() +/// @param sys_num +/// @param param1 +/// @param param2 +/// @param param3 +/// @param param4 +/// @param param5 +/// @return +extern int syscall(int sys_num, uintptr_t param1, uintptr_t param2, uintptr_t param3, uintptr_t param4); +__attribute__((__always_inline__)) static inline int arch_syscall(struct trapframe* tf, int* syscall_num) +{ + // call syscall + *syscall_num = tf->x0; + return syscall(*syscall_num, tf->x1, tf->x2, tf->x3, tf->x4); +} + +/// @brief set return reg to trapframe +/// @param tf +/// @param ret +__attribute__((__always_inline__)) static inline void arch_set_return(struct trapframe* tf, int ret) +{ + tf->x0 = (uint64_t)ret; +} + +void cpu_start_secondary(uint8_t cpu_id); +void start_smp_cache_broadcast(int cpu_id); +#endif diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/Makefile new file mode 100644 index 000000000..aed0b41a7 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/Makefile @@ -0,0 +1,6 @@ +SRC_FILES := boot.S \ + xizi_smp.S \ + smp.c \ + cortex.S + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S new file mode 100644 index 000000000..e50d8d63d --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +#include "core.h" + +#define HCR_VALUE (1 << 31) +#define SPSR_EL2_VALUE (7 << 6) | (5 << 0) +#define SCTLR_EL1_VALUE (0x30D00800) + +.section ".text", "ax" +.globl _boot_start +.globl primary_cpu_init + + +_boot_start: + + j primary_cpu_init + + j . + +primary_cpu_init: + + j bootmain + + + diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk new file mode 100644 index 000000000..62bfef792 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk @@ -0,0 +1,17 @@ +# export CROSS_COMPILE ?= riscv64-linux-gnu- +export CROSS_COMPILE ?= riscv64-unknown-elf- +export ARCH = riscv + +# export KBUILD_CFLAGS := -Wall -Wundef -Werror=strict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -fshort-wchar -fno-PIE -Werror=implicit-function-declaration -Werror=implicit-int -Werror=return-type -Wno-format-security -std=gnu89 -Wno-sign-compare -fno-asynchronous-unwind-tables -fno-delete-null-pointer-checks -fno-stack-protector -Wno-main -fomit-frame-pointer -Wdeclaration-after-statement -Wvla -Wno-pointer-sign -Wno-array-bounds -fno-strict-overflow -fno-stack-check -Werror=date-time +export KBUILD_CFLAGS := -Wall -Wundef -Wno-trigraphs -fno-strict-aliasing -fno-common -fshort-wchar -fno-PIE -Werror=implicit-function-declaration -Werror=implicit-int -Werror=return-type -Wno-format-security -std=gnu89 -Wno-sign-compare -fno-asynchronous-unwind-tables -fno-delete-null-pointer-checks -fno-stack-protector -Wno-main -fomit-frame-pointer -Wvla -Wno-pointer-sign -Wno-array-bounds -fno-strict-overflow -fno-stack-check -Werror=date-time +export KBUILD_CPPFLAGS := -D__KERNEL__ +export KBUILD_AFLAGS := -D__ASSEMBLY__ -fno-PIE -m64 + +export DEVICE := +export CFLAGS := $(KBUILD_CFLAGS) -std=c11 +# .vmlinux.cmd:1:cmd_vmlinux := sh scripts/link-vmlinux.sh "riscv64-linux-gnu-ld" " -melf64lriscv" " --build-id=sha1"; +#export LFLAGS := -melf64lriscv --build-id=sha1 $(KERNEL_ROOT)/hardkernel/arch/riscv/preboot_for_jh7110/jh7110.lds +export LFLAGS := -T $(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds +export CXXFLAGS := + +export DEFINES := diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/cortex.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/cortex.S new file mode 100644 index 000000000..7fb1e6dcc --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/cortex.S @@ -0,0 +1,34 @@ +/*! + * @file cortexA55.s + * @brief This file contains cortexA55 functions + * + */ +/************************************************* +File name: cortexA55.S +Description: This file contains cortexA9 functions +Others: +History: +1. Date: 2024-05-08 +Author: AIIT XUOS Lab +Modification: +1. No modifications +*************************************************/ + .section ".text","ax" + + .global cpu_get_current + # int cpu_get_current(void)@ + # get current CPU ID + .func cpu_get_current +cpu_get_current: + ret + .endfunc + + .global psci_call +psci_call: + ret + + +# ------------------------------------------------------------ +# End of cortexA55.s +# ------------------------------------------------------------ + .end \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/cortex.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/cortex.h new file mode 100644 index 000000000..494fe7a6f --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/cortex.h @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * @file cortex_a55.h + * @brief some cortex A55 core functions + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.24 + */ + +/************************************************* +File name: cortex_a55.h +Description: some cortex A55 core functions +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. No modifications +*************************************************/ + +#if !defined(__CORTEX_A55_H__) +#define __CORTEX_A55_H__ + +#include +#include +#include + +//! @name Instruction macros +//@{ +//#define NOP() __asm__ volatile("nop\n\t") +//#define WFI() __asm__ volatile("wfi\n\t") +//#define WFE() __asm__ volatile("wfe\n\t") +//#define SEV() __asm__ volatile("sev\n\t") +//#define DMB() __asm__ volatile("dmb ish\n\t") +//#define DSB() __asm__ volatile("dsb ish\n\t") +//#define ISB() __asm__ volatile("isb\n\t") +#define NOP() __asm__ volatile("nop\n\t") +#define WFI() __asm__ volatile("nop\n\t") +#define WFE() __asm__ volatile("nop\n\t") +#define SEV() __asm__ volatile("nop\n\t") +#define DMB() __asm__ volatile("nop\n\t") +#define DSB() __asm__ volatile("nop\n\t") +#define ISB() __asm__ volatile("nop\n\t") + +#define _ARM_MRS(coproc, opcode1, Rt, CRn, CRm, opcode2) \ + __asm__ volatile("mrc p" #coproc ", " #opcode1 ", %[output], c" #CRn ", c" #CRm ", " #opcode2 "\n" : [output] "=r"(Rt)) + +#define _ARM_MSR(coproc, opcode1, Rt, CRn, CRm, opcode2) \ + __asm__ volatile("mcr p" #coproc ", " #opcode1 ", %[input], c" #CRn ", c" #CRm ", " #opcode2 "\n" ::[input] "r"(Rt)) + +// #define WriteReg(value, address) (*(volatile unsigned int*)(address) = (value)) +// #define ReadReg(address) (*(volatile unsigned int*)(address)) + +#if defined(__cplusplus) +extern "C" { +#endif + +//! @name Misc +//@{ +//! @brief Enable or disable the IRQ and FIQ state. +bool arm_set_interrupt_state(bool enable); + +//! @brief Get current CPU ID. +int cpu_get_current(void); + +//! @brief Enable the NEON MPE. +void enable_neon_fpu(void); + +//! @brief Disable aborts on unaligned accesses. +void disable_strict_align_check(void); + +//! @brief Get base address of private perpherial space. +//! +//! @return The address of the ARM CPU's private peripherals. +// uint32_t get_arm_private_peripheral_base(void); +//@} + +//! @name Data cache operations +//@{ + +//! @brief Check if dcache is enabled or disabled. +int arm_dcache_state_query(); + +//! @brief Enables data cache at any available cache level. +//! +//! Works only if MMU is enabled! +void arm_dcache_enable(); + +//! @brief Disables the data cache at any available cache level. +void arm_dcache_disable(); + +//! @brief Invalidates the entire data cache. +void arm_dcache_invalidate(); + +//! @brief Invalidate a line of data cache. +void arm_dcache_invalidate_line(const void* addr); + +//! @brief Invalidate a number of lines of data cache. +//! +//! Number of lines depends on length parameter and size of line. +//! Size of line for A9 L1 cache is 32B. +void arm_dcache_invalidate_mlines(const void* addr, size_t length); + +//! @brief Flush (clean) all lines of cache (all sets in all ways). +void arm_dcache_flush(); + +//! @brief Flush (clean) one line of cache. +void arm_dcache_flush_line(const void* addr); + +// @brief Flush (clean) multiple lines of cache. +//! +//! Number of lines depends on length parameter and size of line. +void arm_dcache_flush_mlines(const void* addr, size_t length); +//@} + +//! @name Instrution cache operations +//@{ + +//! @brief Check if icache is enabled or disabled. +int arm_icache_state_query(); + +//! @brief Enables instruction cache at any available cache level. +//! +//! Works without enabled MMU too! +void arm_icache_enable(); + +//! @brief Disables the instruction cache at any available cache level. +void arm_icache_disable(); + +//! @brief Invalidates the entire instruction cache. +void arm_icache_invalidate(); + +//! @brief Invalidates the entire instruction cache inner shareable. +void arm_icache_invalidate_is(); + +//! @brief Invalidate a line of the instruction cache. +void arm_icache_invalidate_line(const void* addr); + +//! @brief Invalidate a number of lines of instruction cache. +//! +//! Number of lines depends on length parameter and size of line. +void arm_icache_invalidate_mlines(const void* addr, size_t length); +//@} + +//! @name TLB operations +//@{ +//! @brief Invalidate entire unified TLB. +void arm_unified_tlb_invalidate(void); + +//! @brief Invalidate entire unified TLB Inner Shareable. +void arm_unified_tlb_invalidate_is(void); +//@} + +//! @name Branch predictor operations +//@{ +//! @brief Enable branch prediction. +void arm_branch_prediction_enable(void); + +//! @brief Disable branch prediction. +void arm_branch_prediction_disable(void); + +//! @brief Invalidate entire branch predictor array. +void arm_branch_target_cache_invalidate(void); + +//! @brief Invalidate entire branch predictor array Inner Shareable +void arm_branch_target_cache_invalidate_is(void); +//@} + +//! @name SCU +//@{ +//! @brief Enables the SCU. +void scu_enable(void); + +//! @brief Set this CPU as participating in SMP. +void scu_join_smp(void); + +//! @brief Set this CPU as not participating in SMP. +void scu_leave_smp(void); + +//! @brief Determine which CPUs are participating in SMP. +//! +//! The return value is 1 bit per core: +//! - bit 0 - CPU 0 +//! - bit 1 - CPU 1 +//! - etc... +unsigned int scu_get_cpus_in_smp(void); + +//! @brief Enable the broadcasting of cache & TLB maintenance operations. +//! +//! When enabled AND in SMP, broadcast all "inner sharable" +//! cache and TLM maintenance operations to other SMP cores +void scu_enable_maintenance_broadcast(void); + +//! @brief Disable the broadcasting of cache & TLB maintenance operations. +void scu_disable_maintenance_broadcast(void); + +//! @brief Invalidates the SCU copy of the tag rams for the specified core. +//! +//! Typically only done at start-up. +//! Possible flow: +//! - Invalidate L1 caches +//! - Invalidate SCU copy of TAG RAMs +//! - Join SMP +//! +//! @param cpu 0x0=CPU 0, 0x1=CPU 1, etc... +//! @param ways The ways to invalidate. Pass 0xf to invalidate all ways. +void scu_secure_invalidate(unsigned int cpu, unsigned int ways); +//@} + +#if defined(__cplusplus) +} +#endif + +#endif //__CORTEX_A55_H__ \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/registers.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/registers.h new file mode 100644 index 000000000..d3c08b923 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/registers.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +#ifndef INC_SYSREGS_H_ +#define INC_SYSREGS_H_ + +/* SCTLR_EL1, System Control Register (EL1). */ +#define SCTLR_RESERVED \ + ((3 << 28) | (3 << 22) | (1 << 20) | (1 << 11) | (1 << 8) | (1 << 7)) +#define SCTLR_EE_LITTLE_ENDIAN (0 << 25) +#define SCTLR_E0E_LITTLE_ENDIAN (0 << 24) +#define SCTLR_I_CACHE (1 << 12) +#define SCTLR_D_CACHE (1 << 2) +#define SCTLR_MMU_DISABLED (0 << 0) +#define SCTLR_MMU_ENABLED (1 << 0) + +#define SCTLR_VALUE_MMU_DISABLED \ + (SCTLR_RESERVED | SCTLR_EE_LITTLE_ENDIAN | SCTLR_E0E_LITTLE_ENDIAN \ + | SCTLR_I_CACHE | SCTLR_D_CACHE | SCTLR_MMU_DISABLED) + +/* HCR_EL2, Hypervisor Configuration Register (EL2). */ +#define HCR_RW (1 << 31) +#define HCR_VALUE HCR_RW + +/* CPACR_EL1, Architectural Feature Access Control Register. */ +#define CPACR_FP_EN (3 << 20) +#define CPACR_TRACE_EN (0 << 28) +#define CPACR_VALUE (CPACR_FP_EN | CPACR_TRACE_EN) + +/* SCR_EL3, Secure Configuration Register (EL3). */ +#define SCR_RESERVED (3 << 4) +#define SCR_RW (1 << 10) +#define SCR_HCE (1 << 8) +#define SCR_SMD (1 << 7) +#define SCR_NS (1 << 0) +#define SCR_VALUE (SCR_RESERVED | SCR_RW | SCR_HCE | SCR_SMD | SCR_NS) + +/* SPSR_EL1/2/3, Saved Program Status Register. */ +#define SPSR_MASK_ALL (7 << 6) +#define SPSR_EL1h (5 << 0) +#define SPSR_EL2h (9 << 0) +#define SPSR_EL3_VALUE (SPSR_MASK_ALL | SPSR_EL2h) +#define SPSR_EL2_VALUE (SPSR_MASK_ALL | SPSR_EL1h) + +/* Exception Class in ESR_EL1. */ +#define EC_SHIFT 26 +#define EC_UNKNOWN 0x00 +#define EC_SVC64 0x15 +#define EC_DABORT 0x24 +#define EC_IABORT 0x20 + +#define PTE_VALID 1 // level 0,1,2 descriptor: valid +#define PTE_TABLE 2 // level 0,1,2 descriptor: table +#define PTE_V 3 // level 3 descriptor: valid +// PTE_AF(Access Flag) +// +// 0 -- this block entry has not yet. +// 1 -- this block entry has been used. +#define PTE_AF (1 << 10) +// PTE_AP(Access Permission) is 2bit field. +// EL0 EL1 +// 00 -- x RW +// 01 -- RW RW +// 10 -- x RO +// 11 -- RO RO +#define PTE_AP(ap) (((ap) & 3) << 6) +#define PTE_U PTE_AP(1) +#define PTE_RO PTE_AP(2) +#define PTE_URO PTE_AP(3) +#define PTE_PXN (1UL << 53) // Privileged eXecute Never +#define PTE_UXN (1UL << 54) // Unprivileged(user) eXecute Never +#define PTE_XN (PTE_PXN | PTE_UXN) // eXecute Never + +// attribute index +// index is set by mair_el1 +#define AI_DEVICE_nGnRnE_IDX 0x0 +#define AI_NORMAL_NC_IDX 0x1 + +// memory type +#define MT_DEVICE_nGnRnE 0x0 +#define MT_NORMAL_NC 0x44 + +#define PTE_INDX(i) (((i) & 7) << 2) +#define PTE_DEVICE PTE_INDX(AI_DEVICE_nGnRnE_IDX) +#define PTE_NORMAL PTE_INDX(AI_NORMAL_NC_IDX) + +// shift a physical address to the right place for a PTE. +#define PA2PTE(pa) ((uint64_t)(pa) & 0xfffffffff000) +#define PTE2PA(pte) ((uint64_t)(pte) & 0xfffffffff000) + +#define PTE_FLAGS(pte) ((pte) & (0x600000000003ff)) + +// translation control register +// #define TCR_T0SZ(n) ((n) & 0x3f) +// #define TCR_TG0(n) (((n) & 0x3) << 14) +// #define TCR_T1SZ(n) (((n) & 0x3f) << 16) +// #define TCR_TG1(n) (((n) & 0x3) << 30) +// #define TCR_IPS(n) (((n) & 0x7) << 32) + +#define ISS_MASK 0xFFFFFF + +#endif // INC_SYSREGS_H_ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds new file mode 100644 index 000000000..fa95d5271 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2010-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file jh7110.lds + * @brief + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.10.10 + */ + +OUTPUT_ARCH(riscv) +/* ENTRY(_start) */ +ENTRY( _boot_start ) + +BOOT_STACK_SIZE = 0x4000; +MEMORY { + phy_ddr3 (rwx) : ORIGIN = 0x10000000, LENGTH = 1024M + vir_ddr3 (rwx) : ORIGIN = 0x000000601040E000, LENGTH = 1024M +} + + +SECTIONS +{ +/* . = ((((-1))) - 0x80000000 + 1); + _start = .; + .head.text : AT(ADDR(.head.text) - ((((-1))) - 0x80000000 + 1)) { KEEP(*(.head.text)) } +*/ + + .start_sec : { + . = ORIGIN(phy_ddr3); + /* initialization start checkpoint. */ + + _start_image_addr = .; + + boot.o(.text) + bootmmu.o(.text .text.*) + /* ns16550.o(.text .text.*) */ + + boot.o(.rodata .rodata.*) + bootmmu.o(.rodata .rodata.*) + /* ns16550.o(.rodata .rodata.*) */ + + boot.o(.data .data.*) + bootmmu.o(.data .data.*) + /* ns16550.o(.data .data.*) */ + + PROVIDE(boot_start_addr = .); + + boot.o(.bss .bss.* COMMON) + bootmmu.o(.bss .bss.* COMMON) + /* ns16550.o(.bss .bss.* COMMON) */ + + /* stack for booting code. */ + . = ALIGN(0x1000); + PROVIDE(stacks_start = .); + . += BOOT_STACK_SIZE; + PROVIDE(stacks_end = .); + PROVIDE(stacks_top = .); + + /* initialization end checkpoint. */ + PROVIDE(boot_end_addr = .); + } > phy_ddr3 + + .text : AT(0x1041C000) { + . = ALIGN(0x1000); + *(.text .text.* .gnu.linkonce.t.*) + } + + . = ALIGN(0x1000); + .data : { + *(.data .data.*) + + . = ALIGN(0x1000); + PROVIDE(_binary_fs_img_start = .); + *(.rawdata_fs_img*) + PROVIDE(_binary_fs_img_end = .); + . = ALIGN(0x1000); + PROVIDE(_binary_init_start = .); + *(.rawdata_init*) + PROVIDE(_binary_init_end = .); + . = ALIGN(0x1000); + PROVIDE(_binary_default_fs_start = .); + *(.rawdata_memfs*) + PROVIDE(_binary_default_fs_end = .); + PROVIDE(__init_array_start = .); + PROVIDE(__init_array_end = .); + } + + . = ALIGN(0x1000); + .bss : { + PROVIDE(kernel_data_begin = .); + PROVIDE(__bss_start__ = .); + *(.bss .bss.* COMMON) + . = ALIGN(0x1000); + PROVIDE(__bss_end__ = .); + PROVIDE(kernel_data_end = .); + } + + . = ALIGN((1 << 21)); + .sdata : { + __global_pointer$ = . + 0x800; + *(.sdata*) + } + + _edata = .; + _end = .; + +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/smp.c b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/smp.c new file mode 100644 index 000000000..395b3e32e --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/smp.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2010-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file smp.c + * @brief start multicore + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.10 + */ + +/************************************************* +File name: smp.c +Description: +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. No modifications +*************************************************/ +#include + +#define PSCI_CPUON 0xc4000003 +struct xizi_smccc_res { + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; +}; + +extern void _boot_start(); +extern void __print(); + +extern void __xizi_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, + unsigned long a3, unsigned long a4, unsigned long a5, + unsigned long a6, unsigned long a7, struct xizi_smccc_res* res); + +static struct xizi_smccc_res __invoke_sip_fn_smc(unsigned long function_id, + unsigned long arg0, + unsigned long arg1, + unsigned long arg2) +{ + struct xizi_smccc_res res; + + __xizi_smccc_smc(function_id, arg0, arg1, arg2, 0, 0, 0, 0, &res); + return res; +} + +void cpu_start_secondary(uint8_t cpu_id) +{ + __invoke_sip_fn_smc(PSCI_CPUON, cpu_id, (uintptr_t)0xa00000, 0); +} + +void start_smp_cache_broadcast(int cpu_id) +{ + return; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/xizi_smp.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/xizi_smp.S new file mode 100644 index 000000000..a729c8e04 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/xizi_smp.S @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +.global __xizi_smccc_smc + +.func __xizi_smccc_smc +__xizi_smccc_smc: +1: ret +.endfunc \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/Makefile index 80385afc3..596b31fca 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/Makefile @@ -1,3 +1,8 @@ +ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), ) SRC_DIR := arm +endif +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := riscv +endif include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/Makefile new file mode 100644 index 000000000..dd587adc4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/Makefile @@ -0,0 +1,5 @@ +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := rv64gc +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/Makefile new file mode 100644 index 000000000..11407977e --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := l1_cache.c cache.S + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/cache.S b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/cache.S new file mode 100644 index 000000000..84df60ab4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/cache.S @@ -0,0 +1,184 @@ +/* + * (C) Copyright 2013 + * David Feng + * + * This file is based on sample code from ARMv8 ARM. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#define ASM_NL ; + +#define SYMBOL_NAME(X) X + +// #define SYMBOL_NAME_LABEL(X) X##: + +#define SYMBOL_NAME_LABEL(X) X: + +#ifndef __ALIGN +#define __ALIGN .align 4 +#endif + +#ifndef __ALIGN_STR +#define __ALIGN_STR ".align 4" +#endif + +#define ALIGN __ALIGN +#define ALIGN_STR __ALIGN_STR + +#define LENTRY(name) \ + ALIGN ASM_NL \ + SYMBOL_NAME_LABEL(name) + +#define ENTRY(name) \ + .globl SYMBOL_NAME(name) ASM_NL \ + LENTRY(name) + +#define WEAK(name) \ + .weak SYMBOL_NAME(name) ASM_NL \ + LENTRY(name) + + +#define END(name) \ + .size name, .-name + +#define ENDPROC(name) \ + .type name STT_FUNC ASM_NL \ + END(name) + +#define CR_M (1 << 0) /* MMU enable */ +#define CR_A (1 << 1) /* Alignment abort enable */ +#define CR_C (1 << 2) /* Dcache enable */ +#define CR_SA (1 << 3) /* Stack Alignment Check Enable */ +#define CR_I (1 << 12) /* Icache enable */ +#define CR_WXN (1 << 19) /* Write Permision Imply XN */ +#define CR_EE (1 << 25) /* Exception (Big) Endian */ + +.macro switch_el, xreg, el3_label, el2_label, el1_label + nop +.endm + + +/* + * void __asm_dcache_level(level) + * flush or invalidate one level cache. + * + * x0: cache level + * x1: 0 clean & invalidate, 1 invalidate only + * x2~x9: clobbered + */ +ENTRY(__asm_dcache_level) + nop + +loop_set: + nop +loop_way: + nop + ret +ENDPROC(__asm_dcache_level) + + +/* + * void __asm_flush_dcache_all(int invalidate_only) + * + * x0: 0 clean & invalidate, 1 invalidate only + * + * flush or invalidate all data cache by SET/WAY. + */ + +ENTRY(__asm_dcache_all) + nop + ret +ENDPROC(__asm_dcache_all) + + +ENTRY(__asm_flush_dcache_all) + j __asm_dcache_all +ENDPROC(__asm_flush_dcache_all) + + +ENTRY(__asm_invalidate_dcache_all) + j __asm_dcache_all +ENDPROC(__asm_invalidate_dcache_all) + + +/* + * void __asm_flush_dcache_range(start, end) + * + * clean & invalidate data cache in the range + * + * x0: start address + * x1: end address + */ + +ENTRY(__asm_flush_dcache_range) + nop + ret +ENDPROC(__asm_flush_dcache_range) + +/* + * void __asm_invalidate_dcache_range(start, end) + * + * invalidate data cache in the range + * + * x0: start address + * x1: end address + */ + +ENTRY(__asm_invalidate_dcache_range) + nop + ret +ENDPROC(__asm_invalidate_dcache_range) + + +/* + * void __asm_invalidate_icache_all(void) + * + * invalidate all tlb entries. + */ + +ENTRY(__asm_invalidate_icache_all) + nop + ret +ENDPROC(__asm_invalidate_icache_all) + + + +ENTRY(__asm_invalidate_l3_dcache) + nop + ret +ENDPROC(__asm_invalidate_l3_dcache) + .weak __asm_invalidate_l3_dcache + + + +ENTRY(__asm_flush_l3_dcache) + nop + ret +ENDPROC(__asm_flush_l3_dcache) + .weak __asm_flush_l3_dcache + + + +ENTRY(__asm_invalidate_l3_icache) + nop + ret +ENDPROC(__asm_invalidate_l3_icache) + .weak __asm_invalidate_l3_icache + + +/* + * void __asm_switch_ttbr(ulong new_ttbr) + * + * Safely switches to a new page table. + */ + +ENTRY(__asm_switch_ttbr) + nop + ret +ENDPROC(__asm_switch_ttbr) + +ENTRY(__asm_invalidate_tlb_all) + ret +ENDPROC(__asm_invalidate_tlb_all) \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/l1_cache.c b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/l1_cache.c new file mode 100644 index 000000000..229558fc4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/l1_cache.c @@ -0,0 +1,81 @@ +/** + * @file: l1_cache.c + * @brief: the general management of L1 cache + * @version: 1.0 + * @author: AIIT XUOS Lab + * @date: 2024/04/23 + * + */ + +/************************************************* +File name: l1_cache.c +Description: the general management of L1 cache +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. implement the l1 cache operations +2. function names are modified to apply softkernel developement +3. function implementations are from modifications of imx6 SDK package +*************************************************/ + +#include "l1_cache.h" +extern void __asm_flush_dcache_all(); +extern void __asm_flush_l3_dcache(); +extern void __asm_invalidate_icache_all(); +extern void __asm_invalidate_l3_icache(); + +void InvalidateL1Dcache(uintptr_t start, uintptr_t end) +{ +} + +void InvalidateL1DcacheAll(void) +{ +} + +void CleanL1Dcache(uintptr_t start, uintptr_t end) +{ +} + +void CleanL1DcacheAll(void) +{ +} + +void FlushL1Dcache(uintptr_t start, uintptr_t end) +{ +} + +void FlushL1DcacheAll(void) +{ + +} + +void InvalidateL1IcacheAll() +{ + +} + +void InvalidateL1Icache(uintptr_t start, uintptr_t end) +{ + +} + +void EnableL1Dcache() +{ + +} + +void DisableL1Dcache() +{ + +} + +void EnableL1Icache() +{ + +} + +void DisableL1Icache() +{ + +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/l1_cache.h b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/l1_cache.h new file mode 100644 index 000000000..c1cddb488 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/riscv/rv64gc/l1_cache.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file: l1_cache.h + * @brief: the general management of L1 cache + * @version: 1.0 + * @author: AIIT XUOS Lab + * @date: 2024/4/23 + * + */ + +/************************************************* +File name: l1_cache.h +Description: the general management of L1 cache +Others: +History: +Author: AIIT XUOS Lab +Modification: +1、define the l1 cache operations +*************************************************/ +#include "core.h" +#include + +/* + * L1 Cache Operation: + * + * IVAC -Invalidate by Virtual Address, to Point of Coherency AArch32Equivalent :DCIMVAC + * + * ISW -Invalidate by Set/Way AArch32Equivalent :DCISW + * + *CVAC -Clean by Virtual Address to Point of Coherency AArch32Equivalent :DCCMVAC + * + *CSW -Clean by Set/Way AArch32Equivalent :DCCSW + * + *CVAU -Clean by Virtual Address to Point of Unification AArch32Equivalent :DCCMVAU + * + *CIVAC -Clean and invalidate data cache line by VA to PoC. AArch32Equivalent :DCCIMVAC + * + *ISW -Clean and invalidate data cache line by Set/Way. AArch32Equivalent :DCCISW + */ + +#define SCTLR_EL1_ICACHE_ENABLE (1 << 12) //!< Instruction cache enable +#define SCTLR_EL1_DCACHE_ENABLE (1 << 2) //!< Data cache enable + +void InvalidateL1Dcache(uintptr_t start, uintptr_t end); + +void InvalidateL1DcacheAll(void); + +void CleanL1Dcache(uintptr_t start, uintptr_t end); + +void CleanL1DcacheAll(void); + +void FlushL1Dcache(uintptr_t start, uintptr_t end); + +void FlushL1DcacheAll(void); + +void InvalidateL1IcacheAll(void); + +void InvalidateL1Icache(uintptr_t start, uintptr_t end); + +void EnableL1Icache(void); +void DisableL1Icache(); + +void EnableL1Dcache(); + +void DisableL1Dcache(); \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/clock/Makefile index 5ccf8946b..596b31fca 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/clock/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/Makefile @@ -1,3 +1,8 @@ -SRC_DIR:= arm +ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), ) +SRC_DIR := arm +endif +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := riscv +endif include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/Makefile new file mode 100644 index 000000000..dd587adc4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/Makefile @@ -0,0 +1,5 @@ +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := rv64gc +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/Makefile new file mode 100644 index 000000000..c87074a06 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := clock.c + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/clock.c b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/clock.c new file mode 100644 index 000000000..39d2995d6 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/clock.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +#include "actracer.h" +#include "core.h" +#include "generic_timer.h" + +#include "clock_common_op.h" + +// armv8 generic timer driver +#define CNTV_CTL_ENABLE (1 << 0) +#define CNTV_CTL_IMASK (1 << 1) +#define CNTV_CTL_ISTATUS (1 << 2) + +static void enable_timer() +{ + uint32_t c = r_cntp_ctl_el0(); + c |= CNTV_CTL_ENABLE; + c &= ~CNTV_CTL_IMASK; + w_cntp_ctl_el0(c); +} + +static void disable_timer() +{ + uint32_t c = r_cntp_ctl_el0(); + c |= CNTV_CTL_IMASK; + c &= ~CNTV_CTL_ENABLE; + w_cntp_ctl_el0(c); +} + +static void reload_timer() +{ + // interval 1ms + static uint32_t ms = 1; + uint32_t interval = ms * 1000; + uint32_t interval_clk = interval * (r_cntfrq_el0() / 1000000); + w_cntp_tval_el0(interval_clk); +} + +void _sys_clock_init() +{ + disable_timer(); + reload_timer(); + enable_timer(); +} + +static uint32_t _get_clock_int() +{ + return 30; +} + +static uint64_t _get_tick() +{ + return r_cntvct_el0(); +} + +static uint64_t _get_second() +{ + return _get_tick() / r_cntfrq_el0(); +} + +static bool _is_timer_expired() +{ + return true; +} + +static void _clear_clock_intr() +{ + disable_timer(); + reload_timer(); + enable_timer(); +} + +static struct XiziClockDriver hardkernel_clock_driver = { + .sys_clock_init = _sys_clock_init, + .get_clock_int = _get_clock_int, + .get_tick = _get_tick, + .get_second = _get_second, + .is_timer_expired = _is_timer_expired, + .clear_clock_intr = _clear_clock_intr, +}; + +struct XiziClockDriver* hardkernel_clock_init(struct TraceTag* hardkernel_tag) +{ + hardkernel_clock_driver.sys_clock_init(); + return &hardkernel_clock_driver; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/Makefile new file mode 100644 index 000000000..c87074a06 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := clock.c + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clock.c b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clock.c new file mode 100644 index 000000000..39d2995d6 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clock.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +#include "actracer.h" +#include "core.h" +#include "generic_timer.h" + +#include "clock_common_op.h" + +// armv8 generic timer driver +#define CNTV_CTL_ENABLE (1 << 0) +#define CNTV_CTL_IMASK (1 << 1) +#define CNTV_CTL_ISTATUS (1 << 2) + +static void enable_timer() +{ + uint32_t c = r_cntp_ctl_el0(); + c |= CNTV_CTL_ENABLE; + c &= ~CNTV_CTL_IMASK; + w_cntp_ctl_el0(c); +} + +static void disable_timer() +{ + uint32_t c = r_cntp_ctl_el0(); + c |= CNTV_CTL_IMASK; + c &= ~CNTV_CTL_ENABLE; + w_cntp_ctl_el0(c); +} + +static void reload_timer() +{ + // interval 1ms + static uint32_t ms = 1; + uint32_t interval = ms * 1000; + uint32_t interval_clk = interval * (r_cntfrq_el0() / 1000000); + w_cntp_tval_el0(interval_clk); +} + +void _sys_clock_init() +{ + disable_timer(); + reload_timer(); + enable_timer(); +} + +static uint32_t _get_clock_int() +{ + return 30; +} + +static uint64_t _get_tick() +{ + return r_cntvct_el0(); +} + +static uint64_t _get_second() +{ + return _get_tick() / r_cntfrq_el0(); +} + +static bool _is_timer_expired() +{ + return true; +} + +static void _clear_clock_intr() +{ + disable_timer(); + reload_timer(); + enable_timer(); +} + +static struct XiziClockDriver hardkernel_clock_driver = { + .sys_clock_init = _sys_clock_init, + .get_clock_int = _get_clock_int, + .get_tick = _get_tick, + .get_second = _get_second, + .is_timer_expired = _is_timer_expired, + .clear_clock_intr = _clear_clock_intr, +}; + +struct XiziClockDriver* hardkernel_clock_init(struct TraceTag* hardkernel_tag) +{ + hardkernel_clock_driver.sys_clock_init(); + return &hardkernel_clock_driver; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/include/generic_timer.h b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/include/generic_timer.h new file mode 100644 index 000000000..58cfd1b07 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/include/generic_timer.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +#pragma once + +#include +#include + +// armv8 generic timer +static inline uint32_t r_cntp_ctl_el0() +{ + uint32_t x; +// __asm__ volatile("mrs %0, cntp_ctl_el0" : "=r"(x)); + return x; +} + +static inline void w_cntp_ctl_el0(uint32_t x) +{ +// __asm__ volatile("msr cntp_ctl_el0, %0" : : "r"(x)); +} + +static inline uint32_t r_cntp_tval_el0() +{ + uint32_t x; +// __asm__ volatile("mrs %0, cntp_tval_el0" : "=r"(x)); + return x; +} + +static inline void w_cntp_tval_el0(uint32_t x) +{ +// __asm__ volatile("msr cntp_tval_el0, %0" : : "r"(x)); +} + +static inline uint64_t r_cntvct_el0() +{ + uint64_t x; +// __asm__ volatile("mrs %0, cntvct_el0" : "=r"(x)); + return x; +} + +static inline uint32_t r_cntfrq_el0() +{ + uint32_t x; +// __asm__ volatile("mrs %0, cntfrq_el0" : "=r"(x)); + return x; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/Makefile index bd7075f60..4fcd6940b 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/Makefile @@ -1,4 +1,10 @@ +ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), ) SRC_DIR := arm +endif +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := riscv +endif + SRC_FILES := spinlock.c include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/Makefile new file mode 100644 index 000000000..dd587adc4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/Makefile @@ -0,0 +1,5 @@ +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := rv64gc +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile new file mode 100644 index 000000000..6fd2fb6d5 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile @@ -0,0 +1,9 @@ +SRC_FILES := trampoline.S $(BOARD)/trap_common.c $(BOARD)/trap.c error_debug.c hard_spinlock.S + +ifeq ($(BOARD), jh7110) +SRC_DIR := gicv3 +SRC_FILES += $(BOARD)/ +endif + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/error_debug.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/error_debug.c new file mode 100644 index 000000000..3e2c2a1ec --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/error_debug.c @@ -0,0 +1,67 @@ +/* Copyright (c) 2006-2018 Frans Kaashoek, Robert Morris, Russ Cox, + * Massachusetts Institute of Technology + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +/** + * @file error_debug.c + * @brief handle program abort + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.4.25 + */ + +/************************************************* +File name: error_debug.c +Description: handle program abort +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. Take only armv8 abort reason part(_abort_reason). +2. Modify iabort and dabort handler(in dabort_handler() and iabort_handler()) +*************************************************/ +#include +#include + +#include "exception_registers.h" + +#include "assert.h" +#include "core.h" +#include "log.h" +#include "multicores.h" +#include "task.h" +#include "trap_common.h" + +void dump_tf(struct trapframe* tf) +{ + +} + +void dabort_reason(struct trapframe* r) +{ + + return; +} + +void iabort_reason(struct trapframe* r) +{ + return; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/Makefile new file mode 100644 index 000000000..c5085627e --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := gicv3.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3.c new file mode 100644 index 000000000..f299f4966 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3.c @@ -0,0 +1,260 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file gicv3.c + * @brief gicv3 operation + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.05.10 + */ + +/************************************************* +File name: gicv3.c +Description: gicv3 operation +Others: +History: +Author: AIIT XUOS Lab +Modification: +*************************************************/ +#include + +#include "core.h" +#include "gicv3_common_opa.h" +#include "gicv3_registers.h" + +static struct { + char* gicd; + char* rdist_addrs[NR_CPU]; +} gicv3; + +static inline uint32_t icc_igrpen1_el1() +{ + uint32_t x; +// __asm__ volatile("mrs %0, S3_0_C12_C12_7" : "=r"(x)); + return x; +} + +static inline void w_icc_igrpen1_el1(uint32_t x) +{ +// __asm__ volatile("msr S3_0_C12_C12_7, %0" : : "r"(x)); +} + +static inline uint32_t icc_pmr_el1() +{ + uint32_t x; +// __asm__ volatile("mrs %0, S3_0_C4_C6_0" : "=r"(x)); + return x; +} + +static inline void w_icc_pmr_el1(uint32_t x) +{ +// __asm__ volatile("msr S3_0_C4_C6_0, %0" : : "r"(x)); +} + +inline uint32_t gic_read_irq_ack() +{ + uint32_t x; +// __asm__ volatile("mrs %0, S3_0_C12_C12_0" : "=r"(x)); + return x; +} + +inline void +gic_write_end_of_irq(uint32_t x) +{ +// __asm__ volatile("msr S3_0_C12_C12_1, %0" : : "r"(x)); +} + +static inline uint32_t icc_sre_el1() +{ + uint32_t x; +// __asm__ volatile("mrs %0, S3_0_C12_C12_5" : "=r"(x)); + return x; +} + +static inline void w_icc_sre_el1(uint32_t x) +{ +// __asm__ volatile("msr S3_0_C12_C12_5, %0" : : "r"(x)); +} + +static void gicd_write(uint32_t off, uint32_t val) +{ +// *(volatile uint32_t*)(gicv3.gicd + off) = val; +} + +static uint32_t gicd_read(uint32_t off) +{ +// return *(volatile uint32_t*)(gicv3.gicd + off); + return 0; +} + +static void gicr_write(uint32_t cpuid, uint32_t off, uint32_t val) +{ +// *(volatile uint32_t*)(gicv3.rdist_addrs[cpuid] + off) = val; +} + +static uint32_t gicr_read(uint32_t cpuid, uint32_t off) +{ +// return *(volatile uint32_t*)(gicv3.rdist_addrs[cpuid] + off); + return 0; +} + +static void giccinit() +{ + w_icc_igrpen1_el1(0); + w_icc_pmr_el1(0xff); +} + +static void gicdinit() +{ + gicd_write(D_CTLR, 0); + + uint32_t typer = gicd_read(D_TYPER); + uint32_t lines = typer & 0x1f; + + for (int i = 0; i < lines; i++) + gicd_write(D_IGROUPR(i), ~0); +} + +static void gicrinit(uint32_t cpuid) +{ + gicr_write(cpuid, R_CTLR, 0); + + w_icc_sre_el1(icc_sre_el1() | 1); + + gicr_write(cpuid, R_IGROUPR0, ~0); + gicr_write(cpuid, R_IGRPMODR0, 0); + + uint32_t waker = gicr_read(cpuid, R_WAKER); + gicr_write(cpuid, R_WAKER, waker & ~(1 << 1)); + while (gicr_read(cpuid, R_WAKER) & (1 << 2)) + ; +} + +void gic_enable() +{ + gicd_write(D_CTLR, (1 << 1)); + w_icc_igrpen1_el1(1); +} + +void gic_init() +{ + gicv3.gicd = (char*)GICV3; + for (int i = 0; i < NR_CPU; i++) { + gicv3.rdist_addrs[i] = (char*)(GICV3_REDIST + (i) * 0x20000); + } + + gicdinit(); +} + +void gicv3inithart(uint32_t cpu_id) +{ + giccinit(); + gicrinit(cpu_id); + + gic_enable(); +} + +static void +gic_enable_int(uint32_t intid) +{ + uint32_t is = gicd_read(D_ISENABLER(intid / 32)); + is |= 1 << (intid % 32); + gicd_write(D_ISENABLER(intid / 32), is); +} + +int gic_int_enabled(uint32_t intid) +{ + uint32_t is = gicd_read(D_ISENABLER(intid / 32)); + return is & (1 << (intid % 32)); +} + +static void +gic_clear_pending(uint32_t intid) +{ + uint32_t ic = gicd_read(D_ICPENDR(intid / 32)); + ic |= 1 << (intid % 32); + gicd_write(D_ICPENDR(intid / 32), ic); +} + +static void +gic_set_prio0(uint32_t intid) +{ + // set priority to 0 + uint32_t p = gicd_read(D_IPRIORITYR(intid / 4)); + p &= ~((uint32_t)0xff << (intid % 4 * 8)); // set prio 0 + gicd_write(D_IPRIORITYR(intid / 4), p); +} + +static void gic_set_target(uint32_t intid, uint32_t cpuid) +{ + uint32_t itargetsr = gicd_read(D_ITARGETSR(intid / 4)); + itargetsr &= ~((uint32_t)0xff << (intid % 4 * 8)); + gicd_write(D_ITARGETSR(intid / 4), itargetsr | ((uint32_t)(1 << cpuid) << (intid % 4 * 8))); +} + +static void +gicr_enable_int(uint32_t cpuid, uint32_t intid) +{ + uint32_t is = gicr_read(cpuid, R_ISENABLER0); + is |= 1 << (intid % 32); + gicr_write(cpuid, R_ISENABLER0, is); +} + +static void +gicr_clear_pending(uint32_t cpuid, uint32_t intid) +{ + uint32_t ic = gicr_read(cpuid, R_ICPENDR0); + ic |= 1 << (intid % 32); + gicr_write(cpuid, R_ICPENDR0, ic); +} + +static void +gicr_set_prio0(uint32_t cpuid, uint32_t intid) +{ + uint32_t p = gicr_read(cpuid, R_IPRIORITYR(intid / 4)); + p &= ~((uint32_t)0xff << (intid % 4 * 8)); // set prio 0 + gicr_write(cpuid, R_IPRIORITYR(intid / 4), p); +} + +void gic_setup_ppi(uint32_t cpuid, uint32_t intid) +{ + gicr_set_prio0(cpuid, intid); + gicr_clear_pending(cpuid, intid); + gicr_enable_int(cpuid, intid); +} + +void gic_setup_spi(uint32_t cpuid, uint32_t intid) +{ + gic_set_prio0(intid); + gic_set_target(intid, cpuid); + gic_clear_pending(intid); + gic_enable_int(intid); +} + +// irq from iar +int gic_iar_irq(uint32_t iar) +{ + return iar & 0x3ff; +} + +// interrupt acknowledge register: +// ask GIC what interrupt we should serve. +uint32_t gic_iar() +{ + return gic_read_irq_ack(); +} + +// tell GIC we've served this IRQ. +void gic_eoi(uint32_t iar) +{ + gic_write_end_of_irq(iar); +} diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_common_opa.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_common_opa.h new file mode 100644 index 000000000..17e3632eb --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_common_opa.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file gicv3_common_opa.h + * @brief gicv3 operation + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.05.07 + */ +/************************************************* +File name: gicv3_common_opa.h +Description: gicv3 operation +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. Rename file +*************************************************/ +#pragma once + +#include +#include + +#include + +//! @name Initialization +//@{ +//! @brief Init interrupt handling. +//! +//! This function is intended to be called only by the primary CPU init code, so it will +//! only be called once during system bootup. +//! +//! Also inits the current CPU. You don't need to call gic_init_cpu() separately. +//! +//! @post The interrupt distributor and the current CPU interface are enabled. All interrupts +//! that were pending are cleared, and all interrupts are made secure (group 0). +void gic_init(void); + +//! @name GIC Interrupt Distributor Functions +//@{ +//! @brief Enable or disable the GIC Distributor. +//! +//! Enables or disables the GIC distributor passing both secure (group 0) and non-secure +//! (group 1) interrupts to the CPU interfaces. +//! +//! @param enableIt Pass true to enable or false to disable. +void gic_enable(); + +//! @brief Set the security mode for an interrupt. +//! +//! @param irqID The interrupt number. +//! @param isSecure Whether the interrupt is taken to secure mode. +void gic_set_irq_security(uint32_t irqID, bool isSecure); + +//! @brief Enable or disable an interrupt. +//! +//! @param irqID The number of the interrupt to control. +//! @param isEnabled Pass true to enable or false to disable. +void gic_enable_irq(uint32_t irqID, bool isEnabled); + +//! @brief Set whether a CPU will receive a particular interrupt. +//! +//! @param irqID The interrupt number. +//! @param cpuNumber The CPU number. The first CPU core is 0. +//! @param enableIt Whether to send the interrupt to the specified CPU. Pass true to enable +//! or false to disable. +void gic_set_cpu_target(uint32_t irqID, unsigned cpuNumber, bool enableIt); + +//! @brief Set an interrupt's priority. +//! +//! @param irq_id The interrupt number. +//! @param priority The priority for the interrupt. In the range of 0 through 0xff, with +//! 0 being the highest priority. +void gic_set_irq_priority(uint32_t irq_id, uint32_t priority); + +void gic_setup_spi(uint32_t cpuid, uint32_t intid); +void gic_setup_ppi(uint32_t cpuid, uint32_t intid); + +void gicv3inithart(uint32_t cpu_id); +//! @brief Send a software generated interrupt to a specific CPU. +//! +//! @param irq_id The interrupt number to send. +//! @param target_list Each bit indicates a CPU to which the interrupt will be forwarded. +//! Bit 0 is CPU 0, bit 1 is CPU 1, and so on. If the value is 0, then the interrupt +//! will not be forwarded to any CPUs. This parameter is only used if @a filter_list +//! is set to #kGicSgiFilter_UseTargetList. +//! @param filter_list One of the enums of the #_gicd_sgi_filter enumeration. The selected +//! option determines which CPUs the interrupt will be sent to. If the value +//! is #kGicSgiFilter_UseTargetList, then the @a target_list parameter is used. +void gic_send_sgi(uint32_t irq_id, uint32_t target_list, uint32_t filter_list); +//@} + +//! @name GIC CPU Interface Functions +//@{ +//! @brief Enable or disable the interface to the GIC for the current CPU. +//! +//! @param enableIt Pass true to enable or false to disable. +void gic_cpu_enable(bool enableIt); + +//! @brief Set the mask of which interrupt priorities the CPU will receive. +//! +//! @param priority The lowest priority that will be passed to the current CPU. Pass 0xff to +//! allow all priority interrupts to signal the CPU. +void gic_set_cpu_priority_mask(uint32_t priority); + +//! @brief Acknowledge starting of interrupt handling and get the interrupt number. +//! +//! Normally, this function is called at the beginning of the IRQ handler. It tells the GIC +//! that you are starting to handle an interupt, and returns the number of the interrupt you +//! need to handle. After the interrupt is handled, you should call gic_write_end_of_irq() +//! to signal that the interrupt is completely handled. +//! +//! In some cases, a spurious interrupt might happen. One possibility is if another CPU handles +//! the interrupt. When a spurious interrupt occurs, the end of the interrupt should be indicated +//! but nothing else. +//! +//! @return The number for the highest priority interrupt available for the calling CPU. If +//! the return value is 1022 or 1023, a spurious interrupt has occurred. +uint32_t gic_read_irq_ack(void); + +//! @brief Signal the end of handling an interrupt. +//! +//! @param irq_id The number of the interrupt for which handling has finished. +void gic_write_end_of_irq(uint32_t irq_id); +//@} + +//! @} + +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_registers.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_registers.h new file mode 100644 index 000000000..389d6a5b1 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_registers.h @@ -0,0 +1,59 @@ +/* + * + * Copyright (C) 2002 ARM Limited, All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/** + * @file gicv3_registers.h + * @brief gicv3 registers + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.05.09 + */ + +/************************************************* +File name: gicv3_registers.c +Description: gicv3 registers +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. Rename the file +*************************************************/ + +#pragma once + +#include "memlayout.h" + +// clang-format off +// interrupt controller GICv3 +#define GICV3 MMIO_P2V_WO(0xFD400000ULL) +#define GICV3_REDIST MMIO_P2V_WO(0xFD460000ULL) + +#define D_CTLR 0x0 +#define D_TYPER 0x4 +#define D_IGROUPR(n) (0x80 + (uint64_t)(n) * 4) +#define D_ISENABLER(n) (0x100 + (uint64_t)(n) * 4) +#define D_ICENABLER(n) (0x180 + (uint64_t)(n) * 4) +#define D_ISPENDR(n) (0x200 + (uint64_t)(n) * 4) +#define D_ICPENDR(n) (0x280 + (uint64_t)(n) * 4) +#define D_IPRIORITYR(n) (0x400 + (uint64_t)(n) * 4) +#define D_ITARGETSR(n) (0x800 + (uint64_t)(n) * 4) +#define D_ICFGR(n) (0xc00 + (uint64_t)(n) * 4) + +#define R_CTLR 0x0 +#define R_WAKER 0x14 + +#define SGI_BASE 0x10000 +#define R_IGROUPR0 (SGI_BASE + 0x80) +#define R_ISENABLER0 (SGI_BASE + 0x100) +#define R_ICENABLER0 (SGI_BASE + 0x180) +#define R_ICPENDR0 (SGI_BASE + 0x280) +#define R_IPRIORITYR(n) (SGI_BASE + 0x400 + (n) * 4) +#define R_ICFGR0 (SGI_BASE + 0xc00) +#define R_ICFGR1 (SGI_BASE + 0xc04) +#define R_IGRPMODR0 (SGI_BASE + 0xd00) +// clang-format on diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S new file mode 100644 index 000000000..b26cf30f3 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2013, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * Portions Copyright (c) 2011-2012 ARM Ltd. All rights reserved. + */ +/** + * @file hard_spinlock.S + * @brief spinlock implementation + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.11 + */ + +/************************************************* +File name: hard_spinlock.S +Description: spinlock implementation +Others: +History: +Author: AIIT XUOS Lab +Modification: +*************************************************/ + +// .arch armv8-a + .section ".text","ax" + + .global cpu_get_current + +#define UNLOCKED 0xFF +// int spinlock_lock(spinlock_t * lock, uint64_t timeout) + .global _spinlock_lock +.func _spinlock_lock +_spinlock_lock: + ret +.endfunc + + +// void spinlock_unlock(spinlock_t * lock) + .global _spinlock_unlock + .func _spinlock_unlock +_spinlock_unlock: + ret +.endfunc + +.end + diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/exception_registers.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/exception_registers.h new file mode 100644 index 000000000..aae7e28c8 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/exception_registers.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file exception_registers.h + * @brief exception registers + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.05.09 + */ + +static inline void w_vbar_el1(uint64_t x) +{ +// __asm__ volatile("msr vbar_el1, %0" : : "r"(x)); +} + +static inline uint64_t r_esr_el1() +{ + uint64_t x; +// __asm__ volatile("mrs %0, esr_el1" : "=r"(x)); + return x; +} + +static inline void w_esr_el1(uint64_t x) +{ +// __asm__ volatile("msr esr_el1, %0" : : "r"(x)); +} + +static inline uint64_t r_elr_el1() +{ + uint64_t x; +// __asm__ volatile("mrs %0, elr_el1" : "=r"(x)); + return x; +} + +static inline uint64_t r_far_el1() +{ + uint64_t x; +// __asm__ volatile("mrs %0, far_el1" : "=r"(x)); + return x; +} + +static inline uint64_t daif() +{ + uint64_t x; +// __asm__ volatile("mrs %0, daif" : "=r"(x)); + return x; +} + +// enable interrupts(irq) +static inline void intr_on() +{ +// __asm__ volatile("msr daifclr, #0xf" ::: "memory"); +} + +// disable interrupts(irq) +static inline void intr_off() +{ +// __asm__ volatile("msr daifset, #0xf" ::: "memory"); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/irq_numbers.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/irq_numbers.h new file mode 100644 index 000000000..c7d5e8ca3 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/irq_numbers.h @@ -0,0 +1,110 @@ +/** + * @file irq_numbers.c + * @brief irq numbers + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.08.25 + */ + +/************************************************* +File name: irq_numbers.c +Description: irq numbers +Others: +History: +1. Date: 2023-08-28 +Author: AIIT XUOS Lab +Modification: +1. Add HW_NR_IRQS +*************************************************/ +#if !defined(__IRQ_NUMBERS_H__) +#define __IRQ_NUMBERS_H__ + +#define HW_NR_IRQS NR_OK1028_INTRS + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @brief i.MX6 interrupt numbers. +//! +//! This enumeration lists the numbers for all of the interrupts available on the i.MX6 series. +//! Use these numbers when specifying an interrupt to the GIC. +//! +//! The first 16 interrupts are special in that they are reserved for software interrupts generated +//! by the SWI instruction. + +enum _ls_interrupts { + SW_INTERRUPT_0 = 0, //!< Software interrupt 0. + SW_INTERRUPT_1 = 1, //!< Software interrupt 1. + SW_INTERRUPT_2 = 2, //!< Software interrupt 2. + SW_INTERRUPT_3 = 3, //!< Software interrupt 3. + SW_INTERRUPT_4 = 4, //!< Software interrupt 4. + SW_INTERRUPT_5 = 5, //!< Software interrupt 5. + SW_INTERRUPT_6 = 6, //!< Software interrupt 6. + SW_INTERRUPT_7 = 7, //!< Software interrupt 7. + SW_INTERRUPT_8 = 8, //!< Software interrupt 8. + SW_INTERRUPT_9 = 9, //!< Software interrupt 9. + SW_INTERRUPT_10 = 10, //!< Software interrupt 10. + SW_INTERRUPT_11 = 11, //!< Software interrupt 11. + SW_INTERRUPT_12 = 12, //!< Software interrupt 12. + SW_INTERRUPT_13 = 13, //!< Software interrupt 13. + SW_INTERRUPT_14 = 14, //!< Software interrupt 14. + SW_INTERRUPT_15 = 15, //!< Software interrupt 15. + RSVD_INTERRUPT_16 = 16, //!< Reserved. + RSVD_INTERRUPT_17 = 17, //!< Reserved. + RSVD_INTERRUPT_18 = 18, //!< Reserved. + RSVD_INTERRUPT_19 = 19, //!< Reserved. + RSVD_INTERRUPT_20 = 20, //!< Reserved. + RSVD_INTERRUPT_21 = 21, //!< Reserved. + + LS_INT_DEBUG_CC = 22, //!<(cluster-internal) COMMIRQ - Debug communications channel + LS_INT_PMU = 23, //!<(cluster-internal) PMUIRQ - Perfmon* + LS_INT_CTI = 24, //!<(cluster-internal) CTIIRQ - Cross-trigger interface* + LS_INT_VMI = 25, //!<(cluster-internal) VCPUMNTIRQ -Virtual maintenance interface* + + LS_INT_WDOG = 28, //!< Watchdog timer + LS_INT_SEC_PHY_TIMER = 29, //!<(cluster-internal) CNTPSIRQ - EL1 Secure physical timer event* + LS_INT_NON_SEC_PHY_TIMER = 30, //!<(cluster-internal) CNTPNSIRQ - EL1 Non-secure physical timer event* + RSVD_INTERRUPT_31 = 31, //!< Reserved. + RSVD_INTERRUPT_32 = 32, //!< Reserved. + RSVD_INTERRUPT_33 = 33, //!< Reserved. + RSVD_INTERRUPT_34 = 34, //!< Reserved. + RSVD_INTERRUPT_35 = 35, //!< Reserved. + RSVD_INTERRUPT_36 = 36, //!< Reserved. + RSVD_INTERRUPT_37 = 37, //!< Reserved. + RSVD_INTERRUPT_38 = 38, //!< Reserved. + RSVD_INTERRUPT_39 = 39, //!< Reserved. + RSVD_INTERRUPT_40 = 40, //!< Reserved. + RSVD_INTERRUPT_41 = 41, //!< Reserved. + RSVD_INTERRUPT_42 = 42, //!< Reserved. + + LS_INT_DUART1 = 64, // Logical OR of DUART1 interrupt requests. + + LS_INT_I2C1_2 = 66, //!< I2C1 and I2C2 ORed + LS_INT_I2C3_4 = 67, //!< I2C3 and I2C4 ORed + LS_INT_GPIO1_2 = 68, //!< GPIO1 and GPIO2 ORed + LS_INT_GPIO3 = 69, //!< GPIO3 + + LS_INT_FLETIMER1 = 76, //!< ORed all Flextimer 1 interrupt signals + LS_INT_FLETIMER2 = 77, //!< ORed all Flextimer 2 interrupt signals + LS_INT_FLETIMER3 = 78, //!< ORed all Flextimer 3 interrupt signals + LS_INT_FLETIMER4 = 79, //!< ORed all Flextimer 4 interrupt signals + + LS_INT_I2C5_6 = 106, //!< I2C5 and I2C6 ORed + LS_INT_I2C7_8 = 107, //!< I2C7 and I2C8 ORed + + LS_INT_USB3_1 = 112, //!< USB1 ORed INT + LS_INT_USB3_2 = 113, //!< USB2 ORed INT + + LS_INT_LPUART1 = 264, //!< LPUART1 interrupt request. + LS_INT_LPUART2 = 265, //!< LPUART1 interrupt request. + LS_INT_LPUART3 = 266, //!< LPUART1 interrupt request. + LS_INT_LPUART4 = 267, //!< LPUART1 interrupt request. + LS_INT_LPUART5 = 268, //!< LPUART1 interrupt request. + LS_INT_LPUART6 = 269, //!< LPUART1 interrupt request. + + NR_OK1028_INTRS, + +}; + +#endif //__IRQ_NUMBERS_H__ \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c new file mode 100644 index 000000000..f28c7a6a3 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file trap.c + * @brief trap interface of hardkernel + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2023.05.06 + */ + +/************************************************* +File name: trap.c +Description: trap interface of hardkernel +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include + +#include "exception_registers.h" + +#include "assert.h" +#include "core.h" +#include "multicores.h" +#include "syscall.h" +#include "task.h" + +#include "mmu.h" + +extern void dabort_handler(struct trapframe* r); +extern void iabort_handler(struct trapframe* r); + +void kernel_abort_handler(struct trapframe* tf) +{ + uint64_t esr = r_esr_el1(); + switch ((esr >> 0x1A) & 0x3F) { + case 0b100100: + case 0b100101: + dabort_handler(tf); + break; + case 0b100000: + case 0b100001: + iabort_handler(tf); + break; + default: { + uint64_t ec = (esr >> 26) & 0x3f; + uint64_t iss = esr & 0x1ffffff; + ERROR("esr: %016lx %016lx %016lx\n", esr, ec, iss); + ERROR("elr = %016lx far = %016lx\n", r_elr_el1(), r_far_el1()); + ERROR("Current Task: %s.\n", cur_cpu()->task->name); + panic("Unimplemented Error Occured.\n"); + } + } + panic("Return from abort handler.\n"); +} + +void kernel_intr_handler(struct trapframe* tf) +{ + panic("Intr at kernel mode should never happen by design.\n"); +} + +extern void context_switch(struct context**, struct context*); +void syscall_arch_handler(struct trapframe* tf) +{ + + uint64_t esr = r_esr_el1(); + uint64_t ec = (esr >> 0x1A) & 0x3F; + switch (ec) { + case 0B010101: + software_irq_dispatch(tf); + break; + case 0b100100: + case 0b100101: + dabort_handler(tf); + break; + case 0b100000: + case 0b100001: + iabort_handler(tf); + break; + default: { + ERROR("USYSCALL: unexpected\n"); + ERROR(" esr: %016lx\n", esr); + ERROR(" elr = %016lx far = %016lx\n", r_elr_el1(), r_far_el1()); + w_esr_el1(0); + extern void dump_tf(struct trapframe * tf); + dump_tf(tf); + + uint32_t sctlr = 0; + SCTLR_R(sctlr); + DEBUG("SCTLR: %x\n", sctlr); + uint32_t spsr = 0; +// __asm__ volatile("mrs %0, spsr_el1" : "=r"(spsr)::"memory"); + DEBUG("SPSR: %x\n", spsr); + uint64_t tcr = 0; +// __asm__ volatile("mrs %0, tcr_el1" : "=r"(tcr)::"memory"); + DEBUG("TCR: %x\n", tcr); + uint64_t mair = 0; +// __asm__ volatile("mrs %0, mair_el1" : "=r"(mair)::"memory"); + DEBUG("MAIR: %x\n", mair); + + // kill error task + xizi_enter_kernel(); + assert(cur_cpu()->task != NULL); + ERROR("Error Task: %s\n", cur_cpu()->task->name); + sys_exit(cur_cpu()->task); + context_switch(&cur_cpu()->task->thread_context.context, cur_cpu()->scheduler); + panic("dabort end should never be reashed.\n"); + } + } +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c new file mode 100644 index 000000000..003c64acc --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file trap_common.c + * @brief trap interface of hardkernel + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2023.05.06 + */ + +/************************************************* +File name: trap_common.c +Description: trap interface of hardkernel +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include + +#include "core.h" +#include "cortex.h" +#include "exception_registers.h" +#include "gicv3_common_opa.h" +#include "trap_common.h" + +#include "log.h" +#include "multicores.h" + +static struct XiziTrapDriver xizi_trap_driver; + +void panic(char* s) +{ + KPrintf("panic: %s\n", s); + for (;;) + ; +} + +extern void alltraps(); +static void _sys_irq_init(int cpu_id) +{ + // primary core init intr + xizi_trap_driver.switch_hw_irqtbl((uintptr_t*)alltraps); + + if (cpu_id == 0) { + gic_init(); + } + gicv3inithart(cpu_id); +} + +static void _cpu_irq_enable(void) +{ + intr_on(); +} + +static void _cpu_irq_disable(void) +{ + intr_off(); +} + +static void _single_irq_enable(int irq, int cpu, int prio) +{ + gic_setup_ppi((uint32_t)cpu, (uint32_t)irq); +} + +static void _single_irq_disable(int irq, int cpu) +{ + return; +} + +static inline uintptr_t* _switch_hw_irqtbl(uintptr_t* new_tbl_base) +{ + w_vbar_el1((uint64_t)new_tbl_base); + + return NULL; +} + +static void _bind_irq_handler(int irq, irq_handler_t handler) +{ + xizi_trap_driver.sw_irqtbl[irq].handler = handler; +} + +static uint32_t _hw_before_irq() +{ + + uint32_t iar = gic_read_irq_ack(); + return iar; +} + +static uint32_t _hw_cur_int_num(uint32_t int_info) +{ + return int_info & 0x3FF; +} + +static void _hw_after_irq(uint32_t int_info) +{ + gic_write_end_of_irq(int_info); +} + +int _cur_cpu_id() +{ + return cpu_get_current(); +} + +static struct XiziTrapDriver xizi_trap_driver = { + .sys_irq_init = _sys_irq_init, + .cur_cpu_id = _cur_cpu_id, + + .cpu_irq_enable = _cpu_irq_enable, + .cpu_irq_disable = _cpu_irq_disable, + .single_irq_enable = _single_irq_enable, + .single_irq_disable = _single_irq_disable, + .switch_hw_irqtbl = _switch_hw_irqtbl, + + .bind_irq_handler = _bind_irq_handler, + + .hw_before_irq = _hw_before_irq, + .hw_cur_int_num = _hw_cur_int_num, + .hw_after_irq = _hw_after_irq, +}; + +struct XiziTrapDriver* hardkernel_intr_init(struct TraceTag* hardkernel_tag) +{ + xizi_trap_driver.sys_irq_init(0); + xizi_trap_driver.cpu_irq_disable(); + return &xizi_trap_driver; +} diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S new file mode 100644 index 000000000..f89a63bc0 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file trampoline.S + * @brief trap in and out code + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024-04-22 + */ + +/************************************************* +File name: trampoline.S +Description: trap in and out code +Others: +History: +1. Date: 2024-04-22 +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ + +#include "memlayout.h" + +#include "core.h" + +.macro savereg + +.endm + +.macro restorereg + +.endm + +.macro usavereg + +.endm + +.macro urestorereg + +.endm + + +.global alltraps +.balign 0x800 +alltraps: +// Current EL with sp0 + j badtrap +.balign 0x80 + j badtrap +.balign 0x80 + j badtrap +.balign 0x80 + j badtrap + +// Current EL with spx +.balign 0x80 + j el1sync +.balign 0x80 + j el1irq +.balign 0x80 + j badtrap +.balign 0x80 + j badtrap + +// Lower EL using aarch64 +.balign 0x80 + j el0sync +.balign 0x80 + j el0irq +.balign 0x80 + j badtrap +.balign 0x80 + j badtrap + +// Lower EL using aarch32 +.balign 0x80 + j badtrap +.balign 0x80 + j badtrap +.balign 0x80 + j badtrap +.balign 0x80 + j badtrap + +badtrap: + j . + +el1sync: + j . + +el1irq: + ret + +el0sync: + + ret + +el0irq: + jal intr_irq_dispatch + +.global trap_return +trap_return: + ret diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/Makefile index 5a96ab711..aaba3c920 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/Makefile @@ -1,4 +1,9 @@ +ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), ) SRC_DIR := arm +endif +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := riscv +endif include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/Makefile index 8b1378917..dd587adc4 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/Makefile @@ -1 +1,5 @@ +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := rv64gc +endif +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/Makefile new file mode 100644 index 000000000..6b8df00e5 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := bootmmu.c mmu.c pagetable_attr.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c new file mode 100644 index 000000000..ba391ff25 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file bootmmu.c + * @brief build pagetable and enable mmu in boot time + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.26 + */ + +/************************************************* +File name: bootmmu.c +Description: build pagetable and enable mmu in boot time +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include "core.h" +#include "memlayout.h" +#include "mmio_access.h" +#include "mmu.h" +#include "pagetable.h" +#include "registers.h" + +#include +#include + +extern uint64_t kernel_data_end[]; +extern uint64_t kernel_data_begin[]; + +// clang-format off +#define L2_TYPE_TAB 2 +#define L2_PTE_VALID 1 + +#define L3_TYPE_TAB 2 +#define L3_PTE_VALID 1 + +#define L4_TYPE_PAGE (3 << 0) +#define L4_PTE_DEV ((0b00) << 2) // Device memory +#define L4_PTE_NORMAL ((0b01) << 2) // Device memory +#define L4_PTE_AF (1 << 10) // Data Access Permissions + +#define L4_PTE_PXN (1UL << 53) // Privileged eXecute Never +#define L4_PTE_UXN (1UL << 54) // Unprivileged(user) eXecute Never +#define L4_PTE_XN (PTE_PXN|PTE_UXN) // eXecute Never + +#define IDX_MASK (0b111111111) +#define L3_PDE_INDEX(idx) ((idx << LEVEL3_PDE_SHIFT) & L3_IDX_MASK) +// clang-format on + +uint64_t boot_l2pgdir[NUM_LEVEL2_PDE] __attribute__((aligned(0x1000))) = { 0 }; + +uint64_t boot_dev_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 }; +uint64_t boot_kern_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 }; + +uint64_t boot_dev_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 }; +uint64_t boot_kern_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 }; + +static void build_boot_pgdir() +{ + static bool built = false; + if (!built) { + uint64_t dev_phy_mem_base = DEV_PHYMEM_BASE; + + // dev mem + boot_l2pgdir[(dev_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID; + boot_l2pgdir[(MMIO_P2V_WO(dev_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID; + + uint64_t cur_mem_paddr = ALIGNDOWN((uint64_t)DEV_PHYMEM_BASE, LEVEL2_PDE_SIZE); + for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) { + boot_dev_l3pgdir[i] = (uint64_t)boot_dev_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID; + + for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) { + boot_dev_l4pgdirs[i][j] = cur_mem_paddr | L4_TYPE_PAGE | L4_PTE_DEV | L4_PTE_AF | L4_PTE_XN; + if (cur_mem_paddr >= DEV_PHYMEM_BASE && cur_mem_paddr < DEV_PHYMEM_BASE + DEV_MEM_SIZE) { + boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403; + } else { + boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403; + } + + cur_mem_paddr += PAGE_SIZE; + } + } + + // identical mem + boot_l2pgdir[(PHY_MEM_BASE >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID; + boot_l2pgdir[(P2V_WO(PHY_MEM_BASE) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID; + + cur_mem_paddr = ALIGNDOWN((uint64_t)0x00000000ULL, PAGE_SIZE); + for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) { + boot_kern_l3pgdir[i] = (uint64_t)boot_kern_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID; + + for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) { + boot_kern_l4pgdirs[i][j] = cur_mem_paddr | 0x713; + + cur_mem_paddr += PAGE_SIZE; + } + } + + built = true; + } +} + +static void load_boot_pgdir() +{ + + TTBR0_W((uintptr_t)boot_l2pgdir); + TTBR1_W(0); + +#define TCR_TRUE_VALUE (0x0000000080813519ULL) + uint64_t tcr = 0; + TCR_R(tcr); + tcr &= (uint64_t)~0xFF; + tcr |= 0x19; + TCR_W(tcr); + + CLEARTLB(0); + ISB(); +} + + +extern void main(void); +static bool _bss_inited = false; +void bootmain() +{ +#if 0 + build_boot_pgdir(); + load_boot_pgdir(); +// __asm__ __volatile__("add sp, sp, %0" ::"r"(KERN_OFFSET)); + if (!_bss_inited) { + memset(&kernel_data_begin, 0x00, (size_t)((uint64_t)kernel_data_end - (uint64_t)kernel_data_begin)); + _bss_inited = true; + } +#endif + main(); +} + diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/mmu.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/mmu.h new file mode 100644 index 000000000..034a5ddf8 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/mmu.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file mmu.h + * @brief mmu related configure and registers + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024-04-26 + */ +/************************************************* +File name: mmu.h +Description: mmu related configure and registers +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#pragma once + +#include + +#include "memlayout.h" + +// #define TCR_SH1_INNER (0b11 << 28) +// #define TCR_ORGN1_IRGN1_WRITEBACK_WRITEALLOC ((0b01 << 26) | (0b01 << 24)) +// #define TCR_SH0_INNER (0b11 << 12) +// #define TCR_ORGN0_IRGN0_WRITEBACK_WRITEALLOC ((0b01 << 10) | (0b01 << 8)) +#define TCR_IPS (0 << 0) +#define TCR_TG1_4K (0b10 << 30) +#define TCR_TOSZ (0b11001 << 0) +#define TCR_T1SZ (0b11001 << 16) +#define TCR_TG0_4K (0 << 14) + +#define TCR_VALUE \ + (TCR_IPS | TCR_TG1_4K | TCR_TG0_4K | TCR_TOSZ | TCR_T1SZ) + +enum AccessPermission { + AccessPermission_NoAccess = 0, + AccessPermission_KernelOnly = 1, // EL1 + AccessPermission_Reserved = 2, + AccessPermission_KernelUser = 3, // EL1&EL0 +}; + +void GetDevPteAttr(uintptr_t* attr); +void GetUsrPteAttr(uintptr_t* attr); +void GetUsrDevPteAttr(uintptr_t* attr); +void GetKernPteAttr(uintptr_t* attr); +void GetPdeAttr(uintptr_t* attr); + +/* +Enable MMU, cache, write buffer, etc. +*/ +//#define SCTLR_R(val) __asm__ volatile("mrs %0, sctlr_el1" : "=r"(val)::"memory") +//#define SCTLR_W(val) __asm__ volatile("msr sctlr_el1, %0" ::"r"(val) : "memory") +#define SCTLR_R(val) 0 +#define SCTLR_W(val) 0 + +/* +Read and write mmu pagetable register base addr +*/ +//#define TTBR0_R(val) __asm__ volatile("mrs %0, ttbr0_el1" : "=r"(val)::"memory") +//#define TTBR0_W(val) __asm__ volatile("msr ttbr0_el1, %0" ::"r"(val) : "memory") +#define TTBR0_R(val) 0 +#define TTBR0_W(val) 0 + +/* +Read and write mmu pagetable register base addr +*/ +//#define TTBR1_R(val) __asm__ volatile("mrs %0, ttbr1_el1" : "=r"(val)::"memory") +//#define TTBR1_W(val) __asm__ volatile("msr ttbr1_el1, %0" ::"r"(val) : "memory") +#define TTBR1_R(val) 0 +#define TTBR1_W(val) 0 + +/* +Translation Control Register（TCR） +*/ +//#define TCR_R(val) __asm__ volatile("mrs %0, tcr_el1" : "=r"(val)::"memory") +//#define TCR_W(val) __asm__ volatile("msr tcr_el1, %0" ::"r"(val) : "memory") +#define TCR_R(val) 0 +#define TCR_W(val) 0 + +//#define MAIR_R(val) __asm__ volatile("mrs %0, mair_el1" : "=r"(val)::"memory") +//#define MAIR_W(val) __asm__ volatile("msr mair_el1, %0" ::"r"(val) : "memory") +#define MAIR_R(val) 0 +#define MAIR_W(val) 0 +/* +Flush TLB when loading a new page table. +@note If nG is not set in the pte attribute, process switching need flush tlb. +*/ +// #define CLEARTLB(val) __asm__ volatile("tlbi vmalle1" ::: "memory") +//#define CLEARTLB(val) __asm__ volatile("tlbi vmalle1is" ::: "memory") +#define CLEARTLB(val) 0 + +/* +When nG is set in the pte attribute, the process is assigned an ASID, which is stored in the lower 8 bits of the CONTEXTIDR register. +When the process switches, the flush TLB is no longer required anymore. +*/ +//#define CONTEXTIDR_R(val) __asm__ volatile("mrs %0, contextidr_el1" : "=r"(val)) +//#define CONTEXTIDR_W(val) __asm__ volatile("msr contextidr_el1, %0" ::"r"(val)) +#define CONTEXTIDR_R(val) 0 +#define CONTEXTIDR_W(val) 0 + +#ifndef __ASSEMBLER__ +#include +__attribute__((always_inline)) static inline uint64_t v2p(void* a) { return ((uint64_t)(a)) - KERN_MEM_BASE; } +__attribute__((always_inline)) static inline void* p2v(uint64_t a) { return (void*)((a) + KERN_MEM_BASE); } +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h new file mode 100644 index 000000000..ef7e8ef24 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file memlayout.h + * @brief virtual memory and physical memory layout + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024-04-25 + */ +/************************************************* +File name: memlayout.h +Description: virtual memory and physical memory layout +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#pragma once + +// Memory layout +// clang-format off + +#define ARCH_BIT 64 + +/* A55 physical memory layout */ +#define PHY_MEM_BASE (0x0000000010000000ULL) +#define PHY_USER_FREEMEM_BASE (0x0000000040000000ULL) +#define PHY_USER_FREEMEM_TOP (0x00000000e0000000ULL) +#define PHY_MEM_STOP (0x00000000e0000000ULL) + +/* PTE-PAGE_SIZE */ +#define LEVEL4_PTE_SHIFT 12 +#define LEVEL4_PTE_SIZE (1 << LEVEL4_PTE_SHIFT) + +/* PDE-SECTION_SIZE */ +#define LEVEL3_PDE_SHIFT 21 +#define LEVEL3_PDE_SIZE (1 << LEVEL3_PDE_SHIFT) + +#define LEVEL2_PDE_SHIFT 30 +#define LEVEL2_PDE_SIZE (1 << LEVEL2_PDE_SHIFT) + +#define LEVEL1_PTE_SHIFT 39 + +#define NUM_LEVEL2_PDE (1 << (LEVEL1_PTE_SHIFT - LEVEL2_PDE_SHIFT)) +#define NUM_LEVEL3_PDE (1 << (LEVEL2_PDE_SHIFT - LEVEL3_PDE_SHIFT)) // how many PDE in a PT +#define NUM_LEVEL4_PTE (1 << (LEVEL3_PDE_SHIFT - LEVEL4_PTE_SHIFT)) // how many PTE in a PT +#define NUM_TOPLEVEL_PDE NUM_LEVEL2_PDE + +#define PAGE_SIZE LEVEL4_PTE_SIZE +#define MAX_NR_FREE_PAGES ((PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT) + +/* Deivce memory layout */ +#define DEV_PHYMEM_BASE (0x00000000F0000000ULL) +#define DEV_VRTMEM_BASE (0x00000040F0000000ULL) +#define DEV_MEM_SIZE (0x0000000010000000ULL) + +/* User memory layout */ +#define USER_STACK_SIZE PAGE_SIZE +#define USER_MEM_BASE (0x0000000000000000ULL) +#define USER_MEM_TOP (0x0000004000000000ULL) +#define USER_IPC_SPACE_BASE (0x0000003000000000ULL) +#define USER_IPC_USE_ALLOCATOR_WATERMARK (0x0000003000010000ULL) +#define USER_IPC_SPACE_TOP (USER_IPC_SPACE_BASE + 0x10000000ULL) + +/* Kernel memory layout */ +#define KERN_MEM_BASE (0x0000006010000000ULL) // First kernel virtual address +#define KERN_OFFSET (KERN_MEM_BASE - PHY_MEM_BASE) + +#define V2P(a) (((uint64_t)(a)) - KERN_OFFSET) +#define P2V(a) ((void *)(((char *)(a)) + KERN_OFFSET)) + +#define V2P_WO(x) ((x) - KERN_OFFSET) // same as V2P, but without casts +#define P2V_WO(x) ((x) + KERN_OFFSET) // same as P2V, but without casts +// clang-format on \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c new file mode 100644 index 000000000..7fcf5a1f6 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file mmu.c + * @brief mmu operations + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.26 + */ + +/************************************************* +File name: mmu.c +Description: mmu operations +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ + +#include + +#include "mmu.h" + +#include "cache_common_ope.h" +#include "mmu_common.h" +#include "trap_common.h" + +// extern struct MmuCommonDone mmu_common_done; +static struct MmuDriverRightGroup right_group; + +void load_pgdir(uintptr_t pgdir_paddr) +{ + /* get cache driver */ + struct ICacheDone* p_icache_done = AchieveResource(&right_group.icache_driver_tag); + struct DCacheDone* p_dcache_done = AchieveResource(&right_group.dcache_driver_tag); + + TTBR0_W((uint64_t)pgdir_paddr); + DSB(); + CLEARTLB(0); + ISB(); + p_icache_done->invalidateall(); + p_dcache_done->flushall(); +} + +__attribute__((always_inline)) inline static void _tlb_flush(uintptr_t va) +{ +// __asm__ volatile("tlbi vae1is, %0" ::"r"(va)); +} + +static void tlb_flush_range(uintptr_t vstart, int len) +{ + uintptr_t vaddr = vstart; + uintptr_t vend = vaddr + len; + for (; vaddr < vend; vaddr += PAGE_SIZE) { + _tlb_flush(vaddr); + } +} + +static void tlb_flush_all() +{ + CLEARTLB(0); +} + +static struct MmuCommonDone mmu_common_done = { + .MmuDevPteAttr = GetDevPteAttr, + .MmuPdeAttr = GetPdeAttr, + .MmuUsrPteAttr = GetUsrPteAttr, + .MmuUsrDevPteAttr = GetUsrDevPteAttr, + .MmuKernPteAttr = GetKernPteAttr, + + .LoadPgdir = load_pgdir, + .TlbFlushAll = tlb_flush_all, + .TlbFlush = tlb_flush_range, +}; + +struct MmuCommonDone* hardkernel_mmu_init(struct TraceTag* hardkernel_tag, char* icache_name, char* dcache_name) +{ + /* init right group for mmu driver */ + AchieveResourceTag(&right_group.icache_driver_tag, hardkernel_tag, icache_name); + AchieveResourceTag(&right_group.dcache_driver_tag, hardkernel_tag, dcache_name); + + return &mmu_common_done; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/pagetable_attr.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/pagetable_attr.c new file mode 100644 index 000000000..8085ad036 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/pagetable_attr.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file pagetable_attr.c + * @brief mmu entry attributes + * @version 1. + * @author AIIT XUOS Lab + * @date 2023.04.26 + */ + +/************************************************* +File name: pagetable_attr.c +Description: mmu entry attributes +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include "mmu.h" +#include "mmu_common.h" + +// clang-format off +#define ARMV8_PTE_ATTR_MASK(attr) (((attr) & 0b111) << 2) +#define ARMV8_PTE_DEVICE ARMV8_PTE_ATTR_MASK(0x0) +#define ARMV8_PTE_NORMAL ARMV8_PTE_ATTR_MASK(0x1) + +#define ARMV8_PTE_AP(ap) (((ap) & 0b11) << 6) +#define ARMV8_PTE_AP_U ARMV8_PTE_AP(0x01) +#define ARMV8_PTE_AP_K ARMV8_PTE_AP(0x00) +#define ARMV8_PTE_AP_RO ARMV8_PTE_AP(0b10) +#define ARMV8_PTE_AP_RW ARMV8_PTE_AP(0b00) + +#define ARMV8_PTE_AF (0x1 << 10) +#define ARMV8_PTE_PXN (1ULL << 53) // Privileged eXecute Never +#define ARMV8_PTE_UXN (1ULL << 54) // Unprivileged(user) eXecute Never +#define ARMV8_PTE_XN (ARMV8_PTE_PXN | ARMV8_PTE_UXN) + +#define ARMV8_PTE_VALID (0b11 << 0) +#define ARMV8_PDE_VALID (0b11 << 0) + +// clang-format on + +void GetUsrPteAttr(uintptr_t* attr) +{ + // *attr = ARMV8_PTE_AP_U | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_NORMAL | ARMV8_PTE_VALID; + *attr = 0x713 | ARMV8_PTE_AP_U; +} + +void GetUsrDevPteAttr(uintptr_t* attr) +{ + // *attr = ARMV8_PTE_AP_U | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_DEVICE | ARMV8_PTE_XN | ARMV8_PTE_VALID; + *attr = 0x403 | ARMV8_PTE_AP_U; +} + +void GetDevPteAttr(uintptr_t* attr) +{ + // *attr = ARMV8_PTE_AP_K | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_DEVICE | ARMV8_PTE_XN | ARMV8_PTE_VALID; + *attr = 0x403ULL; +} + +void GetKernPteAttr(uintptr_t* attr) +{ + // *attr = ARMV8_PTE_AP_K | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_NORMAL | ARMV8_PTE_VALID; + *attr = 0x713ULL; +} + +void GetPdeAttr(uintptr_t* attr) +{ + *attr = ARMV8_PDE_VALID; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/uart/Makefile index b555517f4..f18170cb0 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/Makefile @@ -1,4 +1,10 @@ +ifneq ($(findstring $(BOARD), 3568 imx6q-sabrelite zynq7000-zc702), ) SRC_DIR := arm +endif +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := riscv +endif + SRC_FILES := uart_common_ope.c include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/Makefile new file mode 100644 index 000000000..dd587adc4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/Makefile @@ -0,0 +1,5 @@ +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_DIR := rv64gc +endif + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/Makefile new file mode 100644 index 000000000..42d2e83f3 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/Makefile @@ -0,0 +1,3 @@ +SRC_DIR := uart_io_for_$(BOARD) + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/Makefile new file mode 100644 index 000000000..a8661f85c --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := uart.c ns16550.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h new file mode 100644 index 000000000..8847befca --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h @@ -0,0 +1,198 @@ +/* + * NS16550 Serial Port + * originally from linux source (arch/powerpc/boot/ns16550.h) + * + * Cleanup and unification + * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH + * + * modified slightly to + * have addresses as offsets from CONFIG_SYS_ISA_BASE + * added a few more definitions + * added prototypes for ns16550.c + * reduced no of com ports to 2 + * modifications (c) Rob Taylor, Flying Pig Systems. 2000. + * + * added support for port on 64-bit bus + * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems + */ + +/* + * Note that the following macro magic uses the fact that the compiler + * will not allocate storage for arrays of size 0 + */ + +#include + +/* + * For driver model we always use one byte per register, and sort out the + * differences in the driver + */ +#define CONFIG_SYS_NS16550_REG_SIZE (-1) + +#define UART_REG(x) \ + unsigned char x; \ + unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; + +/** + * struct ns16550_platdata - information about a NS16550 port + * + * @base: Base register address + * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) + * @clock: UART base clock speed in Hz + */ +struct ns16550_platdata { + unsigned long base; + int reg_shift; + int clock; + int reg_offset; + uint32_t fcr; +}; + +struct udevice; + +struct NS16550 { + UART_REG(rbr); /* 0 */ + UART_REG(ier); /* 1 */ + UART_REG(fcr); /* 2 */ + UART_REG(lcr); /* 3 */ + UART_REG(mcr); /* 4 */ + UART_REG(lsr); /* 5 */ + UART_REG(msr); /* 6 */ + UART_REG(spr); /* 7 */ +#ifdef CONFIG_SOC_DA8XX + UART_REG(reg8); /* 8 */ + UART_REG(reg9); /* 9 */ + UART_REG(revid1); /* A */ + UART_REG(revid2); /* B */ + UART_REG(pwr_mgmt); /* C */ + UART_REG(mdr1); /* D */ +#else + UART_REG(mdr1); /* 8 */ + UART_REG(reg9); /* 9 */ + UART_REG(regA); /* A */ + UART_REG(regB); /* B */ + UART_REG(regC); /* C */ + UART_REG(regD); /* D */ + UART_REG(regE); /* E */ + UART_REG(uasr); /* F */ + UART_REG(scr); /* 10*/ + UART_REG(ssr); /* 11*/ +#endif +#ifdef CONFIG_DM_SERIAL + struct ns16550_platdata* plat; +#endif +}; + +#define thr rbr +#define iir fcr +#define dll rbr +#define dlm ier + +typedef struct NS16550* NS16550_t; + +/* + * These are the definitions for the FIFO Control Register + */ +#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ + +#define UART_FCR_RXSR 0x02 /* Receiver soft reset */ +#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ + +/* Ingenic JZ47xx specific UART-enable bit. */ +#define UART_FCR_UME 0x10 + +/* Clear & enable FIFOs */ +#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR) + +/* + * These are the definitions for the Modem Control Register + */ +#define UART_MCR_DTR 0x01 /* DTR */ +#define UART_MCR_RTS 0x02 /* RTS */ +#define UART_MCR_OUT1 0x04 /* Out 1 */ +#define UART_MCR_OUT2 0x08 /* Out 2 */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */ + +#define UART_MCR_DMA_EN 0x04 +#define UART_MCR_TX_DFR 0x08 + +/* + * These are the definitions for the Line Control Register + * + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. + */ +#define UART_LCR_WLS_MSK 0x03 /* character length select mask */ +#define UART_LCR_WLS_5 0x00 /* 5 bit character length */ +#define UART_LCR_WLS_6 0x01 /* 6 bit character length */ +#define UART_LCR_WLS_7 0x02 /* 7 bit character length */ +#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ +#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */ +#define UART_LCR_PEN 0x08 /* Parity eneble */ +#define UART_LCR_EPS 0x10 /* Even Parity Select */ +#define UART_LCR_STKP 0x20 /* Stick Parity */ +#define UART_LCR_SBRK 0x40 /* Set Break */ +#define UART_LCR_BKSE 0x80 /* Bank select enable */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ + +/* + * These are the definitions for the Line Status Register + */ +#define UART_LSR_DR 0x01 /* Data ready */ +#define UART_LSR_OE 0x02 /* Overrun */ +#define UART_LSR_PE 0x04 /* Parity error */ +#define UART_LSR_FE 0x08 /* Framing error */ +#define UART_LSR_BI 0x10 /* Break */ +#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ +#define UART_LSR_TEMT 0x40 /* Xmitter empty */ +#define UART_LSR_ERR 0x80 /* Error */ + +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ + +/* + * These are the definitions for the Interrupt Identification Register + */ +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ + +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ + +/* + * These are the definitions for the Interrupt Enable Register + */ +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ + +/* useful defaults for LCR */ +#define UART_LCR_8N1 0x03 + +void NS16550_init(NS16550_t com_port, int baud_divisor); +void NS16550_putc(NS16550_t com_port, char c); +char NS16550_getc(NS16550_t com_port); +int NS16550_tstc(NS16550_t com_port); +void NS16550_reinit(NS16550_t com_port, int baud_divisor); + +void _debug_uart_init(void); +void _debug_uart_putc(int ch); +int _debug_uart_getc(void); \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/uart.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/uart.h new file mode 100644 index 000000000..a168a10e7 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/uart.h @@ -0,0 +1,29 @@ +#pragma once + +#include "memlayout.h" +#include "mmio_access.h" + +#define UART0_BASE (0x09000000ULL) +#define UART0_REG(reg) ((volatile uint32_t*)(MMIO_P2V_WO(UART0_BASE + reg))) + +// the UART control registers. +// pl011 +#define DR 0x00 +#define FR 0x18 +#define FR_RXFE (1 << 4) // recieve fifo empty +#define FR_TXFF (1 << 5) // transmit fifo full +#define FR_RXFF (1 << 6) // recieve fifo full +#define FR_TXFE (1 << 7) // transmit fifo empty +#define IBRD 0x24 +#define FBRD 0x28 +#define LCRH 0x2c +#define LCRH_FEN (1 << 4) +#define LCRH_WLEN_8BIT (3 << 5) +#define CR 0x30 +#define IMSC 0x38 +#define INT_RX_ENABLE (1 << 4) +#define INT_TX_ENABLE (1 << 5) +#define ICR 0x44 + +#define UART_READ_REG(reg) (*(UART0_REG(reg))) +#define UART_WRITE_REG(reg, v) (*(UART0_REG(reg)) = (v)) \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c new file mode 100644 index 000000000..d9a607d2b --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c @@ -0,0 +1,111 @@ +/* + * COM1 NS16550 support + * originally from linux source (arch/powerpc/boot/ns16550.c) + * modified to use CONFIG_SYS_ISA_MEM and new defines + */ + +#include + +#include "mmio_access.h" +#include "ns16550.h" + +//#define UART_ADDR MMIO_P2V_WO(0xFE660000) +//#define UART_ADDR (0xFE660000) +#define UART_ADDR MMIO_P2V_WO (10000000) + +#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ +#define UART_MCRVAL (UART_MCR_DTR | UART_MCR_RTS) /* RTS/DTR */ + +#define out_le32(a, v) (*(volatile uint32_t*)(a) = (v)) +#define in_le32(a) (*(volatile uint32_t*)(a)) + +#ifndef CONFIG_SYS_NS16550_IER +#define CONFIG_SYS_NS16550_IER 0x00 +#endif /* CONFIG_SYS_NS16550_IER */ + +#define serial_dout(reg, value) \ + serial_out_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \ + 2, value) +#define serial_din(reg) \ + serial_in_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \ + 2) + +static inline void serial_out_shift(void* addr, int shift, int value) +{ + out_le32(addr, value); +} + +static inline int serial_in_shift(void* addr, int shift) +{ + return in_le32(addr); +} + +#ifndef CONFIG_SYS_NS16550_CLK +#define CONFIG_SYS_NS16550_CLK 0 +#endif + +#if 0 +#define DIV_ROUND_CLOSEST(x, divisor) ( \ + { \ + typeof(x) __x = x; \ + typeof(divisor) __d = divisor; \ + (((typeof(x))-1) > 0 || ((typeof(divisor))-1) > 0 || (__x) > 0) ? (((__x) + ((__d) / 2)) / (__d)) : (((__x) - ((__d) / 2)) / (__d)); \ + }) +#endif +#define DIV_ROUND_CLOSEST(x, divisor) ( \ + { \ + ((x) > 0) ? (((x) + ((divisor) / 2)) / (divisor)) : (((x) - ((divisor) / 2)) / (divisor)); \ + }) + + +int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate) +{ + const unsigned int mode_x_div = 16; + + return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate); +} + +void _debug_uart_init(void) +{ + struct NS16550* com_port = (struct NS16550*)UART_ADDR; + + /* + * We copy the code from above because it is already horribly messy. + * Trying to refactor to nicely remove the duplication doesn't seem + * feasible. The better fix is to move all users of this driver to + * driver model. + */ + int baud_divisor = ns16550_calc_divisor(com_port, 24000000, + 115200); + serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER); + serial_dout(&com_port->mcr, UART_MCRVAL); + serial_dout(&com_port->fcr, UART_FCR_DEFVAL); + + serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); + serial_dout(&com_port->dll, baud_divisor & 0xff); + serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); + serial_dout(&com_port->lcr, UART_LCRVAL); +} + +void _debug_uart_putc(int ch) +{ + static struct NS16550* com_port = (struct NS16550*)UART_ADDR; + + if (ch == '\n') { + _debug_uart_putc('\r'); + } + + while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) + ; + serial_dout(&com_port->thr, ch); +} + +int _debug_uart_getc(void) +{ + static struct NS16550* com_port = (struct NS16550*)UART_ADDR; + + while (!(serial_din(&com_port->lsr) & UART_LSR_DR)) + ; + + return serial_din(&com_port->rbr); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/uart.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/uart.c new file mode 100644 index 000000000..de03611a2 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/uart.c @@ -0,0 +1,45 @@ +// +// low-level driver routines for pl011 UART. +// + +#include "uart.h" +#include "actracer.h" +#include "ns16550.h" +#include "uart_common_ope.h" + +// the UART control registers are memory-mapped +// at address UART0. this macro returns the +// address of one of the registers. + +void uartinit(void) +{ + _debug_uart_init(); +} + +void uartputc(uint8_t c) +{ + _debug_uart_putc((int)c); +} + +static uint8_t uartgetc(void) +{ + return (uint8_t)_debug_uart_getc(); +} + +static uint32_t UartGetIrqnum() +{ + return 0; +} + +static struct XiziSerialDriver hardkernel_serial_driver = { + .sys_serial_init = uartinit, + .get_serial_irqnum = UartGetIrqnum, + .putc = uartputc, + .getc = uartgetc, +}; + +struct XiziSerialDriver* hardkernel_uart_init(struct TraceTag* hardkernel_tag) +{ + hardkernel_serial_driver.sys_serial_init(); + return &hardkernel_serial_driver; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/path_kernel.mk b/Ubiquitous/XiZi_AIoT/path_kernel.mk index 2a8bca965..da097bfc9 100755 --- a/Ubiquitous/XiZi_AIoT/path_kernel.mk +++ b/Ubiquitous/XiZi_AIoT/path_kernel.mk @@ -54,6 +54,21 @@ KERNELPATHS += \ -I$(KERNEL_ROOT)/hardkernel/cache/L1/arm/cortex-a55/ endif +ifeq ($(BOARD), jh7110) +KERNELPATHS += \ + -I$(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/preboot_for_$(BOARD)/include \ + -I$(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/ \ + -I$(KERNEL_ROOT)/hardkernel/cache/L1/riscv/rv64gc/ \ + -I$(KERNEL_ROOT)/hardkernel/clock/riscv/rv64gc/$(BOARD)/include \ + -I$(KERNEL_ROOT)/hardkernel/intr/riscv/rv64gc/ \ + -I$(KERNEL_ROOT)/hardkernel/intr/riscv/rv64gc/$(BOARD) \ + -I$(KERNEL_ROOT)/hardkernel/intr/riscv/rv64gc/gicv3 \ + -I$(KERNEL_ROOT)/hardkernel/mmu/riscv/rv64gc/include \ + -I$(KERNEL_ROOT)/hardkernel/mmu/riscv/rv64gc/$(BOARD) \ + -I$(KERNEL_ROOT)/hardkernel/uart/riscv/rv64gc/uart_io_for_$(BOARD)/include \ + -I$(KERNEL_ROOT)/hardkernel/uart/riscv/rv64gc/ +endif + KERNELPATHS += \ -I$(KERNEL_ROOT)/hardkernel \ -I$(KERNEL_ROOT)/hardkernel/clock/ \ diff --git a/Ubiquitous/XiZi_AIoT/softkernel/load_apps.S b/Ubiquitous/XiZi_AIoT/softkernel/load_apps.S index 597d60af0..a12911287 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/load_apps.S +++ b/Ubiquitous/XiZi_AIoT/softkernel/load_apps.S @@ -30,16 +30,16 @@ Modification: .section .rawdata_fs_img .globl user_apps user_apps: - .incbin "../services/app/fs.img" +// .incbin "../services/app/fs.img" .section .rawdata_init .globl initapp initapp: - .incbin "../services/app/bin/shell" +// .incbin "../services/app/bin/shell" .section .rawdata_memfs .globl memfs memfs: - .incbin "../services/app/bin/fs_server" +// .incbin "../services/app/bin/fs_server" .end diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile b/Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile index 67cd1ed69..35bd24a90 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile +++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile @@ -8,6 +8,9 @@ endif ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), ) SRC_FILES:= kalloc.c pagetable.c pagetable_level2.c buddy.c object_allocator.c share_page.c endif +ifneq ($(findstring $(BOARD), jh7110), ) +SRC_FILES := kalloc.c pagetable.c pagetable_level3.c buddy.c object_allocator.c share_page.c +endif include $(KERNEL_ROOT)/compiler.mk From c97fa52c5f9cb8eb054df2d08ee701c24d2d164b Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 18 Oct 2024 11:01:43 +0800 Subject: [PATCH 02/54] jh7110 uart debug serial port printing --- .../riscv/rv64gc/preboot_for_jh7110/boot.S | 23 +- .../rv64gc/preboot_for_jh7110/jh7110.lds | 14 +- .../hardkernel/mmu/riscv/rv64gc/bootmmu.c | 5 +- .../uart_io_for_jh7110/include/ns16550.h | 236 ++++++++-------- .../riscv/rv64gc/uart_io_for_jh7110/ns16550.c | 251 +++++++++++++----- 5 files changed, 332 insertions(+), 197 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S index e50d8d63d..6393c76c0 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S @@ -9,6 +9,8 @@ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. * See the Mulan PSL v2 for more details. */ + +/* #include */ #include "core.h" #define HCR_VALUE (1 << 31) @@ -21,14 +23,19 @@ _boot_start: - - j primary_cpu_init - - j . + j primary_cpu_init + j . primary_cpu_init: - + la t0, boot_start_addr + la t1, boot_end_addr + li t2, 0 + +clear_loop: + bge t0, t1, clear_done + sb t2, 0(t0) + addi t0, t0, 4 + j clear_loop + +clear_done: j bootmain - - - diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds index fa95d5271..9dc78f76d 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds @@ -42,7 +42,7 @@ ENTRY( _boot_start ) BOOT_STACK_SIZE = 0x4000; MEMORY { - phy_ddr3 (rwx) : ORIGIN = 0x10000000, LENGTH = 1024M + phy_ddr3 (rwx) : ORIGIN = 0x40200000, LENGTH = 1024M vir_ddr3 (rwx) : ORIGIN = 0x000000601040E000, LENGTH = 1024M } @@ -62,21 +62,21 @@ SECTIONS boot.o(.text) bootmmu.o(.text .text.*) - /* ns16550.o(.text .text.*) */ + ns16550.o(.text .text.*) boot.o(.rodata .rodata.*) bootmmu.o(.rodata .rodata.*) - /* ns16550.o(.rodata .rodata.*) */ + ns16550.o(.rodata .rodata.*) boot.o(.data .data.*) bootmmu.o(.data .data.*) - /* ns16550.o(.data .data.*) */ + ns16550.o(.data .data.*) PROVIDE(boot_start_addr = .); boot.o(.bss .bss.* COMMON) bootmmu.o(.bss .bss.* COMMON) - /* ns16550.o(.bss .bss.* COMMON) */ + ns16550.o(.bss .bss.* COMMON) /* stack for booting code. */ . = ALIGN(0x1000); @@ -89,11 +89,11 @@ SECTIONS PROVIDE(boot_end_addr = .); } > phy_ddr3 - .text : AT(0x1041C000) { + /* AT: 0x40200000 + 0x0041C000 */ + .text : AT(0x4061C000) { . = ALIGN(0x1000); *(.text .text.* .gnu.linkonce.t.*) } - . = ALIGN(0x1000); .data : { *(.data .data.*) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c index ba391ff25..af7c13eb0 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c @@ -32,6 +32,7 @@ Modification: #include "mmu.h" #include "pagetable.h" #include "registers.h" +#include "ns16550.h" #include #include @@ -134,6 +135,7 @@ extern void main(void); static bool _bss_inited = false; void bootmain() { + _debug_uart_init(); #if 0 build_boot_pgdir(); load_boot_pgdir(); @@ -142,7 +144,8 @@ void bootmain() memset(&kernel_data_begin, 0x00, (size_t)((uint64_t)kernel_data_end - (uint64_t)kernel_data_begin)); _bss_inited = true; } -#endif + main(); +#endif } diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h index 8847befca..fbc0cd530 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h @@ -21,6 +21,9 @@ * will not allocate storage for arrays of size 0 */ +#ifndef __ns16550_h +#define __ns16550_h + #include /* @@ -29,58 +32,58 @@ */ #define CONFIG_SYS_NS16550_REG_SIZE (-1) -#define UART_REG(x) \ - unsigned char x; \ - unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; +#define UART_REG(x) \ + unsigned char x; \ + unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; /** - * struct ns16550_platdata - information about a NS16550 port + * struct ns16550_plat - information about a NS16550 port * * @base: Base register address + * @reg_width: IO accesses size of registers (in bytes, 1 or 4) * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) + * @reg_offset: Offset to start of registers (normally 0) * @clock: UART base clock speed in Hz + * @fcr: Offset of FCR register (normally UART_FCR_DEFVAL) */ -struct ns16550_platdata { - unsigned long base; - int reg_shift; - int clock; - int reg_offset; - uint32_t fcr; +struct ns16550_plat { + unsigned long base; + int reg_width; + int reg_shift; + int reg_offset; + int clock; + uint32_t fcr; }; -struct udevice; - -struct NS16550 { - UART_REG(rbr); /* 0 */ - UART_REG(ier); /* 1 */ - UART_REG(fcr); /* 2 */ - UART_REG(lcr); /* 3 */ - UART_REG(mcr); /* 4 */ - UART_REG(lsr); /* 5 */ - UART_REG(msr); /* 6 */ - UART_REG(spr); /* 7 */ +struct ns16550 { + UART_REG(rbr); /* 0 */ + UART_REG(ier); /* 1 */ + UART_REG(fcr); /* 2 */ + UART_REG(lcr); /* 3 */ + UART_REG(mcr); /* 4 */ + UART_REG(lsr); /* 5 */ + UART_REG(msr); /* 6 */ + UART_REG(spr); /* 7 */ #ifdef CONFIG_SOC_DA8XX - UART_REG(reg8); /* 8 */ - UART_REG(reg9); /* 9 */ - UART_REG(revid1); /* A */ - UART_REG(revid2); /* B */ - UART_REG(pwr_mgmt); /* C */ - UART_REG(mdr1); /* D */ + UART_REG(reg8); /* 8 */ + UART_REG(reg9); /* 9 */ + UART_REG(revid1); /* A */ + UART_REG(revid2); /* B */ + UART_REG(pwr_mgmt); /* C */ + UART_REG(mdr1); /* D */ #else - UART_REG(mdr1); /* 8 */ - UART_REG(reg9); /* 9 */ - UART_REG(regA); /* A */ - UART_REG(regB); /* B */ - UART_REG(regC); /* C */ - UART_REG(regD); /* D */ - UART_REG(regE); /* E */ - UART_REG(uasr); /* F */ - UART_REG(scr); /* 10*/ - UART_REG(ssr); /* 11*/ -#endif -#ifdef CONFIG_DM_SERIAL - struct ns16550_platdata* plat; + UART_REG(mdr1); /* 8 */ + UART_REG(reg9); /* 9 */ + UART_REG(regA); /* A */ + UART_REG(regB); /* B */ + UART_REG(regC); /* C */ + UART_REG(regD); /* D */ + UART_REG(regE); /* E */ + UART_REG(uasr); /* F */ + UART_REG(scr); /* 10*/ + UART_REG(ssr); /* 11*/ #endif + struct ns16550_plat *plat; }; #define thr rbr @@ -88,42 +91,42 @@ struct NS16550 { #define dll rbr #define dlm ier -typedef struct NS16550* NS16550_t; - /* * These are the definitions for the FIFO Control Register */ -#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ -#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ -#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ -#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ -#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ -#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ -#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ -#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ -#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ +#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ -#define UART_FCR_RXSR 0x02 /* Receiver soft reset */ -#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ +#define UART_FCR_RXSR 0x02 /* Receiver soft reset */ +#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ /* Ingenic JZ47xx specific UART-enable bit. */ -#define UART_FCR_UME 0x10 +#define UART_FCR_UME 0x10 /* Clear & enable FIFOs */ -#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR) +#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \ + UART_FCR_RXSR | \ + UART_FCR_TXSR) /* * These are the definitions for the Modem Control Register */ -#define UART_MCR_DTR 0x01 /* DTR */ -#define UART_MCR_RTS 0x02 /* RTS */ -#define UART_MCR_OUT1 0x04 /* Out 1 */ -#define UART_MCR_OUT2 0x08 /* Out 2 */ -#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ -#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */ +#define UART_MCR_DTR 0x01 /* DTR */ +#define UART_MCR_RTS 0x02 /* RTS */ +#define UART_MCR_OUT1 0x04 /* Out 1 */ +#define UART_MCR_OUT2 0x08 /* Out 2 */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */ -#define UART_MCR_DMA_EN 0x04 -#define UART_MCR_TX_DFR 0x08 +#define UART_MCR_DMA_EN 0x04 +#define UART_MCR_TX_DFR 0x08 /* * These are the definitions for the Line Control Register @@ -131,68 +134,85 @@ typedef struct NS16550* NS16550_t; * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. */ -#define UART_LCR_WLS_MSK 0x03 /* character length select mask */ -#define UART_LCR_WLS_5 0x00 /* 5 bit character length */ -#define UART_LCR_WLS_6 0x01 /* 6 bit character length */ -#define UART_LCR_WLS_7 0x02 /* 7 bit character length */ -#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ -#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */ -#define UART_LCR_PEN 0x08 /* Parity eneble */ -#define UART_LCR_EPS 0x10 /* Even Parity Select */ -#define UART_LCR_STKP 0x20 /* Stick Parity */ -#define UART_LCR_SBRK 0x40 /* Set Break */ -#define UART_LCR_BKSE 0x80 /* Bank select enable */ -#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ +#define UART_LCR_WLS_MSK 0x03 /* character length select mask */ +#define UART_LCR_WLS_5 0x00 /* 5 bit character length */ +#define UART_LCR_WLS_6 0x01 /* 6 bit character length */ +#define UART_LCR_WLS_7 0x02 /* 7 bit character length */ +#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ +#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */ +#define UART_LCR_PEN 0x08 /* Parity eneble */ +#define UART_LCR_EPS 0x10 /* Even Parity Select */ +#define UART_LCR_STKP 0x20 /* Stick Parity */ +#define UART_LCR_SBRK 0x40 /* Set Break */ +#define UART_LCR_BKSE 0x80 /* Bank select enable */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ /* * These are the definitions for the Line Status Register */ -#define UART_LSR_DR 0x01 /* Data ready */ -#define UART_LSR_OE 0x02 /* Overrun */ -#define UART_LSR_PE 0x04 /* Parity error */ -#define UART_LSR_FE 0x08 /* Framing error */ -#define UART_LSR_BI 0x10 /* Break */ -#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ -#define UART_LSR_TEMT 0x40 /* Xmitter empty */ -#define UART_LSR_ERR 0x80 /* Error */ +#define UART_LSR_DR 0x01 /* Data ready */ +#define UART_LSR_OE 0x02 /* Overrun */ +#define UART_LSR_PE 0x04 /* Parity error */ +#define UART_LSR_FE 0x08 /* Framing error */ +#define UART_LSR_BI 0x10 /* Break */ +#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ +#define UART_LSR_TEMT 0x40 /* Xmitter empty */ +#define UART_LSR_ERR 0x80 /* Error */ -#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ -#define UART_MSR_RI 0x40 /* Ring Indicator */ -#define UART_MSR_DSR 0x20 /* Data Set Ready */ -#define UART_MSR_CTS 0x10 /* Clear to Send */ -#define UART_MSR_DDCD 0x08 /* Delta DCD */ -#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ -#define UART_MSR_DDSR 0x02 /* Delta DSR */ -#define UART_MSR_DCTS 0x01 /* Delta CTS */ +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ /* * These are the definitions for the Interrupt Identification Register */ -#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ -#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ -#define UART_IIR_MSI 0x00 /* Modem status interrupt */ -#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ -#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ -#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ /* * These are the definitions for the Interrupt Enable Register */ -#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ -#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ -#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ -#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ /* useful defaults for LCR */ -#define UART_LCR_8N1 0x03 +#define UART_LCR_8N1 0x03 + +void ns16550_init(struct ns16550 *com_port, int baud_divisor); +void ns16550_putc(struct ns16550 *com_port, char c); +char ns16550_getc(struct ns16550 *com_port); +int ns16550_tstc(struct ns16550 *com_port); +void ns16550_reinit(struct ns16550 *com_port, int baud_divisor); + +/** + * ns16550_calc_divisor() - calculate the divisor given clock and baud rate + * + * Given the UART input clock and required baudrate, calculate the divisor + * that should be used. + * + * @port: UART port + * @clock: UART input clock speed in Hz + * @baudrate: Required baud rate + * @return baud rate divisor that should be used + */ +int ns16550_calc_divisor(struct ns16550 *port, int clock, int baudrate); -void NS16550_init(NS16550_t com_port, int baud_divisor); -void NS16550_putc(NS16550_t com_port, char c); -char NS16550_getc(NS16550_t com_port); -int NS16550_tstc(NS16550_t com_port); -void NS16550_reinit(NS16550_t com_port, int baud_divisor); void _debug_uart_init(void); void _debug_uart_putc(int ch); -int _debug_uart_getc(void); \ No newline at end of file +int _debug_uart_getc(void); +void _debug_uart_printascii(const char *str); + +#endif /* __ns16550_h */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c index d9a607d2b..275dfe16c 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c @@ -4,108 +4,213 @@ * modified to use CONFIG_SYS_ISA_MEM and new defines */ -#include +#include -#include "mmio_access.h" -#include "ns16550.h" +struct ns16550 g_ns16550_com_port = {0}; +struct ns16550_plat g_ns16550_plat = {0}; -//#define UART_ADDR MMIO_P2V_WO(0xFE660000) -//#define UART_ADDR (0xFE660000) -#define UART_ADDR MMIO_P2V_WO (10000000) +#define CONFIG_SYS_NS16550_UART_BASE 0x10000000 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_NS16550_CLK 24000000 -#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ -#define UART_MCRVAL (UART_MCR_DTR | UART_MCR_RTS) /* RTS/DTR */ -#define out_le32(a, v) (*(volatile uint32_t*)(a) = (v)) -#define in_le32(a) (*(volatile uint32_t*)(a)) +#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ +#define UART_MCRVAL (UART_MCR_DTR | \ + UART_MCR_RTS) /* RTS/DTR */ #ifndef CONFIG_SYS_NS16550_IER -#define CONFIG_SYS_NS16550_IER 0x00 +#define CONFIG_SYS_NS16550_IER 0x00 #endif /* CONFIG_SYS_NS16550_IER */ -#define serial_dout(reg, value) \ - serial_out_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \ - 2, value) -#define serial_din(reg) \ - serial_in_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \ - 2) +#define CONFIG_SYS_NS16550_PORT_MAPPED -static inline void serial_out_shift(void* addr, int shift, int value) +#define readb(addr) \ + ({ unsigned char __v = (*(volatile unsigned char *)(addr)); __v; }) + +#define writeb(b, addr) (void)((*(volatile unsigned char *)(addr)) = (b)) + + +static inline void serial_out_shift(void *addr, int shift, int value) { - out_le32(addr, value); + writeb(value, addr); } -static inline int serial_in_shift(void* addr, int shift) +static inline int serial_in_shift(void *addr, int shift) { - return in_le32(addr); + return readb(addr); } -#ifndef CONFIG_SYS_NS16550_CLK -#define CONFIG_SYS_NS16550_CLK 0 + +static void ns16550_writeb(struct ns16550 *port, int offset, int value) +{ + struct ns16550_plat *plat = port->plat; + unsigned char *addr; + + offset *= 1 << plat->reg_shift; + addr = (unsigned char *)plat->base + offset + plat->reg_offset; + + serial_out_shift(addr, plat->reg_shift, value); +} + +static int ns16550_readb(struct ns16550 *port, int offset) +{ + struct ns16550_plat *plat = port->plat; + unsigned char *addr; + + offset *= 1 << plat->reg_shift; + addr = (unsigned char *)plat->base + offset + plat->reg_offset; + + return serial_in_shift(addr, plat->reg_shift); +} + +static uint32_t ns16550_getfcr(struct ns16550 *port) +{ + struct ns16550_plat *plat = port->plat; + + return plat->fcr; +} + +/* We can clean these up once everything is moved to driver model */ +#define serial_out(value, addr) \ + ns16550_writeb(com_port, \ + (unsigned char *)addr - (unsigned char *)com_port, value) +#define serial_in(addr) \ + ns16550_readb(com_port, \ + (unsigned char *)addr - (unsigned char *)com_port) + +/* Divide positive dividend by positive divisor and round to closest integer. */ +#define DIV_ROUND_CLOSEST(x, divisor) \ + (((x) + ((divisor) / 2)) / (divisor)) + +int ns16550_calc_divisor(struct ns16550 *port, int clock, int baudrate) +{ + const unsigned int mode_x_div = 16; + + return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate); +} + +static void ns16550_setbrg(struct ns16550 *com_port, int baud_divisor) +{ + /* to keep serial format, read lcr before writing BKSE */ + int lcr_val = serial_in(&com_port->lcr) & ~UART_LCR_BKSE; + + serial_out(UART_LCR_BKSE | lcr_val, &com_port->lcr); + serial_out(baud_divisor & 0xff, &com_port->dll); + serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm); + serial_out(lcr_val, &com_port->lcr); +} + +void ns16550_init(struct ns16550 *com_port, int baud_divisor) +{ + while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT)) + ; + serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); + serial_out(UART_MCRVAL, &com_port->mcr); + serial_out(ns16550_getfcr(com_port), &com_port->fcr); + /* initialize serial config to 8N1 before writing baudrate */ + serial_out(UART_LCRVAL, &com_port->lcr); + if (baud_divisor != -1) + ns16550_setbrg(com_port, baud_divisor); +} + +void ns16550_putc(struct ns16550 *com_port, char c) +{ + while ((serial_in(&com_port->lsr) & UART_LSR_THRE) == 0) + ; + serial_out(c, &com_port->thr); +} + + +char ns16550_getc(struct ns16550 *com_port) +{ + while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) + ; + return serial_in(&com_port->rbr); +} + +int ns16550_tstc(struct ns16550 *com_port) +{ + return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0; +} + + +static int ns16550_serial_assign_base(struct ns16550_plat *plat, unsigned long base) +{ +#ifdef CONFIG_SYS_NS16550_PORT_MAPPED + plat->base = base; +#else + plat->base = (unsigned long)map_physmem(base, 0, MAP_NOCACHE); #endif - -#if 0 -#define DIV_ROUND_CLOSEST(x, divisor) ( \ - { \ - typeof(x) __x = x; \ - typeof(divisor) __d = divisor; \ - (((typeof(x))-1) > 0 || ((typeof(divisor))-1) > 0 || (__x) > 0) ? (((__x) + ((__d) / 2)) / (__d)) : (((__x) - ((__d) / 2)) / (__d)); \ - }) -#endif -#define DIV_ROUND_CLOSEST(x, divisor) ( \ - { \ - ((x) > 0) ? (((x) + ((divisor) / 2)) / (divisor)) : (((x) - ((divisor) / 2)) / (divisor)); \ - }) - - -int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate) -{ - const unsigned int mode_x_div = 16; - - return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate); + return 0; } + +static void ns16550_plat_init(void) +{ + struct ns16550_plat *plat = &g_ns16550_plat; + unsigned long addr; + + addr = CONFIG_SYS_NS16550_UART_BASE; + ns16550_serial_assign_base(plat, addr); + /* refer jh7110 u-boot/arch/riscv/dts/jh7110.dtsi */ + plat->reg_offset = 0; + plat->reg_shift = 2; + plat->reg_width = 4; + plat->clock = CONFIG_SYS_NS16550_CLK; + plat->fcr = UART_FCR_DEFVAL; +} + +static void ns16550_serial_init(void) +{ + struct ns16550_plat *plat = &g_ns16550_plat; + struct ns16550 *com_port = &g_ns16550_com_port; + + ns16550_plat_init(); + com_port->plat = plat; + ns16550_init(com_port, -1); +} + +static void ns16550_serial_setbrg(int baudrate) +{ + struct ns16550 *const com_port = &g_ns16550_com_port; + struct ns16550_plat *plat = com_port->plat; + int clock_divisor; + + clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate); + ns16550_setbrg(com_port, clock_divisor); +} + + void _debug_uart_init(void) { - struct NS16550* com_port = (struct NS16550*)UART_ADDR; + int baudrate = CONFIG_BAUDRATE; - /* - * We copy the code from above because it is already horribly messy. - * Trying to refactor to nicely remove the duplication doesn't seem - * feasible. The better fix is to move all users of this driver to - * driver model. - */ - int baud_divisor = ns16550_calc_divisor(com_port, 24000000, - 115200); - serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER); - serial_dout(&com_port->mcr, UART_MCRVAL); - serial_dout(&com_port->fcr, UART_FCR_DEFVAL); - - serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL); - serial_dout(&com_port->dll, baud_divisor & 0xff); - serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); - serial_dout(&com_port->lcr, UART_LCRVAL); + ns16550_serial_init(); + ns16550_serial_setbrg(baudrate); + _debug_uart_printascii("_debug_uart_init success.\n"); } void _debug_uart_putc(int ch) { - static struct NS16550* com_port = (struct NS16550*)UART_ADDR; - - if (ch == '\n') { - _debug_uart_putc('\r'); - } - - while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) - ; - serial_dout(&com_port->thr, ch); + struct ns16550* com_port = &g_ns16550_com_port; + ns16550_putc(com_port, ch); } int _debug_uart_getc(void) { - static struct NS16550* com_port = (struct NS16550*)UART_ADDR; + struct ns16550* com_port = &g_ns16550_com_port; + return ns16550_getc(com_port); +} - while (!(serial_din(&com_port->lsr) & UART_LSR_DR)) - ; +static void _printch(int ch) +{ + if (ch == '\n') + _debug_uart_putc('\r'); + _debug_uart_putc(ch); +} - return serial_din(&com_port->rbr); +void _debug_uart_printascii(const char *str) +{ + while (*str) + _printch(*str++); } \ No newline at end of file From 1eedb9d24e0aa47a2e27e76e1acfe2cbf073d0a3 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Mon, 11 Nov 2024 20:30:14 +0800 Subject: [PATCH 03/54] Debug MMU TLB --- .../arch/riscv/rv64gc/include/asm/asm.h | 48 +++ .../arch/riscv/rv64gc/include/asm/const.h | 37 +++ .../arch/riscv/rv64gc/include/asm/csr.h | 294 ++++++++++++++++++ .../riscv/rv64gc/include/asm/pgtable-bits.h | 48 +++ .../riscv/rv64gc/preboot_for_jh7110/boot.S | 58 +++- .../riscv/rv64gc/preboot_for_jh7110/config.mk | 7 +- .../riscv/rv64gc/preboot_for_jh7110/cortex.S | 2 + .../rv64gc/preboot_for_jh7110/jh7110.lds | 28 +- .../hardkernel/mmu/riscv/rv64gc/bootmmu.c | 87 +++--- .../mmu/riscv/rv64gc/jh7110/memlayout.h | 25 +- .../uart_io_for_jh7110/include/ns16550.h | 1 + .../riscv/rv64gc/uart_io_for_jh7110/ns16550.c | 22 +- Ubiquitous/XiZi_AIoT/path_kernel.mk | 3 +- 13 files changed, 574 insertions(+), 86 deletions(-) create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/asm.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/const.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/csr.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable-bits.h diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/asm.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/asm.h new file mode 100644 index 000000000..32e6cf15f --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/asm.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2015 Regents of the University of California + */ + +#ifndef _ASM_RISCV_ASM_H +#define _ASM_RISCV_ASM_H + +//#define __ASSEMBLY__ + +#ifdef __ASSEMBLY__ +#define __ASM_STR(x) x +#else +#define __ASM_STR(x) #x +#endif + +#if __riscv_xlen == 64 +#define __REG_SEL(a, b) __ASM_STR(a) +#elif __riscv_xlen == 32 +#define __REG_SEL(a, b) __ASM_STR(b) +#else +#error "Unexpected __riscv_xlen" +#endif + +#define REG_L __REG_SEL(ld, lw) +#define REG_S __REG_SEL(sd, sw) +#define REG_SC __REG_SEL(sc.d, sc.w) +#define REG_ASM __REG_SEL(.dword, .word) +#define SZREG __REG_SEL(8, 4) +#define LGREG __REG_SEL(3, 2) + + +#define RISCV_PTR .dword +#define RISCV_SZPTR 8 +#define RISCV_LGPTR 3 + + +#define RISCV_INT __ASM_STR(.word) +#define RISCV_SZINT __ASM_STR(4) +#define RISCV_LGINT __ASM_STR(2) + + +#define RISCV_SHORT __ASM_STR(.half) +#define RISCV_SZSHORT __ASM_STR(2) +#define RISCV_LGSHORT __ASM_STR(1) + + +#endif /* _ASM_RISCV_ASM_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/const.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/const.h new file mode 100644 index 000000000..1921cdcc7 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/const.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* const.h: Macros for dealing with constants. */ + +#ifndef _UAPI_LINUX_CONST_H +#define _UAPI_LINUX_CONST_H + +/* Some constant macros are used in both assembler and + * C code. Therefore we cannot annotate them always with + * 'UL' and other type specifiers unilaterally. We + * use the following macros to deal with this. + * + * Similarly, _AT() will cast an expression with a type in C, but + * leave it unchanged in asm. + */ + +//#ifdef __ASSEMBLY__ +#if 0 +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define __AC(X,Y) (X##Y) +#define _AC(X,Y) __AC(X,Y) +#define _AT(T,X) ((T)(X)) +#endif + +#define _UL(x) (_AC(x, UL)) +#define _ULL(x) (_AC(x, ULL)) + +#define _BITUL(x) (_UL(1) << (x)) +#define _BITULL(x) (_ULL(1) << (x)) + +#define __ALIGN_KERNEL(x, a) __ALIGN_KERNEL_MASK(x, (typeof(x))(a) - 1) +#define __ALIGN_KERNEL_MASK(x, mask) (((x) + (mask)) & ~(mask)) + +#define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) + +#endif /* _UAPI_LINUX_CONST_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/csr.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/csr.h new file mode 100644 index 000000000..0e15289f9 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/csr.h @@ -0,0 +1,294 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2015 Regents of the University of California + */ + +#ifndef _ASM_RISCV_CSR_H +#define _ASM_RISCV_CSR_H + +#include +#include + +#define CONFIG_64BIT + +/* Status register flags */ +#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ +#define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */ +#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */ +#define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */ +#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */ +#define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ +#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ + +#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ +#define SR_FS_OFF _AC(0x00000000, UL) +#define SR_FS_INITIAL _AC(0x00002000, UL) +#define SR_FS_CLEAN _AC(0x00004000, UL) +#define SR_FS_DIRTY _AC(0x00006000, UL) + +#define SR_XS _AC(0x00018000, UL) /* Extension Status */ +#define SR_XS_OFF _AC(0x00000000, UL) +#define SR_XS_INITIAL _AC(0x00008000, UL) +#define SR_XS_CLEAN _AC(0x00010000, UL) +#define SR_XS_DIRTY _AC(0x00018000, UL) + +#ifndef CONFIG_64BIT +#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */ +#else +#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ +#endif + +/* SATP flags */ +#ifndef CONFIG_64BIT +#define SATP_PPN _AC(0x003FFFFF, UL) +#define SATP_MODE_32 _AC(0x80000000, UL) +#define SATP_MODE SATP_MODE_32 +#define SATP_ASID_BITS 9 +#define SATP_ASID_SHIFT 22 +#define SATP_ASID_MASK _AC(0x1FF, UL) +#else +#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL) +#define SATP_MODE_39 _AC(0x8000000000000000, UL) +#define SATP_MODE SATP_MODE_39 +#define SATP_ASID_BITS 16 +#define SATP_ASID_SHIFT 44 +#define SATP_ASID_MASK _AC(0xFFFF, UL) +#endif + +/* Exception cause high bit - is an interrupt if set */ +#define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1)) + +/* Interrupt causes (minus the high bit) */ +#define IRQ_S_SOFT 1 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_M_EXT 11 +#define IRQ_PMU_OVF 13 + +/* Exception causes */ +#define EXC_INST_MISALIGNED 0 +#define EXC_INST_ACCESS 1 +#define EXC_BREAKPOINT 3 +#define EXC_LOAD_ACCESS 5 +#define EXC_STORE_ACCESS 7 +#define EXC_SYSCALL 8 +#define EXC_INST_PAGE_FAULT 12 +#define EXC_LOAD_PAGE_FAULT 13 +#define EXC_STORE_PAGE_FAULT 15 + +/* PMP configuration */ +#define PMP_R 0x01 +#define PMP_W 0x02 +#define PMP_X 0x04 +#define PMP_A 0x18 +#define PMP_A_TOR 0x08 +#define PMP_A_NA4 0x10 +#define PMP_A_NAPOT 0x18 +#define PMP_L 0x80 + +/* symbolic CSR names: */ +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f + +#define CSR_SSCOUNTOVF 0xda0 + +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 +#define CSR_SATP 0x180 + +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MTVAL 0x343 +#define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPADDR0 0x3b0 +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 + +#ifdef CONFIG_RISCV_M_MODE +# define CSR_STATUS CSR_MSTATUS +# define CSR_IE CSR_MIE +# define CSR_TVEC CSR_MTVEC +# define CSR_SCRATCH CSR_MSCRATCH +# define CSR_EPC CSR_MEPC +# define CSR_CAUSE CSR_MCAUSE +# define CSR_TVAL CSR_MTVAL +# define CSR_IP CSR_MIP + +# define SR_IE SR_MIE +# define SR_PIE SR_MPIE +# define SR_PP SR_MPP + +# define RV_IRQ_SOFT IRQ_M_SOFT +# define RV_IRQ_TIMER IRQ_M_TIMER +# define RV_IRQ_EXT IRQ_M_EXT +#else /* CONFIG_RISCV_M_MODE */ +# define CSR_STATUS CSR_SSTATUS +# define CSR_IE CSR_SIE +# define CSR_TVEC CSR_STVEC +# define CSR_SCRATCH CSR_SSCRATCH +# define CSR_EPC CSR_SEPC +# define CSR_CAUSE CSR_SCAUSE +# define CSR_TVAL CSR_STVAL +# define CSR_IP CSR_SIP + +# define SR_IE SR_SIE +# define SR_PIE SR_SPIE +# define SR_PP SR_SPP + +# define RV_IRQ_SOFT IRQ_S_SOFT +# define RV_IRQ_TIMER IRQ_S_TIMER +# define RV_IRQ_EXT IRQ_S_EXT +# define RV_IRQ_PMU IRQ_PMU_OVF +# define SIP_LCOFIP (_AC(0x1, UL) << IRQ_PMU_OVF) + +#endif /* !CONFIG_RISCV_M_MODE */ + +/* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */ +#define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT) +#define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) +#define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT) + +#ifndef __ASSEMBLY__ + +#define csr_swap(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\ + : "=r" (__v) : "rK" (__v) \ + : "memory"); \ + __v; \ +}) + +#define csr_read(csr) \ +({ \ + register unsigned long __v; \ + __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \ + : "=r" (__v) : \ + : "memory"); \ + __v; \ +}) + +#define csr_write(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \ + : : "rK" (__v) \ + : "memory"); \ +}) + +#define csr_read_set(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\ + : "=r" (__v) : "rK" (__v) \ + : "memory"); \ + __v; \ +}) + +#define csr_set(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \ + : : "rK" (__v) \ + : "memory"); \ +}) + +#define csr_read_clear(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\ + : "=r" (__v) : "rK" (__v) \ + : "memory"); \ + __v; \ +}) + +#define csr_clear(csr, val) \ +({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \ + : : "rK" (__v) \ + : "memory"); \ +}) + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_RISCV_CSR_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable-bits.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable-bits.h new file mode 100644 index 000000000..2ee413912 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable-bits.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2012 Regents of the University of California + */ + +#ifndef _ASM_RISCV_PGTABLE_BITS_H +#define _ASM_RISCV_PGTABLE_BITS_H + +/* + * PTE format: + * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 + * PFN reserved for SW D A G U X W R V + */ + +#define _PAGE_ACCESSED_OFFSET 6 + +#define _PAGE_PRESENT (1 << 0) +#define _PAGE_READ (1 << 1) /* Readable */ +#define _PAGE_WRITE (1 << 2) /* Writable */ +#define _PAGE_EXEC (1 << 3) /* Executable */ +#define _PAGE_USER (1 << 4) /* User */ +#define _PAGE_GLOBAL (1 << 5) /* Global */ +#define _PAGE_ACCESSED (1 << 6) /* Set by hardware on any access */ +#define _PAGE_DIRTY (1 << 7) /* Set by hardware on any write */ +#define _PAGE_SOFT (1 << 8) /* Reserved for software */ + +#define _PAGE_SPECIAL _PAGE_SOFT +#define _PAGE_TABLE _PAGE_PRESENT + +/* + * _PAGE_PROT_NONE is set on not-present pages (and ignored by the hardware) to + * distinguish them from swapped out pages + */ +#define _PAGE_PROT_NONE _PAGE_READ + +#define _PAGE_PFN_SHIFT 10 + +/* Set of bits to preserve across pte_modify() */ +#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \ + _PAGE_WRITE | _PAGE_EXEC | \ + _PAGE_USER | _PAGE_GLOBAL)) +/* + * when all of R/W/X are zero, the PTE is a pointer to the next level + * of the page table; otherwise, it is a leaf PTE. + */ +#define _PAGE_LEAF (_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC) + +#endif /* _ASM_RISCV_PGTABLE_BITS_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S index 6393c76c0..1b0c6b54e 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S @@ -10,8 +10,9 @@ * See the Mulan PSL v2 for more details. */ -/* #include */ +#include #include "core.h" +#include "memlayout.h" #define HCR_VALUE (1 << 31) #define SPSR_EL2_VALUE (7 << 6) | (5 << 0) @@ -23,19 +24,60 @@ _boot_start: + /* Mask all interrupts */ + csrw CSR_IE, zero + csrw CSR_IP, zero + + csrr t0, sstatus + srli t0, t0, 8 + andi t0, t0, 1 + beqz t0, switch_to_s_mode + + j continue_execution + + switch_to_s_mode: + li t2, 0x100 + csrw sstatus, t2 + + j continue_execution + +continue_execution: j primary_cpu_init - j . primary_cpu_init: la t0, boot_start_addr la t1, boot_end_addr li t2, 0 - -clear_loop: - bge t0, t1, clear_done + +clear_bss_sec: + bge t0, t1, clear_bss_sec_done sb t2, 0(t0) addi t0, t0, 4 - j clear_loop - -clear_done: + j clear_bss_sec + +clear_bss_sec_done: + + /* Clear BSS for flat non-ELF images */ + la a3, __bss_start + la a4, __bss_end + ble a4, a3, clear_bss_done +clear_bss: + sd zero, (a3) + add a3, a3, RISCV_SZPTR + blt a3, a4, clear_bss + +clear_bss_done: + j bootmain + +/* +.global enable_mmu_relocate +enable_mmu_relocate: + la a2, boot_l2pgdir + srl a2, a2, PAGE_SHIFT + li a1, SATP_MODE + or a2, a2, a1 + sfence.vma + csrw CSR_SATP, a2 + ret +*/ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk index 62bfef792..0198cdc16 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk @@ -1,16 +1,15 @@ -# export CROSS_COMPILE ?= riscv64-linux-gnu- export CROSS_COMPILE ?= riscv64-unknown-elf- export ARCH = riscv # export KBUILD_CFLAGS := -Wall -Wundef -Werror=strict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -fshort-wchar -fno-PIE -Werror=implicit-function-declaration -Werror=implicit-int -Werror=return-type -Wno-format-security -std=gnu89 -Wno-sign-compare -fno-asynchronous-unwind-tables -fno-delete-null-pointer-checks -fno-stack-protector -Wno-main -fomit-frame-pointer -Wdeclaration-after-statement -Wvla -Wno-pointer-sign -Wno-array-bounds -fno-strict-overflow -fno-stack-check -Werror=date-time export KBUILD_CFLAGS := -Wall -Wundef -Wno-trigraphs -fno-strict-aliasing -fno-common -fshort-wchar -fno-PIE -Werror=implicit-function-declaration -Werror=implicit-int -Werror=return-type -Wno-format-security -std=gnu89 -Wno-sign-compare -fno-asynchronous-unwind-tables -fno-delete-null-pointer-checks -fno-stack-protector -Wno-main -fomit-frame-pointer -Wvla -Wno-pointer-sign -Wno-array-bounds -fno-strict-overflow -fno-stack-check -Werror=date-time export KBUILD_CPPFLAGS := -D__KERNEL__ -export KBUILD_AFLAGS := -D__ASSEMBLY__ -fno-PIE -m64 +export KBUILD_AFLAGS := +export CHECKFLAGS += -D__riscv -D__riscv_xlen=64 export DEVICE := -export CFLAGS := $(KBUILD_CFLAGS) -std=c11 +export CFLAGS := $(KBUILD_CFLAGS) $(KBUILD_AFLAGS) $(CHECKFLAGS) -std=c11 # .vmlinux.cmd:1:cmd_vmlinux := sh scripts/link-vmlinux.sh "riscv64-linux-gnu-ld" " -melf64lriscv" " --build-id=sha1"; -#export LFLAGS := -melf64lriscv --build-id=sha1 $(KERNEL_ROOT)/hardkernel/arch/riscv/preboot_for_jh7110/jh7110.lds export LFLAGS := -T $(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds export CXXFLAGS := diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/cortex.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/cortex.S index 7fb1e6dcc..5e15bba09 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/cortex.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/cortex.S @@ -16,10 +16,12 @@ Modification: .section ".text","ax" .global cpu_get_current + # int cpu_get_current(void)@ # get current CPU ID .func cpu_get_current cpu_get_current: + li a0, 0 ret .endfunc diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds index 9dc78f76d..778c33e95 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds @@ -35,7 +35,7 @@ * @author AIIT XUOS Lab * @date 2024.10.10 */ - +OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv") OUTPUT_ARCH(riscv) /* ENTRY(_start) */ ENTRY( _boot_start ) @@ -43,17 +43,11 @@ ENTRY( _boot_start ) BOOT_STACK_SIZE = 0x4000; MEMORY { phy_ddr3 (rwx) : ORIGIN = 0x40200000, LENGTH = 1024M - vir_ddr3 (rwx) : ORIGIN = 0x000000601040E000, LENGTH = 1024M + vir_ddr3 (rwx) : ORIGIN = 0x0000000040800000, LENGTH = 1024M } - SECTIONS { -/* . = ((((-1))) - 0x80000000 + 1); - _start = .; - .head.text : AT(ADDR(.head.text) - ((((-1))) - 0x80000000 + 1)) { KEEP(*(.head.text)) } -*/ - .start_sec : { . = ORIGIN(phy_ddr3); /* initialization start checkpoint. */ @@ -89,11 +83,12 @@ SECTIONS PROVIDE(boot_end_addr = .); } > phy_ddr3 - /* AT: 0x40200000 + 0x0041C000 */ - .text : AT(0x4061C000) { + /* AT: phy_ddr3 + .start_sec size */ + .text : AT(0x40800000) { . = ALIGN(0x1000); *(.text .text.* .gnu.linkonce.t.*) - } + } > vir_ddr3 + . = ALIGN(0x1000); .data : { *(.data .data.*) @@ -112,17 +107,20 @@ SECTIONS PROVIDE(_binary_default_fs_end = .); PROVIDE(__init_array_start = .); PROVIDE(__init_array_end = .); - } + } > vir_ddr3 + + . = ALIGN(0x1000); + _image_size = . - ORIGIN(phy_ddr3); . = ALIGN(0x1000); .bss : { PROVIDE(kernel_data_begin = .); - PROVIDE(__bss_start__ = .); + PROVIDE(__bss_start = .); *(.bss .bss.* COMMON) . = ALIGN(0x1000); - PROVIDE(__bss_end__ = .); + PROVIDE(__bss_end = .); PROVIDE(kernel_data_end = .); - } + } > vir_ddr3 . = ALIGN((1 << 21)); .sdata : { diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c index af7c13eb0..3c674498e 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c @@ -33,6 +33,8 @@ Modification: #include "pagetable.h" #include "registers.h" #include "ns16550.h" +#include +#include #include #include @@ -41,11 +43,9 @@ extern uint64_t kernel_data_end[]; extern uint64_t kernel_data_begin[]; // clang-format off -#define L2_TYPE_TAB 2 -#define L2_PTE_VALID 1 +#define L2_PTE_VALID (1 << 0) -#define L3_TYPE_TAB 2 -#define L3_PTE_VALID 1 +#define L3_PTE_VALID (1 << 0) #define L4_TYPE_PAGE (3 << 0) #define L4_PTE_DEV ((0b00) << 2) // Device memory @@ -58,8 +58,18 @@ extern uint64_t kernel_data_begin[]; #define IDX_MASK (0b111111111) #define L3_PDE_INDEX(idx) ((idx << LEVEL3_PDE_SHIFT) & L3_IDX_MASK) -// clang-format on +#define _PAGE_KERNEL (_PAGE_READ \ + | _PAGE_WRITE \ + | _PAGE_PRESENT \ + | _PAGE_ACCESSED \ + | _PAGE_DIRTY \ + | _PAGE_GLOBAL) +#define PAGE_KERNEL (_PAGE_KERNEL) +#define PAGE_KERNEL_READ (_PAGE_KERNEL & ~_PAGE_WRITE) +#define PAGE_KERNEL_EXEC (_PAGE_KERNEL | _PAGE_EXEC) + +// clang-format on uint64_t boot_l2pgdir[NUM_LEVEL2_PDE] __attribute__((aligned(0x1000))) = { 0 }; uint64_t boot_dev_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 }; @@ -73,38 +83,33 @@ static void build_boot_pgdir() static bool built = false; if (!built) { uint64_t dev_phy_mem_base = DEV_PHYMEM_BASE; + uint64_t kern_phy_mem_base = PHY_MEM_BASE; + uint64_t cur_mem_paddr; // dev mem - boot_l2pgdir[(dev_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID; - boot_l2pgdir[(MMIO_P2V_WO(dev_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_dev_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID; + boot_l2pgdir[(dev_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (((uint64_t)boot_dev_l3pgdir >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | _PAGE_TABLE; + boot_l2pgdir[(MMIO_P2V_WO(dev_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (((uint64_t)boot_dev_l3pgdir >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | _PAGE_TABLE; - uint64_t cur_mem_paddr = ALIGNDOWN((uint64_t)DEV_PHYMEM_BASE, LEVEL2_PDE_SIZE); + cur_mem_paddr = ALIGNDOWN(dev_phy_mem_base, LEVEL2_PDE_SIZE); for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) { - boot_dev_l3pgdir[i] = (uint64_t)boot_dev_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID; + boot_dev_l3pgdir[i] = (((uint64_t)boot_dev_l4pgdirs[i] >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | _PAGE_TABLE; for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) { - boot_dev_l4pgdirs[i][j] = cur_mem_paddr | L4_TYPE_PAGE | L4_PTE_DEV | L4_PTE_AF | L4_PTE_XN; - if (cur_mem_paddr >= DEV_PHYMEM_BASE && cur_mem_paddr < DEV_PHYMEM_BASE + DEV_MEM_SIZE) { - boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403; - } else { - boot_dev_l4pgdirs[i][j] = cur_mem_paddr | 0x403; - } - + boot_dev_l4pgdirs[i][j] = ((cur_mem_paddr >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | PAGE_KERNEL; cur_mem_paddr += PAGE_SIZE; } } // identical mem - boot_l2pgdir[(PHY_MEM_BASE >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID; - boot_l2pgdir[(P2V_WO(PHY_MEM_BASE) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (uint64_t)boot_kern_l3pgdir | L2_TYPE_TAB | L2_PTE_VALID; + boot_l2pgdir[(kern_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (((uint64_t)boot_kern_l3pgdir >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | _PAGE_TABLE; + boot_l2pgdir[(P2V_WO(kern_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (((uint64_t)boot_kern_l3pgdir >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | _PAGE_TABLE; - cur_mem_paddr = ALIGNDOWN((uint64_t)0x00000000ULL, PAGE_SIZE); + cur_mem_paddr = ALIGNDOWN(kern_phy_mem_base, PAGE_SIZE); for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) { - boot_kern_l3pgdir[i] = (uint64_t)boot_kern_l4pgdirs[i] | L3_TYPE_TAB | L3_PTE_VALID; + boot_kern_l3pgdir[i] = (((uint64_t)boot_kern_l4pgdirs[i] >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | _PAGE_TABLE; for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) { - boot_kern_l4pgdirs[i][j] = cur_mem_paddr | 0x713; - + boot_kern_l4pgdirs[i][j] = ((cur_mem_paddr >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | PAGE_KERNEL; cur_mem_paddr += PAGE_SIZE; } } @@ -113,39 +118,43 @@ static void build_boot_pgdir() } } -static void load_boot_pgdir() +static inline void local_flush_tlb_all(void) { - - TTBR0_W((uintptr_t)boot_l2pgdir); - TTBR1_W(0); - -#define TCR_TRUE_VALUE (0x0000000080813519ULL) - uint64_t tcr = 0; - TCR_R(tcr); - tcr &= (uint64_t)~0xFF; - tcr |= 0x19; - TCR_W(tcr); - - CLEARTLB(0); - ISB(); + __asm__ __volatile__ ("sfence.vma" : : : "memory"); } +static void load_boot_pgdir() +{ + unsigned long satp_val = (unsigned long)(((uintptr_t)boot_l2pgdir >> PAGE_SHIFT) | SATP_MODE); + unsigned long status; + + status = csr_read(CSR_STATUS); + if( !(status & 0x100) ) { + _debug_uart_printascii("current is not S mode\n"); + } +#if 0 //to debug + csr_write(CSR_SATP, ((uintptr_t)boot_l2pgdir >> PAGE_SHIFT) | SATP_MODE); +#endif +} extern void main(void); static bool _bss_inited = false; void bootmain() { _debug_uart_init(); -#if 0 + _debug_uart_printascii("bootmain start.\n"); + build_boot_pgdir(); load_boot_pgdir(); -// __asm__ __volatile__("add sp, sp, %0" ::"r"(KERN_OFFSET)); +// _debug_uart_base_map(); + _debug_uart_printascii("boot pgdir success\n"); + + __asm__ __volatile__("addi sp, sp, %0" ::"i"(KERN_OFFSET)); if (!_bss_inited) { memset(&kernel_data_begin, 0x00, (size_t)((uint64_t)kernel_data_end - (uint64_t)kernel_data_begin)); _bss_inited = true; } main(); -#endif } diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h index ef7e8ef24..c1fd498b8 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h @@ -15,7 +15,7 @@ * @brief virtual memory and physical memory layout * @version 1.0 * @author AIIT XUOS Lab - * @date 2024-04-25 + * @date 2024-10-31 */ /************************************************* File name: memlayout.h @@ -33,11 +33,11 @@ Modification: #define ARCH_BIT 64 -/* A55 physical memory layout */ -#define PHY_MEM_BASE (0x0000000010000000ULL) -#define PHY_USER_FREEMEM_BASE (0x0000000040000000ULL) -#define PHY_USER_FREEMEM_TOP (0x00000000e0000000ULL) -#define PHY_MEM_STOP (0x00000000e0000000ULL) +/* physical memory layout */ +#define PHY_MEM_BASE (0x0000000040200000ULL) +#define PHY_USER_FREEMEM_BASE (0x0000000080000000ULL) +#define PHY_USER_FREEMEM_TOP (0x00000000F0000000ULL) +#define PHY_MEM_STOP (0x00000000F0000000ULL) /* PTE-PAGE_SIZE */ #define LEVEL4_PTE_SHIFT 12 @@ -57,24 +57,25 @@ Modification: #define NUM_LEVEL4_PTE (1 << (LEVEL3_PDE_SHIFT - LEVEL4_PTE_SHIFT)) // how many PTE in a PT #define NUM_TOPLEVEL_PDE NUM_LEVEL2_PDE +#define PAGE_SHIFT LEVEL4_PTE_SHIFT #define PAGE_SIZE LEVEL4_PTE_SIZE #define MAX_NR_FREE_PAGES ((PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT) /* Deivce memory layout */ -#define DEV_PHYMEM_BASE (0x00000000F0000000ULL) -#define DEV_VRTMEM_BASE (0x00000040F0000000ULL) -#define DEV_MEM_SIZE (0x0000000010000000ULL) +#define DEV_PHYMEM_BASE (0x0000000010000000ULL) +#define DEV_VRTMEM_BASE (0x0000001010000000ULL) +#define DEV_MEM_SIZE (0x0000000030040000ULL) /* User memory layout */ #define USER_STACK_SIZE PAGE_SIZE -#define USER_MEM_BASE (0x0000000000000000ULL) -#define USER_MEM_TOP (0x0000004000000000ULL) +#define USER_MEM_BASE (0x0000002000000000ULL) +#define USER_MEM_TOP (0x0000008000000000ULL) #define USER_IPC_SPACE_BASE (0x0000003000000000ULL) #define USER_IPC_USE_ALLOCATOR_WATERMARK (0x0000003000010000ULL) #define USER_IPC_SPACE_TOP (USER_IPC_SPACE_BASE + 0x10000000ULL) /* Kernel memory layout */ -#define KERN_MEM_BASE (0x0000006010000000ULL) // First kernel virtual address +#define KERN_MEM_BASE (0x0000000000000000ULL + PHY_MEM_BASE) // First kernel virtual address #define KERN_OFFSET (KERN_MEM_BASE - PHY_MEM_BASE) #define V2P(a) (((uint64_t)(a)) - KERN_OFFSET) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h index fbc0cd530..8f2900357 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h @@ -214,5 +214,6 @@ void _debug_uart_init(void); void _debug_uart_putc(int ch); int _debug_uart_getc(void); void _debug_uart_printascii(const char *str); +void _debug_uart_base_map(void); #endif /* __ns16550_h */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c index 275dfe16c..85ed50944 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c @@ -5,6 +5,7 @@ */ #include +#include "mmio_access.h" struct ns16550 g_ns16550_com_port = {0}; struct ns16550_plat g_ns16550_plat = {0}; @@ -12,7 +13,7 @@ struct ns16550_plat g_ns16550_plat = {0}; #define CONFIG_SYS_NS16550_UART_BASE 0x10000000 #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_NS16550_CLK 24000000 - +#define CONFIG_SYS_NS16550_UART_BASE_MAP MMIO_P2V_WO(CONFIG_SYS_NS16550_UART_BASE) #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ #define UART_MCRVAL (UART_MCR_DTR | \ @@ -136,11 +137,7 @@ int ns16550_tstc(struct ns16550 *com_port) static int ns16550_serial_assign_base(struct ns16550_plat *plat, unsigned long base) { -#ifdef CONFIG_SYS_NS16550_PORT_MAPPED plat->base = base; -#else - plat->base = (unsigned long)map_physmem(base, 0, MAP_NOCACHE); -#endif return 0; } @@ -180,7 +177,6 @@ static void ns16550_serial_setbrg(int baudrate) ns16550_setbrg(com_port, clock_divisor); } - void _debug_uart_init(void) { int baudrate = CONFIG_BAUDRATE; @@ -190,9 +186,21 @@ void _debug_uart_init(void) _debug_uart_printascii("_debug_uart_init success.\n"); } +void _debug_uart_base_map(void) +{ + struct ns16550_plat *plat = &g_ns16550_plat; + unsigned long addr; + + addr = CONFIG_SYS_NS16550_UART_BASE_MAP; + ns16550_serial_assign_base(plat, addr); + _debug_uart_printascii("_debug_uart_init_mapped success.\n"); +} + void _debug_uart_putc(int ch) { struct ns16550* com_port = &g_ns16550_com_port; + if (ch == '\n') + ns16550_putc(com_port, '\r'); ns16550_putc(com_port, ch); } @@ -213,4 +221,4 @@ void _debug_uart_printascii(const char *str) { while (*str) _printch(*str++); -} \ No newline at end of file +} diff --git a/Ubiquitous/XiZi_AIoT/path_kernel.mk b/Ubiquitous/XiZi_AIoT/path_kernel.mk index da097bfc9..7282780e2 100755 --- a/Ubiquitous/XiZi_AIoT/path_kernel.mk +++ b/Ubiquitous/XiZi_AIoT/path_kernel.mk @@ -56,8 +56,9 @@ endif ifeq ($(BOARD), jh7110) KERNELPATHS += \ - -I$(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/preboot_for_$(BOARD)/include \ -I$(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/ \ + -I$(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/include \ + -I$(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/preboot_for_$(BOARD)/include \ -I$(KERNEL_ROOT)/hardkernel/cache/L1/riscv/rv64gc/ \ -I$(KERNEL_ROOT)/hardkernel/clock/riscv/rv64gc/$(BOARD)/include \ -I$(KERNEL_ROOT)/hardkernel/intr/riscv/rv64gc/ \ From 8795b4138edc8b2c3706043276558aa6ee4d939b Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 22 Nov 2024 14:10:46 +0800 Subject: [PATCH 04/54] Modify uart --- .../riscv/rv64gc/preboot_for_jh7110/boot.S | 5 ++++ .../hardkernel/mmu/riscv/rv64gc/bootmmu.c | 28 ++++++------------- .../uart_io_for_jh7110/include/ns16550.h | 2 +- .../riscv/rv64gc/uart_io_for_jh7110/ns16550.c | 28 +++++++------------ 4 files changed, 25 insertions(+), 38 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S index 1b0c6b54e..cd19af272 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S @@ -28,6 +28,10 @@ _boot_start: csrw CSR_IE, zero csrw CSR_IP, zero + j primary_cpu_init + +/* +switch_mode: csrr t0, sstatus srli t0, t0, 8 andi t0, t0, 1 @@ -43,6 +47,7 @@ _boot_start: continue_execution: j primary_cpu_init +*/ primary_cpu_init: la t0, boot_start_addr diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c index 3c674498e..db1385a0c 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c @@ -59,15 +59,10 @@ extern uint64_t kernel_data_begin[]; #define IDX_MASK (0b111111111) #define L3_PDE_INDEX(idx) ((idx << LEVEL3_PDE_SHIFT) & L3_IDX_MASK) -#define _PAGE_KERNEL (_PAGE_READ \ - | _PAGE_WRITE \ - | _PAGE_PRESENT \ - | _PAGE_ACCESSED \ - | _PAGE_DIRTY \ - | _PAGE_GLOBAL) -#define PAGE_KERNEL (_PAGE_KERNEL) -#define PAGE_KERNEL_READ (_PAGE_KERNEL & ~_PAGE_WRITE) -#define PAGE_KERNEL_EXEC (_PAGE_KERNEL | _PAGE_EXEC) +#define _PAGE_KERNEL (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC | _PAGE_ACCESSED | _PAGE_GLOBAL | _PAGE_DIRTY) +#define PAGE_KERNEL (_PAGE_KERNEL) +#define PAGE_KERNEL_READ (_PAGE_KERNEL & ~_PAGE_WRITE) +#define PAGE_KERNEL_EXEC (_PAGE_KERNEL | _PAGE_EXEC) // clang-format on uint64_t boot_l2pgdir[NUM_LEVEL2_PDE] __attribute__((aligned(0x1000))) = { 0 }; @@ -125,15 +120,11 @@ static inline void local_flush_tlb_all(void) static void load_boot_pgdir() { - unsigned long satp_val = (unsigned long)(((uintptr_t)boot_l2pgdir >> PAGE_SHIFT) | SATP_MODE); - unsigned long status; + unsigned long satp_val = 0; - status = csr_read(CSR_STATUS); - if( !(status & 0x100) ) { - _debug_uart_printascii("current is not S mode\n"); - } -#if 0 //to debug - csr_write(CSR_SATP, ((uintptr_t)boot_l2pgdir >> PAGE_SHIFT) | SATP_MODE); + satp_val = (unsigned long)(((uintptr_t)boot_l2pgdir >> PAGE_SHIFT) | SATP_MODE); +#if 1 //to debug + csr_write(CSR_SATP, satp_val); #endif } @@ -141,12 +132,11 @@ extern void main(void); static bool _bss_inited = false; void bootmain() { - _debug_uart_init(); + _debug_uart_phymem_init(); _debug_uart_printascii("bootmain start.\n"); build_boot_pgdir(); load_boot_pgdir(); -// _debug_uart_base_map(); _debug_uart_printascii("boot pgdir success\n"); __asm__ __volatile__("addi sp, sp, %0" ::"i"(KERN_OFFSET)); diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h index 8f2900357..39788ceb6 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h @@ -214,6 +214,6 @@ void _debug_uart_init(void); void _debug_uart_putc(int ch); int _debug_uart_getc(void); void _debug_uart_printascii(const char *str); -void _debug_uart_base_map(void); +void _debug_uart_phymem_init(void); #endif /* __ns16550_h */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c index 85ed50944..9fa44ee17 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c @@ -9,6 +9,7 @@ struct ns16550 g_ns16550_com_port = {0}; struct ns16550_plat g_ns16550_plat = {0}; +unsigned long g_ns16550_uart_base = {0}; #define CONFIG_SYS_NS16550_UART_BASE 0x10000000 #define CONFIG_BAUDRATE 115200 @@ -80,7 +81,7 @@ static uint32_t ns16550_getfcr(struct ns16550 *port) (unsigned char *)addr - (unsigned char *)com_port) /* Divide positive dividend by positive divisor and round to closest integer. */ -#define DIV_ROUND_CLOSEST(x, divisor) \ +#define DIV_ROUND_CLOSEST(x, divisor) \ (((x) + ((divisor) / 2)) / (divisor)) int ns16550_calc_divisor(struct ns16550 *port, int clock, int baudrate) @@ -134,22 +135,12 @@ int ns16550_tstc(struct ns16550 *com_port) return (serial_in(&com_port->lsr) & UART_LSR_DR) != 0; } - -static int ns16550_serial_assign_base(struct ns16550_plat *plat, unsigned long base) -{ - plat->base = base; - return 0; -} - - static void ns16550_plat_init(void) { struct ns16550_plat *plat = &g_ns16550_plat; - unsigned long addr; - addr = CONFIG_SYS_NS16550_UART_BASE; - ns16550_serial_assign_base(plat, addr); /* refer jh7110 u-boot/arch/riscv/dts/jh7110.dtsi */ + plat->base = g_ns16550_uart_base; plat->reg_offset = 0; plat->reg_shift = 2; plat->reg_width = 4; @@ -181,19 +172,20 @@ void _debug_uart_init(void) { int baudrate = CONFIG_BAUDRATE; + g_ns16550_uart_base = CONFIG_SYS_NS16550_UART_BASE_MAP; ns16550_serial_init(); ns16550_serial_setbrg(baudrate); _debug_uart_printascii("_debug_uart_init success.\n"); } -void _debug_uart_base_map(void) +void _debug_uart_phymem_init(void) { - struct ns16550_plat *plat = &g_ns16550_plat; - unsigned long addr; + int baudrate = CONFIG_BAUDRATE; - addr = CONFIG_SYS_NS16550_UART_BASE_MAP; - ns16550_serial_assign_base(plat, addr); - _debug_uart_printascii("_debug_uart_init_mapped success.\n"); + g_ns16550_uart_base = CONFIG_SYS_NS16550_UART_BASE; + ns16550_serial_init(); + ns16550_serial_setbrg(baudrate); + _debug_uart_printascii("_debug_uart_phymem_init success.\n"); } void _debug_uart_putc(int ch) From 87c5f1549f1c204036b87f47ccb7f2cc353561e7 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 3 Dec 2024 10:45:39 +0800 Subject: [PATCH 05/54] Modify uart --- .../riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h | 2 +- .../uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c | 11 ++++++----- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h index 39788ceb6..f5a1639fe 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/include/ns16550.h @@ -214,6 +214,6 @@ void _debug_uart_init(void); void _debug_uart_putc(int ch); int _debug_uart_getc(void); void _debug_uart_printascii(const char *str); -void _debug_uart_phymem_init(void); +void _debug_uart_init_early(void); #endif /* __ns16550_h */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c index 9fa44ee17..27f6592d0 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c @@ -4,7 +4,7 @@ * modified to use CONFIG_SYS_ISA_MEM and new defines */ -#include +#include "ns16550.h" #include "mmio_access.h" struct ns16550 g_ns16550_com_port = {0}; @@ -14,7 +14,8 @@ unsigned long g_ns16550_uart_base = {0}; #define CONFIG_SYS_NS16550_UART_BASE 0x10000000 #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_NS16550_CLK 24000000 -#define CONFIG_SYS_NS16550_UART_BASE_MAP MMIO_P2V_WO(CONFIG_SYS_NS16550_UART_BASE) +#define CONFIG_SYS_NS16550_UART_BASE_VIRT MMIO_P2V_WO(CONFIG_SYS_NS16550_UART_BASE) + #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ #define UART_MCRVAL (UART_MCR_DTR | \ @@ -172,20 +173,20 @@ void _debug_uart_init(void) { int baudrate = CONFIG_BAUDRATE; - g_ns16550_uart_base = CONFIG_SYS_NS16550_UART_BASE_MAP; + g_ns16550_uart_base = CONFIG_SYS_NS16550_UART_BASE_VIRT; ns16550_serial_init(); ns16550_serial_setbrg(baudrate); _debug_uart_printascii("_debug_uart_init success.\n"); } -void _debug_uart_phymem_init(void) +void _debug_uart_init_early(void) { int baudrate = CONFIG_BAUDRATE; g_ns16550_uart_base = CONFIG_SYS_NS16550_UART_BASE; ns16550_serial_init(); ns16550_serial_setbrg(baudrate); - _debug_uart_printascii("_debug_uart_phymem_init success.\n"); + _debug_uart_printascii("_debug_uart_init_early success.\n"); } void _debug_uart_putc(int ch) From a9f8fba6dd8b1aceb0de0e30a0ff1c607ad56687 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 3 Dec 2024 14:41:41 +0800 Subject: [PATCH 06/54] Modify mmu --- .../arch/riscv/rv64gc/include/asm/asm.h | 19 +- .../arch/riscv/rv64gc/include/asm/const.h | 2 + .../arch/riscv/rv64gc/include/asm/csr.h | 2 +- .../arch/riscv/rv64gc/include/asm/page.h | 186 ++++++ .../arch/riscv/rv64gc/include/asm/pfn.h | 23 + .../riscv/rv64gc/include/asm/pgtable-64.h | 47 ++ .../riscv/rv64gc/include/asm/pgtable-bits.h | 4 + .../arch/riscv/rv64gc/include/asm/pgtable.h | 598 ++++++++++++++++++ .../arch/riscv/rv64gc/include/asm/sizes.h | 52 ++ .../riscv/rv64gc/preboot_for_jh7110/boot.S | 126 ++-- .../riscv/rv64gc/preboot_for_jh7110/config.mk | 2 +- .../preboot_for_jh7110/include/autoconf.h | 15 + .../rv64gc/preboot_for_jh7110/jh7110.lds | 92 +-- .../hardkernel/mmu/riscv/rv64gc/Makefile | 5 +- .../hardkernel/mmu/riscv/rv64gc/bootmmu.c | 33 +- .../hardkernel/mmu/riscv/rv64gc/include/mmu.h | 3 +- .../mmu/riscv/rv64gc/include/pgtable.h | 76 +++ .../mmu/riscv/rv64gc/jh7110/memlayout.h | 12 +- .../hardkernel/mmu/riscv/rv64gc/mmu_init.c | 170 +++++ 19 files changed, 1325 insertions(+), 142 deletions(-) create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/page.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pfn.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable-64.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/sizes.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/autoconf.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/pgtable.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/asm.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/asm.h index 32e6cf15f..25660fd26 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/asm.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/asm.h @@ -14,20 +14,13 @@ #define __ASM_STR(x) #x #endif -#if __riscv_xlen == 64 -#define __REG_SEL(a, b) __ASM_STR(a) -#elif __riscv_xlen == 32 -#define __REG_SEL(a, b) __ASM_STR(b) -#else -#error "Unexpected __riscv_xlen" -#endif -#define REG_L __REG_SEL(ld, lw) -#define REG_S __REG_SEL(sd, sw) -#define REG_SC __REG_SEL(sc.d, sc.w) -#define REG_ASM __REG_SEL(.dword, .word) -#define SZREG __REG_SEL(8, 4) -#define LGREG __REG_SEL(3, 2) +#define REG_L ld +#define REG_S sd +#define REG_SC sc.d +#define REG_ASM .dword +#define SZREG 8 +#define LGREG 3 #define RISCV_PTR .dword diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/const.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/const.h index 1921cdcc7..8e57b7f14 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/const.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/const.h @@ -25,6 +25,8 @@ #define _UL(x) (_AC(x, UL)) #define _ULL(x) (_AC(x, ULL)) +#define UL(x) (_UL(x)) +#define ULL(x) (_ULL(x)) #define _BITUL(x) (_UL(1) << (x)) #define _BITULL(x) (_ULL(1) << (x)) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/csr.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/csr.h index 0e15289f9..0f45549da 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/csr.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/csr.h @@ -6,10 +6,10 @@ #ifndef _ASM_RISCV_CSR_H #define _ASM_RISCV_CSR_H +#include "autoconf.h" #include #include -#define CONFIG_64BIT /* Status register flags */ #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/page.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/page.h new file mode 100644 index 000000000..5e1cea44e --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/page.h @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2009 Chen Liqin + * Copyright (C) 2012 Regents of the University of California + * Copyright (C) 2017 SiFive + * Copyright (C) 2017 XiaojingZhu + */ + +#ifndef _ASM_RISCV_PAGE_H +#define _ASM_RISCV_PAGE_H + +#include "autoconf.h" +#include +#include + + +#ifdef CONFIG_PHYS_ADDR_T_64BIT +typedef uint64_t phys_addr_t; +#else +typedef uint64_t phys_addr_t; +#endif + + +#define PAGE_SHIFT (12) +#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE - 1)) + +#ifdef CONFIG_64BIT +#define HUGE_MAX_HSTATE 2 +#else +#define HUGE_MAX_HSTATE 1 +#endif +#define HPAGE_SHIFT PMD_SHIFT +#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) +#define HPAGE_MASK (~(HPAGE_SIZE - 1)) +#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) + +/* + * PAGE_OFFSET -- the first address of the first page of memory. + * When not using MMU this corresponds to the first free page in + * physical memory (aligned on a page boundary). + */ +#define PAGE_OFFSET _AC(CONFIG_PAGE_OFFSET, UL) + +#define KERN_VIRT_SIZE (-PAGE_OFFSET) + +#ifndef __ASSEMBLY__ + +#define clear_page(pgaddr) memset((pgaddr), 0, PAGE_SIZE) +#define copy_page(to, from) memcpy((to), (from), PAGE_SIZE) + +#define clear_user_page(pgaddr, vaddr, page) memset((pgaddr), 0, PAGE_SIZE) +#define copy_user_page(vto, vfrom, vaddr, topg) \ + memcpy((vto), (vfrom), PAGE_SIZE) + +/* + * Use struct definitions to apply C type checking + */ + +/* Page Global Directory entry */ +typedef struct { + unsigned long pgd; +} pgd_t; + +/* Page Table entry */ +typedef struct { + unsigned long pte; +} pte_t; + +typedef struct { + unsigned long pgprot; +} pgprot_t; + +typedef struct page *pgtable_t; + +#define pte_val(x) ((x).pte) +#define pgd_val(x) ((x).pgd) +#define pgprot_val(x) ((x).pgprot) + +#define __pte(x) ((pte_t) { (x) }) +#define __pgd(x) ((pgd_t) { (x) }) +#define __pgprot(x) ((pgprot_t) { (x) }) + +#ifdef CONFIG_64BIT +#define PTE_FMT "%016lx" +#else +#define PTE_FMT "%08lx" +#endif + +#ifdef CONFIG_MMU +extern unsigned long riscv_pfn_base; +#define ARCH_PFN_OFFSET (riscv_pfn_base) +#else +#define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT) +#endif /* CONFIG_MMU */ + +struct kernel_mapping { + unsigned long virt_addr; + uintptr_t phys_addr; + uintptr_t size; + /* Offset between linear mapping virtual address and kernel load address */ + unsigned long va_pa_offset; + /* Offset between kernel mapping virtual address and kernel load address */ + unsigned long va_kernel_pa_offset; + unsigned long va_kernel_xip_pa_offset; +#ifdef CONFIG_XIP_KERNEL + uintptr_t xiprom; + uintptr_t xiprom_sz; +#endif +}; + +extern struct kernel_mapping kernel_map; +extern phys_addr_t phys_ram_base; + +#define is_kernel_mapping(x) \ + ((x) >= kernel_map.virt_addr && (x) < (kernel_map.virt_addr + kernel_map.size)) + +#define is_linear_mapping(x) \ + ((x) >= PAGE_OFFSET && (!IS_ENABLED(CONFIG_64BIT) || (x) < kernel_map.virt_addr)) + +#define linear_mapping_pa_to_va(x) ((void *)((unsigned long)(x) + kernel_map.va_pa_offset)) +#define kernel_mapping_pa_to_va(y) ({ \ + unsigned long _y = y; \ + (IS_ENABLED(CONFIG_XIP_KERNEL) && _y < phys_ram_base) ? \ + (void *)((unsigned long)(_y) + kernel_map.va_kernel_xip_pa_offset) : \ + (void *)((unsigned long)(_y) + kernel_map.va_kernel_pa_offset + XIP_OFFSET); \ + }) +#define __pa_to_va_nodebug(x) linear_mapping_pa_to_va(x) + +#define linear_mapping_va_to_pa(x) ((unsigned long)(x) - kernel_map.va_pa_offset) +#define kernel_mapping_va_to_pa(y) ({ \ + unsigned long _y = y; \ + (IS_ENABLED(CONFIG_XIP_KERNEL) && _y < kernel_map.virt_addr + XIP_OFFSET) ? \ + ((unsigned long)(_y) - kernel_map.va_kernel_xip_pa_offset) : \ + ((unsigned long)(_y) - kernel_map.va_kernel_pa_offset - XIP_OFFSET); \ + }) + +#define __va_to_pa_nodebug(x) ({ \ + unsigned long _x = x; \ + is_linear_mapping(_x) ? \ + linear_mapping_va_to_pa(_x) : kernel_mapping_va_to_pa(_x); \ + }) + +#ifdef CONFIG_DEBUG_VIRTUAL +extern phys_addr_t __virt_to_phys(unsigned long x); +extern phys_addr_t __phys_addr_symbol(unsigned long x); +#else +#define __virt_to_phys(x) __va_to_pa_nodebug(x) +#define __phys_addr_symbol(x) __va_to_pa_nodebug(x) +#endif /* CONFIG_DEBUG_VIRTUAL */ + +#define __pa_symbol(x) __phys_addr_symbol(RELOC_HIDE((unsigned long)(x), 0)) +#define __pa(x) __virt_to_phys((unsigned long)(x)) +#define __va(x) ((void *)__pa_to_va_nodebug((phys_addr_t)(x))) + +#define phys_to_pfn(phys) (PFN_DOWN(phys)) +#define pfn_to_phys(pfn) (PFN_PHYS(pfn)) + +#define virt_to_pfn(vaddr) (phys_to_pfn(__pa(vaddr))) +#define pfn_to_virt(pfn) (__va(pfn_to_phys(pfn))) + +#define virt_to_page(vaddr) (pfn_to_page(virt_to_pfn(vaddr))) +#define page_to_virt(page) (pfn_to_virt(page_to_pfn(page))) + +#define page_to_phys(page) (pfn_to_phys(page_to_pfn(page))) +#define page_to_bus(page) (page_to_phys(page)) +#define phys_to_page(paddr) (pfn_to_page(phys_to_pfn(paddr))) + +#define sym_to_pfn(x) __phys_to_pfn(__pa_symbol(x)) + +#ifdef CONFIG_FLATMEM +#define pfn_valid(pfn) \ + (((pfn) >= ARCH_PFN_OFFSET) && (((pfn) - ARCH_PFN_OFFSET) < max_mapnr)) +#endif + +#endif /* __ASSEMBLY__ */ + +#define virt_addr_valid(vaddr) ({ \ + unsigned long _addr = (unsigned long)vaddr; \ + (unsigned long)(_addr) >= PAGE_OFFSET && pfn_valid(virt_to_pfn(_addr)); \ +}) + +#define VM_DATA_DEFAULT_FLAGS VM_DATA_FLAGS_NON_EXEC + + +#endif /* _ASM_RISCV_PAGE_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pfn.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pfn.h new file mode 100644 index 000000000..3cedc6ea1 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pfn.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_PFN_H_ +#define _LINUX_PFN_H_ + +#ifndef __ASSEMBLER__ +#include +/* + * pfn_t: encapsulates a page-frame number that is optionally backed + * by memmap (struct page). Whether a pfn_t has a 'struct page' + * backing is indicated by flags in the high bits of the value. + */ +typedef struct { + uint64_t val; +} pfn_t; +#endif + +#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK) +#define PFN_UP(x) (((x) + PAGE_SIZE-1) >> PAGE_SHIFT) +#define PFN_DOWN(x) ((x) >> PAGE_SHIFT) +#define PFN_PHYS(x) ((phys_addr_t)(x) << PAGE_SHIFT) +#define PHYS_PFN(x) ((unsigned long)((x) >> PAGE_SHIFT)) + +#endif diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable-64.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable-64.h new file mode 100644 index 000000000..aef16f340 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable-64.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2012 Regents of the University of California + */ + +#ifndef _ASM_RISCV_PGTABLE_64_H +#define _ASM_RISCV_PGTABLE_64_H + +#include +#include + +#define PGDIR_SHIFT 30 +/* Size of region mapped by a page global directory */ +#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT) +#define PGDIR_MASK (~(PGDIR_SIZE - 1)) + +#define PMD_SHIFT 21 +/* Size of region mapped by a page middle directory */ +#define PMD_SIZE (_AC(1, UL) << PMD_SHIFT) +#define PMD_MASK (~(PMD_SIZE - 1)) + +/* Page Middle Directory entry */ +typedef struct { + unsigned long pmd; +} pmd_t; + +#define pmd_val(x) ((x).pmd) +#define __pmd(x) ((pmd_t) { (x) }) + +#define PTRS_PER_PMD (PAGE_SIZE / sizeof(pmd_t)) + +static inline pmd_t pfn_pmd(unsigned long pfn, pgprot_t prot) +{ + return __pmd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); +} + +static inline unsigned long _pmd_pfn(pmd_t pmd) +{ + return pmd_val(pmd) >> _PAGE_PFN_SHIFT; +} + +#define mk_pmd(page, prot) pfn_pmd(page_to_pfn(page), prot) + +#define pmd_ERROR(e) \ + pr_err("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) + +#endif /* _ASM_RISCV_PGTABLE_64_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable-bits.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable-bits.h index 2ee413912..02c5c6ccf 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable-bits.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable-bits.h @@ -6,6 +6,10 @@ #ifndef _ASM_RISCV_PGTABLE_BITS_H #define _ASM_RISCV_PGTABLE_BITS_H +#include + +#define BIT(nr) (UL(1) << (nr)) + /* * PTE format: * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable.h new file mode 100644 index 000000000..4423b2633 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable.h @@ -0,0 +1,598 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2012 Regents of the University of California + */ + +#ifndef _ASM_RISCV_PGTABLE_H +#define _ASM_RISCV_PGTABLE_H + +#include "autoconf.h" +#include +#include + +#ifndef CONFIG_MMU +#define KERNEL_LINK_ADDR PAGE_OFFSET +#else + +#define ADDRESS_SPACE_END (UL(-1)) + +#ifdef CONFIG_64BIT +/* Leave 2GB for kernel and BPF at the end of the address space */ +#define KERNEL_LINK_ADDR (ADDRESS_SPACE_END - SZ_2G + 1) +#else +#define KERNEL_LINK_ADDR PAGE_OFFSET +#endif + +#define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) +#define VMALLOC_END (PAGE_OFFSET - 1) +#define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) + +#define BPF_JIT_REGION_SIZE (SZ_128M) +#ifdef CONFIG_64BIT +#define BPF_JIT_REGION_START (BPF_JIT_REGION_END - BPF_JIT_REGION_SIZE) +#define BPF_JIT_REGION_END (MODULES_END) +#else +#define BPF_JIT_REGION_START (PAGE_OFFSET - BPF_JIT_REGION_SIZE) +#define BPF_JIT_REGION_END (VMALLOC_END) +#endif + +/* Modules always live before the kernel */ +#ifdef CONFIG_64BIT +#define MODULES_VADDR (PFN_ALIGN((unsigned long)&_end) - SZ_2G) +#define MODULES_END (PFN_ALIGN((unsigned long)&_start)) +#endif + +/* + * Roughly size the vmemmap space to be large enough to fit enough + * struct pages to map half the virtual address space. Then + * position vmemmap directly below the VMALLOC region. + */ +#define STRUCT_PAGE_MAX_SHIFT 0 //syg +#define VMEMMAP_SHIFT \ + (CONFIG_VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) +#define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) +#define VMEMMAP_END (VMALLOC_START - 1) +#define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE) + +/* + * Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel + * is configured with CONFIG_SPARSEMEM_VMEMMAP enabled. + */ +#define vmemmap ((struct page *)VMEMMAP_START) + +#define PCI_IO_SIZE SZ_16M +#define PCI_IO_END VMEMMAP_START +#define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) + +#define FIXADDR_TOP PCI_IO_START +#ifdef CONFIG_64BIT +#define FIXADDR_SIZE PMD_SIZE +#else +#define FIXADDR_SIZE PGDIR_SIZE +#endif +#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) + +#endif + +#ifdef CONFIG_XIP_KERNEL +#define XIP_OFFSET SZ_8M +#else +#define XIP_OFFSET 0 +#endif + +#ifndef __ASSEMBLY__ + +/* Page Upper Directory not used in RISC-V */ +//#include +#include + + +#ifdef CONFIG_64BIT +#include +#else +#include +#endif /* CONFIG_64BIT */ + +#ifdef CONFIG_XIP_KERNEL +#define XIP_FIXUP(addr) ({ \ + uintptr_t __a = (uintptr_t)(addr); \ + (__a >= CONFIG_XIP_PHYS_ADDR && __a < CONFIG_XIP_PHYS_ADDR + SZ_16M) ? \ + __a - CONFIG_XIP_PHYS_ADDR + CONFIG_PHYS_RAM_BASE - XIP_OFFSET :\ + __a; \ + }) +#else +#define XIP_FIXUP(addr) (addr) +#endif /* CONFIG_XIP_KERNEL */ + +#ifdef CONFIG_MMU +/* Number of entries in the page global directory */ +#define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) +/* Number of entries in the page table */ +#define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t)) + +/* Number of PGD entries that a user-mode program can use */ +#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) + +/* Page protection bits */ +#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) + +#define PAGE_NONE __pgprot(_PAGE_PROT_NONE) +#define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ) +#define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE) +#define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC) +#define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) +#define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ + _PAGE_EXEC | _PAGE_WRITE) + +#define PAGE_COPY PAGE_READ +#define PAGE_COPY_EXEC PAGE_EXEC +#define PAGE_COPY_READ_EXEC PAGE_READ_EXEC +#define PAGE_SHARED PAGE_WRITE +#define PAGE_SHARED_EXEC PAGE_WRITE_EXEC + +#define _PAGE_KERNEL (_PAGE_READ \ + | _PAGE_WRITE \ + | _PAGE_PRESENT \ + | _PAGE_ACCESSED \ + | _PAGE_DIRTY \ + | _PAGE_GLOBAL) + +#define PAGE_KERNEL __pgprot(_PAGE_KERNEL) +#define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE) +#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC) +#define PAGE_KERNEL_READ_EXEC __pgprot((_PAGE_KERNEL & ~_PAGE_WRITE) \ + | _PAGE_EXEC) + +#define PAGE_TABLE __pgprot(_PAGE_TABLE) + +/* + * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't + * change the properties of memory regions. + */ +#define _PAGE_IOREMAP _PAGE_KERNEL + +extern pgd_t swapper_pg_dir[]; + +/* MAP_PRIVATE permissions: xwr (copy-on-write) */ +#define __P000 PAGE_NONE +#define __P001 PAGE_READ +#define __P010 PAGE_COPY +#define __P011 PAGE_COPY +#define __P100 PAGE_EXEC +#define __P101 PAGE_READ_EXEC +#define __P110 PAGE_COPY_EXEC +#define __P111 PAGE_COPY_READ_EXEC + +/* MAP_SHARED permissions: xwr */ +#define __S000 PAGE_NONE +#define __S001 PAGE_READ +#define __S010 PAGE_SHARED +#define __S011 PAGE_SHARED +#define __S100 PAGE_EXEC +#define __S101 PAGE_READ_EXEC +#define __S110 PAGE_SHARED_EXEC +#define __S111 PAGE_SHARED_EXEC + +#ifdef CONFIG_TRANSPARENT_HUGEPAGE +static inline int pmd_present(pmd_t pmd) +{ + /* + * Checking for _PAGE_LEAF is needed too because: + * When splitting a THP, split_huge_page() will temporarily clear + * the present bit, in this situation, pmd_present() and + * pmd_trans_huge() still needs to return true. + */ + return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE | _PAGE_LEAF)); +} +#else +static inline int pmd_present(pmd_t pmd) +{ + return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); +} +#endif + +static inline int pmd_none(pmd_t pmd) +{ + return (pmd_val(pmd) == 0); +} + +static inline int pmd_bad(pmd_t pmd) +{ + return !pmd_present(pmd) || (pmd_val(pmd) & _PAGE_LEAF); +} + +#define pmd_leaf pmd_leaf +static inline int pmd_leaf(pmd_t pmd) +{ + return pmd_present(pmd) && (pmd_val(pmd) & _PAGE_LEAF); +} + +static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) +{ + *pmdp = pmd; +} + +static inline void pmd_clear(pmd_t *pmdp) +{ + set_pmd(pmdp, __pmd(0)); +} + +static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot) +{ + return __pgd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); +} + +static inline unsigned long _pgd_pfn(pgd_t pgd) +{ + return pgd_val(pgd) >> _PAGE_PFN_SHIFT; +} + +#if 0 +static inline struct page *pmd_page(pmd_t pmd) +{ + return pfn_to_page(pmd_val(pmd) >> _PAGE_PFN_SHIFT); +} +#endif + +static inline unsigned long pmd_page_vaddr(pmd_t pmd) +{ + return (unsigned long)pfn_to_virt(pmd_val(pmd) >> _PAGE_PFN_SHIFT); +} + +static inline pte_t pmd_pte(pmd_t pmd) +{ + return __pte(pmd_val(pmd)); +} + +/* Yields the page frame number (PFN) of a page table entry */ +static inline unsigned long pte_pfn(pte_t pte) +{ + return (pte_val(pte) >> _PAGE_PFN_SHIFT); +} + +#define pte_page(x) pfn_to_page(pte_pfn(x)) + +/* Constructs a page table entry */ +static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) +{ + return __pte((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); +} + +#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) + +static inline int pte_present(pte_t pte) +{ + return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); +} + +static inline int pte_none(pte_t pte) +{ + return (pte_val(pte) == 0); +} + +static inline int pte_write(pte_t pte) +{ + return pte_val(pte) & _PAGE_WRITE; +} + +static inline int pte_exec(pte_t pte) +{ + return pte_val(pte) & _PAGE_EXEC; +} + +static inline int pte_huge(pte_t pte) +{ + return pte_present(pte) && (pte_val(pte) & _PAGE_LEAF); +} + +static inline int pte_dirty(pte_t pte) +{ + return pte_val(pte) & _PAGE_DIRTY; +} + +static inline int pte_young(pte_t pte) +{ + return pte_val(pte) & _PAGE_ACCESSED; +} + +static inline int pte_special(pte_t pte) +{ + return pte_val(pte) & _PAGE_SPECIAL; +} + +/* static inline pte_t pte_rdprotect(pte_t pte) */ + +static inline pte_t pte_wrprotect(pte_t pte) +{ + return __pte(pte_val(pte) & ~(_PAGE_WRITE)); +} + +/* static inline pte_t pte_mkread(pte_t pte) */ + +static inline pte_t pte_mkwrite(pte_t pte) +{ + return __pte(pte_val(pte) | _PAGE_WRITE); +} + +/* static inline pte_t pte_mkexec(pte_t pte) */ + +static inline pte_t pte_mkdirty(pte_t pte) +{ + return __pte(pte_val(pte) | _PAGE_DIRTY); +} + +static inline pte_t pte_mkclean(pte_t pte) +{ + return __pte(pte_val(pte) & ~(_PAGE_DIRTY)); +} + +static inline pte_t pte_mkyoung(pte_t pte) +{ + return __pte(pte_val(pte) | _PAGE_ACCESSED); +} + +static inline pte_t pte_mkold(pte_t pte) +{ + return __pte(pte_val(pte) & ~(_PAGE_ACCESSED)); +} + +static inline pte_t pte_mkspecial(pte_t pte) +{ + return __pte(pte_val(pte) | _PAGE_SPECIAL); +} + +static inline pte_t pte_mkhuge(pte_t pte) +{ + return pte; +} + +#ifdef CONFIG_NUMA_BALANCING +/* + * See the comment in include/asm-generic/pgtable.h + */ +static inline int pte_protnone(pte_t pte) +{ + return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)) == _PAGE_PROT_NONE; +} + +static inline int pmd_protnone(pmd_t pmd) +{ + return pte_protnone(pmd_pte(pmd)); +} +#endif + +/* Modify page protection bits */ +static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) +{ + return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); +} + +#define pgd_ERROR(e) \ + pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e)) + + +/* Commit new configuration to MMU hardware */ +static inline void update_mmu_cache(struct vm_area_struct *vma, + unsigned long address, pte_t *ptep) +{ + /* + * The kernel assumes that TLBs don't cache invalid entries, but + * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a + * cache flush; it is necessary even after writing invalid entries. + * Relying on flush_tlb_fix_spurious_fault would suffice, but + * the extra traps reduce performance. So, eagerly SFENCE.VMA. + */ + #if 0 //syg + local_flush_tlb_page(address); + #endif +} + +static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, + unsigned long address, pmd_t *pmdp) +{ + pte_t *ptep = (pte_t *)pmdp; + + update_mmu_cache(vma, address, ptep); +} + +#define __HAVE_ARCH_PTE_SAME +static inline int pte_same(pte_t pte_a, pte_t pte_b) +{ + return pte_val(pte_a) == pte_val(pte_b); +} + +/* + * Certain architectures need to do special things when PTEs within + * a page table are directly modified. Thus, the following hook is + * made available. + */ +static inline void set_pte(pte_t *ptep, pte_t pteval) +{ + *ptep = pteval; +} + +void flush_icache_pte(pte_t pte); + +static inline void set_pte_at(struct mm_struct *mm, + unsigned long addr, pte_t *ptep, pte_t pteval) +{ + if (pte_present(pteval) && pte_exec(pteval)) + flush_icache_pte(pteval); + + set_pte(ptep, pteval); +} + +static inline void pte_clear(struct mm_struct *mm, + unsigned long addr, pte_t *ptep) +{ + set_pte_at(mm, addr, ptep, __pte(0)); +} + + +/* + * THP functions + */ +static inline pmd_t pte_pmd(pte_t pte) +{ + return __pmd(pte_val(pte)); +} + +static inline pmd_t pmd_mkhuge(pmd_t pmd) +{ + return pmd; +} + +static inline pmd_t pmd_mkinvalid(pmd_t pmd) +{ + return __pmd(pmd_val(pmd) & ~(_PAGE_PRESENT|_PAGE_PROT_NONE)); +} + +#define __pmd_to_phys(pmd) (pmd_val(pmd) >> _PAGE_PFN_SHIFT << PAGE_SHIFT) + +static inline unsigned long pmd_pfn(pmd_t pmd) +{ + return ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT); +} + +static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) +{ + return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); +} + +#define pmd_write pmd_write +static inline int pmd_write(pmd_t pmd) +{ + return pte_write(pmd_pte(pmd)); +} + +static inline int pmd_dirty(pmd_t pmd) +{ + return pte_dirty(pmd_pte(pmd)); +} + +static inline int pmd_young(pmd_t pmd) +{ + return pte_young(pmd_pte(pmd)); +} + +static inline pmd_t pmd_mkold(pmd_t pmd) +{ + return pte_pmd(pte_mkold(pmd_pte(pmd))); +} + +static inline pmd_t pmd_mkyoung(pmd_t pmd) +{ + return pte_pmd(pte_mkyoung(pmd_pte(pmd))); +} + +static inline pmd_t pmd_mkwrite(pmd_t pmd) +{ + return pte_pmd(pte_mkwrite(pmd_pte(pmd))); +} + +static inline pmd_t pmd_wrprotect(pmd_t pmd) +{ + return pte_pmd(pte_wrprotect(pmd_pte(pmd))); +} + +static inline pmd_t pmd_mkclean(pmd_t pmd) +{ + return pte_pmd(pte_mkclean(pmd_pte(pmd))); +} + +static inline pmd_t pmd_mkdirty(pmd_t pmd) +{ + return pte_pmd(pte_mkdirty(pmd_pte(pmd))); +} + +static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, + pmd_t *pmdp, pmd_t pmd) +{ + return set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)); +} + + + +/* + * Encode and decode a swap entry + * + * Format of swap PTE: + * bit 0: _PAGE_PRESENT (zero) + * bit 1: _PAGE_PROT_NONE (zero) + * bits 2 to 6: swap type + * bits 7 to XLEN-1: swap offset + */ +#define __SWP_TYPE_SHIFT 2 +#define __SWP_TYPE_BITS 5 +#define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1) +#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) + +#define MAX_SWAPFILES_CHECK() \ + BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) + +#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) +#define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) +#define __swp_entry(type, offset) ((swp_entry_t) \ + { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) + +#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) +#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) + +/* + * In the RV64 Linux scheme, we give the user half of the virtual-address space + * and give the kernel the other (upper) half. + */ +#ifdef CONFIG_64BIT +#define KERN_VIRT_START (-(BIT(CONFIG_VA_BITS)) + TASK_SIZE) +#else +#define KERN_VIRT_START FIXADDR_START +#endif + +/* + * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. + * Note that PGDIR_SIZE must evenly divide TASK_SIZE. + */ +#ifdef CONFIG_64BIT +#define TASK_SIZE (PGDIR_SIZE * PTRS_PER_PGD / 2) +#else +#define TASK_SIZE FIXADDR_START +#endif + +#else /* CONFIG_MMU */ + +#define PAGE_SHARED __pgprot(0) +#define PAGE_KERNEL __pgprot(0) +#define swapper_pg_dir NULL +#define TASK_SIZE 0xffffffffUL +#define VMALLOC_START 0 +#define VMALLOC_END TASK_SIZE + +#endif /* !CONFIG_MMU */ + +#define kern_addr_valid(addr) (1) /* FIXME */ + +extern char _start[]; +extern char _end[]; +extern void *_dtb_early_va; +extern uintptr_t _dtb_early_pa; +#if defined(CONFIG_XIP_KERNEL) && defined(CONFIG_MMU) +#define dtb_early_va (*(void **)XIP_FIXUP(&_dtb_early_va)) +#define dtb_early_pa (*(uintptr_t *)XIP_FIXUP(&_dtb_early_pa)) +#else +#define dtb_early_va _dtb_early_va +#define dtb_early_pa _dtb_early_pa +#endif /* CONFIG_XIP_KERNEL */ + +void paging_init(void); +void misc_mem_init(void); + +/* + * ZERO_PAGE is a global shared page that is always zero, + * used for zero-mapped memory areas, etc. + */ +extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; +#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) + +#endif /* !__ASSEMBLY__ */ + +#endif /* _ASM_RISCV_PGTABLE_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/sizes.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/sizes.h new file mode 100644 index 000000000..7e395dfc6 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/sizes.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * include/linux/sizes.h + */ +#ifndef __LINUX_SIZES_H__ +#define __LINUX_SIZES_H__ + +#include + +#define SZ_1 0x00000001 +#define SZ_2 0x00000002 +#define SZ_4 0x00000004 +#define SZ_8 0x00000008 +#define SZ_16 0x00000010 +#define SZ_32 0x00000020 +#define SZ_64 0x00000040 +#define SZ_128 0x00000080 +#define SZ_256 0x00000100 +#define SZ_512 0x00000200 + +#define SZ_1K 0x00000400 +#define SZ_2K 0x00000800 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_32K 0x00008000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 + +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 + +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 + +#define SZ_4G _AC(0x100000000, ULL) +#define SZ_8G _AC(0x200000000, ULL) +#define SZ_16G _AC(0x400000000, ULL) +#define SZ_32G _AC(0x800000000, ULL) +#define SZ_64T _AC(0x400000000000, ULL) + +#endif /* __LINUX_SIZES_H__ */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S index cd19af272..2b3016ef7 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S @@ -14,75 +14,97 @@ #include "core.h" #include "memlayout.h" -#define HCR_VALUE (1 << 31) -#define SPSR_EL2_VALUE (7 << 6) | (5 << 0) -#define SCTLR_EL1_VALUE (0x30D00800) .section ".text", "ax" .globl _boot_start -.globl primary_cpu_init _boot_start: - /* Mask all interrupts */ - csrw CSR_IE, zero - csrw CSR_IP, zero + call _debug_uart_init_early + la a0, debug_string_start + call _debug_uart_printascii - j primary_cpu_init + j _start_kernel -/* -switch_mode: - csrr t0, sstatus - srli t0, t0, 8 - andi t0, t0, 1 - beqz t0, switch_to_s_mode - j continue_execution - - switch_to_s_mode: - li t2, 0x100 - csrw sstatus, t2 - - j continue_execution - -continue_execution: - j primary_cpu_init -*/ - -primary_cpu_init: - la t0, boot_start_addr - la t1, boot_end_addr - li t2, 0 - -clear_bss_sec: - bge t0, t1, clear_bss_sec_done - sb t2, 0(t0) - addi t0, t0, 4 - j clear_bss_sec - -clear_bss_sec_done: +_start_kernel: + /* Mask all interrupts */ + csrw CSR_IE, zero + csrw CSR_IP, zero /* Clear BSS for flat non-ELF images */ la a3, __bss_start - la a4, __bss_end + la a4, __bss_stop ble a4, a3, clear_bss_done clear_bss: sd zero, (a3) add a3, a3, RISCV_SZPTR blt a3, a4, clear_bss - clear_bss_done: - j bootmain + /* Initialize page tables and relocate to virtual addresses */ + call setup_vm_early + + la a0, early_pg_dir + call relocate_enable_mmu + la sp, stacks_top + + call _debug_uart_init + + /* Start the kernel */ + tail bootmain + + +relocate_enable_mmu: + /* Relocate return address */ + la a1, kernel_map + ld a1, KERNEL_MAP_VIRT_ADDR(a1) + la a2, _start + sub a1, a1, a2 + add ra, ra, a1 + + /* Point stvec to virtual address of intruction after satp write */ + la a2, 1f + add a2, a2, a1 + csrw CSR_TVEC, a2 + + /* Compute satp for kernel page tables, but don't load it yet */ + srl a2, a0, PAGE_SHIFT + li a1, SATP_MODE + or a2, a2, a1 + + /* + * Load trampoline page directory, which will cause us to trap to + * stvec if VA != PA, or simply fall through if VA == PA. We need a + * full fence here because setup_vm() just wrote these PTEs and we need + * to ensure the new translations are in use. + */ + la a0, trampoline_pg_dir + srl a0, a0, PAGE_SHIFT + or a0, a0, a1 + sfence.vma + csrw CSR_SATP, a0 + +1: + /* Set trap vector to spin forever to help debug */ + la a0, .Lsecondary_park + csrw CSR_TVEC, a0 + + /* + * Switch to kernel page tables. A full fence is necessary in order to + * avoid using the trampoline translations, which are only correct for + * the first superpage. Fetching the fence is guarnteed to work + * because that first superpage is translated the same way. + */ + csrw CSR_SATP, a2 + sfence.vma + ret + +.Lsecondary_park: + /* We lack SMP support or have too many harts, so park this hart */ + wfi + j .Lsecondary_park + + +debug_string_start: .ascii "XiZi boot start\n\0" -/* -.global enable_mmu_relocate -enable_mmu_relocate: - la a2, boot_l2pgdir - srl a2, a2, PAGE_SHIFT - li a1, SATP_MODE - or a2, a2, a1 - sfence.vma - csrw CSR_SATP, a2 - ret -*/ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk index 0198cdc16..b016e2557 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk @@ -8,7 +8,7 @@ export KBUILD_AFLAGS := export CHECKFLAGS += -D__riscv -D__riscv_xlen=64 export DEVICE := -export CFLAGS := $(KBUILD_CFLAGS) $(KBUILD_AFLAGS) $(CHECKFLAGS) -std=c11 +export CFLAGS := $(KBUILD_CFLAGS) $(KBUILD_AFLAGS) $(CHECKFLAGS) -std=c11 -mcmodel=medany # .vmlinux.cmd:1:cmd_vmlinux := sh scripts/link-vmlinux.sh "riscv64-linux-gnu-ld" " -melf64lriscv" " --build-id=sha1"; export LFLAGS := -T $(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds export CXXFLAGS := diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/autoconf.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/autoconf.h new file mode 100644 index 000000000..0e98745f8 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/autoconf.h @@ -0,0 +1,15 @@ +#ifndef _AUTOCONF_H +#define _AUTOCONF_H + +#define CONFIG_64BIT 1 +#define CONFIG_MMU 1 +#define CONFIG_PHYS_ADDR_T_64BIT 1 +#define CONFIG_PAGE_OFFSET 0xffffffe000000000 +#define CONFIG_VA_BITS 39 + + +#define THREAD_SIZE (512 << 2) +#define KERNEL_MAP_VIRT_ADDR 0 /* offsetof(struct kernel_mapping, virt_addr) */ +#define TASK_TI_CPU 32 /* offsetof(struct task_struct, thread_info.cpu) */ + +#endif /* _AUTOCONF_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds index 778c33e95..2ca86cfa0 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds @@ -34,24 +34,29 @@ * @version 1.0 * @author AIIT XUOS Lab * @date 2024.10.10 - */ -OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv") + */ + OUTPUT_ARCH(riscv) +OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv") + /* ENTRY(_start) */ ENTRY( _boot_start ) -BOOT_STACK_SIZE = 0x4000; + MEMORY { phy_ddr3 (rwx) : ORIGIN = 0x40200000, LENGTH = 1024M vir_ddr3 (rwx) : ORIGIN = 0x0000000040800000, LENGTH = 1024M } +BOOT_STACK_SIZE = 0x4000; + SECTIONS { - .start_sec : { - . = ORIGIN(phy_ddr3); - /* initialization start checkpoint. */ + . = ORIGIN(phy_ddr3); + _start = .; + _boot_start = .; + .start_sec : { _start_image_addr = .; boot.o(.text) @@ -66,69 +71,74 @@ SECTIONS bootmmu.o(.data .data.*) ns16550.o(.data .data.*) - PROVIDE(boot_start_addr = .); + PROVIDE(boot_start_addr = .); boot.o(.bss .bss.* COMMON) bootmmu.o(.bss .bss.* COMMON) ns16550.o(.bss .bss.* COMMON) - /* stack for booting code. */ - . = ALIGN(0x1000); - PROVIDE(stacks_start = .); - . += BOOT_STACK_SIZE; - PROVIDE(stacks_end = .); - PROVIDE(stacks_top = .); + . = ALIGN(0x1000); + PROVIDE(stacks_start = .); + . += BOOT_STACK_SIZE; + PROVIDE(stacks_end = .); + PROVIDE(stacks_top = .); - /* initialization end checkpoint. */ - PROVIDE(boot_end_addr = .); - } > phy_ddr3 + PROVIDE(boot_end_addr = .); + } - /* AT: phy_ddr3 + .start_sec size */ - .text : AT(0x40800000) { + .text : { . = ALIGN(0x1000); *(.text .text.* .gnu.linkonce.t.*) - } > vir_ddr3 + } . = ALIGN(0x1000); .data : { *(.data .data.*) + __start_init_task = .; + init_thread_union = .; + init_stack = .; + KEEP(*(.data..init_task)) + KEEP(*(.data..init_thread_info)) + . = __start_init_task + ((1 << (12)) << (2)); + __end_init_task = .; + . = ALIGN(0x1000); PROVIDE(_binary_fs_img_start = .); *(.rawdata_fs_img*) - PROVIDE(_binary_fs_img_end = .); + PROVIDE(_binary_fs_img_end = .); . = ALIGN(0x1000); - PROVIDE(_binary_init_start = .); - *(.rawdata_init*) - PROVIDE(_binary_init_end = .); + PROVIDE(_binary_init_start = .); + *(.rawdata_init*) + PROVIDE(_binary_init_end = .); . = ALIGN(0x1000); - PROVIDE(_binary_default_fs_start = .); - *(.rawdata_memfs*) - PROVIDE(_binary_default_fs_end = .); + PROVIDE(_binary_default_fs_start = .); + *(.rawdata_memfs*) + PROVIDE(_binary_default_fs_end = .); PROVIDE(__init_array_start = .); PROVIDE(__init_array_end = .); - } > vir_ddr3 + } . = ALIGN(0x1000); - _image_size = . - ORIGIN(phy_ddr3); + _image_size = . - _start; . = ALIGN(0x1000); .bss : { PROVIDE(kernel_data_begin = .); PROVIDE(__bss_start = .); - *(.bss .bss.* COMMON) + *(.bss .bss.* COMMON) . = ALIGN(0x1000); - PROVIDE(__bss_end = .); - PROVIDE(kernel_data_end = .); - } > vir_ddr3 + PROVIDE(__bss_end = .); + PROVIDE(kernel_data_end = .); + __bss_stop = .; + } - . = ALIGN((1 << 21)); - .sdata : { - __global_pointer$ = . + 0x800; - *(.sdata*) - } + . = ALIGN((1 << 21)); + .sdata : { + __global_pointer$ = . + 0x800; + *(.sdata*) + } - _edata = .; - _end = .; - -} \ No newline at end of file + _edata = .; + _end = .; +} diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/Makefile index 6b8df00e5..016051139 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/Makefile @@ -1,3 +1,4 @@ -SRC_FILES := bootmmu.c mmu.c pagetable_attr.c +SRC_FILES := bootmmu.c mmu.c pagetable_attr.c mmu_init.c + +include $(KERNEL_ROOT)/compiler.mk -include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c index db1385a0c..bc48c8b75 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c @@ -39,8 +39,6 @@ Modification: #include #include -extern uint64_t kernel_data_end[]; -extern uint64_t kernel_data_begin[]; // clang-format off #define L2_PTE_VALID (1 << 0) @@ -73,6 +71,7 @@ uint64_t boot_kern_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { uint64_t boot_dev_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 }; uint64_t boot_kern_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 }; + static void build_boot_pgdir() { static bool built = false; @@ -87,12 +86,8 @@ static void build_boot_pgdir() cur_mem_paddr = ALIGNDOWN(dev_phy_mem_base, LEVEL2_PDE_SIZE); for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) { - boot_dev_l3pgdir[i] = (((uint64_t)boot_dev_l4pgdirs[i] >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | _PAGE_TABLE; - - for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) { - boot_dev_l4pgdirs[i][j] = ((cur_mem_paddr >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | PAGE_KERNEL; - cur_mem_paddr += PAGE_SIZE; - } + boot_dev_l3pgdir[i] = (((uint64_t)cur_mem_paddr >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | PAGE_KERNEL; + cur_mem_paddr += LEVEL3_PDE_SIZE; } // identical mem @@ -101,18 +96,15 @@ static void build_boot_pgdir() cur_mem_paddr = ALIGNDOWN(kern_phy_mem_base, PAGE_SIZE); for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) { - boot_kern_l3pgdir[i] = (((uint64_t)boot_kern_l4pgdirs[i] >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | _PAGE_TABLE; - - for (size_t j = 0; j < NUM_LEVEL4_PTE; j++) { - boot_kern_l4pgdirs[i][j] = ((cur_mem_paddr >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | PAGE_KERNEL; - cur_mem_paddr += PAGE_SIZE; - } + boot_kern_l3pgdir[i] = (((uint64_t)cur_mem_paddr >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | PAGE_KERNEL; + cur_mem_paddr += LEVEL3_PDE_SIZE; } built = true; } } + static inline void local_flush_tlb_all(void) { __asm__ __volatile__ ("sfence.vma" : : : "memory"); @@ -123,28 +115,19 @@ static void load_boot_pgdir() unsigned long satp_val = 0; satp_val = (unsigned long)(((uintptr_t)boot_l2pgdir >> PAGE_SHIFT) | SATP_MODE); -#if 1 //to debug csr_write(CSR_SATP, satp_val); -#endif } extern void main(void); -static bool _bss_inited = false; -void bootmain() + +void bootmain(void) { - _debug_uart_phymem_init(); _debug_uart_printascii("bootmain start.\n"); build_boot_pgdir(); load_boot_pgdir(); _debug_uart_printascii("boot pgdir success\n"); - __asm__ __volatile__("addi sp, sp, %0" ::"i"(KERN_OFFSET)); - if (!_bss_inited) { - memset(&kernel_data_begin, 0x00, (size_t)((uint64_t)kernel_data_end - (uint64_t)kernel_data_begin)); - _bss_inited = true; - } - main(); } diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/mmu.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/mmu.h index 034a5ddf8..bf46415aa 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/mmu.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/mmu.h @@ -115,4 +115,5 @@ When the process switches, the flush TLB is no longer required anymore. #include __attribute__((always_inline)) static inline uint64_t v2p(void* a) { return ((uint64_t)(a)) - KERN_MEM_BASE; } __attribute__((always_inline)) static inline void* p2v(uint64_t a) { return (void*)((a) + KERN_MEM_BASE); } -#endif \ No newline at end of file +#endif + diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/pgtable.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/pgtable.h new file mode 100644 index 000000000..4c39a88ad --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/pgtable.h @@ -0,0 +1,76 @@ +#ifndef _XIUOS_PGTABLE_H +#define _XIUOS_PGTABLE_H + +#include +#include + + +/* + * On almost all architectures and configurations, 0 can be used as the + * upper ceiling to free_pgtables(): on many architectures it has the same + * effect as using TASK_SIZE. However, there is one configuration which + * must impose a more careful limit, to avoid freeing kernel pgtables. + */ +#ifndef USER_PGTABLES_CEILING +#define USER_PGTABLES_CEILING 0UL +#endif + +/* + * This defines the first usable user address. Platforms + * can override its value with custom FIRST_USER_ADDRESS + * defined in their respective . + */ +#ifndef FIRST_USER_ADDRESS +#define FIRST_USER_ADDRESS 0UL +#endif + +/* + * This defines the generic helper for accessing PMD page + * table page. Although platforms can still override this + * via their respective . + */ +#ifndef pmd_pgtable +#define pmd_pgtable(pmd) pmd_page(pmd) +#endif + +/* + * A page table page can be thought of an array like this: pXd_t[PTRS_PER_PxD] + * + * The pXx_index() functions return the index of the entry in the page + * table page which would control the given virtual address + * + * As these functions may be used by the same code for different levels of + * the page table folding, they are always available, regardless of + * CONFIG_PGTABLE_LEVELS value. For the folded levels they simply return 0 + * because in such cases PTRS_PER_PxD equals 1. + */ + +static inline unsigned long pte_index(unsigned long address) +{ + return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1); +} + +#ifndef pmd_index +static inline unsigned long pmd_index(unsigned long address) +{ + return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1); +} +#define pmd_index pmd_index +#endif + + +#ifndef pgd_index +/* Must be a compile-time constant, so implement it as a macro */ +#define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) +#endif + +#ifndef pte_offset_kernel +static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address) +{ + return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address); +} +#define pte_offset_kernel pte_offset_kernel +#endif + + +#endif /* _XIUOS_PGTABLE_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h index c1fd498b8..b7a67bbc5 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h @@ -36,8 +36,8 @@ Modification: /* physical memory layout */ #define PHY_MEM_BASE (0x0000000040200000ULL) #define PHY_USER_FREEMEM_BASE (0x0000000080000000ULL) -#define PHY_USER_FREEMEM_TOP (0x00000000F0000000ULL) -#define PHY_MEM_STOP (0x00000000F0000000ULL) +#define PHY_USER_FREEMEM_TOP (0x0000000200000000ULL) +#define PHY_MEM_STOP (0x0000000200000000ULL) /* PTE-PAGE_SIZE */ #define LEVEL4_PTE_SHIFT 12 @@ -63,19 +63,19 @@ Modification: /* Deivce memory layout */ #define DEV_PHYMEM_BASE (0x0000000010000000ULL) -#define DEV_VRTMEM_BASE (0x0000001010000000ULL) +#define DEV_VRTMEM_BASE ((0 - 0x0000004000000000ULL) + DEV_PHYMEM_BASE) #define DEV_MEM_SIZE (0x0000000030040000ULL) /* User memory layout */ #define USER_STACK_SIZE PAGE_SIZE -#define USER_MEM_BASE (0x0000002000000000ULL) -#define USER_MEM_TOP (0x0000008000000000ULL) +#define USER_MEM_BASE (0x0000000000000000ULL) +#define USER_MEM_TOP (0x0000004000000000ULL) #define USER_IPC_SPACE_BASE (0x0000003000000000ULL) #define USER_IPC_USE_ALLOCATOR_WATERMARK (0x0000003000010000ULL) #define USER_IPC_SPACE_TOP (USER_IPC_SPACE_BASE + 0x10000000ULL) /* Kernel memory layout */ -#define KERN_MEM_BASE (0x0000000000000000ULL + PHY_MEM_BASE) // First kernel virtual address +#define KERN_MEM_BASE ((0 - 0x0000002000000000ULL) + PHY_MEM_BASE) // First kernel virtual address #define KERN_OFFSET (KERN_MEM_BASE - PHY_MEM_BASE) #define V2P(a) (((uint64_t)(a)) - KERN_OFFSET) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c new file mode 100644 index 000000000..979b78448 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file + * @brief + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.12.02 + */ + +/************************************************* +File name: mmu_init.c +Description: +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include +#include +#include +#include "asm/page.h" +#include "pgtable.h" +#include "memlayout.h" +#include "ns16550.h" + + +#define __ro_after_init __attribute__((section(".data..ro_after_init"))) +#define __page_aligned_data __attribute__((section(".data..page_aligned"))) __attribute__((aligned(PAGE_SIZE))) +#define __page_aligned_bss __attribute__((section(".bss..page_aligned"))) __attribute__((aligned(PAGE_SIZE))) +#define __initdata __attribute__((section(".init.data"))) +#define __init __attribute__((section(".init.text"))) +#define __aligned(x) __attribute__((aligned__(x))) +#define __maybe_unused __attribute__((__unused__)) + + +struct kernel_mapping kernel_map __ro_after_init; +extern char _start[]; + +unsigned long riscv_pfn_base __ro_after_init; + +pgd_t trampoline_pg_dir[PTRS_PER_PGD] __page_aligned_bss; +pgd_t early_pg_dir[PTRS_PER_PGD] __initdata __attribute__((aligned(PAGE_SIZE))); + +static pmd_t trampoline_pmd[PTRS_PER_PMD] __page_aligned_bss; +static pmd_t early_pmd[PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE))); +static pmd_t early_uart_pmd[PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE))); + + +static pmd_t *__init get_pmd_virt_early(phys_addr_t pa) +{ + /* Before MMU is enabled */ + return (pmd_t *)((uintptr_t)pa); +} + + +static phys_addr_t __init alloc_pmd_early(uintptr_t va) +{ + return (uintptr_t)early_pmd; +} + + +static void __init create_pmd_mapping_early(pmd_t *pmdp, + uintptr_t va, phys_addr_t pa, + phys_addr_t sz, pgprot_t prot) +{ + pte_t *ptep; + phys_addr_t pte_phys; + uintptr_t pmd_idx = pmd_index(va); + + if (sz == PMD_SIZE) { + if (pmd_none(pmdp[pmd_idx])) + pmdp[pmd_idx] = pfn_pmd(PFN_DOWN(pa), prot); + + return; + } +} + +void __init create_pgd_mapping_early(pgd_t *pgdp, + uintptr_t va, phys_addr_t pa, + phys_addr_t sz, pgprot_t prot) +{ + pmd_t *nextp; + phys_addr_t next_phys; + uintptr_t pgd_idx = pgd_index(va); + + if (sz == PGDIR_SIZE) { + if (pgd_val(pgdp[pgd_idx]) == 0) + pgdp[pgd_idx] = pfn_pgd(PFN_DOWN(pa), prot); + return; + } + + if (pgd_val(pgdp[pgd_idx]) == 0) { + next_phys = alloc_pmd_early(va); + pgdp[pgd_idx] = pfn_pgd(PFN_DOWN(next_phys), PAGE_TABLE); + nextp = get_pmd_virt_early(next_phys); + memset(nextp, 0, PAGE_SIZE); + } else { + next_phys = PFN_PHYS(_pgd_pfn(pgdp[pgd_idx])); + nextp = get_pmd_virt_early(next_phys); + } + + create_pmd_mapping_early(nextp, va, pa, sz, prot); +} + +static void __init create_kernel_page_table_early(pgd_t *pgdir, bool early) +{ + uintptr_t va, end_va; + int i = 0; + + end_va = kernel_map.virt_addr + kernel_map.size; + for (va = kernel_map.virt_addr; va < end_va; va += PMD_SIZE) { + create_pgd_mapping_early(pgdir, va, + kernel_map.phys_addr + (va - kernel_map.virt_addr), + PMD_SIZE, + PAGE_KERNEL_EXEC); + i++; + } +} + +/* + * setup_vm_early() is called from boot.S with MMU-off. + * + * Following requirements should be honoured for setup_vm() to work + * correctly: + * 1) It should use PC-relative addressing for accessing kernel symbols. + * To achieve this we always use GCC cmodel=medany. + * 2) The compiler instrumentation for FTRACE will not work for setup_vm() + * so disable compiler instrumentation when FTRACE is enabled. + */ + +void __init setup_vm_early(void) +{ + _debug_uart_printascii("setup_vm_early start\n"); + kernel_map.virt_addr = KERN_MEM_BASE; + + kernel_map.phys_addr = (uintptr_t)(&_start); + kernel_map.size = (uintptr_t)(&_end) - kernel_map.phys_addr; + + kernel_map.va_pa_offset = PAGE_OFFSET - kernel_map.phys_addr; + kernel_map.va_kernel_pa_offset = kernel_map.virt_addr - kernel_map.phys_addr; + + riscv_pfn_base = PFN_DOWN(kernel_map.phys_addr); + + /* Setup trampoline PGD and PMD */ + create_pgd_mapping_early(trampoline_pg_dir, kernel_map.virt_addr, (uintptr_t)trampoline_pmd, PGDIR_SIZE, PAGE_TABLE); + create_pmd_mapping_early(trampoline_pmd, kernel_map.virt_addr, kernel_map.phys_addr, PMD_SIZE, PAGE_KERNEL_EXEC); + + /* + * Setup early PGD covering entire kernel which will allow + * us to reach paging_init(). We map all memory banks later + * in setup_vm_final() below. + */ + create_kernel_page_table_early(early_pg_dir, true); + + /* Setup uart PGD and PMD */ + create_pgd_mapping_early(early_pg_dir, DEV_VRTMEM_BASE, (uintptr_t)early_uart_pmd, PGDIR_SIZE, PAGE_TABLE); + create_pmd_mapping_early(early_uart_pmd, DEV_VRTMEM_BASE, DEV_PHYMEM_BASE, PMD_SIZE, PAGE_KERNEL); +} + From a2681352056e1cb80468146e4a1b5ddbc764443d Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 6 Dec 2024 15:20:38 +0800 Subject: [PATCH 07/54] Add printf_early --- Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h | 1 + .../XiZi_AIoT/hardkernel/uart/uart_common_ope.c | 14 +++++++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h index 85c030650..93e207e93 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h @@ -50,6 +50,7 @@ extern "C" { #define KPrintf printf_ #define printf printf_ int printf_(const char* format, ...); +int printf_early(const char* format, ...); /** * Tiny sprintf implementation diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/uart_common_ope.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/uart_common_ope.c index d4a09dfa4..07130da60 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/uart_common_ope.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/uart_common_ope.c @@ -895,4 +895,16 @@ int fctprintf(void (*out)(char character, void* arg), void* arg, const char* for const int ret = _vsnprintf(_out_fct, (char*)(uintptr_t)&out_fct_wrap, (size_t)-1, format, va); va_end(va); return ret; -} \ No newline at end of file +} + +/////////////////////////////////////////////////////////////////////////////// +__attribute__((weak)) void _debug_uart_putc(int ch); +int printf_early(const char* format, ...) +{ + va_list va; + va_start(va, format); + char buffer[1]; + const int ret = _vsnprintf(_debug_uart_putc, buffer, (size_t)-1, format, va); + va_end(va); + return ret; +} From d7c99b7f017db6b9431504a18187b3b64cb6ade9 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 6 Dec 2024 16:25:40 +0800 Subject: [PATCH 08/54] Add kernel free map and linear map --- .../riscv/rv64gc/preboot_for_jh7110/boot.S | 2 + .../rv64gc/preboot_for_jh7110/jh7110.lds | 4 +- .../hardkernel/mmu/riscv/rv64gc/bootmmu.c | 47 +++++++++-- .../mmu/riscv/rv64gc/jh7110/memlayout.h | 2 +- .../hardkernel/mmu/riscv/rv64gc/mmu_init.c | 82 ++++++++++++++++++- .../hardkernel/uart/uart_common_ope.c | 15 +++- 6 files changed, 135 insertions(+), 17 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S index 2b3016ef7..d0edd59c6 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S @@ -42,6 +42,8 @@ clear_bss: blt a3, a4, clear_bss clear_bss_done: + la sp, stacks_top + /* Initialize page tables and relocate to virtual addresses */ call setup_vm_early diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds index 2ca86cfa0..2f3ee3073 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds @@ -88,7 +88,7 @@ SECTIONS .text : { . = ALIGN(0x1000); - *(.text .text.* .gnu.linkonce.t.*) + *(.text .text.*) } . = ALIGN(0x1000); @@ -138,7 +138,7 @@ SECTIONS __global_pointer$ = . + 0x800; *(.sdata*) } - + . = ALIGN((1 << 21)); _edata = .; _end = .; } diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c index bc48c8b75..0ad40cdf5 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c @@ -33,14 +33,14 @@ Modification: #include "pagetable.h" #include "registers.h" #include "ns16550.h" +#include "printf.h" #include #include #include #include - -// clang-format off +// #define L2_PTE_VALID (1 << 0) #define L3_PTE_VALID (1 << 0) @@ -62,7 +62,7 @@ Modification: #define PAGE_KERNEL_READ (_PAGE_KERNEL & ~_PAGE_WRITE) #define PAGE_KERNEL_EXEC (_PAGE_KERNEL | _PAGE_EXEC) -// clang-format on +// uint64_t boot_l2pgdir[NUM_LEVEL2_PDE] __attribute__((aligned(0x1000))) = { 0 }; uint64_t boot_dev_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 }; @@ -71,7 +71,7 @@ uint64_t boot_kern_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { uint64_t boot_dev_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 }; uint64_t boot_kern_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 }; - +// static void build_boot_pgdir() { static bool built = false; @@ -118,16 +118,45 @@ static void load_boot_pgdir() csr_write(CSR_SATP, satp_val); } +// +static int test_access_map_address(void) +{ + unsigned long address = KERN_MEM_BASE + (PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) - 4096; + printf_early("to access 0x%lx\n", address); + *(unsigned long *)address = 0x55; + if(*(unsigned long *)address == 0x55) { + printf_early("access 0x%lx done\n", address); + } + return 0; +} + +static int test_access_unmap_address(void) +{ + unsigned long address = KERN_MEM_BASE + (PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) + 4096; + *(unsigned long *)address = 0x55; + printf_early("access 0x%lx done\n", address); + return 0; +} + +static void test_mmu(void) +{ + test_access_map_address(); + test_access_unmap_address(); +} + +// extern void main(void); void bootmain(void) { - _debug_uart_printascii("bootmain start.\n"); - - build_boot_pgdir(); - load_boot_pgdir(); - _debug_uart_printascii("boot pgdir success\n"); + _debug_uart_printascii("bootmain start\n"); +#if 0 + test_mmu(); +#endif main(); + + _debug_uart_printascii("bootmain end\n"); + while(1); } diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h index b7a67bbc5..2e9e32269 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h @@ -35,7 +35,7 @@ Modification: /* physical memory layout */ #define PHY_MEM_BASE (0x0000000040200000ULL) -#define PHY_USER_FREEMEM_BASE (0x0000000080000000ULL) +#define PHY_USER_FREEMEM_BASE (0x0000000100000000ULL) #define PHY_USER_FREEMEM_TOP (0x0000000200000000ULL) #define PHY_MEM_STOP (0x0000000200000000ULL) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c index 979b78448..698ddee32 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c @@ -55,6 +55,8 @@ pgd_t early_pg_dir[PTRS_PER_PGD] __initdata __attribute__((aligned(PAGE_SIZE))); static pmd_t trampoline_pmd[PTRS_PER_PMD] __page_aligned_bss; static pmd_t early_pmd[PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE))); static pmd_t early_uart_pmd[PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE))); +static pmd_t early_pmd_free[((PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) >> PGDIR_SHIFT) + 1][PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE))); +static pmd_t early_pmd_inear_map[PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE))); static pmd_t *__init get_pmd_virt_early(phys_addr_t pa) @@ -86,7 +88,7 @@ static void __init create_pmd_mapping_early(pmd_t *pmdp, } } -void __init create_pgd_mapping_early(pgd_t *pgdp, +static void __init create_pgd_mapping_early(pgd_t *pgdp, uintptr_t va, phys_addr_t pa, phys_addr_t sz, pgprot_t prot) { @@ -116,7 +118,6 @@ void __init create_pgd_mapping_early(pgd_t *pgdp, static void __init create_kernel_page_table_early(pgd_t *pgdir, bool early) { uintptr_t va, end_va; - int i = 0; end_va = kernel_map.virt_addr + kernel_map.size; for (va = kernel_map.virt_addr; va < end_va; va += PMD_SIZE) { @@ -124,7 +125,76 @@ static void __init create_kernel_page_table_early(pgd_t *pgdir, bool early) kernel_map.phys_addr + (va - kernel_map.virt_addr), PMD_SIZE, PAGE_KERNEL_EXEC); - i++; + } +} + + +static void __init create_kernel_pgd_mapping_free_early(pgd_t *pgdp, + uintptr_t va, phys_addr_t pa, + phys_addr_t sz, pgprot_t prot) +{ + pmd_t *nextp; + phys_addr_t next_phys; + uintptr_t pgd_idx = pgd_index(va); + uintptr_t start_pgd_idx = pgd_index(kernel_map.virt_addr); + + if (pgd_val(pgdp[pgd_idx]) == 0) { + next_phys = early_pmd_free[pgd_idx - start_pgd_idx]; + pgdp[pgd_idx] = pfn_pgd(PFN_DOWN(next_phys), PAGE_TABLE); + nextp = get_pmd_virt_early(next_phys); + memset(nextp, 0, PAGE_SIZE); + } else { + next_phys = PFN_PHYS(_pgd_pfn(pgdp[pgd_idx])); + nextp = get_pmd_virt_early(next_phys); + } + + create_pmd_mapping_early(nextp, va, pa, sz, prot); +} + +static void __init create_kernel_page_table_free_early(pgd_t *pgdir, bool early) +{ + uintptr_t va, end_va; + + end_va = kernel_map.virt_addr + (PHY_USER_FREEMEM_BASE - kernel_map.phys_addr); + for (va = kernel_map.virt_addr + kernel_map.size; va < end_va; va += PMD_SIZE) { + create_kernel_pgd_mapping_free_early(pgdir, va, + kernel_map.phys_addr + (va - kernel_map.virt_addr), + PMD_SIZE, + PAGE_KERNEL_EXEC); + } +} + +static void __init create_kernel_pgd_mapping_linear_map_early(pgd_t *pgdp, + uintptr_t va, phys_addr_t pa, + phys_addr_t sz, pgprot_t prot) +{ + pmd_t *nextp; + phys_addr_t next_phys; + uintptr_t pgd_idx = pgd_index(va); + + if (pgd_val(pgdp[pgd_idx]) == 0) { + next_phys = early_pmd_inear_map; + pgdp[pgd_idx] = pfn_pgd(PFN_DOWN(next_phys), PAGE_TABLE); + nextp = get_pmd_virt_early(next_phys); + memset(nextp, 0, PAGE_SIZE); + } else { + next_phys = PFN_PHYS(_pgd_pfn(pgdp[pgd_idx])); + nextp = get_pmd_virt_early(next_phys); + } + + create_pmd_mapping_early(nextp, va, pa, sz, prot); +} + +static void __init create_kernel_page_table_linear_map_early(pgd_t *pgdir, bool early) +{ + uintptr_t va, end_va; + + end_va = kernel_map.phys_addr + kernel_map.size; + for (va = kernel_map.phys_addr; va < end_va; va += PMD_SIZE) { + create_kernel_pgd_mapping_linear_map_early(pgdir, va, + kernel_map.phys_addr + (va - kernel_map.phys_addr), + PMD_SIZE, + PAGE_KERNEL_EXEC); } } @@ -166,5 +236,11 @@ void __init setup_vm_early(void) /* Setup uart PGD and PMD */ create_pgd_mapping_early(early_pg_dir, DEV_VRTMEM_BASE, (uintptr_t)early_uart_pmd, PGDIR_SIZE, PAGE_TABLE); create_pmd_mapping_early(early_uart_pmd, DEV_VRTMEM_BASE, DEV_PHYMEM_BASE, PMD_SIZE, PAGE_KERNEL); + + /* Setup kernel free PGD and PMD */ + create_kernel_page_table_free_early(early_pg_dir, true); + + /* Setup kernel linear map PGD and PMD */ + create_kernel_page_table_linear_map_early(early_pg_dir, true); } diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/uart_common_ope.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/uart_common_ope.c index 07130da60..4aa8f0939 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/uart_common_ope.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/uart_common_ope.c @@ -898,13 +898,24 @@ int fctprintf(void (*out)(char character, void* arg), void* arg, const char* for } /////////////////////////////////////////////////////////////////////////////// -__attribute__((weak)) void _debug_uart_putc(int ch); +__attribute__((weak)) void _debug_uart_putc(int ch) {} + +static inline void _out_char_early(char character, void* buffer, size_t idx, size_t maxlen) +{ + (void)buffer; + (void)idx; + (void)maxlen; + if (character) { + _debug_uart_putc(character); + } +} + int printf_early(const char* format, ...) { va_list va; va_start(va, format); char buffer[1]; - const int ret = _vsnprintf(_debug_uart_putc, buffer, (size_t)-1, format, va); + const int ret = _vsnprintf(_out_char_early, buffer, (size_t)-1, format, va); va_end(va); return ret; } From ce1c689379b386a8ff5298871e4fb1bbec6dd59e Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 6 Dec 2024 17:06:23 +0800 Subject: [PATCH 09/54] Fix compile warnings --- .../hardkernel/mmu/riscv/rv64gc/bootmmu.c | 80 +------------------ .../hardkernel/mmu/riscv/rv64gc/mmu_init.c | 8 +- .../riscv/rv64gc/uart_io_for_jh7110/ns16550.c | 4 +- 3 files changed, 6 insertions(+), 86 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c index 0ad40cdf5..0f62871c7 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c @@ -41,84 +41,7 @@ Modification: #include // -#define L2_PTE_VALID (1 << 0) - -#define L3_PTE_VALID (1 << 0) - -#define L4_TYPE_PAGE (3 << 0) -#define L4_PTE_DEV ((0b00) << 2) // Device memory -#define L4_PTE_NORMAL ((0b01) << 2) // Device memory -#define L4_PTE_AF (1 << 10) // Data Access Permissions - -#define L4_PTE_PXN (1UL << 53) // Privileged eXecute Never -#define L4_PTE_UXN (1UL << 54) // Unprivileged(user) eXecute Never -#define L4_PTE_XN (PTE_PXN|PTE_UXN) // eXecute Never - -#define IDX_MASK (0b111111111) -#define L3_PDE_INDEX(idx) ((idx << LEVEL3_PDE_SHIFT) & L3_IDX_MASK) - -#define _PAGE_KERNEL (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC | _PAGE_ACCESSED | _PAGE_GLOBAL | _PAGE_DIRTY) -#define PAGE_KERNEL (_PAGE_KERNEL) -#define PAGE_KERNEL_READ (_PAGE_KERNEL & ~_PAGE_WRITE) -#define PAGE_KERNEL_EXEC (_PAGE_KERNEL | _PAGE_EXEC) - -// -uint64_t boot_l2pgdir[NUM_LEVEL2_PDE] __attribute__((aligned(0x1000))) = { 0 }; - -uint64_t boot_dev_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 }; -uint64_t boot_kern_l3pgdir[NUM_LEVEL3_PDE] __attribute__((aligned(0x1000))) = { 0 }; - -uint64_t boot_dev_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 }; -uint64_t boot_kern_l4pgdirs[NUM_LEVEL3_PDE][NUM_LEVEL4_PTE] __attribute__((aligned(0x1000))) = { 0 }; - -// -static void build_boot_pgdir() -{ - static bool built = false; - if (!built) { - uint64_t dev_phy_mem_base = DEV_PHYMEM_BASE; - uint64_t kern_phy_mem_base = PHY_MEM_BASE; - uint64_t cur_mem_paddr; - - // dev mem - boot_l2pgdir[(dev_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (((uint64_t)boot_dev_l3pgdir >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | _PAGE_TABLE; - boot_l2pgdir[(MMIO_P2V_WO(dev_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (((uint64_t)boot_dev_l3pgdir >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | _PAGE_TABLE; - - cur_mem_paddr = ALIGNDOWN(dev_phy_mem_base, LEVEL2_PDE_SIZE); - for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) { - boot_dev_l3pgdir[i] = (((uint64_t)cur_mem_paddr >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | PAGE_KERNEL; - cur_mem_paddr += LEVEL3_PDE_SIZE; - } - - // identical mem - boot_l2pgdir[(kern_phy_mem_base >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (((uint64_t)boot_kern_l3pgdir >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | _PAGE_TABLE; - boot_l2pgdir[(P2V_WO(kern_phy_mem_base) >> LEVEL2_PDE_SHIFT) & IDX_MASK] = (((uint64_t)boot_kern_l3pgdir >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | _PAGE_TABLE; - - cur_mem_paddr = ALIGNDOWN(kern_phy_mem_base, PAGE_SIZE); - for (size_t i = 0; i < NUM_LEVEL3_PDE; i++) { - boot_kern_l3pgdir[i] = (((uint64_t)cur_mem_paddr >> PAGE_SHIFT) << _PAGE_PFN_SHIFT) | PAGE_KERNEL; - cur_mem_paddr += LEVEL3_PDE_SIZE; - } - - built = true; - } -} - - -static inline void local_flush_tlb_all(void) -{ - __asm__ __volatile__ ("sfence.vma" : : : "memory"); -} - -static void load_boot_pgdir() -{ - unsigned long satp_val = 0; - - satp_val = (unsigned long)(((uintptr_t)boot_l2pgdir >> PAGE_SHIFT) | SATP_MODE); - csr_write(CSR_SATP, satp_val); -} - -// +#if 0 static int test_access_map_address(void) { unsigned long address = KERN_MEM_BASE + (PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) - 4096; @@ -143,6 +66,7 @@ static void test_mmu(void) test_access_map_address(); test_access_unmap_address(); } +#endif // extern void main(void); diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c index 698ddee32..0188cc570 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c @@ -40,7 +40,6 @@ Modification: #define __page_aligned_bss __attribute__((section(".bss..page_aligned"))) __attribute__((aligned(PAGE_SIZE))) #define __initdata __attribute__((section(".init.data"))) #define __init __attribute__((section(".init.text"))) -#define __aligned(x) __attribute__((aligned__(x))) #define __maybe_unused __attribute__((__unused__)) @@ -76,8 +75,6 @@ static void __init create_pmd_mapping_early(pmd_t *pmdp, uintptr_t va, phys_addr_t pa, phys_addr_t sz, pgprot_t prot) { - pte_t *ptep; - phys_addr_t pte_phys; uintptr_t pmd_idx = pmd_index(va); if (sz == PMD_SIZE) { @@ -139,7 +136,7 @@ static void __init create_kernel_pgd_mapping_free_early(pgd_t *pgdp, uintptr_t start_pgd_idx = pgd_index(kernel_map.virt_addr); if (pgd_val(pgdp[pgd_idx]) == 0) { - next_phys = early_pmd_free[pgd_idx - start_pgd_idx]; + next_phys = (uintptr_t)early_pmd_free[pgd_idx - start_pgd_idx]; pgdp[pgd_idx] = pfn_pgd(PFN_DOWN(next_phys), PAGE_TABLE); nextp = get_pmd_virt_early(next_phys); memset(nextp, 0, PAGE_SIZE); @@ -173,7 +170,7 @@ static void __init create_kernel_pgd_mapping_linear_map_early(pgd_t *pgdp, uintptr_t pgd_idx = pgd_index(va); if (pgd_val(pgdp[pgd_idx]) == 0) { - next_phys = early_pmd_inear_map; + next_phys = (uintptr_t)early_pmd_inear_map; pgdp[pgd_idx] = pfn_pgd(PFN_DOWN(next_phys), PAGE_TABLE); nextp = get_pmd_virt_early(next_phys); memset(nextp, 0, PAGE_SIZE); @@ -211,7 +208,6 @@ static void __init create_kernel_page_table_linear_map_early(pgd_t *pgdir, bool void __init setup_vm_early(void) { - _debug_uart_printascii("setup_vm_early start\n"); kernel_map.virt_addr = KERN_MEM_BASE; kernel_map.phys_addr = (uintptr_t)(&_start); diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c index 27f6592d0..b0447db7a 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/riscv/rv64gc/uart_io_for_jh7110/ns16550.c @@ -176,7 +176,7 @@ void _debug_uart_init(void) g_ns16550_uart_base = CONFIG_SYS_NS16550_UART_BASE_VIRT; ns16550_serial_init(); ns16550_serial_setbrg(baudrate); - _debug_uart_printascii("_debug_uart_init success.\n"); +// _debug_uart_printascii("_debug_uart_init success.\n"); } void _debug_uart_init_early(void) @@ -186,7 +186,7 @@ void _debug_uart_init_early(void) g_ns16550_uart_base = CONFIG_SYS_NS16550_UART_BASE; ns16550_serial_init(); ns16550_serial_setbrg(baudrate); - _debug_uart_printascii("_debug_uart_init_early success.\n"); +// _debug_uart_printascii("_debug_uart_init_early success.\n"); } void _debug_uart_putc(int ch) From 254651bcd0f66d7e900dad0154e2fbc51eac9ddc Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 11 Dec 2024 11:24:32 +0800 Subject: [PATCH 10/54] Add exception --- .../riscv/rv64gc/include/asm/asm-offsets.h | 156 ++++++++++++++++++ .../hardkernel/intr/riscv/rv64gc/Makefile | 2 +- .../hardkernel/intr/riscv/rv64gc/entry.S | 139 ++++++++++++++++ .../intr/riscv/rv64gc/jh7110/trap.c | 116 ++++++++++++- .../hardkernel/intr/riscv/rv64gc/ptrace.h | 114 +++++++++++++ Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h | 4 +- 6 files changed, 528 insertions(+), 3 deletions(-) create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/asm-offsets.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/entry.S create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/ptrace.h diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/asm-offsets.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/asm-offsets.h new file mode 100644 index 000000000..58e0bf035 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/asm-offsets.h @@ -0,0 +1,156 @@ +#ifndef __ASM_OFFSETS_H__ +#define __ASM_OFFSETS_H__ +/* + * DO NOT MODIFY. + * + * This file was generated by Kbuild + */ + +#define TASK_THREAD_RA 2232 /* offsetof(struct task_struct, thread.ra) */ +#define TASK_THREAD_SP 2240 /* offsetof(struct task_struct, thread.sp) */ +#define TASK_THREAD_S0 2248 /* offsetof(struct task_struct, thread.s[0]) */ +#define TASK_THREAD_S1 2256 /* offsetof(struct task_struct, thread.s[1]) */ +#define TASK_THREAD_S2 2264 /* offsetof(struct task_struct, thread.s[2]) */ +#define TASK_THREAD_S3 2272 /* offsetof(struct task_struct, thread.s[3]) */ +#define TASK_THREAD_S4 2280 /* offsetof(struct task_struct, thread.s[4]) */ +#define TASK_THREAD_S5 2288 /* offsetof(struct task_struct, thread.s[5]) */ +#define TASK_THREAD_S6 2296 /* offsetof(struct task_struct, thread.s[6]) */ +#define TASK_THREAD_S7 2304 /* offsetof(struct task_struct, thread.s[7]) */ +#define TASK_THREAD_S8 2312 /* offsetof(struct task_struct, thread.s[8]) */ +#define TASK_THREAD_S9 2320 /* offsetof(struct task_struct, thread.s[9]) */ +#define TASK_THREAD_S10 2328 /* offsetof(struct task_struct, thread.s[10]) */ +#define TASK_THREAD_S11 2336 /* offsetof(struct task_struct, thread.s[11]) */ +#define TASK_TI_FLAGS 0 /* offsetof(struct task_struct, thread_info.flags) */ +#define TASK_TI_PREEMPT_COUNT 8 /* offsetof(struct task_struct, thread_info.preempt_count) */ +#define TASK_TI_KERNEL_SP 16 /* offsetof(struct task_struct, thread_info.kernel_sp) */ +#define TASK_TI_USER_SP 24 /* offsetof(struct task_struct, thread_info.user_sp) */ +#define TASK_TI_CPU 32 /* offsetof(struct task_struct, thread_info.cpu) */ +#define TASK_THREAD_F0 2344 /* offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F1 2352 /* offsetof(struct task_struct, thread.fstate.f[1]) */ +#define TASK_THREAD_F2 2360 /* offsetof(struct task_struct, thread.fstate.f[2]) */ +#define TASK_THREAD_F3 2368 /* offsetof(struct task_struct, thread.fstate.f[3]) */ +#define TASK_THREAD_F4 2376 /* offsetof(struct task_struct, thread.fstate.f[4]) */ +#define TASK_THREAD_F5 2384 /* offsetof(struct task_struct, thread.fstate.f[5]) */ +#define TASK_THREAD_F6 2392 /* offsetof(struct task_struct, thread.fstate.f[6]) */ +#define TASK_THREAD_F7 2400 /* offsetof(struct task_struct, thread.fstate.f[7]) */ +#define TASK_THREAD_F8 2408 /* offsetof(struct task_struct, thread.fstate.f[8]) */ +#define TASK_THREAD_F9 2416 /* offsetof(struct task_struct, thread.fstate.f[9]) */ +#define TASK_THREAD_F10 2424 /* offsetof(struct task_struct, thread.fstate.f[10]) */ +#define TASK_THREAD_F11 2432 /* offsetof(struct task_struct, thread.fstate.f[11]) */ +#define TASK_THREAD_F12 2440 /* offsetof(struct task_struct, thread.fstate.f[12]) */ +#define TASK_THREAD_F13 2448 /* offsetof(struct task_struct, thread.fstate.f[13]) */ +#define TASK_THREAD_F14 2456 /* offsetof(struct task_struct, thread.fstate.f[14]) */ +#define TASK_THREAD_F15 2464 /* offsetof(struct task_struct, thread.fstate.f[15]) */ +#define TASK_THREAD_F16 2472 /* offsetof(struct task_struct, thread.fstate.f[16]) */ +#define TASK_THREAD_F17 2480 /* offsetof(struct task_struct, thread.fstate.f[17]) */ +#define TASK_THREAD_F18 2488 /* offsetof(struct task_struct, thread.fstate.f[18]) */ +#define TASK_THREAD_F19 2496 /* offsetof(struct task_struct, thread.fstate.f[19]) */ +#define TASK_THREAD_F20 2504 /* offsetof(struct task_struct, thread.fstate.f[20]) */ +#define TASK_THREAD_F21 2512 /* offsetof(struct task_struct, thread.fstate.f[21]) */ +#define TASK_THREAD_F22 2520 /* offsetof(struct task_struct, thread.fstate.f[22]) */ +#define TASK_THREAD_F23 2528 /* offsetof(struct task_struct, thread.fstate.f[23]) */ +#define TASK_THREAD_F24 2536 /* offsetof(struct task_struct, thread.fstate.f[24]) */ +#define TASK_THREAD_F25 2544 /* offsetof(struct task_struct, thread.fstate.f[25]) */ +#define TASK_THREAD_F26 2552 /* offsetof(struct task_struct, thread.fstate.f[26]) */ +#define TASK_THREAD_F27 2560 /* offsetof(struct task_struct, thread.fstate.f[27]) */ +#define TASK_THREAD_F28 2568 /* offsetof(struct task_struct, thread.fstate.f[28]) */ +#define TASK_THREAD_F29 2576 /* offsetof(struct task_struct, thread.fstate.f[29]) */ +#define TASK_THREAD_F30 2584 /* offsetof(struct task_struct, thread.fstate.f[30]) */ +#define TASK_THREAD_F31 2592 /* offsetof(struct task_struct, thread.fstate.f[31]) */ +#define TASK_THREAD_FCSR 2600 /* offsetof(struct task_struct, thread.fstate.fcsr) */ +#define TSK_STACK_CANARY 1080 /* offsetof(struct task_struct, stack_canary) */ +#define PT_SIZE 288 /* sizeof(struct pt_regs) */ +#define PT_EPC 0 /* offsetof(struct pt_regs, epc) */ +#define PT_RA 8 /* offsetof(struct pt_regs, ra) */ +#define PT_FP 64 /* offsetof(struct pt_regs, s0) */ +#define PT_S0 64 /* offsetof(struct pt_regs, s0) */ +#define PT_S1 72 /* offsetof(struct pt_regs, s1) */ +#define PT_S2 144 /* offsetof(struct pt_regs, s2) */ +#define PT_S3 152 /* offsetof(struct pt_regs, s3) */ +#define PT_S4 160 /* offsetof(struct pt_regs, s4) */ +#define PT_S5 168 /* offsetof(struct pt_regs, s5) */ +#define PT_S6 176 /* offsetof(struct pt_regs, s6) */ +#define PT_S7 184 /* offsetof(struct pt_regs, s7) */ +#define PT_S8 192 /* offsetof(struct pt_regs, s8) */ +#define PT_S9 200 /* offsetof(struct pt_regs, s9) */ +#define PT_S10 208 /* offsetof(struct pt_regs, s10) */ +#define PT_S11 216 /* offsetof(struct pt_regs, s11) */ +#define PT_SP 16 /* offsetof(struct pt_regs, sp) */ +#define PT_TP 32 /* offsetof(struct pt_regs, tp) */ +#define PT_A0 80 /* offsetof(struct pt_regs, a0) */ +#define PT_A1 88 /* offsetof(struct pt_regs, a1) */ +#define PT_A2 96 /* offsetof(struct pt_regs, a2) */ +#define PT_A3 104 /* offsetof(struct pt_regs, a3) */ +#define PT_A4 112 /* offsetof(struct pt_regs, a4) */ +#define PT_A5 120 /* offsetof(struct pt_regs, a5) */ +#define PT_A6 128 /* offsetof(struct pt_regs, a6) */ +#define PT_A7 136 /* offsetof(struct pt_regs, a7) */ +#define PT_T0 40 /* offsetof(struct pt_regs, t0) */ +#define PT_T1 48 /* offsetof(struct pt_regs, t1) */ +#define PT_T2 56 /* offsetof(struct pt_regs, t2) */ +#define PT_T3 224 /* offsetof(struct pt_regs, t3) */ +#define PT_T4 232 /* offsetof(struct pt_regs, t4) */ +#define PT_T5 240 /* offsetof(struct pt_regs, t5) */ +#define PT_T6 248 /* offsetof(struct pt_regs, t6) */ +#define PT_GP 24 /* offsetof(struct pt_regs, gp) */ +#define PT_ORIG_A0 280 /* offsetof(struct pt_regs, orig_a0) */ +#define PT_STATUS 256 /* offsetof(struct pt_regs, status) */ +#define PT_BADADDR 264 /* offsetof(struct pt_regs, badaddr) */ +#define PT_CAUSE 272 /* offsetof(struct pt_regs, cause) */ +#define SUSPEND_CONTEXT_REGS 0 /* offsetof(struct suspend_context, regs) */ +#define HIBERN_PBE_ADDR 0 /* offsetof(struct pbe, address) */ +#define HIBERN_PBE_ORIG 8 /* offsetof(struct pbe, orig_address) */ +#define HIBERN_PBE_NEXT 16 /* offsetof(struct pbe, next) */ +#define TASK_THREAD_RA_RA 0 /* offsetof(struct task_struct, thread.ra) - offsetof(struct task_struct, thread.ra) */ +#define TASK_THREAD_SP_RA 8 /* offsetof(struct task_struct, thread.sp) - offsetof(struct task_struct, thread.ra) */ +#define TASK_THREAD_S0_RA 16 /* offsetof(struct task_struct, thread.s[0]) - offsetof(struct task_struct, thread.ra) */ +#define TASK_THREAD_S1_RA 24 /* offsetof(struct task_struct, thread.s[1]) - offsetof(struct task_struct, thread.ra) */ +#define TASK_THREAD_S2_RA 32 /* offsetof(struct task_struct, thread.s[2]) - offsetof(struct task_struct, thread.ra) */ +#define TASK_THREAD_S3_RA 40 /* offsetof(struct task_struct, thread.s[3]) - offsetof(struct task_struct, thread.ra) */ +#define TASK_THREAD_S4_RA 48 /* offsetof(struct task_struct, thread.s[4]) - offsetof(struct task_struct, thread.ra) */ +#define TASK_THREAD_S5_RA 56 /* offsetof(struct task_struct, thread.s[5]) - offsetof(struct task_struct, thread.ra) */ +#define TASK_THREAD_S6_RA 64 /* offsetof(struct task_struct, thread.s[6]) - offsetof(struct task_struct, thread.ra) */ +#define TASK_THREAD_S7_RA 72 /* offsetof(struct task_struct, thread.s[7]) - offsetof(struct task_struct, thread.ra) */ +#define TASK_THREAD_S8_RA 80 /* offsetof(struct task_struct, thread.s[8]) - offsetof(struct task_struct, thread.ra) */ +#define TASK_THREAD_S9_RA 88 /* offsetof(struct task_struct, thread.s[9]) - offsetof(struct task_struct, thread.ra) */ +#define TASK_THREAD_S10_RA 96 /* offsetof(struct task_struct, thread.s[10]) - offsetof(struct task_struct, thread.ra) */ +#define TASK_THREAD_S11_RA 104 /* offsetof(struct task_struct, thread.s[11]) - offsetof(struct task_struct, thread.ra) */ +#define TASK_THREAD_F0_F0 0 /* offsetof(struct task_struct, thread.fstate.f[0]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F1_F0 8 /* offsetof(struct task_struct, thread.fstate.f[1]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F2_F0 16 /* offsetof(struct task_struct, thread.fstate.f[2]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F3_F0 24 /* offsetof(struct task_struct, thread.fstate.f[3]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F4_F0 32 /* offsetof(struct task_struct, thread.fstate.f[4]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F5_F0 40 /* offsetof(struct task_struct, thread.fstate.f[5]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F6_F0 48 /* offsetof(struct task_struct, thread.fstate.f[6]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F7_F0 56 /* offsetof(struct task_struct, thread.fstate.f[7]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F8_F0 64 /* offsetof(struct task_struct, thread.fstate.f[8]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F9_F0 72 /* offsetof(struct task_struct, thread.fstate.f[9]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F10_F0 80 /* offsetof(struct task_struct, thread.fstate.f[10]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F11_F0 88 /* offsetof(struct task_struct, thread.fstate.f[11]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F12_F0 96 /* offsetof(struct task_struct, thread.fstate.f[12]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F13_F0 104 /* offsetof(struct task_struct, thread.fstate.f[13]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F14_F0 112 /* offsetof(struct task_struct, thread.fstate.f[14]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F15_F0 120 /* offsetof(struct task_struct, thread.fstate.f[15]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F16_F0 128 /* offsetof(struct task_struct, thread.fstate.f[16]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F17_F0 136 /* offsetof(struct task_struct, thread.fstate.f[17]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F18_F0 144 /* offsetof(struct task_struct, thread.fstate.f[18]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F19_F0 152 /* offsetof(struct task_struct, thread.fstate.f[19]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F20_F0 160 /* offsetof(struct task_struct, thread.fstate.f[20]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F21_F0 168 /* offsetof(struct task_struct, thread.fstate.f[21]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F22_F0 176 /* offsetof(struct task_struct, thread.fstate.f[22]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F23_F0 184 /* offsetof(struct task_struct, thread.fstate.f[23]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F24_F0 192 /* offsetof(struct task_struct, thread.fstate.f[24]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F25_F0 200 /* offsetof(struct task_struct, thread.fstate.f[25]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F26_F0 208 /* offsetof(struct task_struct, thread.fstate.f[26]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F27_F0 216 /* offsetof(struct task_struct, thread.fstate.f[27]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F28_F0 224 /* offsetof(struct task_struct, thread.fstate.f[28]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F29_F0 232 /* offsetof(struct task_struct, thread.fstate.f[29]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F30_F0 240 /* offsetof(struct task_struct, thread.fstate.f[30]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_F31_F0 248 /* offsetof(struct task_struct, thread.fstate.f[31]) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define TASK_THREAD_FCSR_F0 256 /* offsetof(struct task_struct, thread.fstate.fcsr) - offsetof(struct task_struct, thread.fstate.f[0]) */ +#define PT_SIZE_ON_STACK 288 /* ALIGN(sizeof(struct pt_regs), STACK_ALIGN) */ +#define KERNEL_MAP_VIRT_ADDR 0 /* offsetof(struct kernel_mapping, virt_addr) */ +#define SBI_HART_BOOT_TASK_PTR_OFFSET 0 /* offsetof(struct sbi_hart_boot_data, task_ptr) */ +#define SBI_HART_BOOT_STACK_PTR_OFFSET 8 /* offsetof(struct sbi_hart_boot_data, stack_ptr) */ + +#endif diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile index 6fd2fb6d5..aed82542a 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile @@ -1,4 +1,4 @@ -SRC_FILES := trampoline.S $(BOARD)/trap_common.c $(BOARD)/trap.c error_debug.c hard_spinlock.S +SRC_FILES := entry.S trampoline.S $(BOARD)/trap_common.c $(BOARD)/trap.c error_debug.c hard_spinlock.S ifeq ($(BOARD), jh7110) SRC_DIR := gicv3 diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/entry.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/entry.S new file mode 100644 index 000000000..177610739 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/entry.S @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file entry.S + * @brief trap in and out code + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024-12-10 + */ + +/************************************************* +File name: entry.S +Description: trap in and out code +Others: +History: +1. Date: 2024-12-10 +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ + +#include "asm/asm-offsets.h" + +.macro kernel_entry + addi sp, sp, -(PT_SIZE) + + sd x1, PT_RA(sp) + sd x3, PT_GP(sp) + sd x5, PT_T0(sp) + sd x6, PT_T1(sp) + sd x7, PT_T2(sp) + sd x8, PT_S0(sp) + sd x9, PT_S1(sp) + sd x10, PT_A0(sp) + sd x11, PT_A1(sp) + sd x12, PT_A2(sp) + sd x13, PT_A3(sp) + sd x14, PT_A4(sp) + sd x15, PT_A5(sp) + sd x16, PT_A6(sp) + sd x17, PT_A7(sp) + sd x18, PT_S2(sp) + sd x19, PT_S3(sp) + sd x20, PT_S4(sp) + sd x21, PT_S5(sp) + sd x22, PT_S6(sp) + sd x23, PT_S7(sp) + sd x24, PT_S8(sp) + sd x25, PT_S9(sp) + sd x26, PT_S10(sp) + sd x27, PT_S11(sp) + sd x28, PT_T3(sp) + sd x29, PT_T4(sp) + sd x30, PT_T5(sp) + sd x31, PT_T6(sp) + + csrr s2, sepc + sd s2, PT_EPC(sp) + csrr s3, sbadaddr + sd s3, PT_BADADDR(sp) + csrr s4, scause + sd s4, PT_CAUSE(sp) + csrr s5, sscratch + sd s5, PT_TP(sp) + + addi s0, sp, PT_SIZE + sd sp, PT_SP(sp) +.endm + + +.macro kernel_exit + ld a0, PT_STATUS(sp) + csrw sstatus, a0 + ld a2, PT_EPC(sp) + csrw sepc, a2 + + ld x1, PT_RA(sp) + ld x3, PT_GP(sp) + ld x5, PT_T0(sp) + ld x6, PT_T1(sp) + ld x7, PT_T2(sp) + ld x8, PT_S0(sp) + ld x9, PT_S1(sp) + ld x10, PT_A0(sp) + ld x11, PT_A1(sp) + ld x12, PT_A2(sp) + ld x13, PT_A3(sp) + ld x14, PT_A4(sp) + ld x15, PT_A5(sp) + ld x16, PT_A6(sp) + ld x17, PT_A7(sp) + ld x18, PT_S2(sp) + ld x19, PT_S3(sp) + ld x20, PT_S4(sp) + ld x21, PT_S5(sp) + ld x22, PT_S6(sp) + ld x23, PT_S7(sp) + ld x24, PT_S8(sp) + ld x25, PT_S9(sp) + ld x26, PT_S10(sp) + ld x27, PT_S11(sp) + ld x28, PT_T3(sp) + ld x29, PT_T4(sp) + ld x30, PT_T5(sp) + ld x31, PT_T6(sp) + + ld x2, PT_SP(sp) +.endm + + + +.align 4 + .global do_exception_vector +do_exception_vector: + kernel_entry + la ra, ret_from_exception + mv a0, sp /* pt_regs */ + mv a1, s4 + tail do_exception + +ret_from_exception: +restore_all: + kernel_exit + sret + +.global trigger_fault +trigger_fault: + li a0, 0x70000000 + ld a0, (a0) + ret diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c index f28c7a6a3..5361f8f2a 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c @@ -38,6 +38,10 @@ Modification: #include "mmu.h" +#include "asm/csr.h" +#include "ptrace.h" + + extern void dabort_handler(struct trapframe* r); extern void iabort_handler(struct trapframe* r); @@ -118,4 +122,114 @@ void syscall_arch_handler(struct trapframe* tf) panic("dabort end should never be reashed.\n"); } } -} \ No newline at end of file +} + + + +static void do_trap_error(struct pt_regs *regs, const char *str) +{ + printk("Oops: %s\n", str); + printk("sstatus: 0x%016lx, sbadaddr: 0x%016lx, scause: 0x%016lx\n", + regs->status, regs->badaddr, regs->cause); + panic("Fatal exception\n"); +} + +#define DO_ERROR_INFO(name) \ +static int name(struct pt_regs *regs, const char *str) \ +{ \ + do_trap_error(regs, str); \ + return 0; \ +} + +DO_ERROR_INFO(do_trap_unknown); +DO_ERROR_INFO(do_trap_insn_misaligned); +DO_ERROR_INFO(do_trap_insn_fault); +DO_ERROR_INFO(do_trap_insn_illegal); +DO_ERROR_INFO(do_trap_load_misaligned); +DO_ERROR_INFO(do_trap_load_fault); +DO_ERROR_INFO(do_trap_store_misaligned); +DO_ERROR_INFO(do_trap_store_fault); +DO_ERROR_INFO(do_trap_ecall_u); +DO_ERROR_INFO(do_trap_ecall_s); +DO_ERROR_INFO(do_trap_break); +DO_ERROR_INFO(do_page_fault); + +struct fault_info { + int (*fn)(struct pt_regs *regs, const char *name); + const char *name; +}; + +static const struct fault_info fault_inf[] = { + {do_trap_insn_misaligned, "Instruction address misaligned"}, + {do_trap_insn_fault, "Instruction access fault"}, + {do_trap_insn_illegal, "Illegal instruction"}, + {do_trap_break, "Breakpoint"}, + {do_trap_load_misaligned, "Load address misaligned"}, + {do_trap_load_fault, "Load access fault"}, + {do_trap_store_misaligned, "Store/AMO address misaligned"}, + {do_trap_store_fault, "Store/AMO access fault"}, + {do_trap_ecall_u, "Environment call from U-mode"}, + {do_trap_ecall_s, "Environment call from S-mode"}, + {do_trap_unknown, "unknown 10"}, + {do_trap_unknown, "unknown 11"}, + {do_page_fault, "Instruction page fault"}, + {do_page_fault, "Load page fault"}, + {do_trap_unknown, "unknown 14"}, + {do_page_fault, "Store/AMO page fault"}, +}; + + +/* +void delegate_traps(void) +{ + unsigned long interrupts = MIP_SSIP | MIP_STIP | MIP_SEIP; + + unsigned long exceptions = (1UL << CAUSE_MISALIGNED_FETCH) | + (1UL << CAUSE_FETCH_PAGE_FAULT) | + (1UL << CAUSE_BREAKPOINT) | + (1UL << CAUSE_LOAD_PAGE_FAULT) | + (1UL << CAUSE_STORE_PAGE_FAULT) | + (1UL << CAUSE_USER_ECALL) | + (1UL << CAUSE_LOAD_ACCESS_FAULT) | + (1UL << CAUSE_STORE_ACCESS_FAULT); + + csr_write(mideleg, interrupts); + csr_write(medeleg, exceptions); +} +*/ + + +struct fault_info * ec_to_fault_info(unsigned long scause) +{ + struct fault_info *inf; + if (scause >= (sizeof(fault_inf)/sizeof(fault_inf[0]))) { + printk("The cause is out of range Exception Code, scause=0x%lx\n", scause); + panic("Fatal exception\n"); + } + inf = &fault_inf[scause]; + return inf; +} +extern void do_exception_vector(void); +void trap_init(void) +{ + csr_write(stvec, do_exception_vector); + //printk("stvec=0x%lx, do_exception_vector=0x%lx\n", csr_read(stvec), (unsigned long)do_exception_vector); + csr_write(sie, 0); +} + +void do_exception(struct pt_regs *regs, unsigned long scause) +{ + const struct fault_info *inf; + + printk("%s, scause: 0x%lx\n", __func__, scause); + + if (scause & CAUSE_IRQ_FLAG) { + // TODO: 处理中断 + } + else { + inf = ec_to_fault_info(scause); + if (!inf->fn(regs, inf->name)) { + return; + } + } +} diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/ptrace.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/ptrace.h new file mode 100644 index 000000000..0427b750e --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/ptrace.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2012 Regents of the University of California + */ + +#ifndef _ASM_RISCV_PTRACE_H +#define _ASM_RISCV_PTRACE_H + +//#include +//#include +//#include + + +struct pt_regs { + unsigned long epc; + unsigned long ra; + unsigned long sp; + unsigned long gp; + unsigned long tp; + unsigned long t0; + unsigned long t1; + unsigned long t2; + unsigned long s0; + unsigned long s1; + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; + unsigned long a4; + unsigned long a5; + unsigned long a6; + unsigned long a7; + unsigned long s2; + unsigned long s3; + unsigned long s4; + unsigned long s5; + unsigned long s6; + unsigned long s7; + unsigned long s8; + unsigned long s9; + unsigned long s10; + unsigned long s11; + unsigned long t3; + unsigned long t4; + unsigned long t5; + unsigned long t6; + /* Supervisor/Machine CSRs */ + unsigned long status; + unsigned long badaddr; + unsigned long cause; + /* a0 value before the syscall */ + unsigned long orig_a0; +}; + +#define REG_FMT "%016lx" + +#define user_mode(regs) (((regs)->status & SR_PP) == 0) + +//#define MAX_REG_OFFSET offsetof(struct pt_regs, orig_a0) + +/* Helpers for working with the instruction pointer */ +static inline unsigned long instruction_pointer(struct pt_regs *regs) +{ + return regs->epc; +} +static inline void instruction_pointer_set(struct pt_regs *regs, + unsigned long val) +{ + regs->epc = val; +} + +#define profile_pc(regs) instruction_pointer(regs) + +/* Helpers for working with the user stack pointer */ +static inline unsigned long user_stack_pointer(struct pt_regs *regs) +{ + return regs->sp; +} +static inline void user_stack_pointer_set(struct pt_regs *regs, + unsigned long val) +{ + regs->sp = val; +} + +/* Valid only for Kernel mode traps. */ +static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) +{ + return regs->sp; +} + +/* Helpers for working with the frame pointer */ +static inline unsigned long frame_pointer(struct pt_regs *regs) +{ + return regs->s0; +} +static inline void frame_pointer_set(struct pt_regs *regs, + unsigned long val) +{ + regs->s0 = val; +} + +static inline unsigned long regs_return_value(struct pt_regs *regs) +{ + return regs->a0; +} + +static inline void regs_set_return_value(struct pt_regs *regs, + unsigned long val) +{ + regs->a0 = val; +} + + +#endif /* _ASM_RISCV_PTRACE_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h index 93e207e93..ed0bd0d3b 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/uart/printf.h @@ -51,6 +51,7 @@ extern "C" { #define printf printf_ int printf_(const char* format, ...); int printf_early(const char* format, ...); +#define printk printf_ /** * Tiny sprintf implementation @@ -100,4 +101,5 @@ int fctprintf(void (*out)(char character, void* arg), void* arg, const char* for } #endif -#endif // _PRINTF_H_ \ No newline at end of file +#endif // _PRINTF_H_ + From 72e31757078d98bcbd36cb7981b0275b57527e97 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 12 Dec 2024 16:56:41 +0800 Subject: [PATCH 11/54] Get boot hartid from uboot --- .../hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S | 5 +++++ .../hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/smp.c | 2 ++ 2 files changed, 7 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S index d0edd59c6..7936bc59f 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S @@ -20,9 +20,11 @@ _boot_start: + mv s0, a0 call _debug_uart_init_early la a0, debug_string_start call _debug_uart_printascii + mv a0, s0 j _start_kernel @@ -42,6 +44,9 @@ clear_bss: blt a3, a4, clear_bss clear_bss_done: + la a2, boot_cpu_hartid + sd a0, (a2) + la sp, stacks_top /* Initialize page tables and relocate to virtual addresses */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/smp.c b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/smp.c index 395b3e32e..fc12003e6 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/smp.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/smp.c @@ -47,6 +47,8 @@ Modification: *************************************************/ #include +unsigned long boot_cpu_hartid; + #define PSCI_CPUON 0xc4000003 struct xizi_smccc_res { unsigned long a0; From fe26bb4e5a60b8930a83c9a2049468dd75814728 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 13 Dec 2024 19:42:48 +0800 Subject: [PATCH 12/54] Add PLIC --- .../arch/riscv/rv64gc/include/asm/mmio.h | 175 ++++++++++++++++++ .../hardkernel/intr/riscv/rv64gc/Makefile | 2 +- .../intr/riscv/rv64gc/jh7110/plic.c | 73 ++++++++ .../intr/riscv/rv64gc/jh7110/plic.h | 20 ++ .../intr/riscv/rv64gc/jh7110/trap.c | 54 +++--- .../intr/riscv/rv64gc/jh7110/trap_common.c | 24 ++- .../hardkernel/intr/riscv/rv64gc/ptrace.h | 10 - .../mmu/riscv/rv64gc/jh7110/memlayout.h | 5 + .../hardkernel/mmu/riscv/rv64gc/mmu_init.c | 16 +- 9 files changed, 334 insertions(+), 45 deletions(-) create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/mmio.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/mmio.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/mmio.h new file mode 100644 index 000000000..a3aaf27e5 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/mmio.h @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * {read,write}{b,w,l,q} based on arch/arm64/include/asm/io.h + * which was based on arch/arm/include/io.h + * + * Copyright (C) 1996-2000 Russell King + * Copyright (C) 2012 ARM Ltd. + * Copyright (C) 2014 Regents of the University of California + */ + +#ifndef _ASM_RISCV_MMIO_H +#define _ASM_RISCV_MMIO_H + +//#include +//#include +#include "asm/const.h" +#include + + +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +typedef uint64_t u64; + +typedef uint32_t __le32; + +#ifndef __iomem +#define __iomem +#endif +#ifndef asm +#define asm __asm__ +#endif +#define __force + +#define cpu_to_le32(x) (x) +#define le16_to_cpu(x) (x) +#define le32_to_cpu(x) (x) +#define le64_to_cpu(x) (x) + +/* Generic IO read/write. These perform native-endian accesses. */ +#define __raw_writeb __raw_writeb +static inline void __raw_writeb(u8 val, volatile void __iomem *addr) +{ + asm volatile("sb %0, 0(%1)" : : "r" (val), "r" (addr)); +} + +#define __raw_writew __raw_writew +static inline void __raw_writew(u16 val, volatile void __iomem *addr) +{ + asm volatile("sh %0, 0(%1)" : : "r" (val), "r" (addr)); +} + +#define __raw_writel __raw_writel +static inline void __raw_writel(u32 val, volatile void __iomem *addr) +{ + asm volatile("sw %0, 0(%1)" : : "r" (val), "r" (addr)); +} + +#ifdef CONFIG_64BIT +#define __raw_writeq __raw_writeq +static inline void __raw_writeq(u64 val, volatile void __iomem *addr) +{ + asm volatile("sd %0, 0(%1)" : : "r" (val), "r" (addr)); +} +#endif + +#define __raw_readb __raw_readb +static inline u8 __raw_readb(const volatile void __iomem *addr) +{ + u8 val; + + asm volatile("lb %0, 0(%1)" : "=r" (val) : "r" (addr)); + return val; +} + +#define __raw_readw __raw_readw +static inline u16 __raw_readw(const volatile void __iomem *addr) +{ + u16 val; + + asm volatile("lh %0, 0(%1)" : "=r" (val) : "r" (addr)); + return val; +} + +#define __raw_readl __raw_readl +static inline u32 __raw_readl(const volatile void __iomem *addr) +{ + u32 val; + + asm volatile("lw %0, 0(%1)" : "=r" (val) : "r" (addr)); + return val; +} + +#ifdef CONFIG_64BIT +#define __raw_readq __raw_readq +static inline u64 __raw_readq(const volatile void __iomem *addr) +{ + u64 val; + + asm volatile("ld %0, 0(%1)" : "=r" (val) : "r" (addr)); + return val; +} +#endif + +/* + * Unordered I/O memory access primitives. These are even more relaxed than + * the relaxed versions, as they don't even order accesses between successive + * operations to the I/O regions. + */ +#define readb_cpu(c) ({ u8 __r = __raw_readb(c); __r; }) +#define readw_cpu(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; }) +#define readl_cpu(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) + +#define writeb_cpu(v, c) ((void)__raw_writeb((v), (c))) +#define writew_cpu(v, c) ((void)__raw_writew((__force u16)cpu_to_le16(v), (c))) +#define writel_cpu(v, c) ((void)__raw_writel((__force u32)cpu_to_le32(v), (c))) + +#ifdef CONFIG_64BIT +#define readq_cpu(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; }) +#define writeq_cpu(v, c) ((void)__raw_writeq((__force u64)cpu_to_le64(v), (c))) +#endif + +/* + * Relaxed I/O memory access primitives. These follow the Device memory + * ordering rules but do not guarantee any ordering relative to Normal memory + * accesses. These are defined to order the indicated access (either a read or + * write) with all other I/O memory accesses. Since the platform specification + * defines that all I/O regions are strongly ordered on channel 2, no explicit + * fences are required to enforce this ordering. + */ +/* FIXME: These are now the same as asm-generic */ +#define __io_rbr() do {} while (0) +#define __io_rar() do {} while (0) +#define __io_rbw() do {} while (0) +#define __io_raw() do {} while (0) + +#define readb_relaxed(c) ({ u8 __v; __io_rbr(); __v = readb_cpu(c); __io_rar(); __v; }) +#define readw_relaxed(c) ({ u16 __v; __io_rbr(); __v = readw_cpu(c); __io_rar(); __v; }) +#define readl_relaxed(c) ({ u32 __v; __io_rbr(); __v = readl_cpu(c); __io_rar(); __v; }) + +#define writeb_relaxed(v, c) ({ __io_rbw(); writeb_cpu((v), (c)); __io_raw(); }) +#define writew_relaxed(v, c) ({ __io_rbw(); writew_cpu((v), (c)); __io_raw(); }) +#define writel_relaxed(v, c) ({ __io_rbw(); writel_cpu((v), (c)); __io_raw(); }) + +#ifdef CONFIG_64BIT +#define readq_relaxed(c) ({ u64 __v; __io_rbr(); __v = readq_cpu(c); __io_rar(); __v; }) +#define writeq_relaxed(v, c) ({ __io_rbw(); writeq_cpu((v), (c)); __io_raw(); }) +#endif + +/* + * I/O memory access primitives. Reads are ordered relative to any + * following Normal memory access. Writes are ordered relative to any prior + * Normal memory access. The memory barriers here are necessary as RISC-V + * doesn't define any ordering between the memory space and the I/O space. + */ +#define __io_br() do {} while (0) +#define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory") +#define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory") +//#define __io_aw() mmiowb_set_pending() +#define __io_aw() do {} while (0) + +#define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; }) +#define readw(c) ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; }) +#define readl(c) ({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(__v); __v; }) + +#define writeb(v, c) ({ __io_bw(); writeb_cpu((v), (c)); __io_aw(); }) +#define writew(v, c) ({ __io_bw(); writew_cpu((v), (c)); __io_aw(); }) +#define writel(v, c) ({ __io_bw(); writel_cpu((v), (c)); __io_aw(); }) + +#ifdef CONFIG_64BIT +#define readq(c) ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(__v); __v; }) +#define writeq(v, c) ({ __io_bw(); writeq_cpu((v), (c)); __io_aw(); }) +#endif + +#endif /* _ASM_RISCV_MMIO_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile index aed82542a..8849513ae 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile @@ -1,4 +1,4 @@ -SRC_FILES := entry.S trampoline.S $(BOARD)/trap_common.c $(BOARD)/trap.c error_debug.c hard_spinlock.S +SRC_FILES := entry.S trampoline.S $(BOARD)/trap_common.c $(BOARD)/trap.c $(BOARD)/plic.c error_debug.c hard_spinlock.S ifeq ($(BOARD), jh7110) SRC_DIR := gicv3 diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c new file mode 100644 index 000000000..f30c22c6e --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c @@ -0,0 +1,73 @@ +/* + * This driver implements a version of the RISC-V PLIC with the actual layout + * specified in chapter 8 of the SiFive U5 Coreplex Series Manual: + * + * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf + * + */ +#include "asm/csr.h" +#include "printf.h" +#include "plic.h" +#include "asm/mmio.h" +#include "ptrace.h" + + +extern unsigned long boot_cpu_hartid; + +#define MAX_CPUS 4 +#define MAX_PLIC_IRQS 136 + +#define CPU_TO_HART(cpu) ((2 * cpu) + 2) + + +void plic_set_priority(int hwirq, int pro) +{ + unsigned int reg = PLIC_PRIORITY(hwirq); + writel(pro, reg); +} + +void plic_enable_irq(int cpu, int hwirq, int enable) +{ + unsigned int hwirq_mask = 1 << (hwirq % 32); + int hart = CPU_TO_HART(cpu); + unsigned int reg = PLIC_MENABLE(hart) + 4 * (hwirq / 32); + + if (enable) { + writel(readl(reg) | hwirq_mask, reg); + } + else { + writel(readl(reg) & ~hwirq_mask, reg); + } +} + +//TODO: to debug +int plic_init(void) +{ + int i; + int hwirq; + + printk("plic_init boot_cpu_hartid=%lu\n", boot_cpu_hartid); + + for (i = 0; i < MAX_CPUS; i++) { + writel(0, PLIC_MTHRESHOLD(CPU_TO_HART(i))); + + for (hwirq = 1; hwirq <= MAX_PLIC_IRQS; hwirq++) { + plic_enable_irq(i, hwirq, 0); + plic_set_priority(hwirq, 1); + } + } + csr_set(CSR_IE, IE_EIE); + + return 0; +} + + +void plic_handle_irq(struct pt_regs *regs) +{ + int hwirq; + int hart = CPU_TO_HART(0); + unsigned int claim_reg = PLIC_MCLAIM(hart); + csr_clear(CSR_IE, IE_EIE); + //TODO + csr_set(CSR_IE, IE_EIE); +} diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h new file mode 100644 index 000000000..2b01ec1a0 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h @@ -0,0 +1,20 @@ +#ifndef _RISCV_PLIC_H +#define _RISCV_PLIC_H + +#include "memlayout.h" +#include "ptrace.h" + +#define PLIC_BASE PLIC_PHYMEM_BASE + +#define PLIC_PRIORITY(hwirq) (PLIC_BASE + (hwirq) * 4) +#define PLIC_PENDING(hwirq) (PLIC_BASE + 0x1000 + ((hwirq) / 32) * 4) +#define PLIC_MENABLE(hart) (PLIC_BASE + 0x2000 + (hart) * 0x80) +#define PLIC_MTHRESHOLD(hart) (PLIC_BASE + 0x200000 + (hart) * 0x1000) +#define PLIC_MCLAIM(hart) (PLIC_BASE + 0x200004 + (hart) * 0x1000) + + +int plic_init(void); +void plic_enable_irq(int cpu, int hwirq, int enable); +void plic_handle_irq(struct pt_regs *regs); + +#endif /* _RISCV_PLIC_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c index 5361f8f2a..c13d62a07 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c @@ -40,6 +40,7 @@ Modification: #include "asm/csr.h" #include "ptrace.h" +#include "plic.h" extern void dabort_handler(struct trapframe* r); @@ -126,6 +127,16 @@ void syscall_arch_handler(struct trapframe* tf) +extern void do_exception_vector(void); + +void trap_init(void) +{ + csr_write(stvec, do_exception_vector); + csr_write(sie, 0); +} + + + static void do_trap_error(struct pt_regs *regs, const char *str) { printk("Oops: %s\n", str); @@ -179,26 +190,6 @@ static const struct fault_info fault_inf[] = { }; -/* -void delegate_traps(void) -{ - unsigned long interrupts = MIP_SSIP | MIP_STIP | MIP_SEIP; - - unsigned long exceptions = (1UL << CAUSE_MISALIGNED_FETCH) | - (1UL << CAUSE_FETCH_PAGE_FAULT) | - (1UL << CAUSE_BREAKPOINT) | - (1UL << CAUSE_LOAD_PAGE_FAULT) | - (1UL << CAUSE_STORE_PAGE_FAULT) | - (1UL << CAUSE_USER_ECALL) | - (1UL << CAUSE_LOAD_ACCESS_FAULT) | - (1UL << CAUSE_STORE_ACCESS_FAULT); - - csr_write(mideleg, interrupts); - csr_write(medeleg, exceptions); -} -*/ - - struct fault_info * ec_to_fault_info(unsigned long scause) { struct fault_info *inf; @@ -209,12 +200,22 @@ struct fault_info * ec_to_fault_info(unsigned long scause) inf = &fault_inf[scause]; return inf; } -extern void do_exception_vector(void); -void trap_init(void) + +void handle_irq(struct pt_regs *regs, unsigned long scause) { - csr_write(stvec, do_exception_vector); - //printk("stvec=0x%lx, do_exception_vector=0x%lx\n", csr_read(stvec), (unsigned long)do_exception_vector); - csr_write(sie, 0); + switch (scause & ~CAUSE_IRQ_FLAG) { + case IRQ_S_TIMER: + //handle_timer_irq(); + break; + case IRQ_S_EXT: + plic_handle_irq(regs); + break; + case IRQ_S_SOFT: + // TODO + break; + default: + panic("unexpected interrupt cause\n"); + } } void do_exception(struct pt_regs *regs, unsigned long scause) @@ -224,7 +225,7 @@ void do_exception(struct pt_regs *regs, unsigned long scause) printk("%s, scause: 0x%lx\n", __func__, scause); if (scause & CAUSE_IRQ_FLAG) { - // TODO: 处理中断 + handle_irq(regs, scause); } else { inf = ec_to_fault_info(scause); @@ -233,3 +234,4 @@ void do_exception(struct pt_regs *regs, unsigned long scause) } } } + diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c index 003c64acc..cc869a88a 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c @@ -37,6 +37,8 @@ Modification: #include "log.h" #include "multicores.h" +#include "plic.h" + static struct XiziTrapDriver xizi_trap_driver; void panic(char* s) @@ -46,18 +48,26 @@ void panic(char* s) ; } -extern void alltraps(); +//extern void alltraps(); +extern void trap_init(void); static void _sys_irq_init(int cpu_id) { // primary core init intr - xizi_trap_driver.switch_hw_irqtbl((uintptr_t*)alltraps); - +// xizi_trap_driver.switch_hw_irqtbl((uintptr_t*)alltraps); if (cpu_id == 0) { - gic_init(); + plic_init(); } gicv3inithart(cpu_id); } +static void _sys_trap_init(int cpu_id) +{ + if (cpu_id == 0) { + trap_init(); + } + _sys_irq_init(cpu_id); +} + static void _cpu_irq_enable(void) { intr_on(); @@ -70,12 +80,12 @@ static void _cpu_irq_disable(void) static void _single_irq_enable(int irq, int cpu, int prio) { - gic_setup_ppi((uint32_t)cpu, (uint32_t)irq); + plic_enable_irq(cpu, irq, 1); } static void _single_irq_disable(int irq, int cpu) { - return; + plic_enable_irq(cpu, irq, 0); } static inline uintptr_t* _switch_hw_irqtbl(uintptr_t* new_tbl_base) @@ -113,7 +123,7 @@ int _cur_cpu_id() } static struct XiziTrapDriver xizi_trap_driver = { - .sys_irq_init = _sys_irq_init, + .sys_irq_init = _sys_trap_init, .cur_cpu_id = _cur_cpu_id, .cpu_irq_enable = _cpu_irq_enable, diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/ptrace.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/ptrace.h index 0427b750e..2f8264b0d 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/ptrace.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/ptrace.h @@ -1,16 +1,6 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2012 Regents of the University of California - */ - #ifndef _ASM_RISCV_PTRACE_H #define _ASM_RISCV_PTRACE_H -//#include -//#include -//#include - - struct pt_regs { unsigned long epc; unsigned long ra; diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h index 2e9e32269..d66516710 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h @@ -78,6 +78,11 @@ Modification: #define KERN_MEM_BASE ((0 - 0x0000002000000000ULL) + PHY_MEM_BASE) // First kernel virtual address #define KERN_OFFSET (KERN_MEM_BASE - PHY_MEM_BASE) +/* PLIC (platform-level interrupt controller) memory layout */ +#define PLIC_PHYMEM_BASE (0x0C000000ULL) +#define PLIC_MEM_SIZE (0x00400000ULL) + + #define V2P(a) (((uint64_t)(a)) - KERN_OFFSET) #define P2V(a) ((void *)(((char *)(a)) + KERN_OFFSET)) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c index 0188cc570..88f7f7800 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c @@ -56,6 +56,7 @@ static pmd_t early_pmd[PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE static pmd_t early_uart_pmd[PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE))); static pmd_t early_pmd_free[((PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) >> PGDIR_SHIFT) + 1][PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE))); static pmd_t early_pmd_inear_map[PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE))); +static pmd_t early_plic_pmd[PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE))); static pmd_t *__init get_pmd_virt_early(phys_addr_t pa) @@ -125,7 +126,6 @@ static void __init create_kernel_page_table_early(pgd_t *pgdir, bool early) } } - static void __init create_kernel_pgd_mapping_free_early(pgd_t *pgdp, uintptr_t va, phys_addr_t pa, phys_addr_t sz, pgprot_t prot) @@ -195,6 +195,17 @@ static void __init create_kernel_page_table_linear_map_early(pgd_t *pgdir, bool } } + +static void __init create_plic_page_table_early(pgd_t *pgdir, bool early) +{ + uintptr_t va; + + for (va = PLIC_PHYMEM_BASE; va < PLIC_PHYMEM_BASE + PLIC_MEM_SIZE; va += PMD_SIZE) { + create_pgd_mapping_early(pgdir, va, (uintptr_t)early_plic_pmd, PGDIR_SIZE, PAGE_TABLE); + create_pmd_mapping_early(early_plic_pmd, va, va, PMD_SIZE, PAGE_KERNEL); + } +} + /* * setup_vm_early() is called from boot.S with MMU-off. * @@ -238,5 +249,8 @@ void __init setup_vm_early(void) /* Setup kernel linear map PGD and PMD */ create_kernel_page_table_linear_map_early(early_pg_dir, true); + + /* Setup PLIC PGD and PMD */ + create_plic_page_table_early(early_pg_dir, true); } From 8b08816b606b268a48da217faa53ea2c3bf18df8 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Mon, 16 Dec 2024 10:32:39 +0800 Subject: [PATCH 13/54] Add clint need to debug --- .../hardkernel/clock/riscv/rv64gc/Makefile | 2 +- .../hardkernel/clock/riscv/rv64gc/clock.c | 95 ------------------- .../clock/riscv/rv64gc/jh7110/Makefile | 2 +- .../clock/riscv/rv64gc/jh7110/clint.h | 8 ++ .../clock/riscv/rv64gc/jh7110/clock.c | 4 + .../clock/riscv/rv64gc/jh7110/timer-clint.c | 9 ++ .../intr/riscv/rv64gc/jh7110/plic.c | 1 + 7 files changed, 24 insertions(+), 97 deletions(-) delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/clock.c create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clint.h create mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/timer-clint.c diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/Makefile index c87074a06..aa4fc2f7d 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/Makefile @@ -1,4 +1,4 @@ -SRC_FILES := clock.c +SRC_DIR := $(BOARD) include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/clock.c b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/clock.c deleted file mode 100644 index 39d2995d6..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/clock.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -#include "actracer.h" -#include "core.h" -#include "generic_timer.h" - -#include "clock_common_op.h" - -// armv8 generic timer driver -#define CNTV_CTL_ENABLE (1 << 0) -#define CNTV_CTL_IMASK (1 << 1) -#define CNTV_CTL_ISTATUS (1 << 2) - -static void enable_timer() -{ - uint32_t c = r_cntp_ctl_el0(); - c |= CNTV_CTL_ENABLE; - c &= ~CNTV_CTL_IMASK; - w_cntp_ctl_el0(c); -} - -static void disable_timer() -{ - uint32_t c = r_cntp_ctl_el0(); - c |= CNTV_CTL_IMASK; - c &= ~CNTV_CTL_ENABLE; - w_cntp_ctl_el0(c); -} - -static void reload_timer() -{ - // interval 1ms - static uint32_t ms = 1; - uint32_t interval = ms * 1000; - uint32_t interval_clk = interval * (r_cntfrq_el0() / 1000000); - w_cntp_tval_el0(interval_clk); -} - -void _sys_clock_init() -{ - disable_timer(); - reload_timer(); - enable_timer(); -} - -static uint32_t _get_clock_int() -{ - return 30; -} - -static uint64_t _get_tick() -{ - return r_cntvct_el0(); -} - -static uint64_t _get_second() -{ - return _get_tick() / r_cntfrq_el0(); -} - -static bool _is_timer_expired() -{ - return true; -} - -static void _clear_clock_intr() -{ - disable_timer(); - reload_timer(); - enable_timer(); -} - -static struct XiziClockDriver hardkernel_clock_driver = { - .sys_clock_init = _sys_clock_init, - .get_clock_int = _get_clock_int, - .get_tick = _get_tick, - .get_second = _get_second, - .is_timer_expired = _is_timer_expired, - .clear_clock_intr = _clear_clock_intr, -}; - -struct XiziClockDriver* hardkernel_clock_init(struct TraceTag* hardkernel_tag) -{ - hardkernel_clock_driver.sys_clock_init(); - return &hardkernel_clock_driver; -} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/Makefile index c87074a06..fc344cc8e 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/Makefile @@ -1,4 +1,4 @@ -SRC_FILES := clock.c +SRC_FILES := clock.c timer-clint.c include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clint.h b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clint.h new file mode 100644 index 000000000..4c1dd3686 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clint.h @@ -0,0 +1,8 @@ +#ifndef _ASM_RISCV_CLINT_H +#define _ASM_RISCV_CLINT_H + +#include + +int clint_timer_init(void); + +#endif diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clock.c b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clock.c index 39d2995d6..40929ffa2 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clock.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clock.c @@ -14,6 +14,8 @@ #include "generic_timer.h" #include "clock_common_op.h" +#include "clint.h" + // armv8 generic timer driver #define CNTV_CTL_ENABLE (1 << 0) @@ -45,8 +47,10 @@ static void reload_timer() w_cntp_tval_el0(interval_clk); } + void _sys_clock_init() { + clint_timer_init(); disable_timer(); reload_timer(); enable_timer(); diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/timer-clint.c b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/timer-clint.c new file mode 100644 index 000000000..13fde4a86 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/timer-clint.c @@ -0,0 +1,9 @@ +#include "clint.h" + + +// Refer to linux/drivers/clocksource/timer-clint.c +// TODO: +int clint_timer_init(void) +{ + return 0; +} diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c index f30c22c6e..b003384db 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c @@ -41,6 +41,7 @@ void plic_enable_irq(int cpu, int hwirq, int enable) } //TODO: to debug +//Refer to linux/drivers/irqchip/irq-sifive-plic.c int plic_init(void) { int i; From ffd226230096f77e0ce13b5c0d3994abff2050d0 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 19 Dec 2024 20:05:14 +0800 Subject: [PATCH 14/54] kernel runs in virtual memory --- .../rv64gc/preboot_for_jh7110/jh7110.lds | 13 +- .../mmu/riscv/rv64gc/jh7110/memlayout.h | 11 +- .../hardkernel/mmu/riscv/rv64gc/mmu_init.c | 151 ++++++------------ 3 files changed, 68 insertions(+), 107 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds index 2f3ee3073..f3630b83c 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds @@ -42,17 +42,16 @@ OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv") /* ENTRY(_start) */ ENTRY( _boot_start ) - MEMORY { + vir_ddr3 (rwx) : ORIGIN = (0 - 0x80000000), LENGTH = 1024M phy_ddr3 (rwx) : ORIGIN = 0x40200000, LENGTH = 1024M - vir_ddr3 (rwx) : ORIGIN = 0x0000000040800000, LENGTH = 1024M } BOOT_STACK_SIZE = 0x4000; SECTIONS { - . = ORIGIN(phy_ddr3); + . = ORIGIN(vir_ddr3); _start = .; _boot_start = .; @@ -60,22 +59,22 @@ SECTIONS _start_image_addr = .; boot.o(.text) - bootmmu.o(.text .text.*) ns16550.o(.text .text.*) + mmu_init.o(.text .text.*) boot.o(.rodata .rodata.*) - bootmmu.o(.rodata .rodata.*) ns16550.o(.rodata .rodata.*) + mmu_init.o(.rodata .rodata.*) boot.o(.data .data.*) - bootmmu.o(.data .data.*) ns16550.o(.data .data.*) + mmu_init.o(.data .data.*) PROVIDE(boot_start_addr = .); boot.o(.bss .bss.* COMMON) - bootmmu.o(.bss .bss.* COMMON) ns16550.o(.bss .bss.* COMMON) + mmu_init.o(.bss .bss.* COMMON) . = ALIGN(0x1000); PROVIDE(stacks_start = .); diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h index d66516710..ebc4832ac 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/jh7110/memlayout.h @@ -35,7 +35,7 @@ Modification: /* physical memory layout */ #define PHY_MEM_BASE (0x0000000040200000ULL) -#define PHY_USER_FREEMEM_BASE (0x0000000100000000ULL) +#define PHY_USER_FREEMEM_BASE (0x0000000080000000ULL) #define PHY_USER_FREEMEM_TOP (0x0000000200000000ULL) #define PHY_MEM_STOP (0x0000000200000000ULL) @@ -78,9 +78,14 @@ Modification: #define KERN_MEM_BASE ((0 - 0x0000002000000000ULL) + PHY_MEM_BASE) // First kernel virtual address #define KERN_OFFSET (KERN_MEM_BASE - PHY_MEM_BASE) +/* Leave 2GB for kernel and BPF at the end of the address space */ +#define KERNEL_LINK_ADDR (0 - 0x80000000ULL) +#define KERNEL_LINK_OFFSET (KERNEL_LINK_ADDR - PHY_MEM_BASE) + /* PLIC (platform-level interrupt controller) memory layout */ #define PLIC_PHYMEM_BASE (0x0C000000ULL) #define PLIC_MEM_SIZE (0x00400000ULL) +#define PLIC_VIRTMEM_BASE ((0 - 0x0000003000000000ULL) + PLIC_PHYMEM_BASE) #define V2P(a) (((uint64_t)(a)) - KERN_OFFSET) @@ -88,4 +93,6 @@ Modification: #define V2P_WO(x) ((x) - KERN_OFFSET) // same as V2P, but without casts #define P2V_WO(x) ((x) + KERN_OFFSET) // same as P2V, but without casts -// clang-format on \ No newline at end of file + +#define V2P_LINK(a) (((uint64_t)(a)) - KERNEL_LINK_OFFSET) +#define P2V_LINK(a) ((a) + KERNEL_LINK_OFFSET) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c index 88f7f7800..1224eb13a 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c @@ -33,87 +33,81 @@ Modification: #include "pgtable.h" #include "memlayout.h" #include "ns16550.h" +#include "asm/pgtable-bits.h" +#define PFN_PD(x, prot) (((x) << _PAGE_PFN_SHIFT) | (prot)) +#define _PD_PFN(x) ((x) >> _PAGE_PFN_SHIFT) -#define __ro_after_init __attribute__((section(".data..ro_after_init"))) -#define __page_aligned_data __attribute__((section(".data..page_aligned"))) __attribute__((aligned(PAGE_SIZE))) -#define __page_aligned_bss __attribute__((section(".bss..page_aligned"))) __attribute__((aligned(PAGE_SIZE))) -#define __initdata __attribute__((section(".init.data"))) -#define __init __attribute__((section(".init.text"))) -#define __maybe_unused __attribute__((__unused__)) - - -struct kernel_mapping kernel_map __ro_after_init; extern char _start[]; -unsigned long riscv_pfn_base __ro_after_init; +struct kernel_mapping kernel_map; -pgd_t trampoline_pg_dir[PTRS_PER_PGD] __page_aligned_bss; -pgd_t early_pg_dir[PTRS_PER_PGD] __initdata __attribute__((aligned(PAGE_SIZE))); +uintptr_t trampoline_pg_dir[PTRS_PER_PGD] __attribute__((aligned(PAGE_SIZE))); +uintptr_t early_pg_dir[PTRS_PER_PGD] __attribute__((aligned(PAGE_SIZE))); -static pmd_t trampoline_pmd[PTRS_PER_PMD] __page_aligned_bss; -static pmd_t early_pmd[PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE))); -static pmd_t early_uart_pmd[PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE))); -static pmd_t early_pmd_free[((PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) >> PGDIR_SHIFT) + 1][PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE))); -static pmd_t early_pmd_inear_map[PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE))); -static pmd_t early_plic_pmd[PTRS_PER_PMD] __initdata __attribute__((aligned(PAGE_SIZE))); +static uintptr_t trampoline_pmd[PTRS_PER_PMD] __attribute__((aligned(PAGE_SIZE))); +static uintptr_t early_pmd[PTRS_PER_PMD] __attribute__((aligned(PAGE_SIZE))); +static uintptr_t early_uart_pmd[PTRS_PER_PMD] __attribute__((aligned(PAGE_SIZE))); +static uintptr_t early_pmd_free[((PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) >> PGDIR_SHIFT) + 1][PTRS_PER_PMD] __attribute__((aligned(PAGE_SIZE))); +static uintptr_t early_pmd_inear_map[PTRS_PER_PMD] __attribute__((aligned(PAGE_SIZE))); +static uintptr_t early_plic_pmd[PTRS_PER_PMD] __attribute__((aligned(PAGE_SIZE))); -static pmd_t *__init get_pmd_virt_early(phys_addr_t pa) + +static uintptr_t *get_pmd_virt_early(phys_addr_t pa) { /* Before MMU is enabled */ - return (pmd_t *)((uintptr_t)pa); + return (uintptr_t *)((uintptr_t)pa); } -static phys_addr_t __init alloc_pmd_early(uintptr_t va) +static phys_addr_t alloc_pmd_early(uintptr_t va) { return (uintptr_t)early_pmd; } -static void __init create_pmd_mapping_early(pmd_t *pmdp, +static void create_pmd_mapping_early(uintptr_t *pmdp, uintptr_t va, phys_addr_t pa, - phys_addr_t sz, pgprot_t prot) + phys_addr_t sz, uintptr_t prot) { uintptr_t pmd_idx = pmd_index(va); if (sz == PMD_SIZE) { - if (pmd_none(pmdp[pmd_idx])) - pmdp[pmd_idx] = pfn_pmd(PFN_DOWN(pa), prot); - + if ((pmdp[pmd_idx]) == 0) + pmdp[pmd_idx] = (PFN_PD(PFN_DOWN(pa), prot)); return; } } -static void __init create_pgd_mapping_early(pgd_t *pgdp, +static void create_pgd_mapping_early(uintptr_t *pgdp, uintptr_t va, phys_addr_t pa, - phys_addr_t sz, pgprot_t prot) + phys_addr_t sz, uintptr_t prot) { - pmd_t *nextp; + uintptr_t *nextp; phys_addr_t next_phys; uintptr_t pgd_idx = pgd_index(va); if (sz == PGDIR_SIZE) { - if (pgd_val(pgdp[pgd_idx]) == 0) - pgdp[pgd_idx] = pfn_pgd(PFN_DOWN(pa), prot); + if ((pgdp[pgd_idx]) == 0) + pgdp[pgd_idx] = (PFN_PD(PFN_DOWN(pa), prot)); return; } - if (pgd_val(pgdp[pgd_idx]) == 0) { + if ((pgdp[pgd_idx]) == 0) { next_phys = alloc_pmd_early(va); - pgdp[pgd_idx] = pfn_pgd(PFN_DOWN(next_phys), PAGE_TABLE); + pgdp[pgd_idx] = (PFN_PD(PFN_DOWN(next_phys), _PAGE_TABLE)); nextp = get_pmd_virt_early(next_phys); memset(nextp, 0, PAGE_SIZE); } else { - next_phys = PFN_PHYS(_pgd_pfn(pgdp[pgd_idx])); + next_phys = PFN_PHYS(_PD_PFN((pgdp[pgd_idx]))); nextp = get_pmd_virt_early(next_phys); } create_pmd_mapping_early(nextp, va, pa, sz, prot); } -static void __init create_kernel_page_table_early(pgd_t *pgdir, bool early) +static void create_kernel_page_table_early(uintptr_t *pgdir, bool early) { uintptr_t va, end_va; @@ -122,87 +116,54 @@ static void __init create_kernel_page_table_early(pgd_t *pgdir, bool early) create_pgd_mapping_early(pgdir, va, kernel_map.phys_addr + (va - kernel_map.virt_addr), PMD_SIZE, - PAGE_KERNEL_EXEC); + (_PAGE_KERNEL | _PAGE_EXEC)); } } -static void __init create_kernel_pgd_mapping_free_early(pgd_t *pgdp, +static void create_kernel_pgd_mapping_free_early(uintptr_t *pgdp, uintptr_t va, phys_addr_t pa, - phys_addr_t sz, pgprot_t prot) + phys_addr_t sz, uintptr_t prot) { - pmd_t *nextp; + uintptr_t *nextp; phys_addr_t next_phys; uintptr_t pgd_idx = pgd_index(va); uintptr_t start_pgd_idx = pgd_index(kernel_map.virt_addr); - if (pgd_val(pgdp[pgd_idx]) == 0) { + if ((pgdp[pgd_idx]) == 0) { next_phys = (uintptr_t)early_pmd_free[pgd_idx - start_pgd_idx]; - pgdp[pgd_idx] = pfn_pgd(PFN_DOWN(next_phys), PAGE_TABLE); + pgdp[pgd_idx] = (PFN_PD(PFN_DOWN(next_phys), _PAGE_TABLE)); nextp = get_pmd_virt_early(next_phys); memset(nextp, 0, PAGE_SIZE); } else { - next_phys = PFN_PHYS(_pgd_pfn(pgdp[pgd_idx])); + next_phys = PFN_PHYS(_PD_PFN((pgdp[pgd_idx]))); nextp = get_pmd_virt_early(next_phys); } create_pmd_mapping_early(nextp, va, pa, sz, prot); } -static void __init create_kernel_page_table_free_early(pgd_t *pgdir, bool early) +static void create_kernel_page_table_free_early(uintptr_t *pgdir, bool early) { uintptr_t va, end_va; - end_va = kernel_map.virt_addr + (PHY_USER_FREEMEM_BASE - kernel_map.phys_addr); - for (va = kernel_map.virt_addr + kernel_map.size; va < end_va; va += PMD_SIZE) { + end_va = KERN_MEM_BASE + (PHY_USER_FREEMEM_BASE - PHY_MEM_BASE); + for (va = KERN_MEM_BASE + kernel_map.size; va < end_va; va += PMD_SIZE) { create_kernel_pgd_mapping_free_early(pgdir, va, - kernel_map.phys_addr + (va - kernel_map.virt_addr), + kernel_map.phys_addr + (va - KERN_MEM_BASE), PMD_SIZE, - PAGE_KERNEL_EXEC); + _PAGE_KERNEL); } } -static void __init create_kernel_pgd_mapping_linear_map_early(pgd_t *pgdp, - uintptr_t va, phys_addr_t pa, - phys_addr_t sz, pgprot_t prot) -{ - pmd_t *nextp; - phys_addr_t next_phys; - uintptr_t pgd_idx = pgd_index(va); - - if (pgd_val(pgdp[pgd_idx]) == 0) { - next_phys = (uintptr_t)early_pmd_inear_map; - pgdp[pgd_idx] = pfn_pgd(PFN_DOWN(next_phys), PAGE_TABLE); - nextp = get_pmd_virt_early(next_phys); - memset(nextp, 0, PAGE_SIZE); - } else { - next_phys = PFN_PHYS(_pgd_pfn(pgdp[pgd_idx])); - nextp = get_pmd_virt_early(next_phys); - } - - create_pmd_mapping_early(nextp, va, pa, sz, prot); -} - -static void __init create_kernel_page_table_linear_map_early(pgd_t *pgdir, bool early) -{ - uintptr_t va, end_va; - - end_va = kernel_map.phys_addr + kernel_map.size; - for (va = kernel_map.phys_addr; va < end_va; va += PMD_SIZE) { - create_kernel_pgd_mapping_linear_map_early(pgdir, va, - kernel_map.phys_addr + (va - kernel_map.phys_addr), - PMD_SIZE, - PAGE_KERNEL_EXEC); - } -} - - -static void __init create_plic_page_table_early(pgd_t *pgdir, bool early) +static void create_plic_page_table_early(uintptr_t *pgdir, bool early) { uintptr_t va; + uintptr_t pa; - for (va = PLIC_PHYMEM_BASE; va < PLIC_PHYMEM_BASE + PLIC_MEM_SIZE; va += PMD_SIZE) { - create_pgd_mapping_early(pgdir, va, (uintptr_t)early_plic_pmd, PGDIR_SIZE, PAGE_TABLE); - create_pmd_mapping_early(early_plic_pmd, va, va, PMD_SIZE, PAGE_KERNEL); + for (va = PLIC_VIRTMEM_BASE; va < PLIC_VIRTMEM_BASE + PLIC_MEM_SIZE; va += PMD_SIZE) { + pa = va - PLIC_VIRTMEM_BASE + PLIC_PHYMEM_BASE; + create_pgd_mapping_early(pgdir, va, (uintptr_t)early_plic_pmd, PGDIR_SIZE, _PAGE_TABLE); + create_pmd_mapping_early(early_plic_pmd, va, pa, PMD_SIZE, _PAGE_KERNEL); } } @@ -217,9 +178,9 @@ static void __init create_plic_page_table_early(pgd_t *pgdir, bool early) * so disable compiler instrumentation when FTRACE is enabled. */ -void __init setup_vm_early(void) +void setup_vm_early(void) { - kernel_map.virt_addr = KERN_MEM_BASE; + kernel_map.virt_addr = KERNEL_LINK_ADDR; kernel_map.phys_addr = (uintptr_t)(&_start); kernel_map.size = (uintptr_t)(&_end) - kernel_map.phys_addr; @@ -227,11 +188,9 @@ void __init setup_vm_early(void) kernel_map.va_pa_offset = PAGE_OFFSET - kernel_map.phys_addr; kernel_map.va_kernel_pa_offset = kernel_map.virt_addr - kernel_map.phys_addr; - riscv_pfn_base = PFN_DOWN(kernel_map.phys_addr); - /* Setup trampoline PGD and PMD */ - create_pgd_mapping_early(trampoline_pg_dir, kernel_map.virt_addr, (uintptr_t)trampoline_pmd, PGDIR_SIZE, PAGE_TABLE); - create_pmd_mapping_early(trampoline_pmd, kernel_map.virt_addr, kernel_map.phys_addr, PMD_SIZE, PAGE_KERNEL_EXEC); + create_pgd_mapping_early(trampoline_pg_dir, kernel_map.virt_addr, (uintptr_t)trampoline_pmd, PGDIR_SIZE, _PAGE_TABLE); + create_pmd_mapping_early(trampoline_pmd, kernel_map.virt_addr, kernel_map.phys_addr, PMD_SIZE, (_PAGE_KERNEL | _PAGE_EXEC)); /* * Setup early PGD covering entire kernel which will allow @@ -241,16 +200,12 @@ void __init setup_vm_early(void) create_kernel_page_table_early(early_pg_dir, true); /* Setup uart PGD and PMD */ - create_pgd_mapping_early(early_pg_dir, DEV_VRTMEM_BASE, (uintptr_t)early_uart_pmd, PGDIR_SIZE, PAGE_TABLE); - create_pmd_mapping_early(early_uart_pmd, DEV_VRTMEM_BASE, DEV_PHYMEM_BASE, PMD_SIZE, PAGE_KERNEL); + create_pgd_mapping_early(early_pg_dir, DEV_VRTMEM_BASE, (uintptr_t)early_uart_pmd, PGDIR_SIZE, _PAGE_TABLE); + create_pmd_mapping_early(early_uart_pmd, DEV_VRTMEM_BASE, DEV_PHYMEM_BASE, PMD_SIZE, _PAGE_KERNEL); /* Setup kernel free PGD and PMD */ create_kernel_page_table_free_early(early_pg_dir, true); - /* Setup kernel linear map PGD and PMD */ - create_kernel_page_table_linear_map_early(early_pg_dir, true); - /* Setup PLIC PGD and PMD */ create_plic_page_table_early(early_pg_dir, true); } - From 06bb9c4e9b0457014db80867ab1d35d406f13a08 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 19 Dec 2024 20:07:38 +0800 Subject: [PATCH 15/54] Modify plic --- .../XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c | 7 +++++-- .../XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h | 2 +- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c index b003384db..af02658f7 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c @@ -32,12 +32,15 @@ void plic_enable_irq(int cpu, int hwirq, int enable) int hart = CPU_TO_HART(cpu); unsigned int reg = PLIC_MENABLE(hart) + 4 * (hwirq / 32); + printk("plic_enable_irq hwirq=%d\n", hwirq); +#if 0 if (enable) { writel(readl(reg) | hwirq_mask, reg); } else { writel(readl(reg) & ~hwirq_mask, reg); } +#endif } //TODO: to debug @@ -48,7 +51,7 @@ int plic_init(void) int hwirq; printk("plic_init boot_cpu_hartid=%lu\n", boot_cpu_hartid); - +#if 0 for (i = 0; i < MAX_CPUS; i++) { writel(0, PLIC_MTHRESHOLD(CPU_TO_HART(i))); @@ -58,7 +61,7 @@ int plic_init(void) } } csr_set(CSR_IE, IE_EIE); - +#endif return 0; } diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h index 2b01ec1a0..4ac98fc32 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h @@ -4,7 +4,7 @@ #include "memlayout.h" #include "ptrace.h" -#define PLIC_BASE PLIC_PHYMEM_BASE +#define PLIC_BASE PLIC_VIRTMEM_BASE #define PLIC_PRIORITY(hwirq) (PLIC_BASE + (hwirq) * 4) #define PLIC_PENDING(hwirq) (PLIC_BASE + 0x1000 + ((hwirq) / 32) * 4) From 2087cb7d33b1291a16fab386ab3d6895017c2b2c Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 19 Dec 2024 20:40:29 +0800 Subject: [PATCH 16/54] buddy fits more than 4GB of memory. --- Ubiquitous/XiZi_AIoT/softkernel/include/buddy.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/softkernel/include/buddy.h b/Ubiquitous/XiZi_AIoT/softkernel/include/buddy.h index 4b73e7cd4..f29533e7c 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/include/buddy.h +++ b/Ubiquitous/XiZi_AIoT/softkernel/include/buddy.h @@ -36,7 +36,7 @@ Modification: #include #include -#define MAX_BUDDY_ORDER (14) +#define MAX_BUDDY_ORDER (15) #define FREE_LIST_INDEX(order) \ (1 << order) From 64ba03adef4671ee3622bbafed485b8eb43b925c Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 19 Dec 2024 20:50:29 +0800 Subject: [PATCH 17/54] Modify kalloc for RISCV only supports -2GB to 2GB in link script file --- Ubiquitous/XiZi_AIoT/softkernel/memory/kalloc.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/kalloc.c b/Ubiquitous/XiZi_AIoT/softkernel/memory/kalloc.c index 4bed55c1d..28fef6c67 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/memory/kalloc.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/kalloc.c @@ -33,13 +33,17 @@ Modification: #include "actracer.h" #include "buddy.h" +#ifndef V2P_LINK +#define V2P_LINK V2P +#endif + struct KBuddy kern_virtmem_buddy; struct KBuddy user_phy_freemem_buddy; extern uintptr_t kernel_data_end[]; bool module_phymem_init() { - uintptr_t kern_freemem_start = V2P(kernel_data_end); + uintptr_t kern_freemem_start = V2P_LINK(kernel_data_end); uintptr_t kern_freemem_end = PHY_USER_FREEMEM_BASE; uintptr_t user_freemem_start = PHY_USER_FREEMEM_BASE; uintptr_t user_freemem_end = PHY_MEM_STOP; @@ -55,7 +59,7 @@ char* kalloc(uintptr_t size) if (mem_alloc == NULL) { return NULL; } - assert((uintptr_t)mem_alloc >= V2P(&kernel_data_end) && (uintptr_t)mem_alloc < PHY_USER_FREEMEM_BASE); + assert((uintptr_t)mem_alloc >= V2P_LINK(&kernel_data_end) && (uintptr_t)mem_alloc < PHY_USER_FREEMEM_BASE); mem_alloc = P2V(mem_alloc); if ((uintptr_t)mem_alloc < KERN_MEM_BASE) { DEBUG("Error Alloc: %x by size: %d (Caused by double free)\n", mem_alloc, size); From 8f0c6bbd5c5294cb41e44223aa18b75b4dafe9c2 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 19 Dec 2024 20:59:36 +0800 Subject: [PATCH 18/54] build services --- Ubiquitous/XiZi_AIoT/Makefile | 3 +-- Ubiquitous/XiZi_AIoT/services/Makefile | 6 ++++-- Ubiquitous/XiZi_AIoT/services/app/Makefile | 10 ++++++++++ Ubiquitous/XiZi_AIoT/services/fs/fs_server/Makefile | 5 +++++ Ubiquitous/XiZi_AIoT/services/fs/libfs/Makefile | 5 +++++ Ubiquitous/XiZi_AIoT/services/lib/ipc/Makefile | 5 +++++ Ubiquitous/XiZi_AIoT/services/lib/memory/Makefile | 5 +++++ Ubiquitous/XiZi_AIoT/services/lib/serial/Makefile | 5 +++++ Ubiquitous/XiZi_AIoT/services/lib/usyscall/Makefile | 5 +++++ .../XiZi_AIoT/services/shell/letter-shell/Makefile | 5 +++++ Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile | 2 +- 11 files changed, 51 insertions(+), 5 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/Makefile b/Ubiquitous/XiZi_AIoT/Makefile index c78e94350..0f58c8fda 100755 --- a/Ubiquitous/XiZi_AIoT/Makefile +++ b/Ubiquitous/XiZi_AIoT/Makefile @@ -46,8 +46,7 @@ export CONFIG2H_EXE ?= $(HOSTTOOLS_DIR)/xsconfig.sh export CPPPATHS export SRC_APP_DIR := ../../APP_Framework -# export SRC_KERNEL_DIR := hardkernel kernel_actracer services softkernel -export SRC_KERNEL_DIR := hardkernel kernel_actracer softkernel +export SRC_KERNEL_DIR := hardkernel kernel_actracer services softkernel export SRC_DIR := $(SRC_KERNEL_DIR) export LIBCC diff --git a/Ubiquitous/XiZi_AIoT/services/Makefile b/Ubiquitous/XiZi_AIoT/services/Makefile index b3a5f2c41..873b26eef 100644 --- a/Ubiquitous/XiZi_AIoT/services/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/Makefile @@ -1,5 +1,7 @@ - +ifeq ($(BOARD), jh7110) +SRC_DIR := fs shell lib boards tools app +else SRC_DIR := fs shell lib boards drivers semaphore drivers tools net app - +endif include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/services/app/Makefile b/Ubiquitous/XiZi_AIoT/services/app/Makefile index 2b5808fe6..164a76a2e 100644 --- a/Ubiquitous/XiZi_AIoT/services/app/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/app/Makefile @@ -16,6 +16,12 @@ user_ldflags = -N -Ttext 0 cflags = -Wall -O2 -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie board_specs = stub.o endif +ifeq ($(BOARD), jh7110) +toolchain ?= riscv64-unknown-elf- +user_ldflags = -N -Ttext 0 +cflags = -Wall -O2 -std=c11 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +board_specs = stub.o +endif cc = ${toolchain}gcc ld = ${toolchain}g++ @@ -45,7 +51,11 @@ INC_DIR = -I$(KERNEL_ROOT)/services/shell/letter-shell \ ifeq ($(BOARD), imx6q-sabrelite) all: test_fault simple_client simple_server shell fs_server semaphore_server test_semaphore test_ipc_null test_thread test_irq_hdlr test_irq_block test_irq_send eth_driver epit_server test_net lwip readme.txt | bin else +ifeq ($(BOARD), jh7110) +all: shell fs_server | bin +else all: test_fault simple_client simple_server shell fs_server semaphore_server test_ipc_null test_thread test_semaphore test_net lwip readme.txt eth_hal | bin +endif endif ../tools/mkfs/mkfs ./fs.img $^ @mv $(filter-out readme.txt, $^) bin diff --git a/Ubiquitous/XiZi_AIoT/services/fs/fs_server/Makefile b/Ubiquitous/XiZi_AIoT/services/fs/fs_server/Makefile index 9267ae0a5..be3c9e7c4 100644 --- a/Ubiquitous/XiZi_AIoT/services/fs/fs_server/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/fs/fs_server/Makefile @@ -14,6 +14,11 @@ toolchain ?= aarch64-none-elf- user_ldflags = -N -Ttext 0 cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif +ifeq ($(BOARD), jh7110) +toolchain ?= riscv64-unknown-elf- +user_ldflags = -N -Ttext 0 +cflags = -Wall -O0 -g -std=c11 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +endif cc = ${toolchain}gcc ld = ${toolchain}g++ diff --git a/Ubiquitous/XiZi_AIoT/services/fs/libfs/Makefile b/Ubiquitous/XiZi_AIoT/services/fs/libfs/Makefile index dbbeb93e9..64814b1cd 100644 --- a/Ubiquitous/XiZi_AIoT/services/fs/libfs/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/fs/libfs/Makefile @@ -13,6 +13,11 @@ toolchain ?= aarch64-none-elf- user_ldflags = -N cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif +ifeq ($(BOARD), jh7110) +toolchain ?= riscv64-unknown-elf- +user_ldflags = -N +cflags = -Wall -O0 -g -std=c11 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +endif cc = ${toolchain}gcc ld = ${toolchain}g++ diff --git a/Ubiquitous/XiZi_AIoT/services/lib/ipc/Makefile b/Ubiquitous/XiZi_AIoT/services/lib/ipc/Makefile index f8e1072cd..9d6c02a55 100644 --- a/Ubiquitous/XiZi_AIoT/services/lib/ipc/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/lib/ipc/Makefile @@ -14,6 +14,11 @@ toolchain ?= aarch64-none-elf- user_ldflags = -N -Ttext 0 cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif +ifeq ($(BOARD), jh7110) +toolchain ?= riscv64-unknown-elf- +user_ldflags = -N -Ttext 0 +cflags = -Wall -O0 -g -std=c11 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +endif cc = ${toolchain}gcc ld = ${toolchain}g++ diff --git a/Ubiquitous/XiZi_AIoT/services/lib/memory/Makefile b/Ubiquitous/XiZi_AIoT/services/lib/memory/Makefile index a9516161f..6bfef9888 100644 --- a/Ubiquitous/XiZi_AIoT/services/lib/memory/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/lib/memory/Makefile @@ -13,6 +13,11 @@ toolchain ?= aarch64-none-elf- user_ldflags = -N -Ttext 0 cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif +ifeq ($(BOARD), jh7110) +toolchain ?= riscv64-unknown-elf- +user_ldflags = -N -Ttext 0 +cflags = -Wall -O0 -g -std=c11 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +endif cc = ${toolchain}gcc ld = ${toolchain}g++ diff --git a/Ubiquitous/XiZi_AIoT/services/lib/serial/Makefile b/Ubiquitous/XiZi_AIoT/services/lib/serial/Makefile index ac290a6eb..b11994f45 100644 --- a/Ubiquitous/XiZi_AIoT/services/lib/serial/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/lib/serial/Makefile @@ -13,6 +13,11 @@ toolchain ?= aarch64-none-elf- user_ldflags = -N -Ttext 0 cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif +ifeq ($(BOARD), jh7110) +toolchain ?= riscv64-unknown-elf- +user_ldflags = -N -Ttext 0 +cflags = -Wall -O0 -g -std=c11 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +endif cc = ${toolchain}gcc ld = ${toolchain}g++ diff --git a/Ubiquitous/XiZi_AIoT/services/lib/usyscall/Makefile b/Ubiquitous/XiZi_AIoT/services/lib/usyscall/Makefile index 9cedf87e8..6f13b4713 100644 --- a/Ubiquitous/XiZi_AIoT/services/lib/usyscall/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/lib/usyscall/Makefile @@ -13,6 +13,11 @@ toolchain ?= aarch64-none-elf- user_ldflags = -N -Ttext 0 cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif +ifeq ($(BOARD), jh7110) +toolchain ?= riscv64-unknown-elf- +user_ldflags = -N -Ttext 0 +cflags = -Wall -O0 -g -std=c11 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +endif cc = ${toolchain}gcc ld = ${toolchain}g++ diff --git a/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/Makefile b/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/Makefile index 4c22e10af..3910ec988 100644 --- a/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/Makefile @@ -13,6 +13,11 @@ toolchain ?= aarch64-none-elf- user_ldflags = -N -Ttext 0 cflags = -Wall -O0 -g -std=c11 -mtune=cortex-a55 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie endif +ifeq ($(BOARD), jh7110) +toolchain ?= riscv64-unknown-elf- +user_ldflags = -N -Ttext 0 +cflags = -Wall -O0 -g -std=c11 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +endif cc = ${toolchain}gcc ld = ${toolchain}g++ diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile b/Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile index 35bd24a90..f31e00964 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile +++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/Makefile @@ -9,7 +9,7 @@ ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), ) SRC_FILES:= kalloc.c pagetable.c pagetable_level2.c buddy.c object_allocator.c share_page.c endif ifneq ($(findstring $(BOARD), jh7110), ) -SRC_FILES := kalloc.c pagetable.c pagetable_level3.c buddy.c object_allocator.c share_page.c +SRC_FILES := kalloc.c pagetable_riscv.c pagetable_riscv_level3.c buddy.c object_allocator.c share_page.c endif From 9a6857843bfee19d5159d1cc6d235df4468ebab5 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 19 Dec 2024 21:06:31 +0800 Subject: [PATCH 19/54] load fs.img shell fs_server --- Ubiquitous/XiZi_AIoT/softkernel/load_apps.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/softkernel/load_apps.S b/Ubiquitous/XiZi_AIoT/softkernel/load_apps.S index a12911287..597d60af0 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/load_apps.S +++ b/Ubiquitous/XiZi_AIoT/softkernel/load_apps.S @@ -30,16 +30,16 @@ Modification: .section .rawdata_fs_img .globl user_apps user_apps: -// .incbin "../services/app/fs.img" + .incbin "../services/app/fs.img" .section .rawdata_init .globl initapp initapp: -// .incbin "../services/app/bin/shell" + .incbin "../services/app/bin/shell" .section .rawdata_memfs .globl memfs memfs: -// .incbin "../services/app/bin/fs_server" + .incbin "../services/app/bin/fs_server" .end From a2ed0ee073b48c38dd7e31d91257fe8266ac3870 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 19 Dec 2024 21:10:55 +0800 Subject: [PATCH 20/54] Add pagetable_riscv_level3.c --- .../softkernel/memory/pagetable_riscv.c | 278 ++++++++++++++++++ .../memory/pagetable_riscv_level3.c | 103 +++++++ 2 files changed, 381 insertions(+) create mode 100644 Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c create mode 100644 Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv_level3.c diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c new file mode 100644 index 000000000..53404786f --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file pagetable.c + * @brief build page table + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.08.25 + */ + +/************************************************* +File name: pagetable.c +Description: build page table +Others: +History: +1. Date: 2023-08-28 +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include "memlayout.h" + +#include "trap_common.h" + +#include "assert.h" +#include "buddy.h" +#include "kalloc.h" +#include "pagetable.h" + +static struct PagerRightGroup right_group; +struct MmuCommonDone* _p_pgtbl_mmu_access = NULL; +static bool _new_pgdir(struct TopLevelPageDirectory* pgdir) +{ + void* new_pgdir_addr = 0; + if (UNLIKELY((new_pgdir_addr = kalloc(TOPLEVLE_PAGEDIR_SIZE)) == NULL)) { + return false; + } + + pgdir->pd_addr = new_pgdir_addr; + + memset(new_pgdir_addr, 0, TOPLEVLE_PAGEDIR_SIZE); + return true; +} + +static bool _map_pages(uintptr_t* pgdir, uintptr_t vaddr, uintptr_t paddr, intptr_t len, uintptr_t attr) +{ + assert(len >= 0); + vaddr = ALIGNDOWN(vaddr, LEVEL4_PTE_SIZE); + paddr = ALIGNDOWN(paddr, LEVEL4_PTE_SIZE); + uintptr_t vaddr_last = ALIGNDOWN(vaddr + len - 1, LEVEL4_PTE_SIZE); + + while (true) { + uintptr_t* pte = NULL; + if ((pte = _page_walk(pgdir, vaddr, true)) == NULL) { + ERROR("pte not found for vaddr %p.\n", vaddr); + return false; + } + + if (UNLIKELY(*pte != 0)) { + ERROR("remapping: vaddr: %p | paddr: %p | pte: %p |\n", vaddr, paddr, *pte); + return false; + } + + *pte = paddr | attr; + + if (vaddr == vaddr_last) { + break; + } + + vaddr += PAGE_SIZE; + paddr += PAGE_SIZE; + } + + assert(vaddr == vaddr_last); + return true; +} + +static bool _unmap_pages(uintptr_t* pgdir, uintptr_t vaddr, int len) +{ + assert(len >= 0); + vaddr = ALIGNDOWN(vaddr, LEVEL4_PTE_SIZE); + uintptr_t vaddr_last = ALIGNDOWN(vaddr + len - 1, LEVEL4_PTE_SIZE); + + while (true) { + uintptr_t* pte = NULL; + if ((pte = _page_walk(pgdir, vaddr, false)) == NULL) { + ERROR("pte not found for vaddr %p.\n", vaddr); + return false; + } + + if (*pte == 0) { + ERROR("unmap a unmapped page, vaddr: %p, pte: %p\n", vaddr, *pte); + return false; + } + + *pte = 0; + + if (vaddr == vaddr_last) { + break; + } + + vaddr += PAGE_SIZE; + } + + assert(vaddr == vaddr_last); + return true; +} + +/// @brief map paddr to vaddr for given pgdir (user only) +/// @param pgdir vaddr of pgdir +/// @param vaddr +/// @param paddr +/// @param len +/// @param is_dev +/// @return +static bool _map_user_pages(struct MemSpace* pmemspace, uintptr_t vaddr, uintptr_t paddr, int len, bool is_dev) +{ + if (len < 0) { + return false; + } + + if (UNLIKELY(vaddr >= USER_MEM_TOP)) { + ERROR("mapping kernel space.\n"); + return false; + } + + uintptr_t mem_attr = 0; + if (LIKELY(!is_dev)) { + _p_pgtbl_mmu_access->MmuUsrPteAttr(&mem_attr); + } else { + _p_pgtbl_mmu_access->MmuUsrDevPteAttr(&mem_attr); + } + + return _map_pages(pmemspace->pgdir.pd_addr, vaddr, paddr, (intptr_t)len, mem_attr); +} + +/// assume that a user pagedir is allocated from [0, size) +/// if new_size > old_size, allocate more space, +/// if old_size > new_size, free extra space, to avoid unnecessary alloc/free. +static uintptr_t _resize_user_pgdir(struct MemSpace* pmemspace, uintptr_t old_size, uintptr_t new_size) +{ + if (UNLIKELY(new_size > USER_MEM_TOP)) { + ERROR("user size out of range.\n"); + return old_size; + } + if (UNLIKELY(new_size < old_size)) { + /// @todo: free extra space. + return old_size; + } + + uintptr_t cur_size = ALIGNUP(old_size, PAGE_SIZE); + uintptr_t size_needed = ALIGNUP(new_size, PAGE_SIZE) - cur_size; + + char* new_page = kalloc(size_needed); + if (new_page == NULL) { + ERROR("No memory\n"); + return cur_size; + } + memset(new_page, 0, size_needed); + if (!xizi_pager.map_pages(pmemspace, cur_size, V2P(new_page), size_needed, false)) { + return cur_size; + } + CreateResourceTag(NULL, &pmemspace->tag, NULL, TRACER_MEM_FROM_BUDDY_AC_RESOURCE, V2P_WO(new_page)); + + return new_size; +} + +/// @brief translate virt address to phy address with pgdir +/// @param pgdir +/// @param vaddr accept only page aligned address +/// @return paddr of pgdir(vaddr); zero for unmapped addr +static uintptr_t _address_translate(struct TopLevelPageDirectory* pgdir, uintptr_t vaddr) +{ + assert(vaddr % PAGE_SIZE == 0); + const uintptr_t* const pte = _page_walk(pgdir->pd_addr, vaddr, false); + if (pte == NULL || *pte == 0) { + return 0; + } + return (uintptr_t)ALIGNDOWN(*pte, PAGE_SIZE); +} + +static uintptr_t _cross_vspace_data_copy_in_page(struct TopLevelPageDirectory* pgdir, uintptr_t cross_dest, uintptr_t src, uintptr_t len) +{ + uintptr_t cross_dest_end = cross_dest + len; + assert(ALIGNUP(cross_dest, PAGE_SIZE) == ALIGNUP(cross_dest_end, PAGE_SIZE)); + + uintptr_t paddr = xizi_pager.address_translate(pgdir, ALIGNDOWN(cross_dest, PAGE_SIZE)); + uintptr_t offset = cross_dest - ALIGNDOWN(cross_dest, PAGE_SIZE); + uintptr_t* vdest = (uintptr_t*)((uintptr_t)P2V(paddr) + offset); + uintptr_t* vsrc = (uintptr_t*)src; + memcpy(vdest, vsrc, len); + return len; +} + +/// @brief copy data from src(kernel vspace) to dest of pgdir vspace +/// @param pgdir +/// @param cross_dest vaddress in pgdir +/// @param src +/// @param len +/// @return +static uintptr_t _cross_vspace_data_copy(struct TopLevelPageDirectory* pgdir, uintptr_t cross_dest, uintptr_t src, uintptr_t len) +{ + uintptr_t len_to_top = ALIGNUP(cross_dest, PAGE_SIZE) - cross_dest; + + uintptr_t copied_len = 0; + while (copied_len < len) { + uintptr_t current_copy_len = len_to_top >= len ? len : len_to_top; + + current_copy_len = _cross_vspace_data_copy_in_page(pgdir, cross_dest, src, current_copy_len); + + // update variables + copied_len += current_copy_len; + cross_dest += current_copy_len; + src += current_copy_len; + len_to_top = ALIGNDOWN(cross_dest + PAGE_SIZE, PAGE_SIZE) - ALIGNDOWN(cross_dest, PAGE_SIZE); // actually PAGE_SIZE + assert(len_to_top == PAGE_SIZE); + } + + return len; +} + +struct XiziPageManager xizi_pager = { + .new_pgdir = _new_pgdir, + .free_user_pgdir = _free_user_pgdir, + .map_pages = _map_user_pages, + .unmap_pages = _unmap_pages, + + .resize_user_pgdir = _resize_user_pgdir, + .address_translate = _address_translate, + .cross_vspace_data_copy = _cross_vspace_data_copy, +}; + +bool module_pager_init(struct PagerRightGroup* _right_group) +{ + right_group = *_right_group; + _p_pgtbl_mmu_access = AchieveResource(&right_group.mmu_driver_tag); + return _p_pgtbl_mmu_access != NULL; +} + +/// @brief kernel pagedir +struct TopLevelPageDirectory kern_pgdir; + +void load_kern_pgdir(struct TraceTag* mmu_driver_tag, struct TraceTag* intr_driver_tag) +{ + if (mmu_driver_tag->meta == NULL) { + ERROR("Invalid mmu driver tag.\n"); + return; + } + + if (!_new_pgdir(&kern_pgdir)) { + panic("cannot alloc kernel page directory"); + } + uintptr_t kern_attr = 0; + _p_pgtbl_mmu_access->MmuKernPteAttr(&kern_attr); + uintptr_t dev_attr = 0; + _p_pgtbl_mmu_access->MmuDevPteAttr(&dev_attr); + + // kern mem + _map_pages((uintptr_t*)kern_pgdir.pd_addr, KERN_MEM_BASE, PHY_MEM_BASE, (PHY_MEM_STOP - PHY_MEM_BASE), kern_attr); + // dev mem + _map_pages((uintptr_t*)kern_pgdir.pd_addr, DEV_VRTMEM_BASE, DEV_PHYMEM_BASE, DEV_MEM_SIZE, dev_attr); + + _p_pgtbl_mmu_access->LoadPgdir((uintptr_t)V2P(kern_pgdir.pd_addr)); +} + +void secondary_cpu_load_kern_pgdir(struct TraceTag* mmu_driver_tag, struct TraceTag* intr_driver_tag) +{ + _p_pgtbl_mmu_access->LoadPgdir((uintptr_t)V2P(kern_pgdir.pd_addr)); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv_level3.c b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv_level3.c new file mode 100644 index 000000000..f9501b6f8 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv_level3.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file pagetable_level3.c + * @brief page walk and L2 pagetable + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.05.06 + */ + +/************************************************* +File name: pagetable_level3.c +Description: ok1028 image vector table +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include + +#include "core.h" +#include "memlayout.h" + +#include "assert.h" +#include "buddy.h" +#include "kalloc.h" +#include "pagetable.h" + +uintptr_t* _page_walk(uintptr_t* pgdir, uintptr_t vaddr, bool alloc) +{ + + // get page table addr + assert(pgdir != NULL); + uintptr_t pde_attr = 0; + _p_pgtbl_mmu_access->MmuPdeAttr(&pde_attr); + + uintptr_t* l2_pde_ptr = (uintptr_t*)&pgdir[(vaddr >> LEVEL2_PDE_SHIFT) & (NUM_LEVEL2_PDE - 1)]; + + uintptr_t* l3_pde_vaddr; + if (*l2_pde_ptr != 0) { + uintptr_t l3_table_paddr = ALIGNDOWN(*l2_pde_ptr, PAGE_SIZE); + l3_pde_vaddr = (uintptr_t*)P2V(l3_table_paddr); + } else { + if (!alloc || !(l3_pde_vaddr = (uintptr_t*)kalloc(sizeof(uintptr_t) * NUM_LEVEL3_PDE))) { + return NULL; + } + + memset(l3_pde_vaddr, 0, sizeof(uintptr_t) * NUM_LEVEL3_PDE); + *l2_pde_ptr = V2P(l3_pde_vaddr) | pde_attr; + } + + uintptr_t* l3_pde_ptr = (uintptr_t*)&l3_pde_vaddr[(vaddr >> LEVEL3_PDE_SHIFT) & (NUM_LEVEL3_PDE - 1)]; + + uintptr_t* l4_pte_vaddr; + if (*l3_pde_ptr != 0) { + uintptr_t l4_table_paddr = ALIGNDOWN(*l3_pde_ptr, PAGE_SIZE); + l4_pte_vaddr = (uintptr_t*)P2V(l4_table_paddr); + } else { + if (!alloc || !(l4_pte_vaddr = (uintptr_t*)kalloc(sizeof(uintptr_t) * NUM_LEVEL4_PTE))) { + return NULL; + } + + memset(l4_pte_vaddr, 0, sizeof(uintptr_t) * NUM_LEVEL4_PTE); + *l3_pde_ptr = V2P(l4_pte_vaddr) | pde_attr; + } + + return &l4_pte_vaddr[LEVEL4_PTE_IDX(vaddr)]; +} + +void _free_user_pgdir(struct TopLevelPageDirectory* pgdir) +{ + if (pgdir->pd_addr == NULL) { + return; + } + + uintptr_t end_idx = (USER_MEM_TOP >> LEVEL2_PDE_SHIFT) & (NUM_LEVEL2_PDE - 1); + + for (uintptr_t l2_entry_idx = 0; l2_entry_idx < end_idx; l2_entry_idx++) { + // free each level3 page table + uintptr_t* l3_table_paddr = (uintptr_t*)ALIGNDOWN(pgdir->pd_addr[l2_entry_idx], PAGE_SIZE); + if (l3_table_paddr != NULL) { + uintptr_t* l3_table_vaddr = P2V(l3_table_paddr); + for (uintptr_t l3_entry_idx = 0; l3_entry_idx < NUM_LEVEL3_PDE; l3_entry_idx++) { + uintptr_t* l4_table_paddr = (uintptr_t*)LEVEL4_PTE_ADDR(l3_table_vaddr[l3_entry_idx]); + if (l4_table_paddr != NULL) { + kfree(P2V(l4_table_paddr)); + } + } + kfree(P2V(l3_table_paddr)); + } + } + kfree((char*)pgdir->pd_addr); +} From 197957f202f2a3d1e60056f6a05d5b74eea39eb2 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 19 Dec 2024 21:34:23 +0800 Subject: [PATCH 21/54] Modify map_pages --- .../hardkernel/mmu/riscv/rv64gc/mmu.c | 16 ++++++-- .../mmu/riscv/rv64gc/pagetable_attr.c | 39 ++++++------------- .../XiZi_AIoT/softkernel/include/pagetable.h | 16 +++++++- .../softkernel/memory/pagetable_riscv.c | 25 +++++++++++- .../memory/pagetable_riscv_level3.c | 14 +++---- 5 files changed, 69 insertions(+), 41 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c index 7fcf5a1f6..508c88296 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c @@ -35,21 +35,29 @@ Modification: #include "mmu_common.h" #include "trap_common.h" +#include "asm/csr.h" +#include "asm/pfn.h" +#include "printf.h" + + // extern struct MmuCommonDone mmu_common_done; static struct MmuDriverRightGroup right_group; void load_pgdir(uintptr_t pgdir_paddr) { + /* get cache driver */ struct ICacheDone* p_icache_done = AchieveResource(&right_group.icache_driver_tag); struct DCacheDone* p_dcache_done = AchieveResource(&right_group.dcache_driver_tag); - TTBR0_W((uint64_t)pgdir_paddr); - DSB(); - CLEARTLB(0); - ISB(); + printk("load_pgdir pgdir_paddr=%08lx\n", pgdir_paddr); + csr_write(CSR_SATP, PFN_DOWN(pgdir_paddr) | SATP_MODE); + __asm__ __volatile__ ("sfence.vma" : : : "memory"); + printf_early("load_pgdir pgdir_paddr=%08lx ok\n", pgdir_paddr); + p_icache_done->invalidateall(); p_dcache_done->flushall(); + } __attribute__((always_inline)) inline static void _tlb_flush(uintptr_t va) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/pagetable_attr.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/pagetable_attr.c index 8085ad036..9a540b040 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/pagetable_attr.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/pagetable_attr.c @@ -29,52 +29,37 @@ Modification: #include "mmu.h" #include "mmu_common.h" -// clang-format off -#define ARMV8_PTE_ATTR_MASK(attr) (((attr) & 0b111) << 2) -#define ARMV8_PTE_DEVICE ARMV8_PTE_ATTR_MASK(0x0) -#define ARMV8_PTE_NORMAL ARMV8_PTE_ATTR_MASK(0x1) +#include "asm/pgtable-bits.h" -#define ARMV8_PTE_AP(ap) (((ap) & 0b11) << 6) -#define ARMV8_PTE_AP_U ARMV8_PTE_AP(0x01) -#define ARMV8_PTE_AP_K ARMV8_PTE_AP(0x00) -#define ARMV8_PTE_AP_RO ARMV8_PTE_AP(0b10) -#define ARMV8_PTE_AP_RW ARMV8_PTE_AP(0b00) +#define _PAGE_KERNEL (_PAGE_READ \ + | _PAGE_WRITE \ + | _PAGE_PRESENT \ + | _PAGE_ACCESSED \ + | _PAGE_DIRTY \ + | _PAGE_GLOBAL) -#define ARMV8_PTE_AF (0x1 << 10) -#define ARMV8_PTE_PXN (1ULL << 53) // Privileged eXecute Never -#define ARMV8_PTE_UXN (1ULL << 54) // Unprivileged(user) eXecute Never -#define ARMV8_PTE_XN (ARMV8_PTE_PXN | ARMV8_PTE_UXN) - -#define ARMV8_PTE_VALID (0b11 << 0) -#define ARMV8_PDE_VALID (0b11 << 0) - -// clang-format on void GetUsrPteAttr(uintptr_t* attr) { - // *attr = ARMV8_PTE_AP_U | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_NORMAL | ARMV8_PTE_VALID; - *attr = 0x713 | ARMV8_PTE_AP_U; + *attr = _PAGE_KERNEL | _PAGE_USER | _PAGE_EXEC; } void GetUsrDevPteAttr(uintptr_t* attr) { - // *attr = ARMV8_PTE_AP_U | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_DEVICE | ARMV8_PTE_XN | ARMV8_PTE_VALID; - *attr = 0x403 | ARMV8_PTE_AP_U; + *attr = _PAGE_KERNEL | _PAGE_USER; } void GetDevPteAttr(uintptr_t* attr) { - // *attr = ARMV8_PTE_AP_K | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_DEVICE | ARMV8_PTE_XN | ARMV8_PTE_VALID; - *attr = 0x403ULL; + *attr = _PAGE_KERNEL; } void GetKernPteAttr(uintptr_t* attr) { - // *attr = ARMV8_PTE_AP_K | ARMV8_PTE_AP_RW | ARMV8_PTE_AF | ARMV8_PTE_NORMAL | ARMV8_PTE_VALID; - *attr = 0x713ULL; + *attr = _PAGE_KERNEL | _PAGE_EXEC; } void GetPdeAttr(uintptr_t* attr) { - *attr = ARMV8_PDE_VALID; + *attr = _PAGE_PRESENT; } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h b/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h index e0938d322..2894a4291 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h +++ b/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h @@ -48,6 +48,19 @@ Modification: #define LEVEL3_PDE_ADDR(v) ALIGNDOWN(v, LEVEL3_PDE_SIZE) #define TOPLEVLE_PAGEDIR_SIZE sizeof(uintptr_t) * NUM_TOPLEVEL_PDE + + +//#define PAGE_SHIFT (12) +#define _PAGE_PFN_SHIFT 10 +#define PFN_DOWN(x) ((x) >> PAGE_SHIFT) +#define PFN_PGD(x) ((x) << _PAGE_PFN_SHIFT) +#define PFN_PHYS(x) ((x) << PAGE_SHIFT) +#define _PGD_PFN(x) ((x) >> _PAGE_PFN_SHIFT) +#define PFN_PMD PFN_PGD +#define _PMD_PFN _PGD_PFN +#define PFN_PTE PFN_PGD +#define _PTE_PFN _PGD_PFN + // clang-format on struct PagerRightGroup { @@ -74,4 +87,5 @@ void load_kern_pgdir(struct TraceTag* mmu_driver_tag, struct TraceTag* intr_driv void secondary_cpu_load_kern_pgdir(struct TraceTag* mmu_driver_tag, struct TraceTag* intr_driver_tag); extern struct XiziPageManager xizi_pager; -bool module_pager_init(struct PagerRightGroup*); \ No newline at end of file +bool module_pager_init(struct PagerRightGroup*); +bool _new_pgdir(struct TopLevelPageDirectory* pgdir); \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c index 53404786f..e70a06c81 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c @@ -38,9 +38,11 @@ Modification: static struct PagerRightGroup right_group; struct MmuCommonDone* _p_pgtbl_mmu_access = NULL; + static bool _new_pgdir(struct TopLevelPageDirectory* pgdir) { void* new_pgdir_addr = 0; + if (UNLIKELY((new_pgdir_addr = kalloc(TOPLEVLE_PAGEDIR_SIZE)) == NULL)) { return false; } @@ -70,7 +72,7 @@ static bool _map_pages(uintptr_t* pgdir, uintptr_t vaddr, uintptr_t paddr, intpt return false; } - *pte = paddr | attr; + *pte = PFN_PTE(PFN_DOWN(paddr)) | attr; if (vaddr == vaddr_last) { break; @@ -170,7 +172,6 @@ static uintptr_t _resize_user_pgdir(struct MemSpace* pmemspace, uintptr_t old_si return cur_size; } CreateResourceTag(NULL, &pmemspace->tag, NULL, TRACER_MEM_FROM_BUDDY_AC_RESOURCE, V2P_WO(new_page)); - return new_size; } @@ -246,6 +247,19 @@ bool module_pager_init(struct PagerRightGroup* _right_group) return _p_pgtbl_mmu_access != NULL; } +#if 0 +static int test_access_map_address(void) +{ + unsigned long address = KERN_MEM_BASE + (PHY_MEM_STOP - PHY_MEM_BASE) - 4096; + printf_early("%s to access 0x%lx\n", __func__, address); + *(unsigned long *)address = 0x55; + if(*(unsigned long *)address == 0x55) { + printf_early("%s access 0x%lx done\n", __func__, address); + } + return 0; +} +#endif + /// @brief kernel pagedir struct TopLevelPageDirectory kern_pgdir; @@ -259,17 +273,24 @@ void load_kern_pgdir(struct TraceTag* mmu_driver_tag, struct TraceTag* intr_driv if (!_new_pgdir(&kern_pgdir)) { panic("cannot alloc kernel page directory"); } + uintptr_t kern_attr = 0; _p_pgtbl_mmu_access->MmuKernPteAttr(&kern_attr); uintptr_t dev_attr = 0; _p_pgtbl_mmu_access->MmuDevPteAttr(&dev_attr); + + // kern mem link + _map_pages((uintptr_t*)kern_pgdir.pd_addr, KERNEL_LINK_ADDR, PHY_MEM_BASE, (PHY_USER_FREEMEM_BASE - PHY_MEM_BASE), kern_attr); // kern mem _map_pages((uintptr_t*)kern_pgdir.pd_addr, KERN_MEM_BASE, PHY_MEM_BASE, (PHY_MEM_STOP - PHY_MEM_BASE), kern_attr); // dev mem _map_pages((uintptr_t*)kern_pgdir.pd_addr, DEV_VRTMEM_BASE, DEV_PHYMEM_BASE, DEV_MEM_SIZE, dev_attr); _p_pgtbl_mmu_access->LoadPgdir((uintptr_t)V2P(kern_pgdir.pd_addr)); +#if 0 + test_access_map_address(); +#endif } void secondary_cpu_load_kern_pgdir(struct TraceTag* mmu_driver_tag, struct TraceTag* intr_driver_tag) diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv_level3.c b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv_level3.c index f9501b6f8..04d0afc4c 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv_level3.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv_level3.c @@ -38,7 +38,6 @@ Modification: uintptr_t* _page_walk(uintptr_t* pgdir, uintptr_t vaddr, bool alloc) { - // get page table addr assert(pgdir != NULL); uintptr_t pde_attr = 0; @@ -48,7 +47,7 @@ uintptr_t* _page_walk(uintptr_t* pgdir, uintptr_t vaddr, bool alloc) uintptr_t* l3_pde_vaddr; if (*l2_pde_ptr != 0) { - uintptr_t l3_table_paddr = ALIGNDOWN(*l2_pde_ptr, PAGE_SIZE); + uintptr_t l3_table_paddr = PFN_PHYS(_PGD_PFN(*l2_pde_ptr)); l3_pde_vaddr = (uintptr_t*)P2V(l3_table_paddr); } else { if (!alloc || !(l3_pde_vaddr = (uintptr_t*)kalloc(sizeof(uintptr_t) * NUM_LEVEL3_PDE))) { @@ -56,14 +55,14 @@ uintptr_t* _page_walk(uintptr_t* pgdir, uintptr_t vaddr, bool alloc) } memset(l3_pde_vaddr, 0, sizeof(uintptr_t) * NUM_LEVEL3_PDE); - *l2_pde_ptr = V2P(l3_pde_vaddr) | pde_attr; + *l2_pde_ptr = PFN_PGD(PFN_DOWN(V2P(l3_pde_vaddr))) | pde_attr; } uintptr_t* l3_pde_ptr = (uintptr_t*)&l3_pde_vaddr[(vaddr >> LEVEL3_PDE_SHIFT) & (NUM_LEVEL3_PDE - 1)]; uintptr_t* l4_pte_vaddr; if (*l3_pde_ptr != 0) { - uintptr_t l4_table_paddr = ALIGNDOWN(*l3_pde_ptr, PAGE_SIZE); + uintptr_t l4_table_paddr = PFN_PHYS(_PMD_PFN(*l3_pde_ptr)); l4_pte_vaddr = (uintptr_t*)P2V(l4_table_paddr); } else { if (!alloc || !(l4_pte_vaddr = (uintptr_t*)kalloc(sizeof(uintptr_t) * NUM_LEVEL4_PTE))) { @@ -71,12 +70,13 @@ uintptr_t* _page_walk(uintptr_t* pgdir, uintptr_t vaddr, bool alloc) } memset(l4_pte_vaddr, 0, sizeof(uintptr_t) * NUM_LEVEL4_PTE); - *l3_pde_ptr = V2P(l4_pte_vaddr) | pde_attr; + *l3_pde_ptr = PFN_PMD(PFN_DOWN(V2P(l4_pte_vaddr))) | pde_attr; } return &l4_pte_vaddr[LEVEL4_PTE_IDX(vaddr)]; } + void _free_user_pgdir(struct TopLevelPageDirectory* pgdir) { if (pgdir->pd_addr == NULL) { @@ -87,11 +87,11 @@ void _free_user_pgdir(struct TopLevelPageDirectory* pgdir) for (uintptr_t l2_entry_idx = 0; l2_entry_idx < end_idx; l2_entry_idx++) { // free each level3 page table - uintptr_t* l3_table_paddr = (uintptr_t*)ALIGNDOWN(pgdir->pd_addr[l2_entry_idx], PAGE_SIZE); + uintptr_t* l3_table_paddr = (uintptr_t*)PFN_PHYS(_PMD_PFN(pgdir->pd_addr[l2_entry_idx])); if (l3_table_paddr != NULL) { uintptr_t* l3_table_vaddr = P2V(l3_table_paddr); for (uintptr_t l3_entry_idx = 0; l3_entry_idx < NUM_LEVEL3_PDE; l3_entry_idx++) { - uintptr_t* l4_table_paddr = (uintptr_t*)LEVEL4_PTE_ADDR(l3_table_vaddr[l3_entry_idx]); + uintptr_t* l4_table_paddr = (uintptr_t*)PFN_PHYS(_PTE_PFN(l3_table_vaddr[l3_entry_idx])); if (l4_table_paddr != NULL) { kfree(P2V(l4_table_paddr)); } From 7e94dc5cb2eca82fbfc8f3dc3156ff4eb3db21f8 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 19 Dec 2024 21:40:06 +0800 Subject: [PATCH 22/54] fix build error --- Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h b/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h index 2894a4291..f6f9a2d7a 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h +++ b/Ubiquitous/XiZi_AIoT/softkernel/include/pagetable.h @@ -88,4 +88,4 @@ void secondary_cpu_load_kern_pgdir(struct TraceTag* mmu_driver_tag, struct Trace extern struct XiziPageManager xizi_pager; bool module_pager_init(struct PagerRightGroup*); -bool _new_pgdir(struct TopLevelPageDirectory* pgdir); \ No newline at end of file + From 9fbb5be4996a7b26b8488ec92ed5fc61fe9d4427 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 20 Dec 2024 10:38:34 +0800 Subject: [PATCH 23/54] Modify _address_translate --- Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c index e70a06c81..f07a67660 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c @@ -55,6 +55,7 @@ static bool _new_pgdir(struct TopLevelPageDirectory* pgdir) static bool _map_pages(uintptr_t* pgdir, uintptr_t vaddr, uintptr_t paddr, intptr_t len, uintptr_t attr) { + DEBUG_PRINTF("_map_pages pgdir=%08lx, vaddr=%08lx, paddr=%08lx, len=%08lx, attr==%08lx\n", pgdir, vaddr, paddr, len, attr); assert(len >= 0); vaddr = ALIGNDOWN(vaddr, LEVEL4_PTE_SIZE); paddr = ALIGNDOWN(paddr, LEVEL4_PTE_SIZE); @@ -186,7 +187,7 @@ static uintptr_t _address_translate(struct TopLevelPageDirectory* pgdir, uintptr if (pte == NULL || *pte == 0) { return 0; } - return (uintptr_t)ALIGNDOWN(*pte, PAGE_SIZE); + return (uintptr_t)PFN_PHYS(_PTE_PFN(*pte)); } static uintptr_t _cross_vspace_data_copy_in_page(struct TopLevelPageDirectory* pgdir, uintptr_t cross_dest, uintptr_t src, uintptr_t len) From e20ff7483c099521a68628d52be335e6177c6992 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 25 Dec 2024 19:31:55 +0800 Subject: [PATCH 24/54] Modify _spinlock_lock --- .../intr/riscv/rv64gc/hard_spinlock.S | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S index b26cf30f3..970369a92 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S @@ -57,6 +57,16 @@ Modification: .global _spinlock_lock .func _spinlock_lock _spinlock_lock: + mv s0, a0 + li a0, 0 # cpu_get_current + mv a1, a0 + mv a0, s0 + li a2, UNLOCKED +1: + lr.w a3, (a0) + beq a3, a1, 1b + sc.w a4, a1, (a0) + bnez a4, 1b ret .endfunc @@ -65,6 +75,18 @@ _spinlock_lock: .global _spinlock_unlock .func _spinlock_unlock _spinlock_unlock: + mv s0, a0 + li a0, 0 # cpu_get_current + mv a1, a0 + mv a0, s0 + li a2, UNLOCKED + lw a3, (a0) + bne a3, a1, 1f + sw a2, (a0) + li a0, 0 + ret +1: + li a0, -1 ret .endfunc From a39ab68b4c2ba71ad532d5e238a8b7e8b9ef0a3c Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 25 Dec 2024 19:37:39 +0800 Subject: [PATCH 25/54] Modify _spinlock_lock --- .../XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S index 970369a92..c8eb7f4a4 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S @@ -58,7 +58,7 @@ Modification: .func _spinlock_lock _spinlock_lock: mv s0, a0 - li a0, 0 # cpu_get_current + call cpu_get_current mv a1, a0 mv a0, s0 li a2, UNLOCKED @@ -76,7 +76,7 @@ _spinlock_lock: .func _spinlock_unlock _spinlock_unlock: mv s0, a0 - li a0, 0 # cpu_get_current + call cpu_get_current mv a1, a0 mv a0, s0 li a2, UNLOCKED From 3154da5ec6efae6e22f1273f724aa2cf02a3f9e7 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 26 Dec 2024 09:33:01 +0800 Subject: [PATCH 26/54] Revert "Modify _spinlock_lock" This reverts commit a39ab68b4c2ba71ad532d5e238a8b7e8b9ef0a3c. --- .../XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S index c8eb7f4a4..970369a92 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S @@ -58,7 +58,7 @@ Modification: .func _spinlock_lock _spinlock_lock: mv s0, a0 - call cpu_get_current + li a0, 0 # cpu_get_current mv a1, a0 mv a0, s0 li a2, UNLOCKED @@ -76,7 +76,7 @@ _spinlock_lock: .func _spinlock_unlock _spinlock_unlock: mv s0, a0 - call cpu_get_current + li a0, 0 # cpu_get_current mv a1, a0 mv a0, s0 li a2, UNLOCKED From beef098836c980518e1beb93de539dd4133532ca Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 26 Dec 2024 09:59:09 +0800 Subject: [PATCH 27/54] Modify _spinlock_lock --- .../XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S index 970369a92..522988a95 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/hard_spinlock.S @@ -64,7 +64,7 @@ _spinlock_lock: li a2, UNLOCKED 1: lr.w a3, (a0) - beq a3, a1, 1b + bne a3, a2, 1b sc.w a4, a1, (a0) bnez a4, 1b ret From b6340dee69c9c66de3f421114fa8cd7ef6a1cf24 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 27 Dec 2024 19:01:00 +0800 Subject: [PATCH 28/54] Add riscv context_switch --- .../arch/riscv/rv64gc/context_switch.S | 43 +++++- .../hardkernel/arch/riscv/rv64gc/core.h | 127 +++++++++--------- Ubiquitous/XiZi_AIoT/softkernel/task/task.c | 5 + .../XiZi_AIoT/softkernel/trap/abort_handler.c | 18 +++ 4 files changed, 130 insertions(+), 63 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/context_switch.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/context_switch.S index 681c13524..f37489db4 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/context_switch.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/context_switch.S @@ -23,8 +23,47 @@ Description: task context switch functions Others: History: *************************************************/ + +/* + * Integer register context switch + * The callee-saved registers must be saved and restored. + * + * a0: previous thread_struct (must be preserved across the switch) + * a1: next thread_struct + * + */ .global context_switch context_switch: - nop - ret \ No newline at end of file + sd ra, 0(a0) + sd sp, 8(a0) + sd s0, 16(a0) + sd s1, 24(a0) + sd s2, 32(a0) + sd s3, 40(a0) + sd s4, 48(a0) + sd s5, 56(a0) + sd s6, 64(a0) + sd s7, 72(a0) + sd s8, 80(a0) + sd s9, 88(a0) + sd s10, 96(a0) + sd s11, 104(a0) + + ld ra, 0(a1) + ld sp, 8(a1) + ld s0, 16(a1) + ld s1, 24(a1) + ld s2, 32(a1) + ld s3, 40(a1) + ld s4, 48(a1) + ld s5, 56(a1) + ld s6, 64(a1) + ld s7, 72(a1) + ld s8, 80(a1) + ld s9, 88(a1) + ld s10, 96(a1) + ld s11, 104(a1) + + mv tp, a1 + ret diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h index 9267f1f04..146367454 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h @@ -73,7 +73,9 @@ Modification: #include "cortex.h" -#define NR_CPU 4 // maximum number of CPUs +#define NR_CPU 1 // maximum number of CPUs + +#define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User __attribute__((always_inline)) static inline uint64_t EL0_mode() // Set ARM mode to EL0 { @@ -92,69 +94,72 @@ __attribute__((always_inline, optimize("O0"))) static inline void cpu_leave_low_ SEV(); } -struct context { - uint64_t sp; - /* callee register */ - uint64_t x18; - uint64_t x19; - uint64_t x20; - uint64_t x21; - uint64_t x22; - uint64_t x23; - uint64_t x24; - uint64_t x25; - uint64_t x26; - uint64_t x27; - uint64_t x28; - uint64_t x29; - uint64_t x30; +struct __riscv_d_ext_state { + uint64_t f[32]; + uint32_t fcsr; +}; +/* Refer to struct thread_struct in Linux */ +/* CPU-specific state of a task */ +struct context { + /* Callee-saved registers */ + unsigned long ra; + unsigned long sp; /* Kernel mode stack */ + unsigned long s[12]; /* s[0]: frame pointer */ + struct __riscv_d_ext_state fstate; + unsigned long bad_cause; }; /// @brief init task context, set return address to trap return /// @param ctx extern void task_prepare_enter(void); -__attribute__((__always_inline__)) static inline void arch_init_context(struct context* ctx) +__attribute__((__always_inline__)) static inline void arch_init_context(struct context* ctx, unsigned long sp) { memset(ctx, 0, sizeof(*ctx)); - ctx->x30 = (uintptr_t)(task_prepare_enter + 4); + ctx->ra = (uintptr_t)(task_prepare_enter); + ctx->sp = sp; } +/* Refer to struct pt_regs in Linux */ struct trapframe { - uint64_t x0; - uint64_t x1; - uint64_t x2; - uint64_t x3; - uint64_t x4; - uint64_t x5; - uint64_t x6; - uint64_t x7; - uint64_t x8; - uint64_t x9; - uint64_t x10; - uint64_t x11; - uint64_t x12; - uint64_t x13; - uint64_t x14; - uint64_t x15; - uint64_t x16; - uint64_t x17; - uint64_t x18; - uint64_t x19; - uint64_t x20; - uint64_t x21; - uint64_t x22; - uint64_t x23; - uint64_t x24; - uint64_t x25; - uint64_t x26; - uint64_t x27; - uint64_t x28; - uint64_t x29; - uint64_t x30; - uint64_t pc; - uint64_t spsr; - uint64_t sp; + unsigned long epc; + unsigned long ra; + unsigned long sp; + unsigned long gp; + unsigned long tp; + unsigned long t0; + unsigned long t1; + unsigned long t2; + unsigned long s0; + unsigned long s1; + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; + unsigned long a4; + unsigned long a5; + unsigned long a6; + unsigned long a7; + unsigned long s2; + unsigned long s3; + unsigned long s4; + unsigned long s5; + unsigned long s6; + unsigned long s7; + unsigned long s8; + unsigned long s9; + unsigned long s10; + unsigned long s11; + unsigned long t3; + unsigned long t4; + unsigned long t5; + unsigned long t6; + /* Supervisor/Machine CSRs */ + unsigned long status; + unsigned long badaddr; + unsigned long cause; + /* a0 value before the syscall */ + unsigned long orig_a0; }; /// @brief init task trapframe @@ -165,8 +170,8 @@ __attribute__((__always_inline__)) static inline void arch_init_trapframe(struct { memset(tf, 0, sizeof(*tf)); tf->sp = sp; - tf->spsr = EL0_mode(); - tf->pc = pc; + tf->epc = pc; + tf->status &= ~SSTATUS_SPP; // clear SPP to 0 for user mode } /// @brief set pc and sp to trapframe @@ -176,7 +181,7 @@ __attribute__((__always_inline__)) static inline void arch_init_trapframe(struct __attribute__((__always_inline__)) static inline void arch_trapframe_set_sp_pc(struct trapframe* tf, uintptr_t sp, uintptr_t pc) { tf->sp = sp; - tf->pc = pc; + tf->epc = pc; } /// @brief set params of main(int argc, char** argv) to trapframe (argc, argv) @@ -185,8 +190,8 @@ __attribute__((__always_inline__)) static inline void arch_trapframe_set_sp_pc(s /// @param argv __attribute__((__always_inline__)) static inline void arch_set_main_params(struct trapframe* tf, int argc, uintptr_t argv) { - tf->x0 = (uint64_t)argc; - tf->x1 = (uint64_t)argv; + tf->a0 = (uint64_t)argc; + tf->a1 = (uint64_t)argv; } /// @brief retrieve params to trapframe (up to max number of 6) and pass it to syscall() @@ -201,8 +206,8 @@ extern int syscall(int sys_num, uintptr_t param1, uintptr_t param2, uintptr_t pa __attribute__((__always_inline__)) static inline int arch_syscall(struct trapframe* tf, int* syscall_num) { // call syscall - *syscall_num = tf->x0; - return syscall(*syscall_num, tf->x1, tf->x2, tf->x3, tf->x4); + *syscall_num = tf->a0; + return syscall(*syscall_num, tf->a1, tf->a2, tf->a3, tf->a4); } /// @brief set return reg to trapframe @@ -210,7 +215,7 @@ __attribute__((__always_inline__)) static inline int arch_syscall(struct trapfra /// @param ret __attribute__((__always_inline__)) static inline void arch_set_return(struct trapframe* tf, int ret) { - tf->x0 = (uint64_t)ret; + tf->a0 = (uint64_t)ret; } void cpu_start_secondary(uint8_t cpu_id); diff --git a/Ubiquitous/XiZi_AIoT/softkernel/task/task.c b/Ubiquitous/XiZi_AIoT/softkernel/task/task.c index 27df0e16e..4696a2c42 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/task/task.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/task/task.c @@ -211,6 +211,7 @@ static void _dealloc_task_cb(struct Thread* task) extern void trap_return(void); __attribute__((optimize("O0"))) void task_prepare_enter() { + DEBUG_PRINTF("task_prepare_enter\n"); xizi_leave_kernel(); trap_return(); } @@ -259,7 +260,11 @@ static struct Thread* _new_task_cb(struct MemSpace* pmemspace) /// 2. context into stack sp -= sizeof(*task->thread_context.context); task->thread_context.context = (struct context*)sp; +#ifndef __riscv arch_init_context(task->thread_context.context); +#else + arch_init_context(task->thread_context.context, task->thread_context.kern_stack_addr); +#endif return task; } diff --git a/Ubiquitous/XiZi_AIoT/softkernel/trap/abort_handler.c b/Ubiquitous/XiZi_AIoT/softkernel/trap/abort_handler.c index 119ae2772..9cbc00a8a 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/trap/abort_handler.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/trap/abort_handler.c @@ -51,12 +51,21 @@ Modification: extern void context_switch(struct context**, struct context*); __attribute__((optimize("O0"))) void dabort_handler(struct trapframe* r) { +#ifndef __riscv if (r->pc >= DEV_VRTMEM_BASE && is_spinlock_hold_by_current_cpu(&whole_kernel_lock)) { assert(is_spinlock_hold_by_current_cpu(&whole_kernel_lock)); ERROR("dabort in kernel, current task: %s\n", cur_cpu()->task == NULL ? "NULL" : cur_cpu()->task->name); dabort_reason(r); panic("data abort exception\n"); } +#else + if (r->epc >= DEV_VRTMEM_BASE && is_spinlock_hold_by_current_cpu(&whole_kernel_lock)) { + assert(is_spinlock_hold_by_current_cpu(&whole_kernel_lock)); + ERROR("dabort in kernel, current task: %s\n", cur_cpu()->task == NULL ? "NULL" : cur_cpu()->task->name); + dabort_reason(r); + panic("data abort exception\n"); + } +#endif struct Thread* cur_task = cur_cpu()->task; ERROR("dabort in user space: %s\n", cur_task->name); @@ -71,12 +80,21 @@ __attribute__((optimize("O0"))) void dabort_handler(struct trapframe* r) __attribute__((optimize("O0"))) void iabort_handler(struct trapframe* r) { +#ifndef __riscv if (r->pc >= DEV_VRTMEM_BASE && is_spinlock_hold_by_current_cpu(&whole_kernel_lock)) { assert(is_spinlock_hold_by_current_cpu(&whole_kernel_lock)); ERROR("iabort in kernel, current task: %s\n", cur_cpu()->task == NULL ? "NULL" : cur_cpu()->task->name); iabort_reason(r); panic("kernel prefetch abort exception\n"); } +#else + if (r->epc >= DEV_VRTMEM_BASE && is_spinlock_hold_by_current_cpu(&whole_kernel_lock)) { + assert(is_spinlock_hold_by_current_cpu(&whole_kernel_lock)); + ERROR("iabort in kernel, current task: %s\n", cur_cpu()->task == NULL ? "NULL" : cur_cpu()->task->name); + iabort_reason(r); + panic("kernel prefetch abort exception\n"); + } +#endif struct Thread* cur_task = cur_cpu()->task; ERROR("iabort in user space: %s\n", cur_task->name); From ad6a6d7cc6b9e0bff07e5d5fd70b48e2138155c3 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 27 Dec 2024 19:05:32 +0800 Subject: [PATCH 29/54] Add services for jh7110 --- .../XiZi_AIoT/services/boards/jh7110/Makefile | 28 ++ .../services/boards/jh7110/arch_usyscall.c | 32 +++ .../services/boards/jh7110/libserial.c | 250 ++++++++++++++++++ .../XiZi_AIoT/services/boards/jh7110/stub.c | 91 +++++++ 4 files changed, 401 insertions(+) create mode 100644 Ubiquitous/XiZi_AIoT/services/boards/jh7110/Makefile create mode 100644 Ubiquitous/XiZi_AIoT/services/boards/jh7110/arch_usyscall.c create mode 100644 Ubiquitous/XiZi_AIoT/services/boards/jh7110/libserial.c create mode 100644 Ubiquitous/XiZi_AIoT/services/boards/jh7110/stub.c diff --git a/Ubiquitous/XiZi_AIoT/services/boards/jh7110/Makefile b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/Makefile new file mode 100644 index 000000000..6c59a35cd --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/Makefile @@ -0,0 +1,28 @@ +ifeq ($(BOARD), jh7110) +toolchain ?= riscv64-unknown-elf- +user_ldflags = -N -Ttext 0 +cflags = -Wall -O0 -g -std=c11 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +endif + +cc = ${toolchain}gcc +ld = ${toolchain}g++ +objdump = ${toolchain}objdump + +c_useropts = -O2 + +INC_DIR = -I$(KERNEL_ROOT)/services/fs/libfs \ + -I$(KERNEL_ROOT)/services/lib/ipc \ + -I$(KERNEL_ROOT)/services/lib/memory \ + -I$(KERNEL_ROOT)/services/lib/serial \ + -I$(KERNEL_ROOT)/services/lib/usyscall \ + -I$(KERNEL_ROOT)/services/boards/$(BOARD) \ + -I$(KERNEL_ROOT)/services/app + +board: libserial.o arch_usyscall.o stub.o + @mv $^ $(KERNEL_ROOT)/services/app + +%.o: %.c + @echo "cc $^" + @${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $^ + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/services/boards/jh7110/arch_usyscall.c b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/arch_usyscall.c new file mode 100644 index 000000000..4f9eceb3c --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/arch_usyscall.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +#include "usyscall.h" + +int syscall(int sys_num, intptr_t a1, intptr_t a2, intptr_t a3, intptr_t a4) +{ + int ret = -1; + + __asm__ volatile( + "mv a0, %1;\ + mv a1, %2;\ + mv a2, %3;\ + mv a3, %4;\ + mv a4, %5;\ + ecall;\ + mv %0, a0" + : "=r"(ret) + : "r"(sys_num), "r"(a1), "r"(a2), "r"(a3), "r"(a4) + : "memory", "a0", "a1", "a2", "a3", "a4" + ); + + return ret; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/boards/jh7110/libserial.c b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/libserial.c new file mode 100644 index 000000000..15c5dbd2a --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/libserial.c @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/// this file is only used for debug +#include +#include + +#include "libserial.h" +#include "usyscall.h" + +/* + * For driver model we always use one byte per register, and sort out the + * differences in the driver + */ +#define CONFIG_SYS_NS16550_REG_SIZE (-1) + +#define UART_REG(x) \ + unsigned char x; \ + unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; + +/** + * struct ns16550_platdata - information about a NS16550 port + * + * @base: Base register address + * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) + * @clock: UART base clock speed in Hz + */ +struct ns16550_platdata { + unsigned long base; + int reg_shift; + int clock; + int reg_offset; + uint32_t fcr; +}; + +struct udevice; + +struct NS16550 { + UART_REG(rbr); /* 0 */ + UART_REG(ier); /* 1 */ + UART_REG(fcr); /* 2 */ + UART_REG(lcr); /* 3 */ + UART_REG(mcr); /* 4 */ + UART_REG(lsr); /* 5 */ + UART_REG(msr); /* 6 */ + UART_REG(spr); /* 7 */ +#ifdef CONFIG_SOC_DA8XX + UART_REG(reg8); /* 8 */ + UART_REG(reg9); /* 9 */ + UART_REG(revid1); /* A */ + UART_REG(revid2); /* B */ + UART_REG(pwr_mgmt); /* C */ + UART_REG(mdr1); /* D */ +#else + UART_REG(mdr1); /* 8 */ + UART_REG(reg9); /* 9 */ + UART_REG(regA); /* A */ + UART_REG(regB); /* B */ + UART_REG(regC); /* C */ + UART_REG(regD); /* D */ + UART_REG(regE); /* E */ + UART_REG(uasr); /* F */ + UART_REG(scr); /* 10*/ + UART_REG(ssr); /* 11*/ +#endif +#ifdef CONFIG_DM_SERIAL + struct ns16550_platdata* plat; +#endif +}; + +#define thr rbr +#define iir fcr +#define dll rbr +#define dlm ier + +typedef struct NS16550* NS16550_t; + +/* + * These are the definitions for the FIFO Control Register + */ +#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ + +#define UART_FCR_RXSR 0x02 /* Receiver soft reset */ +#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ + +/* Ingenic JZ47xx specific UART-enable bit. */ +#define UART_FCR_UME 0x10 + +/* Clear & enable FIFOs */ +#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR) + +/* + * These are the definitions for the Modem Control Register + */ +#define UART_MCR_DTR 0x01 /* DTR */ +#define UART_MCR_RTS 0x02 /* RTS */ +#define UART_MCR_OUT1 0x04 /* Out 1 */ +#define UART_MCR_OUT2 0x08 /* Out 2 */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */ + +#define UART_MCR_DMA_EN 0x04 +#define UART_MCR_TX_DFR 0x08 + +/* + * These are the definitions for the Line Control Register + * + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. + */ +#define UART_LCR_WLS_MSK 0x03 /* character length select mask */ +#define UART_LCR_WLS_5 0x00 /* 5 bit character length */ +#define UART_LCR_WLS_6 0x01 /* 6 bit character length */ +#define UART_LCR_WLS_7 0x02 /* 7 bit character length */ +#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ +#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */ +#define UART_LCR_PEN 0x08 /* Parity eneble */ +#define UART_LCR_EPS 0x10 /* Even Parity Select */ +#define UART_LCR_STKP 0x20 /* Stick Parity */ +#define UART_LCR_SBRK 0x40 /* Set Break */ +#define UART_LCR_BKSE 0x80 /* Bank select enable */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ + +/* + * These are the definitions for the Line Status Register + */ +#define UART_LSR_DR 0x01 /* Data ready */ +#define UART_LSR_OE 0x02 /* Overrun */ +#define UART_LSR_PE 0x04 /* Parity error */ +#define UART_LSR_FE 0x08 /* Framing error */ +#define UART_LSR_BI 0x10 /* Break */ +#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ +#define UART_LSR_TEMT 0x40 /* Xmitter empty */ +#define UART_LSR_ERR 0x80 /* Error */ + +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ + +/* + * These are the definitions for the Interrupt Identification Register + */ +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ + +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ + +/* + * These are the definitions for the Interrupt Enable Register + */ +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ + +/* useful defaults for LCR */ +#define UART_LCR_8N1 0x03 + +#define UART_ADDR (0xFE660000) + +#define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ +#define UART_MCRVAL (UART_MCR_DTR | UART_MCR_RTS) /* RTS/DTR */ + +#define out_le32(a, v) (*(volatile uint32_t*)(a) = (v)) +#define in_le32(a) (*(volatile uint32_t*)(a)) + +#ifndef CONFIG_SYS_NS16550_IER +#define CONFIG_SYS_NS16550_IER 0x00 +#endif /* CONFIG_SYS_NS16550_IER */ + +#define serial_dout(reg, value) \ + serial_out_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \ + 2, value) +#define serial_din(reg) \ + serial_in_shift((char*)com_port + ((char*)reg - (char*)com_port) * (1 << 2), \ + 2) + +static inline void serial_out_shift(void* addr, int shift, int value) +{ + out_le32(addr, value); +} + +static inline int serial_in_shift(void* addr, int shift) +{ + return in_le32(addr); +} + +#ifndef CONFIG_SYS_NS16550_CLK +#define CONFIG_SYS_NS16550_CLK 0 +#endif + +bool init_uart_mmio() +{ + static int mapped = 0; + if (mapped == 0) { + if (-1 == mmap(UART_ADDR, UART_ADDR, 4096, true)) { + return false; + } + mapped = 1; + } + return true; +} + +void putc(char ch) +{ + static struct NS16550* com_port = (struct NS16550*)UART_ADDR; + + if (ch == '\n') { + putc('\r'); + } + + while (!(serial_din(&com_port->lsr) & UART_LSR_THRE)) + ; + serial_dout(&com_port->thr, ch); +} + +char getc(void) +{ + static struct NS16550* com_port = (struct NS16550*)UART_ADDR; + + while (!(serial_din(&com_port->lsr) & UART_LSR_DR)) + ; + + return serial_din(&com_port->rbr); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/boards/jh7110/stub.c b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/stub.c new file mode 100644 index 000000000..c2c3af9d4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/stub.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +#include +#include +#include + +// _exit: 用于退出程序 +void _exit(int status) +{ + while (1) { } +} + +// _sbrk: 用于增加程序的数据空间 +void* _sbrk(ptrdiff_t incr) +{ + extern char end; /* Defined by the linker */ + static char* heap_end; + char* prev_heap_end; + + if (heap_end == 0) { + heap_end = &end; + } + prev_heap_end = heap_end; + + // 在这里，你应该添加一些检查来确保堆不会与栈或其他内存区域冲突 + // 例如，检查 incr 是否会导致堆超出预定的内存区域 + + heap_end += incr; + return (void*)prev_heap_end; +} + +// _write: 用于将数据写入文件描述符 +ssize_t _write(int file, const void* ptr, size_t len) +{ + // 在这里，你需要实现将数据写入文件描述符的逻辑 + // 如果你的系统不支持文件系统，你可以将数据发送到串口或其他输出 + + return len; // 假设所有数据都被写入 +} + +// _close: 用于关闭文件描述符 +int _close(int file) +{ + return -1; // 表示失败，因为没有实际关闭文件的功能 +} + +// _fstat: 用于获取文件状态 +int _fstat(int file, struct stat* st) +{ + return 0; // 表示成功 +} + +// _isatty: 检查文件描述符是否指向TTY设备 +int _isatty(int file) +{ + return 1; // 表示是TTY设备 +} + +// _lseek: 用于重新定位文件读/写的位置 +off_t _lseek(int file, off_t offset, int whence) +{ + return -1; // 表示失败，因为不支持文件定位 +} + +// _read: 用于从文件描述符读取数据 +ssize_t _read(int file, void* ptr, size_t len) +{ + return 0; // 表示没有数据被读取 +} + +// _kill: 发送信号给进程 +int _kill(int pid, int sig) +{ + return -1; // 表示失败，因为不支持信号 +} + +// _getpid: 获取进程ID +int _getpid() +{ + return 1; // 返回假设的进程ID +} From 301073476f40f3347be673f1caeb1fcf02f58770 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Mon, 13 Jan 2025 17:25:23 +0800 Subject: [PATCH 30/54] Modify uart address in service --- Ubiquitous/XiZi_AIoT/services/boards/jh7110/libserial.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/services/boards/jh7110/libserial.c b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/libserial.c index 15c5dbd2a..fcc87026a 100644 --- a/Ubiquitous/XiZi_AIoT/services/boards/jh7110/libserial.c +++ b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/libserial.c @@ -181,7 +181,7 @@ typedef struct NS16550* NS16550_t; /* useful defaults for LCR */ #define UART_LCR_8N1 0x03 -#define UART_ADDR (0xFE660000) +#define UART_ADDR (0x10000000) #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ #define UART_MCRVAL (UART_MCR_DTR | UART_MCR_RTS) /* RTS/DTR */ From ee49e0d71c691367a7be6a041e3144a9d48c40d5 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Mon, 13 Jan 2025 18:02:32 +0800 Subject: [PATCH 31/54] Modify handle_exception according to the Linux code --- .../hardkernel/intr/riscv/rv64gc/Makefile | 5 +- .../hardkernel/intr/riscv/rv64gc/entry.S | 139 ---------- .../intr/riscv/rv64gc/jh7110/trap.c | 24 +- .../intr/riscv/rv64gc/jh7110/trap_common.c | 9 +- .../hardkernel/intr/riscv/rv64gc/trampoline.S | 256 +++++++++++++----- 5 files changed, 212 insertions(+), 221 deletions(-) delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/entry.S diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile index 8849513ae..8aaf42053 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile @@ -1,4 +1,4 @@ -SRC_FILES := entry.S trampoline.S $(BOARD)/trap_common.c $(BOARD)/trap.c $(BOARD)/plic.c error_debug.c hard_spinlock.S +SRC_FILES := trampoline.S $(BOARD)/trap_common.c $(BOARD)/trap.c $(BOARD)/plic.c error_debug.c hard_spinlock.S ifeq ($(BOARD), jh7110) SRC_DIR := gicv3 @@ -6,4 +6,5 @@ SRC_FILES += $(BOARD)/ endif -include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file +include $(KERNEL_ROOT)/compiler.mk + diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/entry.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/entry.S deleted file mode 100644 index 177610739..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/entry.S +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -/** - * @file entry.S - * @brief trap in and out code - * @version 1.0 - * @author AIIT XUOS Lab - * @date 2024-12-10 - */ - -/************************************************* -File name: entry.S -Description: trap in and out code -Others: -History: -1. Date: 2024-12-10 -Author: AIIT XUOS Lab -Modification: -1. first version -*************************************************/ - -#include "asm/asm-offsets.h" - -.macro kernel_entry - addi sp, sp, -(PT_SIZE) - - sd x1, PT_RA(sp) - sd x3, PT_GP(sp) - sd x5, PT_T0(sp) - sd x6, PT_T1(sp) - sd x7, PT_T2(sp) - sd x8, PT_S0(sp) - sd x9, PT_S1(sp) - sd x10, PT_A0(sp) - sd x11, PT_A1(sp) - sd x12, PT_A2(sp) - sd x13, PT_A3(sp) - sd x14, PT_A4(sp) - sd x15, PT_A5(sp) - sd x16, PT_A6(sp) - sd x17, PT_A7(sp) - sd x18, PT_S2(sp) - sd x19, PT_S3(sp) - sd x20, PT_S4(sp) - sd x21, PT_S5(sp) - sd x22, PT_S6(sp) - sd x23, PT_S7(sp) - sd x24, PT_S8(sp) - sd x25, PT_S9(sp) - sd x26, PT_S10(sp) - sd x27, PT_S11(sp) - sd x28, PT_T3(sp) - sd x29, PT_T4(sp) - sd x30, PT_T5(sp) - sd x31, PT_T6(sp) - - csrr s2, sepc - sd s2, PT_EPC(sp) - csrr s3, sbadaddr - sd s3, PT_BADADDR(sp) - csrr s4, scause - sd s4, PT_CAUSE(sp) - csrr s5, sscratch - sd s5, PT_TP(sp) - - addi s0, sp, PT_SIZE - sd sp, PT_SP(sp) -.endm - - -.macro kernel_exit - ld a0, PT_STATUS(sp) - csrw sstatus, a0 - ld a2, PT_EPC(sp) - csrw sepc, a2 - - ld x1, PT_RA(sp) - ld x3, PT_GP(sp) - ld x5, PT_T0(sp) - ld x6, PT_T1(sp) - ld x7, PT_T2(sp) - ld x8, PT_S0(sp) - ld x9, PT_S1(sp) - ld x10, PT_A0(sp) - ld x11, PT_A1(sp) - ld x12, PT_A2(sp) - ld x13, PT_A3(sp) - ld x14, PT_A4(sp) - ld x15, PT_A5(sp) - ld x16, PT_A6(sp) - ld x17, PT_A7(sp) - ld x18, PT_S2(sp) - ld x19, PT_S3(sp) - ld x20, PT_S4(sp) - ld x21, PT_S5(sp) - ld x22, PT_S6(sp) - ld x23, PT_S7(sp) - ld x24, PT_S8(sp) - ld x25, PT_S9(sp) - ld x26, PT_S10(sp) - ld x27, PT_S11(sp) - ld x28, PT_T3(sp) - ld x29, PT_T4(sp) - ld x30, PT_T5(sp) - ld x31, PT_T6(sp) - - ld x2, PT_SP(sp) -.endm - - - -.align 4 - .global do_exception_vector -do_exception_vector: - kernel_entry - la ra, ret_from_exception - mv a0, sp /* pt_regs */ - mv a1, s4 - tail do_exception - -ret_from_exception: -restore_all: - kernel_exit - sret - -.global trigger_fault -trigger_fault: - li a0, 0x70000000 - ld a0, (a0) - ret diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c index c13d62a07..84bfdd01f 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c @@ -127,15 +127,24 @@ void syscall_arch_handler(struct trapframe* tf) -extern void do_exception_vector(void); +extern void handle_exception(void); void trap_init(void) { - csr_write(stvec, do_exception_vector); + csr_write(stvec, handle_exception); csr_write(sie, 0); + __asm__ volatile("csrw sscratch, zero" : : : "memory"); +#if 0 + printk("trap_init test\n"); + __asm__ volatile("ebreak"); + printk("trap_init test ok\n"); +#endif } - +void trap_set_exception_vector(uint64_t new_tbl_base) +{ + csr_write(stvec, new_tbl_base); +} static void do_trap_error(struct pt_regs *regs, const char *str) { @@ -225,7 +234,7 @@ void do_exception(struct pt_regs *regs, unsigned long scause) printk("%s, scause: 0x%lx\n", __func__, scause); if (scause & CAUSE_IRQ_FLAG) { - handle_irq(regs, scause); + intr_irq_dispatch((struct trapframe *)regs); } else { inf = ec_to_fault_info(scause); @@ -235,3 +244,10 @@ void do_exception(struct pt_regs *regs, unsigned long scause) } } + +#define INIT_THREAD_INFO \ +{ \ + .flags = 0, \ + .preempt_count = 1, \ +} +struct thread_info init_thread_info = INIT_THREAD_INFO; diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c index cc869a88a..1c9430251 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c @@ -41,6 +41,9 @@ Modification: static struct XiziTrapDriver xizi_trap_driver; +extern void trap_init(void); +extern void trap_set_exception_vector(uint64_t new_tbl_base); + void panic(char* s) { KPrintf("panic: %s\n", s); @@ -48,12 +51,9 @@ void panic(char* s) ; } -//extern void alltraps(); -extern void trap_init(void); static void _sys_irq_init(int cpu_id) { // primary core init intr -// xizi_trap_driver.switch_hw_irqtbl((uintptr_t*)alltraps); if (cpu_id == 0) { plic_init(); } @@ -90,8 +90,7 @@ static void _single_irq_disable(int irq, int cpu) static inline uintptr_t* _switch_hw_irqtbl(uintptr_t* new_tbl_base) { - w_vbar_el1((uint64_t)new_tbl_base); - + trap_set_exception_vector(new_tbl_base); return NULL; } diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S index f89a63bc0..0d6d12b54 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S @@ -29,84 +29,198 @@ Modification: *************************************************/ #include "memlayout.h" - #include "core.h" - -.macro savereg - -.endm - -.macro restorereg - -.endm - -.macro usavereg - -.endm - -.macro urestorereg - -.endm +#include "asm/csr.h" +#include "asm/asm-offsets.h" -.global alltraps -.balign 0x800 -alltraps: -// Current EL with sp0 - j badtrap -.balign 0x80 - j badtrap -.balign 0x80 - j badtrap -.balign 0x80 - j badtrap +.align 4 + .global handle_exception +handle_exception: + csrrw tp, CSR_SCRATCH, tp + bnez tp, _save_context -// Current EL with spx -.balign 0x80 - j el1sync -.balign 0x80 - j el1irq -.balign 0x80 - j badtrap -.balign 0x80 - j badtrap +_restore_kernel_tpsp: + csrr tp, CSR_SCRATCH + REG_S sp, TASK_TI_KERNEL_SP(tp) -// Lower EL using aarch64 -.balign 0x80 - j el0sync -.balign 0x80 - j el0irq -.balign 0x80 - j badtrap -.balign 0x80 - j badtrap +_save_context: + REG_S sp, TASK_TI_USER_SP(tp) + REG_L sp, TASK_TI_KERNEL_SP(tp) + addi sp, sp, -(PT_SIZE_ON_STACK) + REG_S x1, PT_RA(sp) + REG_S x3, PT_GP(sp) + REG_S x5, PT_T0(sp) + REG_S x6, PT_T1(sp) + REG_S x7, PT_T2(sp) + REG_S x8, PT_S0(sp) + REG_S x9, PT_S1(sp) + REG_S x10, PT_A0(sp) + REG_S x11, PT_A1(sp) + REG_S x12, PT_A2(sp) + REG_S x13, PT_A3(sp) + REG_S x14, PT_A4(sp) + REG_S x15, PT_A5(sp) + REG_S x16, PT_A6(sp) + REG_S x17, PT_A7(sp) + REG_S x18, PT_S2(sp) + REG_S x19, PT_S3(sp) + REG_S x20, PT_S4(sp) + REG_S x21, PT_S5(sp) + REG_S x22, PT_S6(sp) + REG_S x23, PT_S7(sp) + REG_S x24, PT_S8(sp) + REG_S x25, PT_S9(sp) + REG_S x26, PT_S10(sp) + REG_S x27, PT_S11(sp) + REG_S x28, PT_T3(sp) + REG_S x29, PT_T4(sp) + REG_S x30, PT_T5(sp) + REG_S x31, PT_T6(sp) -// Lower EL using aarch32 -.balign 0x80 - j badtrap -.balign 0x80 - j badtrap -.balign 0x80 - j badtrap -.balign 0x80 - j badtrap + /* + * Disable user-mode memory access as it should only be set in the + * actual user copy routines. + * + * Disable the FPU to detect illegal usage of floating point in kernel + * space. + */ + li t0, SR_SUM | SR_FS -badtrap: - j . + REG_L s0, TASK_TI_USER_SP(tp) + csrrc s1, CSR_STATUS, t0 + csrr s2, CSR_EPC + csrr s3, CSR_TVAL + csrr s4, CSR_CAUSE + csrr s5, CSR_SCRATCH + REG_S s0, PT_SP(sp) + REG_S s1, PT_STATUS(sp) + REG_S s2, PT_EPC(sp) + REG_S s3, PT_BADADDR(sp) + REG_S s4, PT_CAUSE(sp) + REG_S s5, PT_TP(sp) -el1sync: - j . - -el1irq: - ret - -el0sync: + /* + * Set the scratch register to 0, so that if a recursive exception + * occurs, the exception vector knows it came from the kernel + */ + csrw CSR_SCRATCH, x0 - ret + /* Load the global pointer */ +.option push +.option norelax + la gp, __global_pointer$ +.option pop -el0irq: - jal intr_irq_dispatch - -.global trap_return -trap_return: - ret + /* + * MSB of cause differentiates between + * interrupts and exceptions + */ + bge s4, zero, 1f + + la ra, ret_from_exception + + /* Handle interrupts */ + move a0, sp /* pt_regs */ + //la a1, handle_arch_irq + la a1, intr_irq_dispatch + REG_L a1, (a1) + jr a1 + +1: + /* + * Exceptions run with interrupts enabled or disabled depending on the + * state of SR_PIE in m/sstatus. + */ + andi t0, s1, SR_PIE + beqz t0, 1f + /* kprobes, entered via ebreak, must have interrupts disabled. */ + li t0, EXC_BREAKPOINT + beq s4, t0, 1f + + csrs CSR_STATUS, SR_IE + +1: + la ra, ret_from_exception + /* Handle syscalls */ + li t0, EXC_SYSCALL + beq s4, t0, handle_syscall + + mv a0, sp + mv a1, s4 + tail do_exception + +handle_syscall: + j . + + +ret_from_exception: + REG_L s0, PT_STATUS(sp) + csrc CSR_STATUS, SR_IE + + andi s0, s0, SR_SPP + bnez s0, resume_kernel + +resume_userspace: + /* Save unwound kernel stack pointer in thread_info */ + addi s0, sp, PT_SIZE_ON_STACK + REG_S s0, TASK_TI_KERNEL_SP(tp) + + /* + * Save TP into the scratch register , so we can find the kernel data + * structures again. + */ + csrw CSR_SCRATCH, tp + +restore_all: + REG_L a0, PT_STATUS(sp) + + REG_L a2, PT_EPC(sp) + REG_SC x0, a2, PT_EPC(sp) + + csrw CSR_STATUS, a0 + csrw CSR_EPC, a2 + + REG_L x1, PT_RA(sp) + REG_L x3, PT_GP(sp) + REG_L x4, PT_TP(sp) + REG_L x5, PT_T0(sp) + REG_L x6, PT_T1(sp) + REG_L x7, PT_T2(sp) + REG_L x8, PT_S0(sp) + REG_L x9, PT_S1(sp) + REG_L x10, PT_A0(sp) + REG_L x11, PT_A1(sp) + REG_L x12, PT_A2(sp) + REG_L x13, PT_A3(sp) + REG_L x14, PT_A4(sp) + REG_L x15, PT_A5(sp) + REG_L x16, PT_A6(sp) + REG_L x17, PT_A7(sp) + REG_L x18, PT_S2(sp) + REG_L x19, PT_S3(sp) + REG_L x20, PT_S4(sp) + REG_L x21, PT_S5(sp) + REG_L x22, PT_S6(sp) + REG_L x23, PT_S7(sp) + REG_L x24, PT_S8(sp) + REG_L x25, PT_S9(sp) + REG_L x26, PT_S10(sp) + REG_L x27, PT_S11(sp) + REG_L x28, PT_T3(sp) + REG_L x29, PT_T4(sp) + REG_L x30, PT_T5(sp) + REG_L x31, PT_T6(sp) + + REG_L x2, PT_SP(sp) + + sret + +resume_kernel: + j restore_all + + +.global task_prepare_enter +task_prepare_enter: + call xizi_leave_kernel + j ret_from_exception From 1631e60baa8f5a1149eb7fb978f738423fa1aa55 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Mon, 13 Jan 2025 19:58:37 +0800 Subject: [PATCH 32/54] Modify context and trapframe init --- .../hardkernel/arch/riscv/rv64gc/core.h | 21 ++++++++++++++++--- .../riscv/rv64gc/preboot_for_jh7110/boot.S | 7 ++++++- .../XiZi_AIoT/softkernel/syscall/sys_thread.c | 4 ++++ Ubiquitous/XiZi_AIoT/softkernel/task/task.c | 10 +++++---- 4 files changed, 34 insertions(+), 8 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h index 146367454..d52b8dafb 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h @@ -72,10 +72,11 @@ Modification: #include #include "cortex.h" +#include "asm/csr.h" + #define NR_CPU 1 // maximum number of CPUs -#define SSTATUS_SPP (1L << 8) // Previous mode, 1=Supervisor, 0=User __attribute__((always_inline)) static inline uint64_t EL0_mode() // Set ARM mode to EL0 { @@ -113,10 +114,14 @@ struct context { /// @brief init task context, set return address to trap return /// @param ctx extern void task_prepare_enter(void); -__attribute__((__always_inline__)) static inline void arch_init_context(struct context* ctx, unsigned long sp) +__attribute__((__always_inline__)) static inline void arch_init_context(struct context* ctx) { memset(ctx, 0, sizeof(*ctx)); ctx->ra = (uintptr_t)(task_prepare_enter); +} + +__attribute__((__always_inline__)) static inline void arch_context_set_sp(struct context* ctx, unsigned long sp) +{ ctx->sp = sp; } @@ -171,7 +176,7 @@ __attribute__((__always_inline__)) static inline void arch_init_trapframe(struct memset(tf, 0, sizeof(*tf)); tf->sp = sp; tf->epc = pc; - tf->status &= ~SSTATUS_SPP; // clear SPP to 0 for user mode + tf->status = SR_PIE; } /// @brief set pc and sp to trapframe @@ -218,6 +223,16 @@ __attribute__((__always_inline__)) static inline void arch_set_return(struct tra tf->a0 = (uint64_t)ret; } +// TODO: refer to jh7110 Linux +struct thread_info { + unsigned long flags; /* low level flags */ + int preempt_count; /* 0=>preemptible, <0=>BUG */ + long kernel_sp; /* Kernel stack pointer */ + long user_sp; /* User stack pointer */ + int cpu; +}; + + void cpu_start_secondary(uint8_t cpu_id); void start_smp_cache_broadcast(int cpu_id); #endif diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S index 7936bc59f..089df000e 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S @@ -44,6 +44,7 @@ clear_bss: blt a3, a4, clear_bss clear_bss_done: + li a0, 1 la a2, boot_cpu_hartid sd a0, (a2) @@ -58,10 +59,14 @@ clear_bss_done: call _debug_uart_init + /* Restore C environment */ + la tp, init_thread_info + sw zero, TASK_TI_CPU(tp) + la sp, init_thread_union + THREAD_SIZE + /* Start the kernel */ tail bootmain - relocate_enable_mmu: /* Relocate return address */ la a1, kernel_map diff --git a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_thread.c b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_thread.c index f98ed1c81..7560f8afa 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_thread.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_thread.c @@ -53,6 +53,10 @@ int sys_new_thread(struct MemSpace* pmemspace, struct Thread* task, uintptr_t en arch_trapframe_set_sp_pc(task->thread_context.trapframe, loaded_sp.user_sp, (uintptr_t)entry); arch_set_main_params(task->thread_context.trapframe, loaded_sp.argc, loaded_sp.user_sp); +#ifdef __riscv + arch_context_set_sp(task->thread_context.context, (uintptr_t)task->thread_context.trapframe); +#endif + // init thread name char* last = NULL; for (last = name; *name; name++) { diff --git a/Ubiquitous/XiZi_AIoT/softkernel/task/task.c b/Ubiquitous/XiZi_AIoT/softkernel/task/task.c index 4696a2c42..06354eb99 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/task/task.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/task/task.c @@ -207,6 +207,7 @@ static void _dealloc_task_cb(struct Thread* task) slab_free(&xizi_task_manager.task_allocator, (void*)task); } +#ifndef __riscv /* alloc a new task with init */ extern void trap_return(void); __attribute__((optimize("O0"))) void task_prepare_enter() @@ -215,6 +216,7 @@ __attribute__((optimize("O0"))) void task_prepare_enter() xizi_leave_kernel(); trap_return(); } +#endif static struct Thread* _new_task_cb(struct MemSpace* pmemspace) { @@ -251,7 +253,11 @@ static struct Thread* _new_task_cb(struct MemSpace* pmemspace) /* set context of main thread stack */ /// stack bottom memset((void*)task->thread_context.kern_stack_addr, 0x00, USER_STACK_SIZE); +#ifndef __riscv char* sp = (char*)task->thread_context.kern_stack_addr + USER_STACK_SIZE - 4; +#else + char* sp = (char*)task->thread_context.kern_stack_addr + USER_STACK_SIZE; +#endif /// 1. trap frame into stack, for process to nomally return by trap_return sp -= sizeof(*task->thread_context.trapframe); @@ -260,11 +266,7 @@ static struct Thread* _new_task_cb(struct MemSpace* pmemspace) /// 2. context into stack sp -= sizeof(*task->thread_context.context); task->thread_context.context = (struct context*)sp; -#ifndef __riscv arch_init_context(task->thread_context.context); -#else - arch_init_context(task->thread_context.context, task->thread_context.kern_stack_addr); -#endif return task; } From 5190dadd120505774f2ee3b34561c4f3de2bc543 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 15 Jan 2025 17:06:57 +0800 Subject: [PATCH 33/54] Modify syscall --- .../hardkernel/arch/riscv/rv64gc/core.h | 4 +- .../intr/riscv/rv64gc/jh7110/trap.c | 32 +++------------ .../hardkernel/intr/riscv/rv64gc/trampoline.S | 36 +++++++++++++++- .../services/boards/jh7110/arch_usyscall.c | 41 ++++++++++++------- .../XiZi_AIoT/softkernel/syscall/sys_state.c | 5 +++ 5 files changed, 73 insertions(+), 45 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h index d52b8dafb..21a86db89 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h @@ -211,8 +211,8 @@ extern int syscall(int sys_num, uintptr_t param1, uintptr_t param2, uintptr_t pa __attribute__((__always_inline__)) static inline int arch_syscall(struct trapframe* tf, int* syscall_num) { // call syscall - *syscall_num = tf->a0; - return syscall(*syscall_num, tf->a1, tf->a2, tf->a3, tf->a4); + *syscall_num = tf->a7; + return syscall(*syscall_num, tf->a0, tf->a1, tf->a2, tf->a3); } /// @brief set return reg to trapframe diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c index 84bfdd01f..3a1a4c8db 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c @@ -78,42 +78,20 @@ void kernel_intr_handler(struct trapframe* tf) extern void context_switch(struct context**, struct context*); void syscall_arch_handler(struct trapframe* tf) { + uint64_t ec = tf->cause; - uint64_t esr = r_esr_el1(); - uint64_t ec = (esr >> 0x1A) & 0x3F; switch (ec) { - case 0B010101: + case EXC_SYSCALL: software_irq_dispatch(tf); break; - case 0b100100: - case 0b100101: - dabort_handler(tf); - break; - case 0b100000: - case 0b100001: - iabort_handler(tf); - break; + default: { ERROR("USYSCALL: unexpected\n"); - ERROR(" esr: %016lx\n", esr); - ERROR(" elr = %016lx far = %016lx\n", r_elr_el1(), r_far_el1()); - w_esr_el1(0); + ERROR("tf->cause: %016lx\n", tf->cause); + extern void dump_tf(struct trapframe * tf); dump_tf(tf); - uint32_t sctlr = 0; - SCTLR_R(sctlr); - DEBUG("SCTLR: %x\n", sctlr); - uint32_t spsr = 0; -// __asm__ volatile("mrs %0, spsr_el1" : "=r"(spsr)::"memory"); - DEBUG("SPSR: %x\n", spsr); - uint64_t tcr = 0; -// __asm__ volatile("mrs %0, tcr_el1" : "=r"(tcr)::"memory"); - DEBUG("TCR: %x\n", tcr); - uint64_t mair = 0; -// __asm__ volatile("mrs %0, mair_el1" : "=r"(mair)::"memory"); - DEBUG("MAIR: %x\n", mair); - // kill error task xizi_enter_kernel(); assert(cur_cpu()->task != NULL); diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S index 0d6d12b54..c8c2ce3fa 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S @@ -151,7 +151,41 @@ _save_context: tail do_exception handle_syscall: - j . + /* save the initial A0 value (needed in signal handlers) */ + REG_S a0, PT_ORIG_A0(sp) + /* + * Advance SEPC to avoid executing the original + * scall instruction on sret + */ + addi s2, s2, 0x4 + REG_S s2, PT_EPC(sp) + + /* Trace syscalls, but only if requested by the user. */ + j handle_syscall_trace_enter + + ret + + +/* Slow paths for ptrace. */ +handle_syscall_trace_enter: + move a0, sp + //call do_syscall_trace_enter + call syscall_arch_handler + move t0, a0 + REG_L a0, PT_A0(sp) + REG_L a1, PT_A1(sp) + REG_L a2, PT_A2(sp) + REG_L a3, PT_A3(sp) + REG_L a4, PT_A4(sp) + REG_L a5, PT_A5(sp) + REG_L a6, PT_A6(sp) + REG_L a7, PT_A7(sp) + //bnez t0, ret_from_syscall_rejected + //j check_syscall_nr +handle_syscall_trace_exit: + move a0, sp + //call do_syscall_trace_exit + j ret_from_exception ret_from_exception: diff --git a/Ubiquitous/XiZi_AIoT/services/boards/jh7110/arch_usyscall.c b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/arch_usyscall.c index 4f9eceb3c..9b2d788d6 100644 --- a/Ubiquitous/XiZi_AIoT/services/boards/jh7110/arch_usyscall.c +++ b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/arch_usyscall.c @@ -11,22 +11,33 @@ */ #include "usyscall.h" +int sbi_ecall(int ext, int fid, unsigned long arg0, + unsigned long arg1, unsigned long arg2, + unsigned long arg3, unsigned long arg4, + unsigned long arg5) +{ + int ret; + + register uintptr_t a0 __asm__ ("a0") = (uintptr_t)(arg0); + register uintptr_t a1 __asm__ ("a1") = (uintptr_t)(arg1); + register uintptr_t a2 __asm__ ("a2") = (uintptr_t)(arg2); + register uintptr_t a3 __asm__ ("a3") = (uintptr_t)(arg3); + register uintptr_t a4 __asm__ ("a4") = (uintptr_t)(arg4); + register uintptr_t a5 __asm__ ("a5") = (uintptr_t)(arg5); + register uintptr_t a6 __asm__ ("a6") = (uintptr_t)(fid); + register uintptr_t a7 __asm__ ("a7") = (uintptr_t)(ext); + __asm__ volatile ("ecall" + : "+r" (a0), "+r" (a1) + : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7) + : "memory"); + ret = a0; + + return ret; +} + int syscall(int sys_num, intptr_t a1, intptr_t a2, intptr_t a3, intptr_t a4) { int ret = -1; - - __asm__ volatile( - "mv a0, %1;\ - mv a1, %2;\ - mv a2, %3;\ - mv a3, %4;\ - mv a4, %5;\ - ecall;\ - mv %0, a0" - : "=r"(ret) - : "r"(sys_num), "r"(a1), "r"(a2), "r"(a3), "r"(a4) - : "memory", "a0", "a1", "a2", "a3", "a4" - ); - + ret = sbi_ecall(sys_num, 0, a1, a2, a3, a4, 0, 0); return ret; -} \ No newline at end of file +} diff --git a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c index 67aea6b05..6f672a1bb 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c @@ -153,8 +153,13 @@ int sys_state(sys_state_option option, sys_state_info* info) { switch (option) { case SYS_STATE_MEMBLOCK_INFO: { +#ifndef __riscv info->memblock_info.memblock_start = (uintptr_t)V2P(_binary_fs_img_start); info->memblock_info.memblock_end = (uintptr_t)V2P(_binary_fs_img_end); +#else + info->memblock_info.memblock_start = (uintptr_t)V2P_LINK(_binary_fs_img_start); + info->memblock_info.memblock_end = (uintptr_t)V2P_LINK(_binary_fs_img_end); +#endif break; } case SYS_STATE_GET_HEAP_BASE: From b8c77c57587116fe17029919505725e33e884a50 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 16 Jan 2025 16:16:03 +0800 Subject: [PATCH 34/54] S-mode to access the memory of U-mode in the riscv --- .../hardkernel/intr/riscv/rv64gc/trampoline.S | 10 ++++++++ .../softkernel/memory/pagetable_riscv.c | 23 ++++++++++++++++++- .../XiZi_AIoT/softkernel/task/memspace.c | 4 ++++ Ubiquitous/XiZi_AIoT/softkernel/task/task.c | 9 ++++++++ 4 files changed, 45 insertions(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S index c8c2ce3fa..44fac5f1e 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S @@ -168,6 +168,12 @@ handle_syscall: /* Slow paths for ptrace. */ handle_syscall_trace_enter: + csrr s0, satp + la a0, riscv_kernel_satp + ld a0, 0(a0) + csrw satp, a0 + sfence.vma + move a0, sp //call do_syscall_trace_enter call syscall_arch_handler @@ -185,6 +191,10 @@ handle_syscall_trace_enter: handle_syscall_trace_exit: move a0, sp //call do_syscall_trace_exit + + csrw satp, s0 + sfence.vma + j ret_from_exception diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c index f07a67660..bfc173b36 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c @@ -127,6 +127,8 @@ static bool _unmap_pages(uintptr_t* pgdir, uintptr_t vaddr, int len) /// @return static bool _map_user_pages(struct MemSpace* pmemspace, uintptr_t vaddr, uintptr_t paddr, int len, bool is_dev) { + bool ret; + if (len < 0) { return false; } @@ -143,7 +145,26 @@ static bool _map_user_pages(struct MemSpace* pmemspace, uintptr_t vaddr, uintptr _p_pgtbl_mmu_access->MmuUsrDevPteAttr(&mem_attr); } - return _map_pages(pmemspace->pgdir.pd_addr, vaddr, paddr, (intptr_t)len, mem_attr); + ret = _map_pages(pmemspace->pgdir.pd_addr, vaddr, paddr, (intptr_t)len, mem_attr); + if (ret == false) { + ERROR("mapping _map_pages fail.\n"); + return false; + } + + // In order for the S-mode to access the memory of the U-mode, in the riscv architecture. + if (LIKELY(!is_dev)) { + _p_pgtbl_mmu_access->MmuKernPteAttr(&mem_attr); + } else { + _p_pgtbl_mmu_access->MmuDevPteAttr(&mem_attr); + } + + ret = _map_pages(pmemspace->pgdir_riscv.pd_addr, vaddr, paddr, (intptr_t)len, mem_attr); + if (ret == false) { + ERROR("mapping _map_pages riscv fail.\n"); + return false; + } + + return true; } /// assume that a user pagedir is allocated from [0, size) diff --git a/Ubiquitous/XiZi_AIoT/softkernel/task/memspace.c b/Ubiquitous/XiZi_AIoT/softkernel/task/memspace.c index 3fce45d05..8c906d1bd 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/task/memspace.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/task/memspace.c @@ -120,6 +120,10 @@ uintptr_t* load_memspace(struct MemSpace* pmemspace, char* img_start) } /* copy kernel pagetable so that interrupt and syscall wont corrupt */ memcpy(pmemspace->pgdir.pd_addr, kern_pgdir.pd_addr, TOPLEVLE_PAGEDIR_SIZE); +#ifdef __riscv + xizi_pager.new_pgdir(&pmemspace->pgdir_riscv); + memcpy(pmemspace->pgdir_riscv.pd_addr, kern_pgdir.pd_addr, TOPLEVLE_PAGEDIR_SIZE); +#endif // read elf file by (header, section) uintptr_t load_size = 0; diff --git a/Ubiquitous/XiZi_AIoT/softkernel/task/task.c b/Ubiquitous/XiZi_AIoT/softkernel/task/task.c index 06354eb99..527752d00 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/task/task.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/task/task.c @@ -288,6 +288,9 @@ static void task_state_set_running(struct Thread* task) doubleListAddOnHead(&task->node, &xizi_task_manager.task_running_list_head); } +#ifdef __riscv +uintptr_t riscv_kernel_satp = 0; +#endif struct Thread* next_task_emergency = NULL; extern void context_switch(struct context**, struct context*); static void _scheduler(struct SchedulerRightGroup right_group) @@ -318,8 +321,14 @@ static void _scheduler(struct SchedulerRightGroup right_group) /* run the chosen task */ task_state_set_running(next_task); cpu->task = next_task; + +#ifdef __riscv + riscv_kernel_satp = PFN_DOWN((uintptr_t)V2P(next_task->memspace->pgdir_riscv.pd_addr)) | SATP_MODE; +#endif + assert(next_task->memspace->pgdir.pd_addr != NULL); p_mmu_driver->LoadPgdir((uintptr_t)V2P(next_task->memspace->pgdir.pd_addr)); + context_switch(&cpu->scheduler, next_task->thread_context.context); assert(next_task->state != RUNNING); } From eb5f73251c8a2c240a6b328a7e7dcf5019e0a903 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 16 Jan 2025 20:14:00 +0800 Subject: [PATCH 35/54] Modify context_switch parameters --- .../XiZi_AIoT/softkernel/trap/software_irq_handler.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/softkernel/trap/software_irq_handler.c b/Ubiquitous/XiZi_AIoT/softkernel/trap/software_irq_handler.c index 25c4bd1de..4c1902a45 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/trap/software_irq_handler.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/trap/software_irq_handler.c @@ -52,21 +52,24 @@ void software_irq_dispatch(struct trapframe* tf) assert(p_intr_driver != NULL); // get current task + struct CPU* cpu = cur_cpu(); struct Thread* cur_task = cur_cpu()->task; /// @todo: Handle dead task - int syscall_num = -1; if (cur_task && cur_task->state != DEAD) { cur_task->thread_context.trapframe = tf; // call syscall - int ret = arch_syscall(cur_task->thread_context.trapframe, &syscall_num); arch_set_return(tf, ret); } if ((cur_cpu()->task == NULL && cur_task != NULL) || cur_task->state != RUNNING) { cur_cpu()->task = NULL; +#ifndef __riscv context_switch(&cur_task->thread_context.context, cur_cpu()->scheduler); +#else + context_switch(&cur_task->thread_context.context, &cpu->scheduler); +#endif } if (syscall_num == SYSCALL_EXIT) { panic("Exit reaches"); @@ -74,4 +77,4 @@ void software_irq_dispatch(struct trapframe* tf) assert(cur_task == cur_cpu()->task); xizi_leave_kernel(); -} \ No newline at end of file +} From 675da41f027e5fffe8a86d0b086d5451b53d6ec3 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 17 Jan 2025 17:17:01 +0800 Subject: [PATCH 36/54] Modify user print --- Ubiquitous/XiZi_AIoT/services/app/shell_port.c | 1 + .../XiZi_AIoT/services/boards/jh7110/libserial.c | 10 +++++----- .../XiZi_AIoT/services/shell/letter-shell/shell.c | 3 +++ 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/app/shell_port.c b/Ubiquitous/XiZi_AIoT/services/app/shell_port.c index 7f9c286c4..69164a88f 100644 --- a/Ubiquitous/XiZi_AIoT/services/app/shell_port.c +++ b/Ubiquitous/XiZi_AIoT/services/app/shell_port.c @@ -49,6 +49,7 @@ int main(void) shell.read = userShellRead; shellInit(&shell, shellBuffer, 512); + printf("shell init\n"); while (connect_session(&session_fs, "MemFS", 0x10000) < 0) ; diff --git a/Ubiquitous/XiZi_AIoT/services/boards/jh7110/libserial.c b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/libserial.c index fcc87026a..409ce5f13 100644 --- a/Ubiquitous/XiZi_AIoT/services/boards/jh7110/libserial.c +++ b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/libserial.c @@ -216,19 +216,19 @@ static inline int serial_in_shift(void* addr, int shift) bool init_uart_mmio() { - static int mapped = 0; - if (mapped == 0) { + static int mapped = 0xff; + if (mapped != 0) { if (-1 == mmap(UART_ADDR, UART_ADDR, 4096, true)) { return false; } - mapped = 1; + mapped = 0; } return true; } void putc(char ch) { - static struct NS16550* com_port = (struct NS16550*)UART_ADDR; + struct NS16550* com_port = (struct NS16550*)UART_ADDR; if (ch == '\n') { putc('\r'); @@ -241,7 +241,7 @@ void putc(char ch) char getc(void) { - static struct NS16550* com_port = (struct NS16550*)UART_ADDR; + struct NS16550* com_port = (struct NS16550*)UART_ADDR; while (!(serial_din(&com_port->lsr) & UART_LSR_DR)) ; diff --git a/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/shell.c b/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/shell.c index 34b99616e..ec1ff011b 100644 --- a/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/shell.c +++ b/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/shell.c @@ -203,6 +203,7 @@ void shellInit(Shell* shell, char* buffer, unsigned short size) shellAdd(shell); shellSetUser(shell, shellSeekCommand(shell, SHELL_DEFAULT_USER, shell->commandList.base, 0)); + shellWritePrompt(shell, 1); } @@ -322,9 +323,11 @@ static void shellWritePrompt(Shell* shell, unsigned char newline) if (newline) { shellWriteString(shell, "\r\n"); } +#ifndef __riscv shellWriteString(shell, shell->info.user->data.user.name); shellWriteString(shell, ":"); shellWriteString(shell, shell->info.path ? shell->info.path : "/"); +#endif shellWriteString(shell, "$ "); } else { shellWriteString(shell, shellText[SHELL_TEXT_PASSWORD_HINT]); From b03330f0f81386b0f40dc3e8fb6720521a772188 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 17 Jan 2025 18:56:37 +0800 Subject: [PATCH 37/54] Modify MemSpace for riscv --- Ubiquitous/XiZi_AIoT/softkernel/include/memspace.h | 1 + 1 file changed, 1 insertion(+) diff --git a/Ubiquitous/XiZi_AIoT/softkernel/include/memspace.h b/Ubiquitous/XiZi_AIoT/softkernel/include/memspace.h index 44cc9575c..9c63a20c4 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/include/memspace.h +++ b/Ubiquitous/XiZi_AIoT/softkernel/include/memspace.h @@ -50,6 +50,7 @@ struct MemSpace { TraceTag tag; /* task memory resources */ struct TopLevelPageDirectory pgdir; // [phy] vm pgtbl base address + struct TopLevelPageDirectory pgdir_riscv; // [phy] vm pgtbl base address uintptr_t heap_base; // mem size of proc used(allocated by kernel) uintptr_t mem_size; /* task communication mem resources */ From 994145bd63dd8d723b739b443818467ae570624a Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 17 Jan 2025 19:23:34 +0800 Subject: [PATCH 38/54] Modify CPU context scheduler --- .../hardkernel/intr/riscv/rv64gc/jh7110/trap.c | 4 ++-- Ubiquitous/XiZi_AIoT/softkernel/include/multicores.h | 4 ++++ Ubiquitous/XiZi_AIoT/softkernel/task/task.c | 4 ++++ Ubiquitous/XiZi_AIoT/softkernel/trap/abort_handler.c | 12 ++++++++++++ .../XiZi_AIoT/softkernel/trap/default_irq_handler.c | 8 ++++++++ .../XiZi_AIoT/softkernel/trap/software_irq_handler.c | 6 +++++- 6 files changed, 35 insertions(+), 3 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c index 3a1a4c8db..32c66ca5c 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c @@ -75,7 +75,7 @@ void kernel_intr_handler(struct trapframe* tf) panic("Intr at kernel mode should never happen by design.\n"); } -extern void context_switch(struct context**, struct context*); +extern void context_switch(struct context*, struct context*); void syscall_arch_handler(struct trapframe* tf) { uint64_t ec = tf->cause; @@ -97,7 +97,7 @@ void syscall_arch_handler(struct trapframe* tf) assert(cur_cpu()->task != NULL); ERROR("Error Task: %s\n", cur_cpu()->task->name); sys_exit(cur_cpu()->task); - context_switch(&cur_cpu()->task->thread_context.context, cur_cpu()->scheduler); + context_switch(&cur_cpu()->task->thread_context.context, &cur_cpu()->scheduler); panic("dabort end should never be reashed.\n"); } } diff --git a/Ubiquitous/XiZi_AIoT/softkernel/include/multicores.h b/Ubiquitous/XiZi_AIoT/softkernel/include/multicores.h index 2b0765cc8..fcc9625e8 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/include/multicores.h +++ b/Ubiquitous/XiZi_AIoT/softkernel/include/multicores.h @@ -37,7 +37,11 @@ struct CPU { int cpuid; struct Thread* task; +#ifndef __riscv struct context* scheduler; +#else + struct context scheduler; +#endif }; extern struct CPU global_cpus[NR_CPU]; diff --git a/Ubiquitous/XiZi_AIoT/softkernel/task/task.c b/Ubiquitous/XiZi_AIoT/softkernel/task/task.c index 527752d00..6567dc599 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/task/task.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/task/task.c @@ -292,7 +292,11 @@ static void task_state_set_running(struct Thread* task) uintptr_t riscv_kernel_satp = 0; #endif struct Thread* next_task_emergency = NULL; +#ifndef __riscv extern void context_switch(struct context**, struct context*); +#else +extern void context_switch(struct context*, struct context*); +#endif static void _scheduler(struct SchedulerRightGroup right_group) { struct MmuCommonDone* p_mmu_driver = AchieveResource(&right_group.mmu_driver_tag); diff --git a/Ubiquitous/XiZi_AIoT/softkernel/trap/abort_handler.c b/Ubiquitous/XiZi_AIoT/softkernel/trap/abort_handler.c index 9cbc00a8a..5ddcd649f 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/trap/abort_handler.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/trap/abort_handler.c @@ -48,7 +48,11 @@ Modification: #include "syscall.h" #include "task.h" +#ifndef __riscv extern void context_switch(struct context**, struct context*); +#else +extern void context_switch(struct context*, struct context*); +#endif __attribute__((optimize("O0"))) void dabort_handler(struct trapframe* r) { #ifndef __riscv @@ -74,7 +78,11 @@ __attribute__((optimize("O0"))) void dabort_handler(struct trapframe* r) xizi_enter_kernel(); sys_exit(cur_task); assert(cur_cpu()->task == NULL); +#ifndef __riscv context_switch(&cur_task->thread_context.context, cur_cpu()->scheduler); +#else + context_switch(cur_task->thread_context.context, &cur_cpu()->scheduler); +#endif panic("dabort end should never be reashed.\n"); } @@ -103,6 +111,10 @@ __attribute__((optimize("O0"))) void iabort_handler(struct trapframe* r) xizi_enter_kernel(); sys_exit(cur_task); assert(cur_cpu()->task == NULL); +#ifndef __riscv context_switch(&cur_task->thread_context.context, cur_cpu()->scheduler); +#else + context_switch(cur_task->thread_context.context, &cur_cpu()->scheduler); +#endif panic("iabort end should never be reashed.\n"); } diff --git a/Ubiquitous/XiZi_AIoT/softkernel/trap/default_irq_handler.c b/Ubiquitous/XiZi_AIoT/softkernel/trap/default_irq_handler.c index baa3ae2de..07fe4dcef 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/trap/default_irq_handler.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/trap/default_irq_handler.c @@ -53,7 +53,11 @@ void default_interrupt_routine(int irq) ERROR("Interrupt %d has been asserted\n", irq); } +#ifndef __riscv extern void context_switch(struct context**, struct context*); +#else +extern void context_switch(struct context*, struct context*); +#endif void intr_irq_dispatch(struct trapframe* tf) { xizi_enter_kernel(); @@ -86,7 +90,11 @@ void intr_irq_dispatch(struct trapframe* tf) if (cur_cpu()->task == NULL || current_task->state != RUNNING) { cur_cpu()->task = NULL; +#ifndef __riscv context_switch(¤t_task->thread_context.context, cur_cpu()->scheduler); +#else + context_switch(current_task->thread_context.context, &cur_cpu()->scheduler); +#endif } assert(current_task == cur_cpu()->task); diff --git a/Ubiquitous/XiZi_AIoT/softkernel/trap/software_irq_handler.c b/Ubiquitous/XiZi_AIoT/softkernel/trap/software_irq_handler.c index 4c1902a45..276f0e034 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/trap/software_irq_handler.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/trap/software_irq_handler.c @@ -45,7 +45,11 @@ bool swi_distributer_init(struct SwiDispatcherRightGroup* _right_group) return p_intr_driver != NULL; } +#ifndef __riscv extern void context_switch(struct context**, struct context*); +#else +extern void context_switch(struct context*, struct context*); +#endif void software_irq_dispatch(struct trapframe* tf) { xizi_enter_kernel(); @@ -68,7 +72,7 @@ void software_irq_dispatch(struct trapframe* tf) #ifndef __riscv context_switch(&cur_task->thread_context.context, cur_cpu()->scheduler); #else - context_switch(&cur_task->thread_context.context, &cpu->scheduler); + context_switch(cur_task->thread_context.context, &cpu->scheduler); #endif } if (syscall_num == SYSCALL_EXIT) { From f872eaea25eaa7027862991745cc8f04e558cd03 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Fri, 17 Jan 2025 20:33:08 +0800 Subject: [PATCH 39/54] Modify build --- Ubiquitous/XiZi_AIoT/softkernel/trap/software_irq_handler.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Ubiquitous/XiZi_AIoT/softkernel/trap/software_irq_handler.c b/Ubiquitous/XiZi_AIoT/softkernel/trap/software_irq_handler.c index 276f0e034..6b9ce865c 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/trap/software_irq_handler.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/trap/software_irq_handler.c @@ -56,7 +56,6 @@ void software_irq_dispatch(struct trapframe* tf) assert(p_intr_driver != NULL); // get current task - struct CPU* cpu = cur_cpu(); struct Thread* cur_task = cur_cpu()->task; /// @todo: Handle dead task int syscall_num = -1; @@ -72,6 +71,7 @@ void software_irq_dispatch(struct trapframe* tf) #ifndef __riscv context_switch(&cur_task->thread_context.context, cur_cpu()->scheduler); #else + struct CPU* cpu = cur_cpu(); context_switch(cur_task->thread_context.context, &cpu->scheduler); #endif } From 6176717125bbe12c7b08e72c0592b819595ee761 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Mon, 20 Jan 2025 10:58:09 +0800 Subject: [PATCH 40/54] Fixed non-zero global variable issue in kernel --- .../arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds index f3630b83c..93f0e549e 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds @@ -85,6 +85,7 @@ SECTIONS PROVIDE(boot_end_addr = .); } +. = ALIGN(0x1000); .text : { . = ALIGN(0x1000); *(.text .text.*) @@ -92,6 +93,9 @@ SECTIONS . = ALIGN(0x1000); .data : { + . = ALIGN(16); + *(.sdata .sdata.*) + . = ALIGN(16); *(.data .data.*) __start_init_task = .; From 619b32ad499e3edb0162f81878934e6463a0c505 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 21 Jan 2025 09:46:53 +0800 Subject: [PATCH 41/54] Modify user build cflags and lds --- Ubiquitous/XiZi_AIoT/services/app/Makefile | 8 +- .../XiZi_AIoT/services/boards/jh7110/Makefile | 3 +- .../services/boards/jh7110/jh7110_user.lds | 146 ++++++++++++++++++ .../XiZi_AIoT/services/fs/fs_server/Makefile | 3 +- .../XiZi_AIoT/services/fs/libfs/Makefile | 3 +- .../XiZi_AIoT/services/lib/ipc/Makefile | 3 +- .../XiZi_AIoT/services/lib/memory/Makefile | 3 +- .../XiZi_AIoT/services/lib/serial/Makefile | 3 +- .../XiZi_AIoT/services/lib/usyscall/Makefile | 3 +- .../services/shell/letter-shell/Makefile | 3 +- 10 files changed, 167 insertions(+), 11 deletions(-) create mode 100644 Ubiquitous/XiZi_AIoT/services/boards/jh7110/jh7110_user.lds diff --git a/Ubiquitous/XiZi_AIoT/services/app/Makefile b/Ubiquitous/XiZi_AIoT/services/app/Makefile index 164a76a2e..13dd7d87b 100644 --- a/Ubiquitous/XiZi_AIoT/services/app/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/app/Makefile @@ -19,7 +19,9 @@ endif ifeq ($(BOARD), jh7110) toolchain ?= riscv64-unknown-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -O2 -std=c11 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +CFLAGS = -Wall -Werror -O -fno-omit-frame-pointer -ggdb -gdwarf-2 -MD -mcmodel=medany -fno-common -nostdlib -fno-builtin-strncpy -fno-builtin-strncmp -fno-builtin-strlen -fno-builtin-memset -fno-builtin-memmove -fno-builtin-memcmp -fno-builtin-log -fno-builtin-bzero -fno-builtin-strchr -fno-builtin-exit -fno-builtin-malloc -fno-builtin-putc -fno-builtin-free -fno-builtin-memcpy -Wno-main -fno-builtin-printf -fno-builtin-fprintf -fno-builtin-vprintf -I. -fno-stack-protector -fno-pie -no-pie +cflags = $(CFLAGS) -Wno-unused -fno-strict-aliasing + board_specs = stub.o endif @@ -104,7 +106,7 @@ test_irq_hdlr: test_irq_handler.o libserial.o printf.o libipc.o session.o usysca @${objdump} -S $@ > $@.asm shell: shell_port.o libserial.o printf.o shell_cmd_list.o shell.o shell_ext.o libfs.o libipc.o session.o usyscall.o arch_usyscall.o libmem.o - @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs} + @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs} -T $(KERNEL_ROOT)/services/boards/jh7110/jh7110_user.lds @${objdump} -S $@ > $@.asm test_fault: test_fault.o libserial.o printf.o usyscall.o arch_usyscall.o @@ -120,7 +122,7 @@ simple_server: simple_server.o libserial.o printf.o libipc.o session.o simple_se @${objdump} -S $@ > $@.asm fs_server: fs_server.o libfs.o fs.o libserial.o printf.o libipc.o session.o block_io.o usyscall.o arch_usyscall.o libmem.o - @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs} + @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs} -T $(KERNEL_ROOT)/services/boards/jh7110/jh7110_user.lds @${objdump} -S $@ > $@.asm test_priority: test_priority.o libserial.o printf.o usyscall.o arch_usyscall.o libmem.o diff --git a/Ubiquitous/XiZi_AIoT/services/boards/jh7110/Makefile b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/Makefile index 6c59a35cd..e5a9387ed 100644 --- a/Ubiquitous/XiZi_AIoT/services/boards/jh7110/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/Makefile @@ -1,7 +1,8 @@ ifeq ($(BOARD), jh7110) toolchain ?= riscv64-unknown-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -O0 -g -std=c11 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +CFLAGS = -Wall -Werror -O -fno-omit-frame-pointer -ggdb -gdwarf-2 -MD -mcmodel=medany -fno-common -nostdlib -fno-builtin-strncpy -fno-builtin-strncmp -fno-builtin-strlen -fno-builtin-memset -fno-builtin-memmove -fno-builtin-memcmp -fno-builtin-log -fno-builtin-bzero -fno-builtin-strchr -fno-builtin-exit -fno-builtin-malloc -fno-builtin-putc -fno-builtin-free -fno-builtin-memcpy -Wno-main -fno-builtin-printf -fno-builtin-fprintf -fno-builtin-vprintf -I. -fno-stack-protector -fno-pie -no-pie +cflags = $(CFLAGS) -Wno-unused -fno-strict-aliasing endif cc = ${toolchain}gcc diff --git a/Ubiquitous/XiZi_AIoT/services/boards/jh7110/jh7110_user.lds b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/jh7110_user.lds new file mode 100644 index 000000000..fb0dc78e0 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/jh7110_user.lds @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2010-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file jh7110_user.lds + * @brief refer to XV6 riscv + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.10.10 + */ + + +OUTPUT_ARCH("riscv") + + +SECTIONS +{ + . = 0x0; + + .text : { + *(.text .text.*) + } + + .rodata : { + . = ALIGN(16); + *(.srodata .srodata.*) + . = ALIGN(16); + *(.rodata .rodata.*) + } + + .eh_frame : { + *(.eh_frame) + *(.eh_frame.*) + } + + . = ALIGN(0x1000); + .data : { + . = ALIGN(16); + *(.sdata .sdata.*) + . = ALIGN(16); + *(.data .data.*) + } + + .bss : { + . = ALIGN(16); + *(.sbss .sbss.*) + . = ALIGN(16); + *(.bss .bss.*) + } + + . = ALIGN((1 << 21)); + .sdata : { + __global_pointer$ = . + 0x800; + *(.sdata*) + } + + . = ALIGN((1 << 21)); + _edata = .; + _end = .; + PROVIDE(end = .); +} + +/* +SECTIONS +{ + _start = .; + _boot_start = .; + +. = ALIGN(0x1000); + .text : { + . = ALIGN(0x1000); + *(.text .text.*) + } + + . = ALIGN(0x1000); + .data : { + . = ALIGN(16); + *(.sdata .sdata.*) + . = ALIGN(16); + *(.data .data.*) + + __start_init_task = .; + init_thread_union = .; + init_stack = .; + KEEP(*(.data..init_task)) + KEEP(*(.data..init_thread_info)) + . = __start_init_task + ((1 << (12)) << (2)); + __end_init_task = .; + + + PROVIDE(__init_array_start = .); + PROVIDE(__init_array_end = .); + } + + . = ALIGN(0x1000); + _image_size = . - _start; + + . = ALIGN(0x1000); + .bss : { + PROVIDE(kernel_data_begin = .); + PROVIDE(__bss_start = .); + *(.bss .bss.* COMMON) + . = ALIGN(0x1000); + PROVIDE(__bss_end = .); + PROVIDE(kernel_data_end = .); + __bss_stop = .; + } + + . = ALIGN((1 << 21)); + .sdata : { + __global_pointer$ = . + 0x800; + *(.sdata*) + } + . = ALIGN((1 << 21)); + _edata = .; + _end = .; + PROVIDE(end = .); +} +*/ \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/services/fs/fs_server/Makefile b/Ubiquitous/XiZi_AIoT/services/fs/fs_server/Makefile index be3c9e7c4..812be4b53 100644 --- a/Ubiquitous/XiZi_AIoT/services/fs/fs_server/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/fs/fs_server/Makefile @@ -17,7 +17,8 @@ endif ifeq ($(BOARD), jh7110) toolchain ?= riscv64-unknown-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -O0 -g -std=c11 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +CFLAGS = -Wall -Werror -O -fno-omit-frame-pointer -ggdb -gdwarf-2 -MD -mcmodel=medany -fno-common -nostdlib -fno-builtin-strncpy -fno-builtin-strncmp -fno-builtin-strlen -fno-builtin-memset -fno-builtin-memmove -fno-builtin-memcmp -fno-builtin-log -fno-builtin-bzero -fno-builtin-strchr -fno-builtin-exit -fno-builtin-malloc -fno-builtin-putc -fno-builtin-free -fno-builtin-memcpy -Wno-main -fno-builtin-printf -fno-builtin-fprintf -fno-builtin-vprintf -I. -fno-stack-protector -fno-pie -no-pie +cflags = $(CFLAGS) -Wno-unused -fno-strict-aliasing endif cc = ${toolchain}gcc diff --git a/Ubiquitous/XiZi_AIoT/services/fs/libfs/Makefile b/Ubiquitous/XiZi_AIoT/services/fs/libfs/Makefile index 64814b1cd..58194caea 100644 --- a/Ubiquitous/XiZi_AIoT/services/fs/libfs/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/fs/libfs/Makefile @@ -16,7 +16,8 @@ endif ifeq ($(BOARD), jh7110) toolchain ?= riscv64-unknown-elf- user_ldflags = -N -cflags = -Wall -O0 -g -std=c11 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +CFLAGS = -Wall -Werror -O -fno-omit-frame-pointer -ggdb -gdwarf-2 -MD -mcmodel=medany -fno-common -nostdlib -fno-builtin-strncpy -fno-builtin-strncmp -fno-builtin-strlen -fno-builtin-memset -fno-builtin-memmove -fno-builtin-memcmp -fno-builtin-log -fno-builtin-bzero -fno-builtin-strchr -fno-builtin-exit -fno-builtin-malloc -fno-builtin-putc -fno-builtin-free -fno-builtin-memcpy -Wno-main -fno-builtin-printf -fno-builtin-fprintf -fno-builtin-vprintf -I. -fno-stack-protector -fno-pie -no-pie +cflags = $(CFLAGS) -Wno-unused -fno-strict-aliasing endif cc = ${toolchain}gcc diff --git a/Ubiquitous/XiZi_AIoT/services/lib/ipc/Makefile b/Ubiquitous/XiZi_AIoT/services/lib/ipc/Makefile index 9d6c02a55..88e25e434 100644 --- a/Ubiquitous/XiZi_AIoT/services/lib/ipc/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/lib/ipc/Makefile @@ -17,7 +17,8 @@ endif ifeq ($(BOARD), jh7110) toolchain ?= riscv64-unknown-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -O0 -g -std=c11 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +CFLAGS = -Wall -Werror -O -fno-omit-frame-pointer -ggdb -gdwarf-2 -MD -mcmodel=medany -fno-common -nostdlib -fno-builtin-strncpy -fno-builtin-strncmp -fno-builtin-strlen -fno-builtin-memset -fno-builtin-memmove -fno-builtin-memcmp -fno-builtin-log -fno-builtin-bzero -fno-builtin-strchr -fno-builtin-exit -fno-builtin-malloc -fno-builtin-putc -fno-builtin-free -fno-builtin-memcpy -Wno-main -fno-builtin-printf -fno-builtin-fprintf -fno-builtin-vprintf -I. -fno-stack-protector -fno-pie -no-pie +cflags = $(CFLAGS) -Wno-unused -fno-strict-aliasing endif cc = ${toolchain}gcc diff --git a/Ubiquitous/XiZi_AIoT/services/lib/memory/Makefile b/Ubiquitous/XiZi_AIoT/services/lib/memory/Makefile index 6bfef9888..e69f65cf1 100644 --- a/Ubiquitous/XiZi_AIoT/services/lib/memory/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/lib/memory/Makefile @@ -16,7 +16,8 @@ endif ifeq ($(BOARD), jh7110) toolchain ?= riscv64-unknown-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -O0 -g -std=c11 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +CFLAGS = -Wall -Werror -O -fno-omit-frame-pointer -ggdb -gdwarf-2 -MD -mcmodel=medany -fno-common -nostdlib -fno-builtin-strncpy -fno-builtin-strncmp -fno-builtin-strlen -fno-builtin-memset -fno-builtin-memmove -fno-builtin-memcmp -fno-builtin-log -fno-builtin-bzero -fno-builtin-strchr -fno-builtin-exit -fno-builtin-malloc -fno-builtin-putc -fno-builtin-free -fno-builtin-memcpy -Wno-main -fno-builtin-printf -fno-builtin-fprintf -fno-builtin-vprintf -I. -fno-stack-protector -fno-pie -no-pie +cflags = $(CFLAGS) -Wno-unused -fno-strict-aliasing endif cc = ${toolchain}gcc diff --git a/Ubiquitous/XiZi_AIoT/services/lib/serial/Makefile b/Ubiquitous/XiZi_AIoT/services/lib/serial/Makefile index b11994f45..9c01d3ef4 100644 --- a/Ubiquitous/XiZi_AIoT/services/lib/serial/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/lib/serial/Makefile @@ -16,7 +16,8 @@ endif ifeq ($(BOARD), jh7110) toolchain ?= riscv64-unknown-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -O0 -g -std=c11 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +CFLAGS = -Wall -Werror -O -fno-omit-frame-pointer -ggdb -gdwarf-2 -MD -mcmodel=medany -fno-common -nostdlib -fno-builtin-strncpy -fno-builtin-strncmp -fno-builtin-strlen -fno-builtin-memset -fno-builtin-memmove -fno-builtin-memcmp -fno-builtin-log -fno-builtin-bzero -fno-builtin-strchr -fno-builtin-exit -fno-builtin-malloc -fno-builtin-putc -fno-builtin-free -fno-builtin-memcpy -Wno-main -fno-builtin-printf -fno-builtin-fprintf -fno-builtin-vprintf -I. -fno-stack-protector -fno-pie -no-pie +cflags = $(CFLAGS) -Wno-unused -fno-strict-aliasing endif cc = ${toolchain}gcc diff --git a/Ubiquitous/XiZi_AIoT/services/lib/usyscall/Makefile b/Ubiquitous/XiZi_AIoT/services/lib/usyscall/Makefile index 6f13b4713..93c92133d 100644 --- a/Ubiquitous/XiZi_AIoT/services/lib/usyscall/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/lib/usyscall/Makefile @@ -16,7 +16,8 @@ endif ifeq ($(BOARD), jh7110) toolchain ?= riscv64-unknown-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -O0 -g -std=c11 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +CFLAGS = -Wall -Werror -O -fno-omit-frame-pointer -ggdb -gdwarf-2 -MD -mcmodel=medany -fno-common -nostdlib -fno-builtin-strncpy -fno-builtin-strncmp -fno-builtin-strlen -fno-builtin-memset -fno-builtin-memmove -fno-builtin-memcmp -fno-builtin-log -fno-builtin-bzero -fno-builtin-strchr -fno-builtin-exit -fno-builtin-malloc -fno-builtin-putc -fno-builtin-free -fno-builtin-memcpy -Wno-main -fno-builtin-printf -fno-builtin-fprintf -fno-builtin-vprintf -I. -fno-stack-protector -fno-pie -no-pie +cflags = $(CFLAGS) -Wno-unused -fno-strict-aliasing endif cc = ${toolchain}gcc diff --git a/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/Makefile b/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/Makefile index 3910ec988..77d4e63ed 100644 --- a/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/Makefile @@ -16,7 +16,8 @@ endif ifeq ($(BOARD), jh7110) toolchain ?= riscv64-unknown-elf- user_ldflags = -N -Ttext 0 -cflags = -Wall -O0 -g -std=c11 -nostdlib -nodefaultlibs -fno-pic -static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie +CFLAGS = -Wall -Werror -O -fno-omit-frame-pointer -ggdb -gdwarf-2 -MD -mcmodel=medany -fno-common -nostdlib -fno-builtin-strncpy -fno-builtin-strncmp -fno-builtin-strlen -fno-builtin-memset -fno-builtin-memmove -fno-builtin-memcmp -fno-builtin-log -fno-builtin-bzero -fno-builtin-strchr -fno-builtin-exit -fno-builtin-malloc -fno-builtin-putc -fno-builtin-free -fno-builtin-memcpy -Wno-main -fno-builtin-printf -fno-builtin-fprintf -fno-builtin-vprintf -I. -fno-stack-protector -fno-pie -no-pie +cflags = $(CFLAGS) -Wno-unused -fno-strict-aliasing endif cc = ${toolchain}gcc From e0fb6dc92609886f81a6904197f8d4aa2a4662a2 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 21 Jan 2025 10:02:42 +0800 Subject: [PATCH 42/54] Modify shell --- Ubiquitous/XiZi_AIoT/services/app/shell_port.c | 1 - Ubiquitous/XiZi_AIoT/services/boards/jh7110/libserial.c | 6 +++--- Ubiquitous/XiZi_AIoT/services/shell/letter-shell/shell.c | 3 --- 3 files changed, 3 insertions(+), 7 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/app/shell_port.c b/Ubiquitous/XiZi_AIoT/services/app/shell_port.c index 69164a88f..7f9c286c4 100644 --- a/Ubiquitous/XiZi_AIoT/services/app/shell_port.c +++ b/Ubiquitous/XiZi_AIoT/services/app/shell_port.c @@ -49,7 +49,6 @@ int main(void) shell.read = userShellRead; shellInit(&shell, shellBuffer, 512); - printf("shell init\n"); while (connect_session(&session_fs, "MemFS", 0x10000) < 0) ; diff --git a/Ubiquitous/XiZi_AIoT/services/boards/jh7110/libserial.c b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/libserial.c index 409ce5f13..716d81cc1 100644 --- a/Ubiquitous/XiZi_AIoT/services/boards/jh7110/libserial.c +++ b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/libserial.c @@ -216,12 +216,12 @@ static inline int serial_in_shift(void* addr, int shift) bool init_uart_mmio() { - static int mapped = 0xff; - if (mapped != 0) { + static int mapped = 0; + if (mapped == 0) { if (-1 == mmap(UART_ADDR, UART_ADDR, 4096, true)) { return false; } - mapped = 0; + mapped = 1; } return true; } diff --git a/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/shell.c b/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/shell.c index ec1ff011b..34b99616e 100644 --- a/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/shell.c +++ b/Ubiquitous/XiZi_AIoT/services/shell/letter-shell/shell.c @@ -203,7 +203,6 @@ void shellInit(Shell* shell, char* buffer, unsigned short size) shellAdd(shell); shellSetUser(shell, shellSeekCommand(shell, SHELL_DEFAULT_USER, shell->commandList.base, 0)); - shellWritePrompt(shell, 1); } @@ -323,11 +322,9 @@ static void shellWritePrompt(Shell* shell, unsigned char newline) if (newline) { shellWriteString(shell, "\r\n"); } -#ifndef __riscv shellWriteString(shell, shell->info.user->data.user.name); shellWriteString(shell, ":"); shellWriteString(shell, shell->info.path ? shell->info.path : "/"); -#endif shellWriteString(shell, "$ "); } else { shellWriteString(shell, shellText[SHELL_TEXT_PASSWORD_HINT]); From e98cffed83757b66aa1f8cafbafe9f44cb93b6b5 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 21 Jan 2025 10:16:39 +0800 Subject: [PATCH 43/54] Modify log --- .../hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S | 2 +- .../XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c | 4 ++-- Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c | 2 -- Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c | 1 - 4 files changed, 3 insertions(+), 6 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S index 089df000e..f9ba432d3 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S @@ -118,5 +118,5 @@ relocate_enable_mmu: j .Lsecondary_park -debug_string_start: .ascii "XiZi boot start\n\0" +debug_string_start: .ascii "XiZi jh7110 boot start\n\0" diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c index af02658f7..aa3546ee5 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c @@ -32,7 +32,7 @@ void plic_enable_irq(int cpu, int hwirq, int enable) int hart = CPU_TO_HART(cpu); unsigned int reg = PLIC_MENABLE(hart) + 4 * (hwirq / 32); - printk("plic_enable_irq hwirq=%d\n", hwirq); +// printk("plic_enable_irq hwirq=%d\n", hwirq); #if 0 if (enable) { writel(readl(reg) | hwirq_mask, reg); @@ -50,7 +50,7 @@ int plic_init(void) int i; int hwirq; - printk("plic_init boot_cpu_hartid=%lu\n", boot_cpu_hartid); +// printk("plic_init boot_cpu_hartid=%lu\n", boot_cpu_hartid); #if 0 for (i = 0; i < MAX_CPUS; i++) { writel(0, PLIC_MTHRESHOLD(CPU_TO_HART(i))); diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c index 508c88296..cb5849baa 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c @@ -50,10 +50,8 @@ void load_pgdir(uintptr_t pgdir_paddr) struct ICacheDone* p_icache_done = AchieveResource(&right_group.icache_driver_tag); struct DCacheDone* p_dcache_done = AchieveResource(&right_group.dcache_driver_tag); - printk("load_pgdir pgdir_paddr=%08lx\n", pgdir_paddr); csr_write(CSR_SATP, PFN_DOWN(pgdir_paddr) | SATP_MODE); __asm__ __volatile__ ("sfence.vma" : : : "memory"); - printf_early("load_pgdir pgdir_paddr=%08lx ok\n", pgdir_paddr); p_icache_done->invalidateall(); p_dcache_done->flushall(); diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c index bfc173b36..68adee8fa 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/pagetable_riscv.c @@ -55,7 +55,6 @@ static bool _new_pgdir(struct TopLevelPageDirectory* pgdir) static bool _map_pages(uintptr_t* pgdir, uintptr_t vaddr, uintptr_t paddr, intptr_t len, uintptr_t attr) { - DEBUG_PRINTF("_map_pages pgdir=%08lx, vaddr=%08lx, paddr=%08lx, len=%08lx, attr==%08lx\n", pgdir, vaddr, paddr, len, attr); assert(len >= 0); vaddr = ALIGNDOWN(vaddr, LEVEL4_PTE_SIZE); paddr = ALIGNDOWN(paddr, LEVEL4_PTE_SIZE); From 7c2b3d10b5f16096d6d35ab73c7bcb70f4bc3e18 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 21 Jan 2025 10:28:47 +0800 Subject: [PATCH 44/54] Modify app build --- Ubiquitous/XiZi_AIoT/services/app/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/app/Makefile b/Ubiquitous/XiZi_AIoT/services/app/Makefile index 13dd7d87b..7d004482d 100644 --- a/Ubiquitous/XiZi_AIoT/services/app/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/app/Makefile @@ -21,7 +21,7 @@ toolchain ?= riscv64-unknown-elf- user_ldflags = -N -Ttext 0 CFLAGS = -Wall -Werror -O -fno-omit-frame-pointer -ggdb -gdwarf-2 -MD -mcmodel=medany -fno-common -nostdlib -fno-builtin-strncpy -fno-builtin-strncmp -fno-builtin-strlen -fno-builtin-memset -fno-builtin-memmove -fno-builtin-memcmp -fno-builtin-log -fno-builtin-bzero -fno-builtin-strchr -fno-builtin-exit -fno-builtin-malloc -fno-builtin-putc -fno-builtin-free -fno-builtin-memcpy -Wno-main -fno-builtin-printf -fno-builtin-fprintf -fno-builtin-vprintf -I. -fno-stack-protector -fno-pie -no-pie cflags = $(CFLAGS) -Wno-unused -fno-strict-aliasing - +user_lds = -T $(KERNEL_ROOT)/services/boards/jh7110/jh7110_user.lds board_specs = stub.o endif @@ -106,7 +106,7 @@ test_irq_hdlr: test_irq_handler.o libserial.o printf.o libipc.o session.o usysca @${objdump} -S $@ > $@.asm shell: shell_port.o libserial.o printf.o shell_cmd_list.o shell.o shell_ext.o libfs.o libipc.o session.o usyscall.o arch_usyscall.o libmem.o - @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs} -T $(KERNEL_ROOT)/services/boards/jh7110/jh7110_user.lds + @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs} ${user_lds} @${objdump} -S $@ > $@.asm test_fault: test_fault.o libserial.o printf.o usyscall.o arch_usyscall.o @@ -122,7 +122,7 @@ simple_server: simple_server.o libserial.o printf.o libipc.o session.o simple_se @${objdump} -S $@ > $@.asm fs_server: fs_server.o libfs.o fs.o libserial.o printf.o libipc.o session.o block_io.o usyscall.o arch_usyscall.o libmem.o - @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs} -T $(KERNEL_ROOT)/services/boards/jh7110/jh7110_user.lds + @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs} ${user_lds} @${objdump} -S $@ > $@.asm test_priority: test_priority.o libserial.o printf.o usyscall.o arch_usyscall.o libmem.o From 861795f8bd99e7ea11028d56fc161d2e2e38a3ad Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 21 Jan 2025 11:26:32 +0800 Subject: [PATCH 45/54] Fix showMemInfo issue --- Ubiquitous/XiZi_AIoT/softkernel/memory/kalloc.c | 11 ++++++++--- Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c | 4 ++++ 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/softkernel/memory/kalloc.c b/Ubiquitous/XiZi_AIoT/softkernel/memory/kalloc.c index 28fef6c67..39b2138f1 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/memory/kalloc.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/memory/kalloc.c @@ -33,9 +33,6 @@ Modification: #include "actracer.h" #include "buddy.h" -#ifndef V2P_LINK -#define V2P_LINK V2P -#endif struct KBuddy kern_virtmem_buddy; struct KBuddy user_phy_freemem_buddy; @@ -43,7 +40,11 @@ struct KBuddy user_phy_freemem_buddy; extern uintptr_t kernel_data_end[]; bool module_phymem_init() { +#ifndef __riscv + uintptr_t kern_freemem_start = V2P(kernel_data_end); +#else uintptr_t kern_freemem_start = V2P_LINK(kernel_data_end); +#endif uintptr_t kern_freemem_end = PHY_USER_FREEMEM_BASE; uintptr_t user_freemem_start = PHY_USER_FREEMEM_BASE; uintptr_t user_freemem_end = PHY_MEM_STOP; @@ -59,7 +60,11 @@ char* kalloc(uintptr_t size) if (mem_alloc == NULL) { return NULL; } +#ifndef __riscv + assert((uintptr_t)mem_alloc >= V2P(&kernel_data_end) && (uintptr_t)mem_alloc < PHY_USER_FREEMEM_BASE); +#else assert((uintptr_t)mem_alloc >= V2P_LINK(&kernel_data_end) && (uintptr_t)mem_alloc < PHY_USER_FREEMEM_BASE); +#endif mem_alloc = P2V(mem_alloc); if ((uintptr_t)mem_alloc < KERN_MEM_BASE) { DEBUG("Error Alloc: %x by size: %d (Caused by double free)\n", mem_alloc, size); diff --git a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c index 6f672a1bb..502fde0e4 100644 --- a/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c +++ b/Ubiquitous/XiZi_AIoT/softkernel/syscall/sys_state.c @@ -113,7 +113,11 @@ void show_mem(void) { SHOWINFO_BORDER_LINE(); +#ifndef __riscv uint64_t total = (PHY_MEM_STOP - V2P(kernel_data_end)); +#else + uint64_t total = (PHY_MEM_STOP - V2P_LINK(kernel_data_end)); +#endif uint64_t user_dynamic_free = 0; uint64_t kernel_free = 0; for (int j = 0; j < MAX_BUDDY_ORDER; j++) { From 32977dd3019d52f36fdebf762fe0f7729adc22e1 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 21 Jan 2025 15:21:09 +0800 Subject: [PATCH 46/54] Modify boot.S --- .../hardkernel/arch/riscv/rv64gc/core.h | 4 +- .../riscv/rv64gc/preboot_for_jh7110/boot.S | 6 +- .../rv64gc/preboot_for_jh7110/jh7110.lds | 32 ++++------ .../services/boards/jh7110/jh7110_user.lds | 58 ------------------- 4 files changed, 14 insertions(+), 86 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h index 21a86db89..0bfa4b198 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h @@ -226,10 +226,10 @@ __attribute__((__always_inline__)) static inline void arch_set_return(struct tra // TODO: refer to jh7110 Linux struct thread_info { unsigned long flags; /* low level flags */ - int preempt_count; /* 0=>preemptible, <0=>BUG */ + long preempt_count; /* 0=>preemptible, <0=>BUG */ long kernel_sp; /* Kernel stack pointer */ long user_sp; /* User stack pointer */ - int cpu; + long cpu; }; diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S index f9ba432d3..d445c8883 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S @@ -11,7 +11,6 @@ */ #include -#include "core.h" #include "memlayout.h" @@ -61,8 +60,7 @@ clear_bss_done: /* Restore C environment */ la tp, init_thread_info - sw zero, TASK_TI_CPU(tp) - la sp, init_thread_union + THREAD_SIZE + sw zero, 32(tp) /* Start the kernel */ tail bootmain @@ -70,7 +68,7 @@ clear_bss_done: relocate_enable_mmu: /* Relocate return address */ la a1, kernel_map - ld a1, KERNEL_MAP_VIRT_ADDR(a1) + ld a1, 0(a1) la a2, _start sub a1, a1, a2 add ra, ra, a1 diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds index 93f0e549e..94aed0350 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds @@ -39,7 +39,6 @@ OUTPUT_ARCH(riscv) OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv") -/* ENTRY(_start) */ ENTRY( _boot_start ) MEMORY { @@ -85,27 +84,15 @@ SECTIONS PROVIDE(boot_end_addr = .); } -. = ALIGN(0x1000); .text : { . = ALIGN(0x1000); *(.text .text.*) } - . = ALIGN(0x1000); .data : { - . = ALIGN(16); - *(.sdata .sdata.*) - . = ALIGN(16); + . = ALIGN(0x1000); *(.data .data.*) - __start_init_task = .; - init_thread_union = .; - init_stack = .; - KEEP(*(.data..init_task)) - KEEP(*(.data..init_thread_info)) - . = __start_init_task + ((1 << (12)) << (2)); - __end_init_task = .; - . = ALIGN(0x1000); PROVIDE(_binary_fs_img_start = .); *(.rawdata_fs_img*) @@ -122,11 +109,14 @@ SECTIONS PROVIDE(__init_array_end = .); } - . = ALIGN(0x1000); - _image_size = . - _start; + .sdata : { + . = ALIGN(0x1000); + __global_pointer$ = . + 0x800; + *(.sdata*) + } - . = ALIGN(0x1000); .bss : { + . = ALIGN(0x1000); PROVIDE(kernel_data_begin = .); PROVIDE(__bss_start = .); *(.bss .bss.* COMMON) @@ -136,11 +126,9 @@ SECTIONS __bss_stop = .; } - . = ALIGN((1 << 21)); - .sdata : { - __global_pointer$ = . + 0x800; - *(.sdata*) - } + . = ALIGN(0x1000); + _image_size = . - _start; + . = ALIGN((1 << 21)); _edata = .; _end = .; diff --git a/Ubiquitous/XiZi_AIoT/services/boards/jh7110/jh7110_user.lds b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/jh7110_user.lds index fb0dc78e0..d06e84c91 100644 --- a/Ubiquitous/XiZi_AIoT/services/boards/jh7110/jh7110_user.lds +++ b/Ubiquitous/XiZi_AIoT/services/boards/jh7110/jh7110_user.lds @@ -86,61 +86,3 @@ SECTIONS _end = .; PROVIDE(end = .); } - -/* -SECTIONS -{ - _start = .; - _boot_start = .; - -. = ALIGN(0x1000); - .text : { - . = ALIGN(0x1000); - *(.text .text.*) - } - - . = ALIGN(0x1000); - .data : { - . = ALIGN(16); - *(.sdata .sdata.*) - . = ALIGN(16); - *(.data .data.*) - - __start_init_task = .; - init_thread_union = .; - init_stack = .; - KEEP(*(.data..init_task)) - KEEP(*(.data..init_thread_info)) - . = __start_init_task + ((1 << (12)) << (2)); - __end_init_task = .; - - - PROVIDE(__init_array_start = .); - PROVIDE(__init_array_end = .); - } - - . = ALIGN(0x1000); - _image_size = . - _start; - - . = ALIGN(0x1000); - .bss : { - PROVIDE(kernel_data_begin = .); - PROVIDE(__bss_start = .); - *(.bss .bss.* COMMON) - . = ALIGN(0x1000); - PROVIDE(__bss_end = .); - PROVIDE(kernel_data_end = .); - __bss_stop = .; - } - - . = ALIGN((1 << 21)); - .sdata : { - __global_pointer$ = . + 0x800; - *(.sdata*) - } - . = ALIGN((1 << 21)); - _edata = .; - _end = .; - PROVIDE(end = .); -} -*/ \ No newline at end of file From 0d05dab7b3d1536b66a772bf3232c99280563599 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Tue, 21 Jan 2025 17:48:56 +0800 Subject: [PATCH 47/54] Modify mmu, delete invalid headers --- .../arch/riscv/rv64gc/include/asm/page.h | 186 ------ .../arch/riscv/rv64gc/include/asm/pfn.h | 23 - .../riscv/rv64gc/include/asm/pgtable-64.h | 47 -- .../arch/riscv/rv64gc/include/asm/pgtable.h | 598 ------------------ .../arch/riscv/rv64gc/include/asm/sizes.h | 52 -- .../hardkernel/mmu/riscv/rv64gc/include/mmu.h | 40 -- .../mmu/riscv/rv64gc/include/pgtable.h | 76 --- .../hardkernel/mmu/riscv/rv64gc/mmu.c | 7 +- .../hardkernel/mmu/riscv/rv64gc/mmu_init.c | 46 +- 9 files changed, 42 insertions(+), 1033 deletions(-) delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/page.h delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pfn.h delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable-64.h delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable.h delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/sizes.h delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/pgtable.h diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/page.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/page.h deleted file mode 100644 index 5e1cea44e..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/page.h +++ /dev/null @@ -1,186 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2009 Chen Liqin - * Copyright (C) 2012 Regents of the University of California - * Copyright (C) 2017 SiFive - * Copyright (C) 2017 XiaojingZhu - */ - -#ifndef _ASM_RISCV_PAGE_H -#define _ASM_RISCV_PAGE_H - -#include "autoconf.h" -#include -#include - - -#ifdef CONFIG_PHYS_ADDR_T_64BIT -typedef uint64_t phys_addr_t; -#else -typedef uint64_t phys_addr_t; -#endif - - -#define PAGE_SHIFT (12) -#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE - 1)) - -#ifdef CONFIG_64BIT -#define HUGE_MAX_HSTATE 2 -#else -#define HUGE_MAX_HSTATE 1 -#endif -#define HPAGE_SHIFT PMD_SHIFT -#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) -#define HPAGE_MASK (~(HPAGE_SIZE - 1)) -#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) - -/* - * PAGE_OFFSET -- the first address of the first page of memory. - * When not using MMU this corresponds to the first free page in - * physical memory (aligned on a page boundary). - */ -#define PAGE_OFFSET _AC(CONFIG_PAGE_OFFSET, UL) - -#define KERN_VIRT_SIZE (-PAGE_OFFSET) - -#ifndef __ASSEMBLY__ - -#define clear_page(pgaddr) memset((pgaddr), 0, PAGE_SIZE) -#define copy_page(to, from) memcpy((to), (from), PAGE_SIZE) - -#define clear_user_page(pgaddr, vaddr, page) memset((pgaddr), 0, PAGE_SIZE) -#define copy_user_page(vto, vfrom, vaddr, topg) \ - memcpy((vto), (vfrom), PAGE_SIZE) - -/* - * Use struct definitions to apply C type checking - */ - -/* Page Global Directory entry */ -typedef struct { - unsigned long pgd; -} pgd_t; - -/* Page Table entry */ -typedef struct { - unsigned long pte; -} pte_t; - -typedef struct { - unsigned long pgprot; -} pgprot_t; - -typedef struct page *pgtable_t; - -#define pte_val(x) ((x).pte) -#define pgd_val(x) ((x).pgd) -#define pgprot_val(x) ((x).pgprot) - -#define __pte(x) ((pte_t) { (x) }) -#define __pgd(x) ((pgd_t) { (x) }) -#define __pgprot(x) ((pgprot_t) { (x) }) - -#ifdef CONFIG_64BIT -#define PTE_FMT "%016lx" -#else -#define PTE_FMT "%08lx" -#endif - -#ifdef CONFIG_MMU -extern unsigned long riscv_pfn_base; -#define ARCH_PFN_OFFSET (riscv_pfn_base) -#else -#define ARCH_PFN_OFFSET (PAGE_OFFSET >> PAGE_SHIFT) -#endif /* CONFIG_MMU */ - -struct kernel_mapping { - unsigned long virt_addr; - uintptr_t phys_addr; - uintptr_t size; - /* Offset between linear mapping virtual address and kernel load address */ - unsigned long va_pa_offset; - /* Offset between kernel mapping virtual address and kernel load address */ - unsigned long va_kernel_pa_offset; - unsigned long va_kernel_xip_pa_offset; -#ifdef CONFIG_XIP_KERNEL - uintptr_t xiprom; - uintptr_t xiprom_sz; -#endif -}; - -extern struct kernel_mapping kernel_map; -extern phys_addr_t phys_ram_base; - -#define is_kernel_mapping(x) \ - ((x) >= kernel_map.virt_addr && (x) < (kernel_map.virt_addr + kernel_map.size)) - -#define is_linear_mapping(x) \ - ((x) >= PAGE_OFFSET && (!IS_ENABLED(CONFIG_64BIT) || (x) < kernel_map.virt_addr)) - -#define linear_mapping_pa_to_va(x) ((void *)((unsigned long)(x) + kernel_map.va_pa_offset)) -#define kernel_mapping_pa_to_va(y) ({ \ - unsigned long _y = y; \ - (IS_ENABLED(CONFIG_XIP_KERNEL) && _y < phys_ram_base) ? \ - (void *)((unsigned long)(_y) + kernel_map.va_kernel_xip_pa_offset) : \ - (void *)((unsigned long)(_y) + kernel_map.va_kernel_pa_offset + XIP_OFFSET); \ - }) -#define __pa_to_va_nodebug(x) linear_mapping_pa_to_va(x) - -#define linear_mapping_va_to_pa(x) ((unsigned long)(x) - kernel_map.va_pa_offset) -#define kernel_mapping_va_to_pa(y) ({ \ - unsigned long _y = y; \ - (IS_ENABLED(CONFIG_XIP_KERNEL) && _y < kernel_map.virt_addr + XIP_OFFSET) ? \ - ((unsigned long)(_y) - kernel_map.va_kernel_xip_pa_offset) : \ - ((unsigned long)(_y) - kernel_map.va_kernel_pa_offset - XIP_OFFSET); \ - }) - -#define __va_to_pa_nodebug(x) ({ \ - unsigned long _x = x; \ - is_linear_mapping(_x) ? \ - linear_mapping_va_to_pa(_x) : kernel_mapping_va_to_pa(_x); \ - }) - -#ifdef CONFIG_DEBUG_VIRTUAL -extern phys_addr_t __virt_to_phys(unsigned long x); -extern phys_addr_t __phys_addr_symbol(unsigned long x); -#else -#define __virt_to_phys(x) __va_to_pa_nodebug(x) -#define __phys_addr_symbol(x) __va_to_pa_nodebug(x) -#endif /* CONFIG_DEBUG_VIRTUAL */ - -#define __pa_symbol(x) __phys_addr_symbol(RELOC_HIDE((unsigned long)(x), 0)) -#define __pa(x) __virt_to_phys((unsigned long)(x)) -#define __va(x) ((void *)__pa_to_va_nodebug((phys_addr_t)(x))) - -#define phys_to_pfn(phys) (PFN_DOWN(phys)) -#define pfn_to_phys(pfn) (PFN_PHYS(pfn)) - -#define virt_to_pfn(vaddr) (phys_to_pfn(__pa(vaddr))) -#define pfn_to_virt(pfn) (__va(pfn_to_phys(pfn))) - -#define virt_to_page(vaddr) (pfn_to_page(virt_to_pfn(vaddr))) -#define page_to_virt(page) (pfn_to_virt(page_to_pfn(page))) - -#define page_to_phys(page) (pfn_to_phys(page_to_pfn(page))) -#define page_to_bus(page) (page_to_phys(page)) -#define phys_to_page(paddr) (pfn_to_page(phys_to_pfn(paddr))) - -#define sym_to_pfn(x) __phys_to_pfn(__pa_symbol(x)) - -#ifdef CONFIG_FLATMEM -#define pfn_valid(pfn) \ - (((pfn) >= ARCH_PFN_OFFSET) && (((pfn) - ARCH_PFN_OFFSET) < max_mapnr)) -#endif - -#endif /* __ASSEMBLY__ */ - -#define virt_addr_valid(vaddr) ({ \ - unsigned long _addr = (unsigned long)vaddr; \ - (unsigned long)(_addr) >= PAGE_OFFSET && pfn_valid(virt_to_pfn(_addr)); \ -}) - -#define VM_DATA_DEFAULT_FLAGS VM_DATA_FLAGS_NON_EXEC - - -#endif /* _ASM_RISCV_PAGE_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pfn.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pfn.h deleted file mode 100644 index 3cedc6ea1..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pfn.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _LINUX_PFN_H_ -#define _LINUX_PFN_H_ - -#ifndef __ASSEMBLER__ -#include -/* - * pfn_t: encapsulates a page-frame number that is optionally backed - * by memmap (struct page). Whether a pfn_t has a 'struct page' - * backing is indicated by flags in the high bits of the value. - */ -typedef struct { - uint64_t val; -} pfn_t; -#endif - -#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK) -#define PFN_UP(x) (((x) + PAGE_SIZE-1) >> PAGE_SHIFT) -#define PFN_DOWN(x) ((x) >> PAGE_SHIFT) -#define PFN_PHYS(x) ((phys_addr_t)(x) << PAGE_SHIFT) -#define PHYS_PFN(x) ((unsigned long)((x) >> PAGE_SHIFT)) - -#endif diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable-64.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable-64.h deleted file mode 100644 index aef16f340..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable-64.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2012 Regents of the University of California - */ - -#ifndef _ASM_RISCV_PGTABLE_64_H -#define _ASM_RISCV_PGTABLE_64_H - -#include -#include - -#define PGDIR_SHIFT 30 -/* Size of region mapped by a page global directory */ -#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT) -#define PGDIR_MASK (~(PGDIR_SIZE - 1)) - -#define PMD_SHIFT 21 -/* Size of region mapped by a page middle directory */ -#define PMD_SIZE (_AC(1, UL) << PMD_SHIFT) -#define PMD_MASK (~(PMD_SIZE - 1)) - -/* Page Middle Directory entry */ -typedef struct { - unsigned long pmd; -} pmd_t; - -#define pmd_val(x) ((x).pmd) -#define __pmd(x) ((pmd_t) { (x) }) - -#define PTRS_PER_PMD (PAGE_SIZE / sizeof(pmd_t)) - -static inline pmd_t pfn_pmd(unsigned long pfn, pgprot_t prot) -{ - return __pmd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); -} - -static inline unsigned long _pmd_pfn(pmd_t pmd) -{ - return pmd_val(pmd) >> _PAGE_PFN_SHIFT; -} - -#define mk_pmd(page, prot) pfn_pmd(page_to_pfn(page), prot) - -#define pmd_ERROR(e) \ - pr_err("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e)) - -#endif /* _ASM_RISCV_PGTABLE_64_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable.h deleted file mode 100644 index 4423b2633..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/pgtable.h +++ /dev/null @@ -1,598 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2012 Regents of the University of California - */ - -#ifndef _ASM_RISCV_PGTABLE_H -#define _ASM_RISCV_PGTABLE_H - -#include "autoconf.h" -#include -#include - -#ifndef CONFIG_MMU -#define KERNEL_LINK_ADDR PAGE_OFFSET -#else - -#define ADDRESS_SPACE_END (UL(-1)) - -#ifdef CONFIG_64BIT -/* Leave 2GB for kernel and BPF at the end of the address space */ -#define KERNEL_LINK_ADDR (ADDRESS_SPACE_END - SZ_2G + 1) -#else -#define KERNEL_LINK_ADDR PAGE_OFFSET -#endif - -#define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) -#define VMALLOC_END (PAGE_OFFSET - 1) -#define VMALLOC_START (PAGE_OFFSET - VMALLOC_SIZE) - -#define BPF_JIT_REGION_SIZE (SZ_128M) -#ifdef CONFIG_64BIT -#define BPF_JIT_REGION_START (BPF_JIT_REGION_END - BPF_JIT_REGION_SIZE) -#define BPF_JIT_REGION_END (MODULES_END) -#else -#define BPF_JIT_REGION_START (PAGE_OFFSET - BPF_JIT_REGION_SIZE) -#define BPF_JIT_REGION_END (VMALLOC_END) -#endif - -/* Modules always live before the kernel */ -#ifdef CONFIG_64BIT -#define MODULES_VADDR (PFN_ALIGN((unsigned long)&_end) - SZ_2G) -#define MODULES_END (PFN_ALIGN((unsigned long)&_start)) -#endif - -/* - * Roughly size the vmemmap space to be large enough to fit enough - * struct pages to map half the virtual address space. Then - * position vmemmap directly below the VMALLOC region. - */ -#define STRUCT_PAGE_MAX_SHIFT 0 //syg -#define VMEMMAP_SHIFT \ - (CONFIG_VA_BITS - PAGE_SHIFT - 1 + STRUCT_PAGE_MAX_SHIFT) -#define VMEMMAP_SIZE BIT(VMEMMAP_SHIFT) -#define VMEMMAP_END (VMALLOC_START - 1) -#define VMEMMAP_START (VMALLOC_START - VMEMMAP_SIZE) - -/* - * Define vmemmap for pfn_to_page & page_to_pfn calls. Needed if kernel - * is configured with CONFIG_SPARSEMEM_VMEMMAP enabled. - */ -#define vmemmap ((struct page *)VMEMMAP_START) - -#define PCI_IO_SIZE SZ_16M -#define PCI_IO_END VMEMMAP_START -#define PCI_IO_START (PCI_IO_END - PCI_IO_SIZE) - -#define FIXADDR_TOP PCI_IO_START -#ifdef CONFIG_64BIT -#define FIXADDR_SIZE PMD_SIZE -#else -#define FIXADDR_SIZE PGDIR_SIZE -#endif -#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) - -#endif - -#ifdef CONFIG_XIP_KERNEL -#define XIP_OFFSET SZ_8M -#else -#define XIP_OFFSET 0 -#endif - -#ifndef __ASSEMBLY__ - -/* Page Upper Directory not used in RISC-V */ -//#include -#include - - -#ifdef CONFIG_64BIT -#include -#else -#include -#endif /* CONFIG_64BIT */ - -#ifdef CONFIG_XIP_KERNEL -#define XIP_FIXUP(addr) ({ \ - uintptr_t __a = (uintptr_t)(addr); \ - (__a >= CONFIG_XIP_PHYS_ADDR && __a < CONFIG_XIP_PHYS_ADDR + SZ_16M) ? \ - __a - CONFIG_XIP_PHYS_ADDR + CONFIG_PHYS_RAM_BASE - XIP_OFFSET :\ - __a; \ - }) -#else -#define XIP_FIXUP(addr) (addr) -#endif /* CONFIG_XIP_KERNEL */ - -#ifdef CONFIG_MMU -/* Number of entries in the page global directory */ -#define PTRS_PER_PGD (PAGE_SIZE / sizeof(pgd_t)) -/* Number of entries in the page table */ -#define PTRS_PER_PTE (PAGE_SIZE / sizeof(pte_t)) - -/* Number of PGD entries that a user-mode program can use */ -#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) - -/* Page protection bits */ -#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_USER) - -#define PAGE_NONE __pgprot(_PAGE_PROT_NONE) -#define PAGE_READ __pgprot(_PAGE_BASE | _PAGE_READ) -#define PAGE_WRITE __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_WRITE) -#define PAGE_EXEC __pgprot(_PAGE_BASE | _PAGE_EXEC) -#define PAGE_READ_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | _PAGE_EXEC) -#define PAGE_WRITE_EXEC __pgprot(_PAGE_BASE | _PAGE_READ | \ - _PAGE_EXEC | _PAGE_WRITE) - -#define PAGE_COPY PAGE_READ -#define PAGE_COPY_EXEC PAGE_EXEC -#define PAGE_COPY_READ_EXEC PAGE_READ_EXEC -#define PAGE_SHARED PAGE_WRITE -#define PAGE_SHARED_EXEC PAGE_WRITE_EXEC - -#define _PAGE_KERNEL (_PAGE_READ \ - | _PAGE_WRITE \ - | _PAGE_PRESENT \ - | _PAGE_ACCESSED \ - | _PAGE_DIRTY \ - | _PAGE_GLOBAL) - -#define PAGE_KERNEL __pgprot(_PAGE_KERNEL) -#define PAGE_KERNEL_READ __pgprot(_PAGE_KERNEL & ~_PAGE_WRITE) -#define PAGE_KERNEL_EXEC __pgprot(_PAGE_KERNEL | _PAGE_EXEC) -#define PAGE_KERNEL_READ_EXEC __pgprot((_PAGE_KERNEL & ~_PAGE_WRITE) \ - | _PAGE_EXEC) - -#define PAGE_TABLE __pgprot(_PAGE_TABLE) - -/* - * The RISC-V ISA doesn't yet specify how to query or modify PMAs, so we can't - * change the properties of memory regions. - */ -#define _PAGE_IOREMAP _PAGE_KERNEL - -extern pgd_t swapper_pg_dir[]; - -/* MAP_PRIVATE permissions: xwr (copy-on-write) */ -#define __P000 PAGE_NONE -#define __P001 PAGE_READ -#define __P010 PAGE_COPY -#define __P011 PAGE_COPY -#define __P100 PAGE_EXEC -#define __P101 PAGE_READ_EXEC -#define __P110 PAGE_COPY_EXEC -#define __P111 PAGE_COPY_READ_EXEC - -/* MAP_SHARED permissions: xwr */ -#define __S000 PAGE_NONE -#define __S001 PAGE_READ -#define __S010 PAGE_SHARED -#define __S011 PAGE_SHARED -#define __S100 PAGE_EXEC -#define __S101 PAGE_READ_EXEC -#define __S110 PAGE_SHARED_EXEC -#define __S111 PAGE_SHARED_EXEC - -#ifdef CONFIG_TRANSPARENT_HUGEPAGE -static inline int pmd_present(pmd_t pmd) -{ - /* - * Checking for _PAGE_LEAF is needed too because: - * When splitting a THP, split_huge_page() will temporarily clear - * the present bit, in this situation, pmd_present() and - * pmd_trans_huge() still needs to return true. - */ - return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE | _PAGE_LEAF)); -} -#else -static inline int pmd_present(pmd_t pmd) -{ - return (pmd_val(pmd) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); -} -#endif - -static inline int pmd_none(pmd_t pmd) -{ - return (pmd_val(pmd) == 0); -} - -static inline int pmd_bad(pmd_t pmd) -{ - return !pmd_present(pmd) || (pmd_val(pmd) & _PAGE_LEAF); -} - -#define pmd_leaf pmd_leaf -static inline int pmd_leaf(pmd_t pmd) -{ - return pmd_present(pmd) && (pmd_val(pmd) & _PAGE_LEAF); -} - -static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) -{ - *pmdp = pmd; -} - -static inline void pmd_clear(pmd_t *pmdp) -{ - set_pmd(pmdp, __pmd(0)); -} - -static inline pgd_t pfn_pgd(unsigned long pfn, pgprot_t prot) -{ - return __pgd((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); -} - -static inline unsigned long _pgd_pfn(pgd_t pgd) -{ - return pgd_val(pgd) >> _PAGE_PFN_SHIFT; -} - -#if 0 -static inline struct page *pmd_page(pmd_t pmd) -{ - return pfn_to_page(pmd_val(pmd) >> _PAGE_PFN_SHIFT); -} -#endif - -static inline unsigned long pmd_page_vaddr(pmd_t pmd) -{ - return (unsigned long)pfn_to_virt(pmd_val(pmd) >> _PAGE_PFN_SHIFT); -} - -static inline pte_t pmd_pte(pmd_t pmd) -{ - return __pte(pmd_val(pmd)); -} - -/* Yields the page frame number (PFN) of a page table entry */ -static inline unsigned long pte_pfn(pte_t pte) -{ - return (pte_val(pte) >> _PAGE_PFN_SHIFT); -} - -#define pte_page(x) pfn_to_page(pte_pfn(x)) - -/* Constructs a page table entry */ -static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) -{ - return __pte((pfn << _PAGE_PFN_SHIFT) | pgprot_val(prot)); -} - -#define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) - -static inline int pte_present(pte_t pte) -{ - return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)); -} - -static inline int pte_none(pte_t pte) -{ - return (pte_val(pte) == 0); -} - -static inline int pte_write(pte_t pte) -{ - return pte_val(pte) & _PAGE_WRITE; -} - -static inline int pte_exec(pte_t pte) -{ - return pte_val(pte) & _PAGE_EXEC; -} - -static inline int pte_huge(pte_t pte) -{ - return pte_present(pte) && (pte_val(pte) & _PAGE_LEAF); -} - -static inline int pte_dirty(pte_t pte) -{ - return pte_val(pte) & _PAGE_DIRTY; -} - -static inline int pte_young(pte_t pte) -{ - return pte_val(pte) & _PAGE_ACCESSED; -} - -static inline int pte_special(pte_t pte) -{ - return pte_val(pte) & _PAGE_SPECIAL; -} - -/* static inline pte_t pte_rdprotect(pte_t pte) */ - -static inline pte_t pte_wrprotect(pte_t pte) -{ - return __pte(pte_val(pte) & ~(_PAGE_WRITE)); -} - -/* static inline pte_t pte_mkread(pte_t pte) */ - -static inline pte_t pte_mkwrite(pte_t pte) -{ - return __pte(pte_val(pte) | _PAGE_WRITE); -} - -/* static inline pte_t pte_mkexec(pte_t pte) */ - -static inline pte_t pte_mkdirty(pte_t pte) -{ - return __pte(pte_val(pte) | _PAGE_DIRTY); -} - -static inline pte_t pte_mkclean(pte_t pte) -{ - return __pte(pte_val(pte) & ~(_PAGE_DIRTY)); -} - -static inline pte_t pte_mkyoung(pte_t pte) -{ - return __pte(pte_val(pte) | _PAGE_ACCESSED); -} - -static inline pte_t pte_mkold(pte_t pte) -{ - return __pte(pte_val(pte) & ~(_PAGE_ACCESSED)); -} - -static inline pte_t pte_mkspecial(pte_t pte) -{ - return __pte(pte_val(pte) | _PAGE_SPECIAL); -} - -static inline pte_t pte_mkhuge(pte_t pte) -{ - return pte; -} - -#ifdef CONFIG_NUMA_BALANCING -/* - * See the comment in include/asm-generic/pgtable.h - */ -static inline int pte_protnone(pte_t pte) -{ - return (pte_val(pte) & (_PAGE_PRESENT | _PAGE_PROT_NONE)) == _PAGE_PROT_NONE; -} - -static inline int pmd_protnone(pmd_t pmd) -{ - return pte_protnone(pmd_pte(pmd)); -} -#endif - -/* Modify page protection bits */ -static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) -{ - return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); -} - -#define pgd_ERROR(e) \ - pr_err("%s:%d: bad pgd " PTE_FMT ".\n", __FILE__, __LINE__, pgd_val(e)) - - -/* Commit new configuration to MMU hardware */ -static inline void update_mmu_cache(struct vm_area_struct *vma, - unsigned long address, pte_t *ptep) -{ - /* - * The kernel assumes that TLBs don't cache invalid entries, but - * in RISC-V, SFENCE.VMA specifies an ordering constraint, not a - * cache flush; it is necessary even after writing invalid entries. - * Relying on flush_tlb_fix_spurious_fault would suffice, but - * the extra traps reduce performance. So, eagerly SFENCE.VMA. - */ - #if 0 //syg - local_flush_tlb_page(address); - #endif -} - -static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, - unsigned long address, pmd_t *pmdp) -{ - pte_t *ptep = (pte_t *)pmdp; - - update_mmu_cache(vma, address, ptep); -} - -#define __HAVE_ARCH_PTE_SAME -static inline int pte_same(pte_t pte_a, pte_t pte_b) -{ - return pte_val(pte_a) == pte_val(pte_b); -} - -/* - * Certain architectures need to do special things when PTEs within - * a page table are directly modified. Thus, the following hook is - * made available. - */ -static inline void set_pte(pte_t *ptep, pte_t pteval) -{ - *ptep = pteval; -} - -void flush_icache_pte(pte_t pte); - -static inline void set_pte_at(struct mm_struct *mm, - unsigned long addr, pte_t *ptep, pte_t pteval) -{ - if (pte_present(pteval) && pte_exec(pteval)) - flush_icache_pte(pteval); - - set_pte(ptep, pteval); -} - -static inline void pte_clear(struct mm_struct *mm, - unsigned long addr, pte_t *ptep) -{ - set_pte_at(mm, addr, ptep, __pte(0)); -} - - -/* - * THP functions - */ -static inline pmd_t pte_pmd(pte_t pte) -{ - return __pmd(pte_val(pte)); -} - -static inline pmd_t pmd_mkhuge(pmd_t pmd) -{ - return pmd; -} - -static inline pmd_t pmd_mkinvalid(pmd_t pmd) -{ - return __pmd(pmd_val(pmd) & ~(_PAGE_PRESENT|_PAGE_PROT_NONE)); -} - -#define __pmd_to_phys(pmd) (pmd_val(pmd) >> _PAGE_PFN_SHIFT << PAGE_SHIFT) - -static inline unsigned long pmd_pfn(pmd_t pmd) -{ - return ((__pmd_to_phys(pmd) & PMD_MASK) >> PAGE_SHIFT); -} - -static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) -{ - return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); -} - -#define pmd_write pmd_write -static inline int pmd_write(pmd_t pmd) -{ - return pte_write(pmd_pte(pmd)); -} - -static inline int pmd_dirty(pmd_t pmd) -{ - return pte_dirty(pmd_pte(pmd)); -} - -static inline int pmd_young(pmd_t pmd) -{ - return pte_young(pmd_pte(pmd)); -} - -static inline pmd_t pmd_mkold(pmd_t pmd) -{ - return pte_pmd(pte_mkold(pmd_pte(pmd))); -} - -static inline pmd_t pmd_mkyoung(pmd_t pmd) -{ - return pte_pmd(pte_mkyoung(pmd_pte(pmd))); -} - -static inline pmd_t pmd_mkwrite(pmd_t pmd) -{ - return pte_pmd(pte_mkwrite(pmd_pte(pmd))); -} - -static inline pmd_t pmd_wrprotect(pmd_t pmd) -{ - return pte_pmd(pte_wrprotect(pmd_pte(pmd))); -} - -static inline pmd_t pmd_mkclean(pmd_t pmd) -{ - return pte_pmd(pte_mkclean(pmd_pte(pmd))); -} - -static inline pmd_t pmd_mkdirty(pmd_t pmd) -{ - return pte_pmd(pte_mkdirty(pmd_pte(pmd))); -} - -static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, - pmd_t *pmdp, pmd_t pmd) -{ - return set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)); -} - - - -/* - * Encode and decode a swap entry - * - * Format of swap PTE: - * bit 0: _PAGE_PRESENT (zero) - * bit 1: _PAGE_PROT_NONE (zero) - * bits 2 to 6: swap type - * bits 7 to XLEN-1: swap offset - */ -#define __SWP_TYPE_SHIFT 2 -#define __SWP_TYPE_BITS 5 -#define __SWP_TYPE_MASK ((1UL << __SWP_TYPE_BITS) - 1) -#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) - -#define MAX_SWAPFILES_CHECK() \ - BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) - -#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) -#define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) -#define __swp_entry(type, offset) ((swp_entry_t) \ - { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) - -#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) -#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) - -/* - * In the RV64 Linux scheme, we give the user half of the virtual-address space - * and give the kernel the other (upper) half. - */ -#ifdef CONFIG_64BIT -#define KERN_VIRT_START (-(BIT(CONFIG_VA_BITS)) + TASK_SIZE) -#else -#define KERN_VIRT_START FIXADDR_START -#endif - -/* - * Task size is 0x4000000000 for RV64 or 0x9fc00000 for RV32. - * Note that PGDIR_SIZE must evenly divide TASK_SIZE. - */ -#ifdef CONFIG_64BIT -#define TASK_SIZE (PGDIR_SIZE * PTRS_PER_PGD / 2) -#else -#define TASK_SIZE FIXADDR_START -#endif - -#else /* CONFIG_MMU */ - -#define PAGE_SHARED __pgprot(0) -#define PAGE_KERNEL __pgprot(0) -#define swapper_pg_dir NULL -#define TASK_SIZE 0xffffffffUL -#define VMALLOC_START 0 -#define VMALLOC_END TASK_SIZE - -#endif /* !CONFIG_MMU */ - -#define kern_addr_valid(addr) (1) /* FIXME */ - -extern char _start[]; -extern char _end[]; -extern void *_dtb_early_va; -extern uintptr_t _dtb_early_pa; -#if defined(CONFIG_XIP_KERNEL) && defined(CONFIG_MMU) -#define dtb_early_va (*(void **)XIP_FIXUP(&_dtb_early_va)) -#define dtb_early_pa (*(uintptr_t *)XIP_FIXUP(&_dtb_early_pa)) -#else -#define dtb_early_va _dtb_early_va -#define dtb_early_pa _dtb_early_pa -#endif /* CONFIG_XIP_KERNEL */ - -void paging_init(void); -void misc_mem_init(void); - -/* - * ZERO_PAGE is a global shared page that is always zero, - * used for zero-mapped memory areas, etc. - */ -extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; -#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) - -#endif /* !__ASSEMBLY__ */ - -#endif /* _ASM_RISCV_PGTABLE_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/sizes.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/sizes.h deleted file mode 100644 index 7e395dfc6..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/sizes.h +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * include/linux/sizes.h - */ -#ifndef __LINUX_SIZES_H__ -#define __LINUX_SIZES_H__ - -#include - -#define SZ_1 0x00000001 -#define SZ_2 0x00000002 -#define SZ_4 0x00000004 -#define SZ_8 0x00000008 -#define SZ_16 0x00000010 -#define SZ_32 0x00000020 -#define SZ_64 0x00000040 -#define SZ_128 0x00000080 -#define SZ_256 0x00000100 -#define SZ_512 0x00000200 - -#define SZ_1K 0x00000400 -#define SZ_2K 0x00000800 -#define SZ_4K 0x00001000 -#define SZ_8K 0x00002000 -#define SZ_16K 0x00004000 -#define SZ_32K 0x00008000 -#define SZ_64K 0x00010000 -#define SZ_128K 0x00020000 -#define SZ_256K 0x00040000 -#define SZ_512K 0x00080000 - -#define SZ_1M 0x00100000 -#define SZ_2M 0x00200000 -#define SZ_4M 0x00400000 -#define SZ_8M 0x00800000 -#define SZ_16M 0x01000000 -#define SZ_32M 0x02000000 -#define SZ_64M 0x04000000 -#define SZ_128M 0x08000000 -#define SZ_256M 0x10000000 -#define SZ_512M 0x20000000 - -#define SZ_1G 0x40000000 -#define SZ_2G 0x80000000 - -#define SZ_4G _AC(0x100000000, ULL) -#define SZ_8G _AC(0x200000000, ULL) -#define SZ_16G _AC(0x400000000, ULL) -#define SZ_32G _AC(0x800000000, ULL) -#define SZ_64T _AC(0x400000000000, ULL) - -#endif /* __LINUX_SIZES_H__ */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/mmu.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/mmu.h index bf46415aa..7d2855110 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/mmu.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/mmu.h @@ -69,47 +69,7 @@ Enable MMU, cache, write buffer, etc. /* Read and write mmu pagetable register base addr */ -//#define TTBR0_R(val) __asm__ volatile("mrs %0, ttbr0_el1" : "=r"(val)::"memory") -//#define TTBR0_W(val) __asm__ volatile("msr ttbr0_el1, %0" ::"r"(val) : "memory") -#define TTBR0_R(val) 0 -#define TTBR0_W(val) 0 -/* -Read and write mmu pagetable register base addr -*/ -//#define TTBR1_R(val) __asm__ volatile("mrs %0, ttbr1_el1" : "=r"(val)::"memory") -//#define TTBR1_W(val) __asm__ volatile("msr ttbr1_el1, %0" ::"r"(val) : "memory") -#define TTBR1_R(val) 0 -#define TTBR1_W(val) 0 - -/* -Translation Control Register（TCR） -*/ -//#define TCR_R(val) __asm__ volatile("mrs %0, tcr_el1" : "=r"(val)::"memory") -//#define TCR_W(val) __asm__ volatile("msr tcr_el1, %0" ::"r"(val) : "memory") -#define TCR_R(val) 0 -#define TCR_W(val) 0 - -//#define MAIR_R(val) __asm__ volatile("mrs %0, mair_el1" : "=r"(val)::"memory") -//#define MAIR_W(val) __asm__ volatile("msr mair_el1, %0" ::"r"(val) : "memory") -#define MAIR_R(val) 0 -#define MAIR_W(val) 0 -/* -Flush TLB when loading a new page table. -@note If nG is not set in the pte attribute, process switching need flush tlb. -*/ -// #define CLEARTLB(val) __asm__ volatile("tlbi vmalle1" ::: "memory") -//#define CLEARTLB(val) __asm__ volatile("tlbi vmalle1is" ::: "memory") -#define CLEARTLB(val) 0 - -/* -When nG is set in the pte attribute, the process is assigned an ASID, which is stored in the lower 8 bits of the CONTEXTIDR register. -When the process switches, the flush TLB is no longer required anymore. -*/ -//#define CONTEXTIDR_R(val) __asm__ volatile("mrs %0, contextidr_el1" : "=r"(val)) -//#define CONTEXTIDR_W(val) __asm__ volatile("msr contextidr_el1, %0" ::"r"(val)) -#define CONTEXTIDR_R(val) 0 -#define CONTEXTIDR_W(val) 0 #ifndef __ASSEMBLER__ #include diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/pgtable.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/pgtable.h deleted file mode 100644 index 4c39a88ad..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/include/pgtable.h +++ /dev/null @@ -1,76 +0,0 @@ -#ifndef _XIUOS_PGTABLE_H -#define _XIUOS_PGTABLE_H - -#include -#include - - -/* - * On almost all architectures and configurations, 0 can be used as the - * upper ceiling to free_pgtables(): on many architectures it has the same - * effect as using TASK_SIZE. However, there is one configuration which - * must impose a more careful limit, to avoid freeing kernel pgtables. - */ -#ifndef USER_PGTABLES_CEILING -#define USER_PGTABLES_CEILING 0UL -#endif - -/* - * This defines the first usable user address. Platforms - * can override its value with custom FIRST_USER_ADDRESS - * defined in their respective . - */ -#ifndef FIRST_USER_ADDRESS -#define FIRST_USER_ADDRESS 0UL -#endif - -/* - * This defines the generic helper for accessing PMD page - * table page. Although platforms can still override this - * via their respective . - */ -#ifndef pmd_pgtable -#define pmd_pgtable(pmd) pmd_page(pmd) -#endif - -/* - * A page table page can be thought of an array like this: pXd_t[PTRS_PER_PxD] - * - * The pXx_index() functions return the index of the entry in the page - * table page which would control the given virtual address - * - * As these functions may be used by the same code for different levels of - * the page table folding, they are always available, regardless of - * CONFIG_PGTABLE_LEVELS value. For the folded levels they simply return 0 - * because in such cases PTRS_PER_PxD equals 1. - */ - -static inline unsigned long pte_index(unsigned long address) -{ - return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1); -} - -#ifndef pmd_index -static inline unsigned long pmd_index(unsigned long address) -{ - return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1); -} -#define pmd_index pmd_index -#endif - - -#ifndef pgd_index -/* Must be a compile-time constant, so implement it as a macro */ -#define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) -#endif - -#ifndef pte_offset_kernel -static inline pte_t *pte_offset_kernel(pmd_t *pmd, unsigned long address) -{ - return (pte_t *)pmd_page_vaddr(*pmd) + pte_index(address); -} -#define pte_offset_kernel pte_offset_kernel -#endif - - -#endif /* _XIUOS_PGTABLE_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c index cb5849baa..5f3d0ce44 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu.c @@ -36,7 +36,6 @@ Modification: #include "trap_common.h" #include "asm/csr.h" -#include "asm/pfn.h" #include "printf.h" @@ -50,7 +49,7 @@ void load_pgdir(uintptr_t pgdir_paddr) struct ICacheDone* p_icache_done = AchieveResource(&right_group.icache_driver_tag); struct DCacheDone* p_dcache_done = AchieveResource(&right_group.dcache_driver_tag); - csr_write(CSR_SATP, PFN_DOWN(pgdir_paddr) | SATP_MODE); + csr_write(CSR_SATP, (pgdir_paddr >> PAGE_SHIFT) | SATP_MODE); __asm__ __volatile__ ("sfence.vma" : : : "memory"); p_icache_done->invalidateall(); @@ -60,7 +59,7 @@ void load_pgdir(uintptr_t pgdir_paddr) __attribute__((always_inline)) inline static void _tlb_flush(uintptr_t va) { -// __asm__ volatile("tlbi vae1is, %0" ::"r"(va)); + ; } static void tlb_flush_range(uintptr_t vstart, int len) @@ -74,7 +73,7 @@ static void tlb_flush_range(uintptr_t vstart, int len) static void tlb_flush_all() { - CLEARTLB(0); + ; } static struct MmuCommonDone mmu_common_done = { diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c index 1224eb13a..4b3b1ab94 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/mmu_init.c @@ -29,16 +29,50 @@ Modification: #include #include #include -#include "asm/page.h" -#include "pgtable.h" #include "memlayout.h" -#include "ns16550.h" -#include "asm/pgtable-bits.h" +#include + + +#define PTRS_PER_PGD NUM_LEVEL2_PDE +#define PTRS_PER_PMD NUM_LEVEL3_PDE +#define PGDIR_SHIFT LEVEL2_PDE_SHIFT +#define PGDIR_SIZE (1 << PGDIR_SHIFT) +#define PMD_SHIFT LEVEL3_PDE_SHIFT +#define PMD_SIZE (1 << PMD_SHIFT) + +#define _PAGE_KERNEL (_PAGE_READ \ + | _PAGE_WRITE \ + | _PAGE_PRESENT \ + | _PAGE_ACCESSED \ + | _PAGE_DIRTY \ + | _PAGE_GLOBAL) #define PFN_PD(x, prot) (((x) << _PAGE_PFN_SHIFT) | (prot)) #define _PD_PFN(x) ((x) >> _PAGE_PFN_SHIFT) +#define PFN_DOWN(x) ((x) >> PAGE_SHIFT) +#define PFN_PHYS(x) ((x) << PAGE_SHIFT) + +#define pgd_index(a) (((a) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) +#define pmd_index(a) (((a) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) + + extern char _start[]; +extern char _end[]; + + +struct kernel_mapping { + unsigned long virt_addr; + uintptr_t phys_addr; + uintptr_t size; + /* Offset between linear mapping virtual address and kernel load address */ + unsigned long va_pa_offset; + /* Offset between kernel mapping virtual address and kernel load address */ + unsigned long va_kernel_pa_offset; + unsigned long va_kernel_xip_pa_offset; +}; +typedef uint64_t phys_addr_t; + struct kernel_mapping kernel_map; @@ -49,11 +83,9 @@ static uintptr_t trampoline_pmd[PTRS_PER_PMD] __attribute__((aligned(PAGE_SIZE)) static uintptr_t early_pmd[PTRS_PER_PMD] __attribute__((aligned(PAGE_SIZE))); static uintptr_t early_uart_pmd[PTRS_PER_PMD] __attribute__((aligned(PAGE_SIZE))); static uintptr_t early_pmd_free[((PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) >> PGDIR_SHIFT) + 1][PTRS_PER_PMD] __attribute__((aligned(PAGE_SIZE))); -static uintptr_t early_pmd_inear_map[PTRS_PER_PMD] __attribute__((aligned(PAGE_SIZE))); static uintptr_t early_plic_pmd[PTRS_PER_PMD] __attribute__((aligned(PAGE_SIZE))); - static uintptr_t *get_pmd_virt_early(phys_addr_t pa) { /* Before MMU is enabled */ @@ -185,7 +217,7 @@ void setup_vm_early(void) kernel_map.phys_addr = (uintptr_t)(&_start); kernel_map.size = (uintptr_t)(&_end) - kernel_map.phys_addr; - kernel_map.va_pa_offset = PAGE_OFFSET - kernel_map.phys_addr; + kernel_map.va_pa_offset = KERN_OFFSET - kernel_map.phys_addr; kernel_map.va_kernel_pa_offset = kernel_map.virt_addr - kernel_map.phys_addr; /* Setup trampoline PGD and PMD */ From ca35c72d020c057b87bc1c4510340017a4da7bd0 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 22 Jan 2025 09:42:33 +0800 Subject: [PATCH 48/54] Modify riscv csr --- .../arch/riscv/rv64gc/include/asm/csr.h | 3 ++- .../rv64gc/preboot_for_jh7110/include/autoconf.h | 15 --------------- 2 files changed, 2 insertions(+), 16 deletions(-) delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/autoconf.h diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/csr.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/csr.h index 0f45549da..ad0e09892 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/csr.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/csr.h @@ -6,11 +6,12 @@ #ifndef _ASM_RISCV_CSR_H #define _ASM_RISCV_CSR_H -#include "autoconf.h" #include #include +#define CONFIG_64BIT 1 + /* Status register flags */ #define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */ #define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/autoconf.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/autoconf.h deleted file mode 100644 index 0e98745f8..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/autoconf.h +++ /dev/null @@ -1,15 +0,0 @@ -#ifndef _AUTOCONF_H -#define _AUTOCONF_H - -#define CONFIG_64BIT 1 -#define CONFIG_MMU 1 -#define CONFIG_PHYS_ADDR_T_64BIT 1 -#define CONFIG_PAGE_OFFSET 0xffffffe000000000 -#define CONFIG_VA_BITS 39 - - -#define THREAD_SIZE (512 << 2) -#define KERNEL_MAP_VIRT_ADDR 0 /* offsetof(struct kernel_mapping, virt_addr) */ -#define TASK_TI_CPU 32 /* offsetof(struct task_struct, thread_info.cpu) */ - -#endif /* _AUTOCONF_H */ From a6ed30fd5ec698ac3943a4905f21baaa816c10f9 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 22 Jan 2025 16:26:12 +0800 Subject: [PATCH 49/54] Delete invalid code --- .../riscv/rv64gc/include/asm/asm-offsets.h | 112 ------------------ .../arch/riscv/rv64gc/include/asm/mmio.h | 2 + .../riscv/rv64gc/preboot_for_jh7110/config.mk | 3 - .../hardkernel/intr/riscv/rv64gc/trampoline.S | 12 +- 4 files changed, 9 insertions(+), 120 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/asm-offsets.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/asm-offsets.h index 58e0bf035..24bb3db19 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/asm-offsets.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/asm-offsets.h @@ -1,64 +1,6 @@ #ifndef __ASM_OFFSETS_H__ #define __ASM_OFFSETS_H__ -/* - * DO NOT MODIFY. - * - * This file was generated by Kbuild - */ -#define TASK_THREAD_RA 2232 /* offsetof(struct task_struct, thread.ra) */ -#define TASK_THREAD_SP 2240 /* offsetof(struct task_struct, thread.sp) */ -#define TASK_THREAD_S0 2248 /* offsetof(struct task_struct, thread.s[0]) */ -#define TASK_THREAD_S1 2256 /* offsetof(struct task_struct, thread.s[1]) */ -#define TASK_THREAD_S2 2264 /* offsetof(struct task_struct, thread.s[2]) */ -#define TASK_THREAD_S3 2272 /* offsetof(struct task_struct, thread.s[3]) */ -#define TASK_THREAD_S4 2280 /* offsetof(struct task_struct, thread.s[4]) */ -#define TASK_THREAD_S5 2288 /* offsetof(struct task_struct, thread.s[5]) */ -#define TASK_THREAD_S6 2296 /* offsetof(struct task_struct, thread.s[6]) */ -#define TASK_THREAD_S7 2304 /* offsetof(struct task_struct, thread.s[7]) */ -#define TASK_THREAD_S8 2312 /* offsetof(struct task_struct, thread.s[8]) */ -#define TASK_THREAD_S9 2320 /* offsetof(struct task_struct, thread.s[9]) */ -#define TASK_THREAD_S10 2328 /* offsetof(struct task_struct, thread.s[10]) */ -#define TASK_THREAD_S11 2336 /* offsetof(struct task_struct, thread.s[11]) */ -#define TASK_TI_FLAGS 0 /* offsetof(struct task_struct, thread_info.flags) */ -#define TASK_TI_PREEMPT_COUNT 8 /* offsetof(struct task_struct, thread_info.preempt_count) */ -#define TASK_TI_KERNEL_SP 16 /* offsetof(struct task_struct, thread_info.kernel_sp) */ -#define TASK_TI_USER_SP 24 /* offsetof(struct task_struct, thread_info.user_sp) */ -#define TASK_TI_CPU 32 /* offsetof(struct task_struct, thread_info.cpu) */ -#define TASK_THREAD_F0 2344 /* offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F1 2352 /* offsetof(struct task_struct, thread.fstate.f[1]) */ -#define TASK_THREAD_F2 2360 /* offsetof(struct task_struct, thread.fstate.f[2]) */ -#define TASK_THREAD_F3 2368 /* offsetof(struct task_struct, thread.fstate.f[3]) */ -#define TASK_THREAD_F4 2376 /* offsetof(struct task_struct, thread.fstate.f[4]) */ -#define TASK_THREAD_F5 2384 /* offsetof(struct task_struct, thread.fstate.f[5]) */ -#define TASK_THREAD_F6 2392 /* offsetof(struct task_struct, thread.fstate.f[6]) */ -#define TASK_THREAD_F7 2400 /* offsetof(struct task_struct, thread.fstate.f[7]) */ -#define TASK_THREAD_F8 2408 /* offsetof(struct task_struct, thread.fstate.f[8]) */ -#define TASK_THREAD_F9 2416 /* offsetof(struct task_struct, thread.fstate.f[9]) */ -#define TASK_THREAD_F10 2424 /* offsetof(struct task_struct, thread.fstate.f[10]) */ -#define TASK_THREAD_F11 2432 /* offsetof(struct task_struct, thread.fstate.f[11]) */ -#define TASK_THREAD_F12 2440 /* offsetof(struct task_struct, thread.fstate.f[12]) */ -#define TASK_THREAD_F13 2448 /* offsetof(struct task_struct, thread.fstate.f[13]) */ -#define TASK_THREAD_F14 2456 /* offsetof(struct task_struct, thread.fstate.f[14]) */ -#define TASK_THREAD_F15 2464 /* offsetof(struct task_struct, thread.fstate.f[15]) */ -#define TASK_THREAD_F16 2472 /* offsetof(struct task_struct, thread.fstate.f[16]) */ -#define TASK_THREAD_F17 2480 /* offsetof(struct task_struct, thread.fstate.f[17]) */ -#define TASK_THREAD_F18 2488 /* offsetof(struct task_struct, thread.fstate.f[18]) */ -#define TASK_THREAD_F19 2496 /* offsetof(struct task_struct, thread.fstate.f[19]) */ -#define TASK_THREAD_F20 2504 /* offsetof(struct task_struct, thread.fstate.f[20]) */ -#define TASK_THREAD_F21 2512 /* offsetof(struct task_struct, thread.fstate.f[21]) */ -#define TASK_THREAD_F22 2520 /* offsetof(struct task_struct, thread.fstate.f[22]) */ -#define TASK_THREAD_F23 2528 /* offsetof(struct task_struct, thread.fstate.f[23]) */ -#define TASK_THREAD_F24 2536 /* offsetof(struct task_struct, thread.fstate.f[24]) */ -#define TASK_THREAD_F25 2544 /* offsetof(struct task_struct, thread.fstate.f[25]) */ -#define TASK_THREAD_F26 2552 /* offsetof(struct task_struct, thread.fstate.f[26]) */ -#define TASK_THREAD_F27 2560 /* offsetof(struct task_struct, thread.fstate.f[27]) */ -#define TASK_THREAD_F28 2568 /* offsetof(struct task_struct, thread.fstate.f[28]) */ -#define TASK_THREAD_F29 2576 /* offsetof(struct task_struct, thread.fstate.f[29]) */ -#define TASK_THREAD_F30 2584 /* offsetof(struct task_struct, thread.fstate.f[30]) */ -#define TASK_THREAD_F31 2592 /* offsetof(struct task_struct, thread.fstate.f[31]) */ -#define TASK_THREAD_FCSR 2600 /* offsetof(struct task_struct, thread.fstate.fcsr) */ -#define TSK_STACK_CANARY 1080 /* offsetof(struct task_struct, stack_canary) */ #define PT_SIZE 288 /* sizeof(struct pt_regs) */ #define PT_EPC 0 /* offsetof(struct pt_regs, epc) */ #define PT_RA 8 /* offsetof(struct pt_regs, ra) */ @@ -97,60 +39,6 @@ #define PT_STATUS 256 /* offsetof(struct pt_regs, status) */ #define PT_BADADDR 264 /* offsetof(struct pt_regs, badaddr) */ #define PT_CAUSE 272 /* offsetof(struct pt_regs, cause) */ -#define SUSPEND_CONTEXT_REGS 0 /* offsetof(struct suspend_context, regs) */ -#define HIBERN_PBE_ADDR 0 /* offsetof(struct pbe, address) */ -#define HIBERN_PBE_ORIG 8 /* offsetof(struct pbe, orig_address) */ -#define HIBERN_PBE_NEXT 16 /* offsetof(struct pbe, next) */ -#define TASK_THREAD_RA_RA 0 /* offsetof(struct task_struct, thread.ra) - offsetof(struct task_struct, thread.ra) */ -#define TASK_THREAD_SP_RA 8 /* offsetof(struct task_struct, thread.sp) - offsetof(struct task_struct, thread.ra) */ -#define TASK_THREAD_S0_RA 16 /* offsetof(struct task_struct, thread.s[0]) - offsetof(struct task_struct, thread.ra) */ -#define TASK_THREAD_S1_RA 24 /* offsetof(struct task_struct, thread.s[1]) - offsetof(struct task_struct, thread.ra) */ -#define TASK_THREAD_S2_RA 32 /* offsetof(struct task_struct, thread.s[2]) - offsetof(struct task_struct, thread.ra) */ -#define TASK_THREAD_S3_RA 40 /* offsetof(struct task_struct, thread.s[3]) - offsetof(struct task_struct, thread.ra) */ -#define TASK_THREAD_S4_RA 48 /* offsetof(struct task_struct, thread.s[4]) - offsetof(struct task_struct, thread.ra) */ -#define TASK_THREAD_S5_RA 56 /* offsetof(struct task_struct, thread.s[5]) - offsetof(struct task_struct, thread.ra) */ -#define TASK_THREAD_S6_RA 64 /* offsetof(struct task_struct, thread.s[6]) - offsetof(struct task_struct, thread.ra) */ -#define TASK_THREAD_S7_RA 72 /* offsetof(struct task_struct, thread.s[7]) - offsetof(struct task_struct, thread.ra) */ -#define TASK_THREAD_S8_RA 80 /* offsetof(struct task_struct, thread.s[8]) - offsetof(struct task_struct, thread.ra) */ -#define TASK_THREAD_S9_RA 88 /* offsetof(struct task_struct, thread.s[9]) - offsetof(struct task_struct, thread.ra) */ -#define TASK_THREAD_S10_RA 96 /* offsetof(struct task_struct, thread.s[10]) - offsetof(struct task_struct, thread.ra) */ -#define TASK_THREAD_S11_RA 104 /* offsetof(struct task_struct, thread.s[11]) - offsetof(struct task_struct, thread.ra) */ -#define TASK_THREAD_F0_F0 0 /* offsetof(struct task_struct, thread.fstate.f[0]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F1_F0 8 /* offsetof(struct task_struct, thread.fstate.f[1]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F2_F0 16 /* offsetof(struct task_struct, thread.fstate.f[2]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F3_F0 24 /* offsetof(struct task_struct, thread.fstate.f[3]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F4_F0 32 /* offsetof(struct task_struct, thread.fstate.f[4]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F5_F0 40 /* offsetof(struct task_struct, thread.fstate.f[5]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F6_F0 48 /* offsetof(struct task_struct, thread.fstate.f[6]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F7_F0 56 /* offsetof(struct task_struct, thread.fstate.f[7]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F8_F0 64 /* offsetof(struct task_struct, thread.fstate.f[8]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F9_F0 72 /* offsetof(struct task_struct, thread.fstate.f[9]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F10_F0 80 /* offsetof(struct task_struct, thread.fstate.f[10]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F11_F0 88 /* offsetof(struct task_struct, thread.fstate.f[11]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F12_F0 96 /* offsetof(struct task_struct, thread.fstate.f[12]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F13_F0 104 /* offsetof(struct task_struct, thread.fstate.f[13]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F14_F0 112 /* offsetof(struct task_struct, thread.fstate.f[14]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F15_F0 120 /* offsetof(struct task_struct, thread.fstate.f[15]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F16_F0 128 /* offsetof(struct task_struct, thread.fstate.f[16]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F17_F0 136 /* offsetof(struct task_struct, thread.fstate.f[17]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F18_F0 144 /* offsetof(struct task_struct, thread.fstate.f[18]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F19_F0 152 /* offsetof(struct task_struct, thread.fstate.f[19]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F20_F0 160 /* offsetof(struct task_struct, thread.fstate.f[20]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F21_F0 168 /* offsetof(struct task_struct, thread.fstate.f[21]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F22_F0 176 /* offsetof(struct task_struct, thread.fstate.f[22]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F23_F0 184 /* offsetof(struct task_struct, thread.fstate.f[23]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F24_F0 192 /* offsetof(struct task_struct, thread.fstate.f[24]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F25_F0 200 /* offsetof(struct task_struct, thread.fstate.f[25]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F26_F0 208 /* offsetof(struct task_struct, thread.fstate.f[26]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F27_F0 216 /* offsetof(struct task_struct, thread.fstate.f[27]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F28_F0 224 /* offsetof(struct task_struct, thread.fstate.f[28]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F29_F0 232 /* offsetof(struct task_struct, thread.fstate.f[29]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F30_F0 240 /* offsetof(struct task_struct, thread.fstate.f[30]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_F31_F0 248 /* offsetof(struct task_struct, thread.fstate.f[31]) - offsetof(struct task_struct, thread.fstate.f[0]) */ -#define TASK_THREAD_FCSR_F0 256 /* offsetof(struct task_struct, thread.fstate.fcsr) - offsetof(struct task_struct, thread.fstate.f[0]) */ #define PT_SIZE_ON_STACK 288 /* ALIGN(sizeof(struct pt_regs), STACK_ALIGN) */ -#define KERNEL_MAP_VIRT_ADDR 0 /* offsetof(struct kernel_mapping, virt_addr) */ -#define SBI_HART_BOOT_TASK_PTR_OFFSET 0 /* offsetof(struct sbi_hart_boot_data, task_ptr) */ -#define SBI_HART_BOOT_STACK_PTR_OFFSET 8 /* offsetof(struct sbi_hart_boot_data, stack_ptr) */ #endif diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/mmio.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/mmio.h index a3aaf27e5..bd1007705 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/mmio.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/include/asm/mmio.h @@ -17,6 +17,8 @@ #include +#define CONFIG_64BIT 1 + typedef uint8_t u8; typedef uint16_t u16; typedef uint32_t u32; diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk index b016e2557..5bcfefbdf 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/config.mk @@ -1,15 +1,12 @@ export CROSS_COMPILE ?= riscv64-unknown-elf- export ARCH = riscv -# export KBUILD_CFLAGS := -Wall -Wundef -Werror=strict-prototypes -Wno-trigraphs -fno-strict-aliasing -fno-common -fshort-wchar -fno-PIE -Werror=implicit-function-declaration -Werror=implicit-int -Werror=return-type -Wno-format-security -std=gnu89 -Wno-sign-compare -fno-asynchronous-unwind-tables -fno-delete-null-pointer-checks -fno-stack-protector -Wno-main -fomit-frame-pointer -Wdeclaration-after-statement -Wvla -Wno-pointer-sign -Wno-array-bounds -fno-strict-overflow -fno-stack-check -Werror=date-time export KBUILD_CFLAGS := -Wall -Wundef -Wno-trigraphs -fno-strict-aliasing -fno-common -fshort-wchar -fno-PIE -Werror=implicit-function-declaration -Werror=implicit-int -Werror=return-type -Wno-format-security -std=gnu89 -Wno-sign-compare -fno-asynchronous-unwind-tables -fno-delete-null-pointer-checks -fno-stack-protector -Wno-main -fomit-frame-pointer -Wvla -Wno-pointer-sign -Wno-array-bounds -fno-strict-overflow -fno-stack-check -Werror=date-time -export KBUILD_CPPFLAGS := -D__KERNEL__ export KBUILD_AFLAGS := export CHECKFLAGS += -D__riscv -D__riscv_xlen=64 export DEVICE := export CFLAGS := $(KBUILD_CFLAGS) $(KBUILD_AFLAGS) $(CHECKFLAGS) -std=c11 -mcmodel=medany -# .vmlinux.cmd:1:cmd_vmlinux := sh scripts/link-vmlinux.sh "riscv64-linux-gnu-ld" " -melf64lriscv" " --build-id=sha1"; export LFLAGS := -T $(KERNEL_ROOT)/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/jh7110.lds export CXXFLAGS := diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S index 44fac5f1e..eef6e6fed 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S @@ -37,16 +37,18 @@ Modification: .align 4 .global handle_exception handle_exception: + # Here tp is struct thread_info csrrw tp, CSR_SCRATCH, tp bnez tp, _save_context _restore_kernel_tpsp: csrr tp, CSR_SCRATCH - REG_S sp, TASK_TI_KERNEL_SP(tp) + REG_S sp, 16(tp) _save_context: - REG_S sp, TASK_TI_USER_SP(tp) - REG_L sp, TASK_TI_KERNEL_SP(tp) + REG_S sp, 24(tp) + REG_L sp, 16(tp) + # Here sp is struct trapframe addi sp, sp, -(PT_SIZE_ON_STACK) REG_S x1, PT_RA(sp) REG_S x3, PT_GP(sp) @@ -87,7 +89,7 @@ _save_context: */ li t0, SR_SUM | SR_FS - REG_L s0, TASK_TI_USER_SP(tp) + REG_L s0, 24(tp) csrrc s1, CSR_STATUS, t0 csrr s2, CSR_EPC csrr s3, CSR_TVAL @@ -208,7 +210,7 @@ ret_from_exception: resume_userspace: /* Save unwound kernel stack pointer in thread_info */ addi s0, sp, PT_SIZE_ON_STACK - REG_S s0, TASK_TI_KERNEL_SP(tp) + REG_S s0, 16(tp) /* * Save TP into the scratch register , so we can find the kernel data From 1559013f2beea92a6acde924c290db4256b2d84b Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 22 Jan 2025 17:01:19 +0800 Subject: [PATCH 50/54] boot.S start main --- .../riscv/rv64gc/preboot_for_jh7110/boot.S | 2 +- .../hardkernel/intr/riscv/rv64gc/trampoline.S | 2 - .../hardkernel/mmu/riscv/rv64gc/Makefile | 2 +- .../hardkernel/mmu/riscv/rv64gc/bootmmu.c | 86 ------------------- 4 files changed, 2 insertions(+), 90 deletions(-) delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S index d445c8883..21159e7ea 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/boot.S @@ -63,7 +63,7 @@ clear_bss_done: sw zero, 32(tp) /* Start the kernel */ - tail bootmain + tail main relocate_enable_mmu: /* Relocate return address */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S index eef6e6fed..8f32731f9 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/trampoline.S @@ -28,8 +28,6 @@ Modification: 1. first version *************************************************/ -#include "memlayout.h" -#include "core.h" #include "asm/csr.h" #include "asm/asm-offsets.h" diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/Makefile index 016051139..8d25fd00f 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/Makefile @@ -1,4 +1,4 @@ -SRC_FILES := bootmmu.c mmu.c pagetable_attr.c mmu_init.c +SRC_FILES := mmu_init.c mmu.c pagetable_attr.c include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c deleted file mode 100644 index 0f62871c7..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/riscv/rv64gc/bootmmu.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -/** - * @file bootmmu.c - * @brief build pagetable and enable mmu in boot time - * @version 1.0 - * @author AIIT XUOS Lab - * @date 2024.04.26 - */ - -/************************************************* -File name: bootmmu.c -Description: build pagetable and enable mmu in boot time -Others: -History: -Author: AIIT XUOS Lab -Modification: -1. first version -*************************************************/ -#include "core.h" -#include "memlayout.h" -#include "mmio_access.h" -#include "mmu.h" -#include "pagetable.h" -#include "registers.h" -#include "ns16550.h" -#include "printf.h" -#include -#include - -#include -#include - -// -#if 0 -static int test_access_map_address(void) -{ - unsigned long address = KERN_MEM_BASE + (PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) - 4096; - printf_early("to access 0x%lx\n", address); - *(unsigned long *)address = 0x55; - if(*(unsigned long *)address == 0x55) { - printf_early("access 0x%lx done\n", address); - } - return 0; -} - -static int test_access_unmap_address(void) -{ - unsigned long address = KERN_MEM_BASE + (PHY_USER_FREEMEM_BASE - PHY_MEM_BASE) + 4096; - *(unsigned long *)address = 0x55; - printf_early("access 0x%lx done\n", address); - return 0; -} - -static void test_mmu(void) -{ - test_access_map_address(); - test_access_unmap_address(); -} -#endif - -// -extern void main(void); - -void bootmain(void) -{ - _debug_uart_printascii("bootmain start\n"); -#if 0 - test_mmu(); -#endif - - main(); - - _debug_uart_printascii("bootmain end\n"); - while(1); -} - From 25bfec1560a94b36611bdb81da1eed1ca58d0422 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Wed, 22 Jan 2025 18:21:10 +0800 Subject: [PATCH 51/54] Delete unused files --- .../hardkernel/intr/riscv/rv64gc/Makefile | 6 - .../intr/riscv/rv64gc/gicv3/Makefile | 3 - .../intr/riscv/rv64gc/gicv3/gicv3.c | 260 ------------------ .../riscv/rv64gc/gicv3/gicv3_common_opa.h | 140 ---------- .../intr/riscv/rv64gc/gicv3/gicv3_registers.h | 59 ---- .../intr/riscv/rv64gc/jh7110/plic.c | 16 +- .../intr/riscv/rv64gc/jh7110/plic.h | 4 + .../intr/riscv/rv64gc/jh7110/trap.c | 4 +- .../intr/riscv/rv64gc/jh7110/trap_common.c | 9 +- 9 files changed, 25 insertions(+), 476 deletions(-) delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/Makefile delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3.c delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_common_opa.h delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_registers.h diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile index 8aaf42053..ee8377f49 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/Makefile @@ -1,10 +1,4 @@ SRC_FILES := trampoline.S $(BOARD)/trap_common.c $(BOARD)/trap.c $(BOARD)/plic.c error_debug.c hard_spinlock.S - -ifeq ($(BOARD), jh7110) -SRC_DIR := gicv3 SRC_FILES += $(BOARD)/ -endif - include $(KERNEL_ROOT)/compiler.mk - diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/Makefile deleted file mode 100644 index c5085627e..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -SRC_FILES := gicv3.c - -include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3.c deleted file mode 100644 index f299f4966..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3.c +++ /dev/null @@ -1,260 +0,0 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -/** - * @file gicv3.c - * @brief gicv3 operation - * @version 1.0 - * @author AIIT XUOS Lab - * @date 2024.05.10 - */ - -/************************************************* -File name: gicv3.c -Description: gicv3 operation -Others: -History: -Author: AIIT XUOS Lab -Modification: -*************************************************/ -#include - -#include "core.h" -#include "gicv3_common_opa.h" -#include "gicv3_registers.h" - -static struct { - char* gicd; - char* rdist_addrs[NR_CPU]; -} gicv3; - -static inline uint32_t icc_igrpen1_el1() -{ - uint32_t x; -// __asm__ volatile("mrs %0, S3_0_C12_C12_7" : "=r"(x)); - return x; -} - -static inline void w_icc_igrpen1_el1(uint32_t x) -{ -// __asm__ volatile("msr S3_0_C12_C12_7, %0" : : "r"(x)); -} - -static inline uint32_t icc_pmr_el1() -{ - uint32_t x; -// __asm__ volatile("mrs %0, S3_0_C4_C6_0" : "=r"(x)); - return x; -} - -static inline void w_icc_pmr_el1(uint32_t x) -{ -// __asm__ volatile("msr S3_0_C4_C6_0, %0" : : "r"(x)); -} - -inline uint32_t gic_read_irq_ack() -{ - uint32_t x; -// __asm__ volatile("mrs %0, S3_0_C12_C12_0" : "=r"(x)); - return x; -} - -inline void -gic_write_end_of_irq(uint32_t x) -{ -// __asm__ volatile("msr S3_0_C12_C12_1, %0" : : "r"(x)); -} - -static inline uint32_t icc_sre_el1() -{ - uint32_t x; -// __asm__ volatile("mrs %0, S3_0_C12_C12_5" : "=r"(x)); - return x; -} - -static inline void w_icc_sre_el1(uint32_t x) -{ -// __asm__ volatile("msr S3_0_C12_C12_5, %0" : : "r"(x)); -} - -static void gicd_write(uint32_t off, uint32_t val) -{ -// *(volatile uint32_t*)(gicv3.gicd + off) = val; -} - -static uint32_t gicd_read(uint32_t off) -{ -// return *(volatile uint32_t*)(gicv3.gicd + off); - return 0; -} - -static void gicr_write(uint32_t cpuid, uint32_t off, uint32_t val) -{ -// *(volatile uint32_t*)(gicv3.rdist_addrs[cpuid] + off) = val; -} - -static uint32_t gicr_read(uint32_t cpuid, uint32_t off) -{ -// return *(volatile uint32_t*)(gicv3.rdist_addrs[cpuid] + off); - return 0; -} - -static void giccinit() -{ - w_icc_igrpen1_el1(0); - w_icc_pmr_el1(0xff); -} - -static void gicdinit() -{ - gicd_write(D_CTLR, 0); - - uint32_t typer = gicd_read(D_TYPER); - uint32_t lines = typer & 0x1f; - - for (int i = 0; i < lines; i++) - gicd_write(D_IGROUPR(i), ~0); -} - -static void gicrinit(uint32_t cpuid) -{ - gicr_write(cpuid, R_CTLR, 0); - - w_icc_sre_el1(icc_sre_el1() | 1); - - gicr_write(cpuid, R_IGROUPR0, ~0); - gicr_write(cpuid, R_IGRPMODR0, 0); - - uint32_t waker = gicr_read(cpuid, R_WAKER); - gicr_write(cpuid, R_WAKER, waker & ~(1 << 1)); - while (gicr_read(cpuid, R_WAKER) & (1 << 2)) - ; -} - -void gic_enable() -{ - gicd_write(D_CTLR, (1 << 1)); - w_icc_igrpen1_el1(1); -} - -void gic_init() -{ - gicv3.gicd = (char*)GICV3; - for (int i = 0; i < NR_CPU; i++) { - gicv3.rdist_addrs[i] = (char*)(GICV3_REDIST + (i) * 0x20000); - } - - gicdinit(); -} - -void gicv3inithart(uint32_t cpu_id) -{ - giccinit(); - gicrinit(cpu_id); - - gic_enable(); -} - -static void -gic_enable_int(uint32_t intid) -{ - uint32_t is = gicd_read(D_ISENABLER(intid / 32)); - is |= 1 << (intid % 32); - gicd_write(D_ISENABLER(intid / 32), is); -} - -int gic_int_enabled(uint32_t intid) -{ - uint32_t is = gicd_read(D_ISENABLER(intid / 32)); - return is & (1 << (intid % 32)); -} - -static void -gic_clear_pending(uint32_t intid) -{ - uint32_t ic = gicd_read(D_ICPENDR(intid / 32)); - ic |= 1 << (intid % 32); - gicd_write(D_ICPENDR(intid / 32), ic); -} - -static void -gic_set_prio0(uint32_t intid) -{ - // set priority to 0 - uint32_t p = gicd_read(D_IPRIORITYR(intid / 4)); - p &= ~((uint32_t)0xff << (intid % 4 * 8)); // set prio 0 - gicd_write(D_IPRIORITYR(intid / 4), p); -} - -static void gic_set_target(uint32_t intid, uint32_t cpuid) -{ - uint32_t itargetsr = gicd_read(D_ITARGETSR(intid / 4)); - itargetsr &= ~((uint32_t)0xff << (intid % 4 * 8)); - gicd_write(D_ITARGETSR(intid / 4), itargetsr | ((uint32_t)(1 << cpuid) << (intid % 4 * 8))); -} - -static void -gicr_enable_int(uint32_t cpuid, uint32_t intid) -{ - uint32_t is = gicr_read(cpuid, R_ISENABLER0); - is |= 1 << (intid % 32); - gicr_write(cpuid, R_ISENABLER0, is); -} - -static void -gicr_clear_pending(uint32_t cpuid, uint32_t intid) -{ - uint32_t ic = gicr_read(cpuid, R_ICPENDR0); - ic |= 1 << (intid % 32); - gicr_write(cpuid, R_ICPENDR0, ic); -} - -static void -gicr_set_prio0(uint32_t cpuid, uint32_t intid) -{ - uint32_t p = gicr_read(cpuid, R_IPRIORITYR(intid / 4)); - p &= ~((uint32_t)0xff << (intid % 4 * 8)); // set prio 0 - gicr_write(cpuid, R_IPRIORITYR(intid / 4), p); -} - -void gic_setup_ppi(uint32_t cpuid, uint32_t intid) -{ - gicr_set_prio0(cpuid, intid); - gicr_clear_pending(cpuid, intid); - gicr_enable_int(cpuid, intid); -} - -void gic_setup_spi(uint32_t cpuid, uint32_t intid) -{ - gic_set_prio0(intid); - gic_set_target(intid, cpuid); - gic_clear_pending(intid); - gic_enable_int(intid); -} - -// irq from iar -int gic_iar_irq(uint32_t iar) -{ - return iar & 0x3ff; -} - -// interrupt acknowledge register: -// ask GIC what interrupt we should serve. -uint32_t gic_iar() -{ - return gic_read_irq_ack(); -} - -// tell GIC we've served this IRQ. -void gic_eoi(uint32_t iar) -{ - gic_write_end_of_irq(iar); -} diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_common_opa.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_common_opa.h deleted file mode 100644 index 17e3632eb..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_common_opa.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -/** - * @file gicv3_common_opa.h - * @brief gicv3 operation - * @version 1.0 - * @author AIIT XUOS Lab - * @date 2024.05.07 - */ -/************************************************* -File name: gicv3_common_opa.h -Description: gicv3 operation -Others: -History: -Author: AIIT XUOS Lab -Modification: -1. Rename file -*************************************************/ -#pragma once - -#include -#include - -#include - -//! @name Initialization -//@{ -//! @brief Init interrupt handling. -//! -//! This function is intended to be called only by the primary CPU init code, so it will -//! only be called once during system bootup. -//! -//! Also inits the current CPU. You don't need to call gic_init_cpu() separately. -//! -//! @post The interrupt distributor and the current CPU interface are enabled. All interrupts -//! that were pending are cleared, and all interrupts are made secure (group 0). -void gic_init(void); - -//! @name GIC Interrupt Distributor Functions -//@{ -//! @brief Enable or disable the GIC Distributor. -//! -//! Enables or disables the GIC distributor passing both secure (group 0) and non-secure -//! (group 1) interrupts to the CPU interfaces. -//! -//! @param enableIt Pass true to enable or false to disable. -void gic_enable(); - -//! @brief Set the security mode for an interrupt. -//! -//! @param irqID The interrupt number. -//! @param isSecure Whether the interrupt is taken to secure mode. -void gic_set_irq_security(uint32_t irqID, bool isSecure); - -//! @brief Enable or disable an interrupt. -//! -//! @param irqID The number of the interrupt to control. -//! @param isEnabled Pass true to enable or false to disable. -void gic_enable_irq(uint32_t irqID, bool isEnabled); - -//! @brief Set whether a CPU will receive a particular interrupt. -//! -//! @param irqID The interrupt number. -//! @param cpuNumber The CPU number. The first CPU core is 0. -//! @param enableIt Whether to send the interrupt to the specified CPU. Pass true to enable -//! or false to disable. -void gic_set_cpu_target(uint32_t irqID, unsigned cpuNumber, bool enableIt); - -//! @brief Set an interrupt's priority. -//! -//! @param irq_id The interrupt number. -//! @param priority The priority for the interrupt. In the range of 0 through 0xff, with -//! 0 being the highest priority. -void gic_set_irq_priority(uint32_t irq_id, uint32_t priority); - -void gic_setup_spi(uint32_t cpuid, uint32_t intid); -void gic_setup_ppi(uint32_t cpuid, uint32_t intid); - -void gicv3inithart(uint32_t cpu_id); -//! @brief Send a software generated interrupt to a specific CPU. -//! -//! @param irq_id The interrupt number to send. -//! @param target_list Each bit indicates a CPU to which the interrupt will be forwarded. -//! Bit 0 is CPU 0, bit 1 is CPU 1, and so on. If the value is 0, then the interrupt -//! will not be forwarded to any CPUs. This parameter is only used if @a filter_list -//! is set to #kGicSgiFilter_UseTargetList. -//! @param filter_list One of the enums of the #_gicd_sgi_filter enumeration. The selected -//! option determines which CPUs the interrupt will be sent to. If the value -//! is #kGicSgiFilter_UseTargetList, then the @a target_list parameter is used. -void gic_send_sgi(uint32_t irq_id, uint32_t target_list, uint32_t filter_list); -//@} - -//! @name GIC CPU Interface Functions -//@{ -//! @brief Enable or disable the interface to the GIC for the current CPU. -//! -//! @param enableIt Pass true to enable or false to disable. -void gic_cpu_enable(bool enableIt); - -//! @brief Set the mask of which interrupt priorities the CPU will receive. -//! -//! @param priority The lowest priority that will be passed to the current CPU. Pass 0xff to -//! allow all priority interrupts to signal the CPU. -void gic_set_cpu_priority_mask(uint32_t priority); - -//! @brief Acknowledge starting of interrupt handling and get the interrupt number. -//! -//! Normally, this function is called at the beginning of the IRQ handler. It tells the GIC -//! that you are starting to handle an interupt, and returns the number of the interrupt you -//! need to handle. After the interrupt is handled, you should call gic_write_end_of_irq() -//! to signal that the interrupt is completely handled. -//! -//! In some cases, a spurious interrupt might happen. One possibility is if another CPU handles -//! the interrupt. When a spurious interrupt occurs, the end of the interrupt should be indicated -//! but nothing else. -//! -//! @return The number for the highest priority interrupt available for the calling CPU. If -//! the return value is 1022 or 1023, a spurious interrupt has occurred. -uint32_t gic_read_irq_ack(void); - -//! @brief Signal the end of handling an interrupt. -//! -//! @param irq_id The number of the interrupt for which handling has finished. -void gic_write_end_of_irq(uint32_t irq_id); -//@} - -//! @} - -//////////////////////////////////////////////////////////////////////////////// -// EOF -//////////////////////////////////////////////////////////////////////////////// \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_registers.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_registers.h deleted file mode 100644 index 389d6a5b1..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/gicv3/gicv3_registers.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * - * Copyright (C) 2002 ARM Limited, All Rights Reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/** - * @file gicv3_registers.h - * @brief gicv3 registers - * @version 1.0 - * @author AIIT XUOS Lab - * @date 2024.05.09 - */ - -/************************************************* -File name: gicv3_registers.c -Description: gicv3 registers -Others: -History: -Author: AIIT XUOS Lab -Modification: -1. Rename the file -*************************************************/ - -#pragma once - -#include "memlayout.h" - -// clang-format off -// interrupt controller GICv3 -#define GICV3 MMIO_P2V_WO(0xFD400000ULL) -#define GICV3_REDIST MMIO_P2V_WO(0xFD460000ULL) - -#define D_CTLR 0x0 -#define D_TYPER 0x4 -#define D_IGROUPR(n) (0x80 + (uint64_t)(n) * 4) -#define D_ISENABLER(n) (0x100 + (uint64_t)(n) * 4) -#define D_ICENABLER(n) (0x180 + (uint64_t)(n) * 4) -#define D_ISPENDR(n) (0x200 + (uint64_t)(n) * 4) -#define D_ICPENDR(n) (0x280 + (uint64_t)(n) * 4) -#define D_IPRIORITYR(n) (0x400 + (uint64_t)(n) * 4) -#define D_ITARGETSR(n) (0x800 + (uint64_t)(n) * 4) -#define D_ICFGR(n) (0xc00 + (uint64_t)(n) * 4) - -#define R_CTLR 0x0 -#define R_WAKER 0x14 - -#define SGI_BASE 0x10000 -#define R_IGROUPR0 (SGI_BASE + 0x80) -#define R_ISENABLER0 (SGI_BASE + 0x100) -#define R_ICENABLER0 (SGI_BASE + 0x180) -#define R_ICPENDR0 (SGI_BASE + 0x280) -#define R_IPRIORITYR(n) (SGI_BASE + 0x400 + (n) * 4) -#define R_ICFGR0 (SGI_BASE + 0xc00) -#define R_ICFGR1 (SGI_BASE + 0xc04) -#define R_IGRPMODR0 (SGI_BASE + 0xd00) -// clang-format on diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c index aa3546ee5..6a4ae7674 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c @@ -65,7 +65,6 @@ int plic_init(void) return 0; } - void plic_handle_irq(struct pt_regs *regs) { int hwirq; @@ -75,3 +74,18 @@ void plic_handle_irq(struct pt_regs *regs) //TODO csr_set(CSR_IE, IE_EIE); } + +void plic_init_hart(uint32_t cpu_id) +{ + ; +} + +uint32_t plic_read_irq_ack(void) +{ + return 0; +} + +void plic_write_end_of_irq(uint32_t x) +{ + ; +} diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h index 4ac98fc32..db627a4de 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h @@ -3,6 +3,7 @@ #include "memlayout.h" #include "ptrace.h" +#include #define PLIC_BASE PLIC_VIRTMEM_BASE @@ -16,5 +17,8 @@ int plic_init(void); void plic_enable_irq(int cpu, int hwirq, int enable); void plic_handle_irq(struct pt_regs *regs); +void plic_init_hart(uint32_t cpu_id); +uint32_t plic_read_irq_ack(void); +void plic_write_end_of_irq(uint32_t x); #endif /* _RISCV_PLIC_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c index 32c66ca5c..dda066780 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c @@ -97,7 +97,7 @@ void syscall_arch_handler(struct trapframe* tf) assert(cur_cpu()->task != NULL); ERROR("Error Task: %s\n", cur_cpu()->task->name); sys_exit(cur_cpu()->task); - context_switch(&cur_cpu()->task->thread_context.context, &cur_cpu()->scheduler); + context_switch(cur_cpu()->task->thread_context.context, &cur_cpu()->scheduler); panic("dabort end should never be reashed.\n"); } } @@ -157,7 +157,7 @@ struct fault_info { const char *name; }; -static const struct fault_info fault_inf[] = { +static struct fault_info fault_inf[] = { {do_trap_insn_misaligned, "Instruction address misaligned"}, {do_trap_insn_fault, "Instruction access fault"}, {do_trap_insn_illegal, "Illegal instruction"}, diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c index 1c9430251..35442bb23 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c @@ -31,7 +31,6 @@ Modification: #include "core.h" #include "cortex.h" #include "exception_registers.h" -#include "gicv3_common_opa.h" #include "trap_common.h" #include "log.h" @@ -57,7 +56,7 @@ static void _sys_irq_init(int cpu_id) if (cpu_id == 0) { plic_init(); } - gicv3inithart(cpu_id); + plic_init_hart(cpu_id); } static void _sys_trap_init(int cpu_id) @@ -90,7 +89,7 @@ static void _single_irq_disable(int irq, int cpu) static inline uintptr_t* _switch_hw_irqtbl(uintptr_t* new_tbl_base) { - trap_set_exception_vector(new_tbl_base); + trap_set_exception_vector((uintptr_t)new_tbl_base); return NULL; } @@ -102,7 +101,7 @@ static void _bind_irq_handler(int irq, irq_handler_t handler) static uint32_t _hw_before_irq() { - uint32_t iar = gic_read_irq_ack(); + uint32_t iar = plic_read_irq_ack(); return iar; } @@ -113,7 +112,7 @@ static uint32_t _hw_cur_int_num(uint32_t int_info) static void _hw_after_irq(uint32_t int_info) { - gic_write_end_of_irq(int_info); + plic_write_end_of_irq(int_info); } int _cur_cpu_id() From 15a3ac11300330084ab8edc21def5d8400baff69 Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 23 Jan 2025 15:19:10 +0800 Subject: [PATCH 52/54] Modify plic --- .../clock/riscv/rv64gc/jh7110/clock.c | 27 ++------ .../rv64gc/jh7110/include/generic_timer.h | 54 --------------- .../intr/riscv/rv64gc/error_debug.c | 2 - .../riscv/rv64gc/jh7110/exception_registers.h | 68 ------------------- .../intr/riscv/rv64gc/jh7110/plic.c | 22 +++++- .../intr/riscv/rv64gc/jh7110/plic.h | 2 + .../intr/riscv/rv64gc/jh7110/trap.c | 30 ++++---- .../intr/riscv/rv64gc/jh7110/trap_common.c | 2 +- 8 files changed, 45 insertions(+), 162 deletions(-) delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/include/generic_timer.h delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/exception_registers.h diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clock.c b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clock.c index 40929ffa2..f5fa20ec9 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clock.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/clock.c @@ -11,40 +11,25 @@ */ #include "actracer.h" #include "core.h" -#include "generic_timer.h" #include "clock_common_op.h" #include "clint.h" - -// armv8 generic timer driver -#define CNTV_CTL_ENABLE (1 << 0) -#define CNTV_CTL_IMASK (1 << 1) -#define CNTV_CTL_ISTATUS (1 << 2) - +//TODO: static void enable_timer() { - uint32_t c = r_cntp_ctl_el0(); - c |= CNTV_CTL_ENABLE; - c &= ~CNTV_CTL_IMASK; - w_cntp_ctl_el0(c); + ; } static void disable_timer() { - uint32_t c = r_cntp_ctl_el0(); - c |= CNTV_CTL_IMASK; - c &= ~CNTV_CTL_ENABLE; - w_cntp_ctl_el0(c); + ; } static void reload_timer() { // interval 1ms - static uint32_t ms = 1; - uint32_t interval = ms * 1000; - uint32_t interval_clk = interval * (r_cntfrq_el0() / 1000000); - w_cntp_tval_el0(interval_clk); + ; } @@ -63,12 +48,12 @@ static uint32_t _get_clock_int() static uint64_t _get_tick() { - return r_cntvct_el0(); + return 0; } static uint64_t _get_second() { - return _get_tick() / r_cntfrq_el0(); + return 0; } static bool _is_timer_expired() diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/include/generic_timer.h b/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/include/generic_timer.h deleted file mode 100644 index 58cfd1b07..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/clock/riscv/rv64gc/jh7110/include/generic_timer.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -#pragma once - -#include -#include - -// armv8 generic timer -static inline uint32_t r_cntp_ctl_el0() -{ - uint32_t x; -// __asm__ volatile("mrs %0, cntp_ctl_el0" : "=r"(x)); - return x; -} - -static inline void w_cntp_ctl_el0(uint32_t x) -{ -// __asm__ volatile("msr cntp_ctl_el0, %0" : : "r"(x)); -} - -static inline uint32_t r_cntp_tval_el0() -{ - uint32_t x; -// __asm__ volatile("mrs %0, cntp_tval_el0" : "=r"(x)); - return x; -} - -static inline void w_cntp_tval_el0(uint32_t x) -{ -// __asm__ volatile("msr cntp_tval_el0, %0" : : "r"(x)); -} - -static inline uint64_t r_cntvct_el0() -{ - uint64_t x; -// __asm__ volatile("mrs %0, cntvct_el0" : "=r"(x)); - return x; -} - -static inline uint32_t r_cntfrq_el0() -{ - uint32_t x; -// __asm__ volatile("mrs %0, cntfrq_el0" : "=r"(x)); - return x; -} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/error_debug.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/error_debug.c index 3e2c2a1ec..f3afaf934 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/error_debug.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/error_debug.c @@ -41,8 +41,6 @@ Modification: #include #include -#include "exception_registers.h" - #include "assert.h" #include "core.h" #include "log.h" diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/exception_registers.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/exception_registers.h deleted file mode 100644 index aae7e28c8..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/exception_registers.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -/** - * @file exception_registers.h - * @brief exception registers - * @version 1.0 - * @author AIIT XUOS Lab - * @date 2024.05.09 - */ - -static inline void w_vbar_el1(uint64_t x) -{ -// __asm__ volatile("msr vbar_el1, %0" : : "r"(x)); -} - -static inline uint64_t r_esr_el1() -{ - uint64_t x; -// __asm__ volatile("mrs %0, esr_el1" : "=r"(x)); - return x; -} - -static inline void w_esr_el1(uint64_t x) -{ -// __asm__ volatile("msr esr_el1, %0" : : "r"(x)); -} - -static inline uint64_t r_elr_el1() -{ - uint64_t x; -// __asm__ volatile("mrs %0, elr_el1" : "=r"(x)); - return x; -} - -static inline uint64_t r_far_el1() -{ - uint64_t x; -// __asm__ volatile("mrs %0, far_el1" : "=r"(x)); - return x; -} - -static inline uint64_t daif() -{ - uint64_t x; -// __asm__ volatile("mrs %0, daif" : "=r"(x)); - return x; -} - -// enable interrupts(irq) -static inline void intr_on() -{ -// __asm__ volatile("msr daifclr, #0xf" ::: "memory"); -} - -// disable interrupts(irq) -static inline void intr_off() -{ -// __asm__ volatile("msr daifset, #0xf" ::: "memory"); -} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c index 6a4ae7674..b81cf4390 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c @@ -20,20 +20,25 @@ extern unsigned long boot_cpu_hartid; #define CPU_TO_HART(cpu) ((2 * cpu) + 2) +//TODO: to debug void plic_set_priority(int hwirq, int pro) { +#if 0 unsigned int reg = PLIC_PRIORITY(hwirq); writel(pro, reg); +#endif } +//TODO: to debug void plic_enable_irq(int cpu, int hwirq, int enable) { +#if 0 unsigned int hwirq_mask = 1 << (hwirq % 32); int hart = CPU_TO_HART(cpu); unsigned int reg = PLIC_MENABLE(hart) + 4 * (hwirq / 32); // printk("plic_enable_irq hwirq=%d\n", hwirq); -#if 0 + if (enable) { writel(readl(reg) | hwirq_mask, reg); } @@ -47,11 +52,12 @@ void plic_enable_irq(int cpu, int hwirq, int enable) //Refer to linux/drivers/irqchip/irq-sifive-plic.c int plic_init(void) { +#if 0 int i; int hwirq; // printk("plic_init boot_cpu_hartid=%lu\n", boot_cpu_hartid); -#if 0 + for (i = 0; i < MAX_CPUS; i++) { writel(0, PLIC_MTHRESHOLD(CPU_TO_HART(i))); @@ -67,12 +73,14 @@ int plic_init(void) void plic_handle_irq(struct pt_regs *regs) { +#if 0 int hwirq; int hart = CPU_TO_HART(0); unsigned int claim_reg = PLIC_MCLAIM(hart); csr_clear(CSR_IE, IE_EIE); //TODO csr_set(CSR_IE, IE_EIE); +#endif } void plic_init_hart(uint32_t cpu_id) @@ -89,3 +97,13 @@ void plic_write_end_of_irq(uint32_t x) { ; } + +void intr_on(void) +{ + ; +} + +void intr_off(void) +{ + ; +} diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h index db627a4de..ee5802694 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h @@ -20,5 +20,7 @@ void plic_handle_irq(struct pt_regs *regs); void plic_init_hart(uint32_t cpu_id); uint32_t plic_read_irq_ack(void); void plic_write_end_of_irq(uint32_t x); +void intr_on(void); +void intr_off(void); #endif /* _RISCV_PLIC_H */ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c index dda066780..fffd77a2b 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap.c @@ -28,8 +28,6 @@ Modification: *************************************************/ #include -#include "exception_registers.h" - #include "assert.h" #include "core.h" #include "multicores.h" @@ -48,21 +46,25 @@ extern void iabort_handler(struct trapframe* r); void kernel_abort_handler(struct trapframe* tf) { - uint64_t esr = r_esr_el1(); - switch ((esr >> 0x1A) & 0x3F) { - case 0b100100: - case 0b100101: - dabort_handler(tf); - break; - case 0b100000: - case 0b100001: + uint64_t ec = tf->cause; + + switch (ec) { + case 0: + case 1: + case 2: + case 12: iabort_handler(tf); break; + case 4: + case 5: + case 6: + case 7: + case 13: + case 15: + dabort_handler(tf); + break; default: { - uint64_t ec = (esr >> 26) & 0x3f; - uint64_t iss = esr & 0x1ffffff; - ERROR("esr: %016lx %016lx %016lx\n", esr, ec, iss); - ERROR("elr = %016lx far = %016lx\n", r_elr_el1(), r_far_el1()); + ERROR("tf->cause: %016lx\n", tf->cause); ERROR("Current Task: %s.\n", cur_cpu()->task->name); panic("Unimplemented Error Occured.\n"); } diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c index 35442bb23..304165448 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/trap_common.c @@ -30,7 +30,7 @@ Modification: #include "core.h" #include "cortex.h" -#include "exception_registers.h" + #include "trap_common.h" #include "log.h" From c5bd15ab91534025617928f3a6f48ea8ffce834e Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 23 Jan 2025 16:38:32 +0800 Subject: [PATCH 53/54] Modify user ldflags --- Ubiquitous/XiZi_AIoT/services/app/Makefile | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/Ubiquitous/XiZi_AIoT/services/app/Makefile b/Ubiquitous/XiZi_AIoT/services/app/Makefile index 7d004482d..2575bfa7e 100644 --- a/Ubiquitous/XiZi_AIoT/services/app/Makefile +++ b/Ubiquitous/XiZi_AIoT/services/app/Makefile @@ -18,10 +18,9 @@ board_specs = stub.o endif ifeq ($(BOARD), jh7110) toolchain ?= riscv64-unknown-elf- -user_ldflags = -N -Ttext 0 +user_ldflags = -N -Ttext 0 -T $(KERNEL_ROOT)/services/boards/jh7110/jh7110_user.lds CFLAGS = -Wall -Werror -O -fno-omit-frame-pointer -ggdb -gdwarf-2 -MD -mcmodel=medany -fno-common -nostdlib -fno-builtin-strncpy -fno-builtin-strncmp -fno-builtin-strlen -fno-builtin-memset -fno-builtin-memmove -fno-builtin-memcmp -fno-builtin-log -fno-builtin-bzero -fno-builtin-strchr -fno-builtin-exit -fno-builtin-malloc -fno-builtin-putc -fno-builtin-free -fno-builtin-memcpy -Wno-main -fno-builtin-printf -fno-builtin-fprintf -fno-builtin-vprintf -I. -fno-stack-protector -fno-pie -no-pie cflags = $(CFLAGS) -Wno-unused -fno-strict-aliasing -user_lds = -T $(KERNEL_ROOT)/services/boards/jh7110/jh7110_user.lds board_specs = stub.o endif @@ -106,7 +105,7 @@ test_irq_hdlr: test_irq_handler.o libserial.o printf.o libipc.o session.o usysca @${objdump} -S $@ > $@.asm shell: shell_port.o libserial.o printf.o shell_cmd_list.o shell.o shell_ext.o libfs.o libipc.o session.o usyscall.o arch_usyscall.o libmem.o - @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs} ${user_lds} + @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs} @${objdump} -S $@ > $@.asm test_fault: test_fault.o libserial.o printf.o usyscall.o arch_usyscall.o @@ -122,7 +121,7 @@ simple_server: simple_server.o libserial.o printf.o libipc.o session.o simple_se @${objdump} -S $@ > $@.asm fs_server: fs_server.o libfs.o fs.o libserial.o printf.o libipc.o session.o block_io.o usyscall.o arch_usyscall.o libmem.o - @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs} ${user_lds} + @${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs} @${objdump} -S $@ > $@.asm test_priority: test_priority.o libserial.o printf.o usyscall.o arch_usyscall.o libmem.o From 3e70ccddce10ee62ca9f69327e2290a9a2c304ff Mon Sep 17 00:00:00 2001 From: songyanguang <345810377@qq.com> Date: Thu, 23 Jan 2025 16:51:24 +0800 Subject: [PATCH 54/54] Delete unused code --- .../hardkernel/arch/riscv/rv64gc/core.h | 18 --- .../riscv/rv64gc/preboot_for_jh7110/cortex.S | 4 +- .../preboot_for_jh7110/include/cortex.h | 4 +- .../preboot_for_jh7110/include/registers.h | 110 ------------------ 4 files changed, 4 insertions(+), 132 deletions(-) delete mode 100644 Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/registers.h diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h index 0bfa4b198..1af3df2e6 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/core.h @@ -78,24 +78,6 @@ Modification: #define NR_CPU 1 // maximum number of CPUs -__attribute__((always_inline)) static inline uint64_t EL0_mode() // Set ARM mode to EL0 -{ - uint64_t val = 0; - - return val; -} - -__attribute__((always_inline, optimize("O0"))) static inline void cpu_into_low_power() -{ - WFE(); -} - -__attribute__((always_inline, optimize("O0"))) static inline void cpu_leave_low_power() -{ - SEV(); -} - - struct __riscv_d_ext_state { uint64_t f[32]; uint32_t fcsr; diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/cortex.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/cortex.S index 5e15bba09..f0a900093 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/cortex.S +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/cortex.S @@ -1,10 +1,10 @@ /*! - * @file cortexA55.s + * @file cortex.s * @brief This file contains cortexA55 functions * */ /************************************************* -File name: cortexA55.S +File name: cortex.S Description: This file contains cortexA9 functions Others: History: diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/cortex.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/cortex.h index 494fe7a6f..439dedfbc 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/cortex.h +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/cortex.h @@ -28,7 +28,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /** - * @file cortex_a55.h + * @file cortex.h * @brief some cortex A55 core functions * @version 1.0 * @author AIIT XUOS Lab @@ -36,7 +36,7 @@ */ /************************************************* -File name: cortex_a55.h +File name: cortex.h Description: some cortex A55 core functions Others: History: diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/registers.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/registers.h deleted file mode 100644 index d3c08b923..000000000 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/riscv/rv64gc/preboot_for_jh7110/include/registers.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2020 AIIT XUOS Lab - * XiUOS is licensed under Mulan PSL v2. - * You can use this software according to the terms and conditions of the Mulan PSL v2. - * You may obtain a copy of Mulan PSL v2 at: - * http://license.coscl.org.cn/MulanPSL2 - * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, - * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, - * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. - * See the Mulan PSL v2 for more details. - */ -#ifndef INC_SYSREGS_H_ -#define INC_SYSREGS_H_ - -/* SCTLR_EL1, System Control Register (EL1). */ -#define SCTLR_RESERVED \ - ((3 << 28) | (3 << 22) | (1 << 20) | (1 << 11) | (1 << 8) | (1 << 7)) -#define SCTLR_EE_LITTLE_ENDIAN (0 << 25) -#define SCTLR_E0E_LITTLE_ENDIAN (0 << 24) -#define SCTLR_I_CACHE (1 << 12) -#define SCTLR_D_CACHE (1 << 2) -#define SCTLR_MMU_DISABLED (0 << 0) -#define SCTLR_MMU_ENABLED (1 << 0) - -#define SCTLR_VALUE_MMU_DISABLED \ - (SCTLR_RESERVED | SCTLR_EE_LITTLE_ENDIAN | SCTLR_E0E_LITTLE_ENDIAN \ - | SCTLR_I_CACHE | SCTLR_D_CACHE | SCTLR_MMU_DISABLED) - -/* HCR_EL2, Hypervisor Configuration Register (EL2). */ -#define HCR_RW (1 << 31) -#define HCR_VALUE HCR_RW - -/* CPACR_EL1, Architectural Feature Access Control Register. */ -#define CPACR_FP_EN (3 << 20) -#define CPACR_TRACE_EN (0 << 28) -#define CPACR_VALUE (CPACR_FP_EN | CPACR_TRACE_EN) - -/* SCR_EL3, Secure Configuration Register (EL3). */ -#define SCR_RESERVED (3 << 4) -#define SCR_RW (1 << 10) -#define SCR_HCE (1 << 8) -#define SCR_SMD (1 << 7) -#define SCR_NS (1 << 0) -#define SCR_VALUE (SCR_RESERVED | SCR_RW | SCR_HCE | SCR_SMD | SCR_NS) - -/* SPSR_EL1/2/3, Saved Program Status Register. */ -#define SPSR_MASK_ALL (7 << 6) -#define SPSR_EL1h (5 << 0) -#define SPSR_EL2h (9 << 0) -#define SPSR_EL3_VALUE (SPSR_MASK_ALL | SPSR_EL2h) -#define SPSR_EL2_VALUE (SPSR_MASK_ALL | SPSR_EL1h) - -/* Exception Class in ESR_EL1. */ -#define EC_SHIFT 26 -#define EC_UNKNOWN 0x00 -#define EC_SVC64 0x15 -#define EC_DABORT 0x24 -#define EC_IABORT 0x20 - -#define PTE_VALID 1 // level 0,1,2 descriptor: valid -#define PTE_TABLE 2 // level 0,1,2 descriptor: table -#define PTE_V 3 // level 3 descriptor: valid -// PTE_AF(Access Flag) -// -// 0 -- this block entry has not yet. -// 1 -- this block entry has been used. -#define PTE_AF (1 << 10) -// PTE_AP(Access Permission) is 2bit field. -// EL0 EL1 -// 00 -- x RW -// 01 -- RW RW -// 10 -- x RO -// 11 -- RO RO -#define PTE_AP(ap) (((ap) & 3) << 6) -#define PTE_U PTE_AP(1) -#define PTE_RO PTE_AP(2) -#define PTE_URO PTE_AP(3) -#define PTE_PXN (1UL << 53) // Privileged eXecute Never -#define PTE_UXN (1UL << 54) // Unprivileged(user) eXecute Never -#define PTE_XN (PTE_PXN | PTE_UXN) // eXecute Never - -// attribute index -// index is set by mair_el1 -#define AI_DEVICE_nGnRnE_IDX 0x0 -#define AI_NORMAL_NC_IDX 0x1 - -// memory type -#define MT_DEVICE_nGnRnE 0x0 -#define MT_NORMAL_NC 0x44 - -#define PTE_INDX(i) (((i) & 7) << 2) -#define PTE_DEVICE PTE_INDX(AI_DEVICE_nGnRnE_IDX) -#define PTE_NORMAL PTE_INDX(AI_NORMAL_NC_IDX) - -// shift a physical address to the right place for a PTE. -#define PA2PTE(pa) ((uint64_t)(pa) & 0xfffffffff000) -#define PTE2PA(pte) ((uint64_t)(pte) & 0xfffffffff000) - -#define PTE_FLAGS(pte) ((pte) & (0x600000000003ff)) - -// translation control register -// #define TCR_T0SZ(n) ((n) & 0x3f) -// #define TCR_TG0(n) (((n) & 0x3) << 14) -// #define TCR_T1SZ(n) (((n) & 0x3f) << 16) -// #define TCR_TG1(n) (((n) & 0x3) << 30) -// #define TCR_IPS(n) (((n) & 0x7) << 32) - -#define ISS_MASK 0xFFFFFF - -#endif // INC_SYSREGS_H_