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Modify plic

This commit is contained in:
songyanguang 2024-12-19 20:07:38 +08:00
parent ffd2262300
commit 06bb9c4e9b
2 changed files with 6 additions and 3 deletions
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7
Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c
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@ -32,12 +32,15 @@ void plic_enable_irq(int cpu, int hwirq, int enable)
int hart = CPU_TO_HART(cpu); int hart = CPU_TO_HART(cpu);
unsigned int reg = PLIC_MENABLE(hart) + 4 * (hwirq / 32); unsigned int reg = PLIC_MENABLE(hart) + 4 * (hwirq / 32);
printk("plic_enable_irq hwirq=%d\n", hwirq);
#if 0
if (enable) { if (enable) {
writel(readl(reg) | hwirq_mask, reg); writel(readl(reg) | hwirq_mask, reg);
} }
else { else {
writel(readl(reg) & ~hwirq_mask, reg); writel(readl(reg) & ~hwirq_mask, reg);
} }
#endif
} }
//TODO: to debug //TODO: to debug
@ -48,7 +51,7 @@ int plic_init(void)
int hwirq; int hwirq;
printk("plic_init boot_cpu_hartid=%lu\n", boot_cpu_hartid); printk("plic_init boot_cpu_hartid=%lu\n", boot_cpu_hartid);
#if 0
for (i = 0; i < MAX_CPUS; i++) { for (i = 0; i < MAX_CPUS; i++) {
writel(0, PLIC_MTHRESHOLD(CPU_TO_HART(i))); writel(0, PLIC_MTHRESHOLD(CPU_TO_HART(i)));
@ -58,7 +61,7 @@ int plic_init(void)
} }
} }
csr_set(CSR_IE, IE_EIE); csr_set(CSR_IE, IE_EIE);
#endif
return 0; return 0;
} }

2
Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h
View File

@ -4,7 +4,7 @@
#include "memlayout.h" #include "memlayout.h"
#include "ptrace.h" #include "ptrace.h"
#define PLIC_BASE PLIC_PHYMEM_BASE #define PLIC_BASE PLIC_VIRTMEM_BASE
#define PLIC_PRIORITY(hwirq) (PLIC_BASE + (hwirq) * 4) #define PLIC_PRIORITY(hwirq) (PLIC_BASE + (hwirq) * 4)
#define PLIC_PENDING(hwirq) (PLIC_BASE + 0x1000 + ((hwirq) / 32) * 4) #define PLIC_PENDING(hwirq) (PLIC_BASE + 0x1000 + ((hwirq) / 32) * 4)