diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c
index b003384db..af02658f7 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.c
@@ -32,12 +32,15 @@ void plic_enable_irq(int cpu, int hwirq, int enable)
     int hart = CPU_TO_HART(cpu);
     unsigned int reg = PLIC_MENABLE(hart) + 4 * (hwirq / 32);
 
+    printk("plic_enable_irq hwirq=%d\n", hwirq);
+#if 0
     if (enable) {
         writel(readl(reg) | hwirq_mask, reg);
     }
     else {
         writel(readl(reg) & ~hwirq_mask, reg);
     }
+#endif
 }
 
 //TODO: to debug
@@ -48,7 +51,7 @@ int plic_init(void)
     int hwirq;
 
     printk("plic_init boot_cpu_hartid=%lu\n", boot_cpu_hartid);
-
+#if 0
     for (i = 0; i < MAX_CPUS; i++) {
         writel(0, PLIC_MTHRESHOLD(CPU_TO_HART(i)));
 
@@ -58,7 +61,7 @@ int plic_init(void)
         }
     }
     csr_set(CSR_IE, IE_EIE);
-
+#endif
     return 0;
 }
 
diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h
index 2b01ec1a0..4ac98fc32 100644
--- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h
+++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/riscv/rv64gc/jh7110/plic.h
@@ -4,7 +4,7 @@
 #include "memlayout.h"
 #include "ptrace.h"
 
-#define PLIC_BASE    PLIC_PHYMEM_BASE
+#define PLIC_BASE    PLIC_VIRTMEM_BASE
 
 #define PLIC_PRIORITY(hwirq) (PLIC_BASE + (hwirq) * 4)
 #define PLIC_PENDING(hwirq) (PLIC_BASE + 0x1000 + ((hwirq) / 32) * 4)