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d7ba7679b6a45dafdbdc4d4709ab49e2c0ec54cf
OpenBLAS/kernel
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Zhang Xianyi d7ba7679b6 Merge branch 'develop' into risc-v
2020-10-16 23:27:38 +08:00
..
alpha
…
arm
Add double precision universal intrinsics for X86/ARM
2020-10-15 10:29:42 +08:00
arm64
Merge pull request #2867 from Qiyu8/usimd-floatdot
2020-10-10 12:10:25 +02:00
generic
Rename "HALF" and "sh" to "BFLOAT16" and "sb"
2020-10-11 23:56:17 +02:00
ia64
…
mips
Delete KERNEL.1004K
2020-04-19 15:44:30 +02:00
mips64
Fix compilation problem on loongson platform
2020-04-09 19:28:15 +08:00
power
POWER10: Change the packing format for bfloat16
2020-10-13 16:05:10 -05:00
riscv64
Change default RISC-V 64-bit corename to RISCV64_GENERIC
2020-02-27 14:46:15 +08:00
simd
Revert "add double precision SSE"
2020-10-15 08:37:02 +02:00
sparc
…
x86
Enable COOPERLAKE build target
2020-08-13 06:18:00 +08:00
x86_64
Silence a redefinition warning
2020-10-15 19:08:12 +02:00
zarch
s390x: fix cscal and zscal implementations
2020-09-21 13:10:05 +02:00
CMakeLists.txt
Change "HALF" and "sh" to "BFLOAT16" and "sb"
2020-10-12 00:00:55 +02:00
Makefile
fix core list for sse/sse2
2020-10-16 09:55:48 +02:00
Makefile.L1
Fix build issues with bfloat16
2020-10-13 11:00:22 -05:00
Makefile.L2
Allow compiling only a subset of kernels for specific variable types
2020-10-11 14:52:09 +02:00
Makefile.L3
Merge branch 'develop' into risc-v
2020-10-16 23:27:38 +08:00
Makefile.LA
…
setparam-ref.c
Use ifdef instead of if
2020-10-15 19:05:37 +02:00
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