 Xianyi
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bfaa80c316
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fixed #4 csrot & drot returned the wrong result when incx==incy==0 on i686 arch.
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2011-02-18 03:00:58 +08:00 |
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Xianyi Zhang
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c5852d4e30
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fixed #4 csrot returned the wrong result when incx==incy==0.
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2011-02-16 23:39:43 +08:00 |
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Xianyi Zhang
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84ba64e65b
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fixed a bug in drot whe incx or incy equals to zero.
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2011-02-16 23:35:41 +08:00 |
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Xianyi Zhang
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1e671b49f3
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Did the experiment with Loongson 3A 128bit load & store instruction.
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2011-01-29 03:05:27 +08:00 |
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Xianyi Zhang
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77b7020d69
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changed prefetch order.
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2011-01-29 03:03:34 +08:00 |
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Xianyi Zhang
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e003b811ab
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load x & y contiguously in axpy.
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2011-01-28 11:18:50 +08:00 |
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Xianyi Zhang
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ebe2da8474
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Modified aligned size. Added additional prefetch instruction because of cache line is 32 bytes in Loongson 3A.
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2011-01-27 23:07:06 +08:00 |
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Xianyi Zhang
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c0b5992fab
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added axpy kernel with prefetch for Loongson3A. To-Do: tuning prefetch distance & instruction order.
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2011-01-26 22:34:33 +08:00 |
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Xianyi Zhang
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342bbc3871
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Import GotoBLAS2 1.13 BSD version codes.
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2011-01-24 14:54:24 +00:00 |
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