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1318 Commits

Author SHA1 Message Date
Xianyi Zhang 141091f528 Merge branch 'master' of github.com:xianyi/OpenBLAS into x86 2011-03-22 14:16:18 +08:00
Xianyi Zhang e4bb6f2482 Fixed the detecting bug on Intel Core i5. Thank ggl329 for the patch. 2011-03-22 14:09:47 +08:00
Xianyi Zhang 0edcdd470e Updated the developing version to v0.1 alpha2. 2011-03-20 23:35:31 +08:00
Xianyi Zhang d672491122 Init Changelog file for next release version(v0.1alpha2). 2011-03-20 23:30:09 +08:00
Xianyi Zhang 972062903c OpenBLAS 0.1 alpha version 1. 2011-03-20 22:44:57 +08:00
Xianyi Zhang d9aa359e69 Merge remote branch 'origin/loongson3a' into x86 2011-03-20 21:57:58 +08:00
Xianyi Zhang 04769bdf54 Merge remote branch 'origin/loongson3a' into x86 2011-03-20 21:57:09 +08:00
Xianyi Zhang 6f058487ab Detect Intel Core Clarkdale & Arrandale 2011-03-20 21:56:40 +08:00
Xianyi Zhang f405b5bcc5 Fixed the bug about Loongson3A gsLQC1 & gsSQC1 instructions in daxpy kernel. Now daxpy is correct. 2011-03-18 23:05:56 +00:00
Xianyi Zhang 2b8643e0de Merge branch 'loongson3a' of github.com:xianyi/OpenBLAS into loongson3a 2011-03-18 01:20:15 +00:00
Xianyi Zhang c84f8be453 Supported detecting new kernel(2.6.36) & new Loongson3A03 CPU. 2011-03-18 01:10:58 +00:00
Wang Qian d5cffd506a Modified the default kernel makefile in MIPS64 arch. 2011-03-07 11:23:12 +00:00
Xianyi Zhang 5838f12995 Support unalign address in daxpy on loongson3a simd.. 2011-03-05 10:17:10 +08:00
Xianyi Zhang 5444a3f8f7 Unroll to 16 in daxpy on loongson3a. 2011-03-04 17:50:17 +08:00
Xianyi Zhang 88cbfcc5b5 Merge commit 'origin/x86' into loongson3a 2011-03-04 14:11:52 +00:00
Xianyi Zhang ce78abe37e Merge branch 'x86' of github.com:xianyi/OpenBLAS into x86 2011-03-04 11:53:04 +08:00
Xianyi Zhang 8f1090d32a Support NO_LAPACK=1 to build the lib without LAPACK functions. 2011-03-04 11:51:32 +08:00
Xianyi 272f62a2b6 Changed movlps macro name in capital in x86/zdot_sse2.S file. 2011-03-03 00:46:39 +08:00
Xianyi 36016fe349 On x86 32bits, gcc 4.4.3 generated wrong codes (movsd) from movlps in zdot_sse2.S line 191. 
This would casue zdotu & zdotc failures. Instead, use movlpd to walk around it. Fixed #8. Fixed #9.
 2011-03-02 18:45:43 +08:00
Xianyi Zhang 44acb7503e Added zdotu with x & y offset=1 test case. 2011-03-02 18:03:40 +08:00
Xianyi Zhang 6eb02bbb9c Merge remote branch 'origin/x86' into loongson3a 2011-03-02 13:52:05 +08:00
Xianyi Zhang 0e782b9bd3 updated the changelog. 2011-03-02 13:40:55 +08:00
Xianyi Zhang 588737210d Fixed randomly SEGFAULT when nodemask==NULL with above Linux 2.6.34. Fixed #12. Thank Mr.Ei-ji Nakama providing this patch. 2011-03-02 13:38:32 +08:00
Xianyi Zhang cdf33edac3 Added Changelog. Fixed #11. 2011-02-26 12:27:56 +08:00
Xianyi Zhang f7a5e049e2 Enable Debug flags in memory alloc and init functions. 2011-02-26 11:51:39 +08:00
Xianyi Zhang 1b97ec1a7c Added DEBUG option in Makefile.rule. Fixed DEBUG typo mistakes. 2011-02-26 11:19:54 +08:00
Xianyi Zhang 36b3a730d3 Merge branch 'x86' of github.com:xianyi/OpenBLAS into x86 2011-02-24 17:02:52 +08:00
Xianyi Zhang 128418f49b Fixed #10. Supported GOTO_NUM_THREADS & GOTO_THREADS_TIMEOUT environment variables. 2011-02-24 16:32:13 +08:00
Xianyi 12214e1d0f Fixed #7. Modified axpy kernel codes to avoid unloop with incx==0 or incy==0 in x86 32bits arch. 2011-02-23 20:08:34 +08:00
Xianyi Zhang cd2cbabecc Added unit test case (zdotu, N=1). 2011-02-22 14:16:46 +08:00
Xianyi Zhang 854137e0fd Supported building debug version. 2011-02-22 13:40:40 +08:00
Xianyi Zhang afbe3c9791 Improved the quality of codes in unit test. 
Thanks José Luis García Pallero
 2011-02-21 00:43:15 +08:00
Xianyi Zhang 0cfd29a819 Fixed #7. 1)Disable the multi-thread and 2) Modified kernel codes to avoid unloop in axpy function when incx==0 or incy==0. 2011-02-21 00:24:21 +08:00
Xianyi Zhang 109b86d00e Added axpy unit test with incx==0 and incy==0. 2011-02-21 00:17:33 +08:00
Xianyi Zhang 78da0e0a0c Fixed #6. Disable multi-thread swap when incx==0 or incy==0. 2011-02-20 17:14:38 +08:00
Xianyi Zhang 8dd3fd7f26 Added swap unit test with incx==0 and incy==0. 2011-02-20 17:13:12 +08:00
Xianyi Zhang 51454082c6 Updated readme file. 2011-02-19 00:18:17 +08:00
Xianyi Zhang e51364edb4 Fixed #5 Detected Intel Westmere (using Nehalem codes) in build and dynamic arch build. 
Thanks Cao He from Dawning supporting Intel Xeon 5660 testbed.
 2011-02-19 00:03:50 +08:00
Xianyi bfaa80c316 fixed #4 csrot & drot returned the wrong result when incx==incy==0 on i686 arch. 2011-02-18 03:00:58 +08:00
Xianyi bd7a74234f Disable quad and x precision objs in reference. 2011-02-18 02:50:32 +08:00
Xianyi Zhang 029d5d16d0 Merge branch 'master' into loongson3a 2011-02-17 00:39:09 +08:00
Xianyi Zhang c84315782c Merge branch 'x86' of github.com:xianyi/OpenBLAS into x86 2011-02-16 23:41:15 +08:00
Xianyi Zhang c5852d4e30 fixed #4 csrot returned the wrong result when incx==incy==0. 2011-02-16 23:39:43 +08:00
Xianyi Zhang c79696cc61 Added rot testcase when incx == incy ==1. 2011-02-16 23:35:41 +08:00
Xianyi Zhang 84ba64e65b fixed a bug in drot whe incx or incy equals to zero. 2011-02-16 23:35:41 +08:00
Xianyi Zhang e3e7547712 Merge branch 'master' into x86 2011-02-16 17:42:12 +08:00
Xianyi Zhang 1dd1bba66c Updated gitignore. 2011-02-16 17:37:48 +08:00
Xianyi Zhang fbf95688d6 Added utest frame using CUnit(http://cunit.sourceforge.net/). 2011-02-16 17:33:06 +08:00
Xianyi Zhang b8b27bec5c fixed a bug in drot whe incx or incy equals to zero. 2011-02-16 00:18:45 +08:00
Xianyi Zhang 1e671b49f3 Did the experiment with Loongson 3A 128bit load & store instruction. 2011-01-29 03:05:27 +08:00