Jiaxun Yang
4197c354fa
Set proper assembler arch for MIPS64
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Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2022-08-12 13:13:31 +01:00
gxw
4b548857d6
Add msa support for loongson
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1. Using core loongson3r3 and loongson3r4 for loongson
2. Add DYNAMIC_ARCH for loongson
Change-Id: I1c6b54dbeca3a0cc31d1222af36a7e9bd6ab54c1
2020-12-09 10:28:46 +08:00
Martin Kroeker
2d89603e9d
Increase BUFFER_SIZE on mips64 to match SGEMM parameters
2020-04-28 10:40:40 +02:00
Martin Kroeker
99dde1d2c9
Add read barrier definition
2020-04-13 12:14:58 +02:00
fengrl
d4c8853a02
Update common_mips64.h
2018-10-09 11:20:16 +08:00
James Cowgill
de7875ca5d
mips: remove incorrect blas_lock implementations
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MIPS 32-bit currently has an empty blas_lock implementation which is
worse than nothing at all. MIPS 64-bit does has a blas_lock
implementation but is broken. Remove them and fallback to the generic
version in common.h which should do the right thing on MIPS.
2017-05-05 17:28:03 +01:00
James Cowgill
67836c2ab4
mips: implement MB and WMB
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The MIPS architecture has weak memory ordering and therefore requires
sutible memory barriers when doing lock free programming with multiple
threads (just like ARM does). This commit implements those barriers for
MIPS and MIPS64 using GCC bultins which is probably easiest way.
2017-05-05 17:14:03 +01:00
Shivraj Patil
2c3dfe2bf3
MIPS P5600(32 bit) and I6400(64 bit) cores support added.
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Seperated mips and mips64 files.
Configurations support for mips 32 bit.
Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 14:03:18 +05:30
Grazvydas Ignotas
6b92204a7c
add fallback blas_lock implementation
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to be used on armv5 and new platforms
2015-08-16 18:59:17 +02:00
Grazvydas Ignotas
e12cf1123e
add fallback rpcc implementation
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- use on arm, arm64 and any new platform
- use faster integer math instead of double
- use similar scale as rdtsc so that timeouts work
2015-08-16 18:59:16 +02:00
Zhang Xianyi
2fb02626da
Update organization info.
2014-11-25 15:28:58 +08:00
Timothy Gu
6c2ead30f0
Remove all trailing whitespace except lapack-netlib
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Signed-off-by: Timothy Gu <timothygu99@gmail.com>
2014-06-27 12:05:18 -07:00
Zhang Xianyi
16eb780e13
Refs #262 . Fixed compatibility issues of GNU stack markings with PathScale EKOPath(tm) Compiler Suite: Version 4.0.12.1
2013-09-22 09:37:59 +08:00
Zhang Xianyi
a2930664f4
Refs #262 . Added executable stack markings.
2013-07-28 00:09:40 +08:00
Xianyi Zhang
6958c1a1aa
Fixed the SEGFAULT bug with Loongcc and Loongson3.
2013-04-11 15:33:43 +08:00
Wang Qian
c2dad58ad1
Adding n32 multiple threads condition.
2011-12-01 16:33:11 +00:00
Xianyi Zhang
285e69e2d1
Disable using simple thread level3 to fix a bug on Loongson 3B.
2011-11-17 16:46:26 +00:00
Xianyi Zhang
d1baf14a64
Enable thread affinity on Loongson 3B. Fixed the bug of reading cycle counter.
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In Loongson 3A and 3B, the CPU core increases the counter in every 2 cycles by default.
2011-11-11 17:49:41 +00:00
Xianyi Zhang
b95ad4cfaf
Support detecting ICT Loongson-3B CPU.
2011-11-09 19:29:50 +00:00
traz
7fa3d23dd9
Complete cgemm function, but no optimization.
2011-09-15 16:08:23 +00:00
traz
cb0214787b
Modify compile options.
2011-08-30 20:57:00 +00:00
Xianyi Zhang
921e040b15
Changed default page size to 16KB on Loongson 3A.
2011-04-11 21:46:48 +00:00
Xianyi Zhang
c0b5992fab
added axpy kernel with prefetch for Loongson3A. To-Do: tuning prefetch distance & instruction order.
2011-01-26 22:34:33 +08:00
Xianyi Zhang
376677452f
Modified the unsupported instruction on Loongson3A. Closed #1 OpenBLAS could run on Loongson3A now.
2011-01-25 17:34:47 +08:00
Xianyi Zhang
342bbc3871
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 14:54:24 +00:00