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mips: implement MB and WMB 

The MIPS architecture has weak memory ordering and therefore requires
sutible memory barriers when doing lock free programming with multiple
threads (just like ARM does). This commit implements those barriers for
MIPS and MIPS64 using GCC bultins which is probably easiest way.
This commit is contained in:
James Cowgill 2017-05-04 14:32:46 +01:00
parent bba6676803
commit 67836c2ab4
2 changed files with 4 additions and 4 deletions
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4
common_mips.h
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@ -33,8 +33,8 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#ifndef COMMON_MIPS
#define COMMON_MIPS
#define MB
#define WMB
#define MB __sync_synchronize()
#define WMB __sync_synchronize()
#define INLINE inline

4
common_mips64.h
View File

@ -71,8 +71,8 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#ifndef COMMON_MIPS64
#define COMMON_MIPS64
#define MB
#define WMB
#define MB __sync_synchronize()
#define WMB __sync_synchronize()
#define INLINE inline