From 67836c2ab48a5d6a8cd227358fa67e2a260eba34 Mon Sep 17 00:00:00 2001 From: James Cowgill Date: Thu, 4 May 2017 14:32:46 +0100 Subject: [PATCH] mips: implement MB and WMB The MIPS architecture has weak memory ordering and therefore requires sutible memory barriers when doing lock free programming with multiple threads (just like ARM does). This commit implements those barriers for MIPS and MIPS64 using GCC bultins which is probably easiest way. --- common_mips.h | 4 ++-- common_mips64.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/common_mips.h b/common_mips.h index 5a2881415..bb579d166 100644 --- a/common_mips.h +++ b/common_mips.h @@ -33,8 +33,8 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef COMMON_MIPS #define COMMON_MIPS -#define MB -#define WMB +#define MB __sync_synchronize() +#define WMB __sync_synchronize() #define INLINE inline diff --git a/common_mips64.h b/common_mips64.h index 6078bf35b..21e706ca3 100644 --- a/common_mips64.h +++ b/common_mips64.h @@ -71,8 +71,8 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #ifndef COMMON_MIPS64 #define COMMON_MIPS64 -#define MB -#define WMB +#define MB __sync_synchronize() +#define WMB __sync_synchronize() #define INLINE inline