48698b2b1d
LoongArch64: Rename core
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Use microarchitecture name instead of meaningless strings to name the core,
the legacy core is still retained.
1. Rename LOONGSONGENERIC to LA64_GENERIC
2. Rename LOONGSON3R5 to LA464
3. Rename LOONGSON2K1000 to LA264
2024-09-29 09:35:21 +08:00
b925f61fb0
Add support for Cortex-A76
2024-04-02 19:44:17 +02:00
bf2310442b
Fix get_num_cores for AIX.
2024-02-21 13:26:28 -06:00
1093def0d1
Merge branch 'risc-v' into develop
2024-01-29 11:11:39 +00:00
9c49a81d54
Resolve conflicts
2024-01-23 19:08:53 +03:00
e1afb23811
Fix BLAS and LAPACK tests for C910V and RISCV64_ZVL256B targets
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* Fixed bugs in dgemm, [a]min\max, asum kernels
* Added zero checks for BLAS kernels
* Added dsdot implementation for RVV 0.7.1
* Fixed bugs in _vector files for C910V and RISCV64_ZVL256B targets
* Added additional definitions for RISCV64_ZVL256B target
2024-01-23 19:01:31 +03:00
ec89466e14
Add CSKY support
2024-01-16 23:45:06 +08:00
e4586e81b8
[RISC-V] Add RISC-V Vector 128-bit target
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Current RVV x280 target depends on vlen=512-bits for Level 3 operations.
Commit adds generic target that supports vlen=128-bits.
New target uses the same scalable kernels as x280 for Level 1&2 operations, and autogenerated kernels for Level 3 operations.
Functional correctness of Level 3 operations tested on vlen=128-bits using QEMU v8.1.1 for ctests and BLAS-Tester.
2023-12-04 11:02:18 +00:00
281e834566
do not pass -j flag to the MAKE variable
2023-03-31 09:25:51 -04:00
31fd13d048
MIPS: make HAVE_MSA reflect cpu capability and NO_MSA software/env
2023-01-02 22:19:13 +01:00
e5313f53d5
Merge branch 'develop' of https://github.com/HellerZheng/OpenBLAS_riscv_x280 into HellerZheng-develop
2022-12-03 12:00:52 +08:00
fd4f52c797
Add SVE implementation for sdot/ddot
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This adds an SVE implementation to sdot/ddot when available, falling back to the previous Advanced SIMD kernel where there's no SVE implementation for the kernel.
All the targets were essentially treating `dot_thunderx2t99.c` as the Advanced SIMD implementation so I've renamed it to better fit with the feature detection.
2022-12-01 12:07:50 +00:00
bef47917bd
Initial version for riscv sifive x280
2022-11-15 00:06:25 -08:00
bd30120ba7
Merge pull request #3720 from FlyGoat/mips64
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Make it work on general MIPS64 processors
2022-08-19 20:24:27 +02:00
a50b29c540
Provide a fallback MIPS64_GENERIC target
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It is really dangerous to fallback to Loongson core on other
MIPS64 processors.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2022-08-12 13:13:28 +01:00
a03ed065e1
Wire up alpha in new build system
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Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
2022-08-11 15:08:46 +01:00
3573306a69
LoongArch64: Add core LOONGSON2K1000 and LOONGSONGENERIC
2022-07-25 16:04:56 +08:00
14ae22bf7a
Add fallback value for bogus sc_nprocessors_conf
2022-05-27 00:29:17 +02:00
8f13ab94d2
Merge pull request #3613 from Rabenda/fix-riscv
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Fix riscv64 detect
2022-05-04 07:22:47 +02:00
18427f3759
Have getarch downgrade the RISCV C910V target to GENERIC if compiler lacks vector support
2022-05-03 23:29:55 +02:00
8123324c99
Fix riscv64 arch detect
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Signed-off-by: Han Gao <gaohan@uniontech.com>
2022-04-27 02:29:43 +08:00
48e421934f
CortexX1 is only ArmV8
2022-03-28 17:31:26 +02:00
09b8545fc5
Add initial support for M1 on Linux, Phytium FT2xxx series, ARM Cortex 510/710/X1/X2
2022-03-27 15:24:40 +02:00
93a81856ae
Revert AVX512 capability check from PR #1980 (moved to build)
2022-03-23 15:22:13 +01:00
bc93f468ef
Add Elbrus E2000 architecture as generic x86_64 compatible
2022-01-22 18:53:38 +01:00
19c8f615dc
OpenBLAS: aarch64: Add neoverse-v1/n2 architecture specifics
2022-01-07 00:28:17 +00:00
454edd741c
Merge pull request #3425 from binebrank/arm_sve_dgemm
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Add dgemm kernel for arm64 SVE
2021-11-26 16:14:55 +01:00
9388f05a3c
configure SVE Makefile
2021-11-21 18:33:43 +01:00
a569fa1540
MIPS P5600 and 24KC,1004K cpus do not support MSA
2021-11-13 23:26:48 +01:00
7093372e32
add ARMV8SVE target
2021-11-01 22:53:21 +01:00
22bf5c27ba
Add basic support for the Fujitsu A64FX ( #3415 )
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* Add initial support for Fujitsu A64FX as generic ARMV8
2021-10-18 15:00:19 +02:00
4280dff103
Add NO_AVX=1 fallbacks to Sapphire Rapids build
2021-10-12 01:39:09 -07:00
3dc6052c7e
initial support for Sapphire Rapids platform
2021-10-12 01:30:40 -07:00
32fee86033
Correct misplaced ifdef lines
2021-09-06 23:44:20 +02:00
72f3ce5f08
Add NO_AVX=1 fallbacks to newer generation x86_64 for completeness ( #3360 )
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* Add NO_AVX=1 fallbacks to newer generation x86_64 for completeness
* Update .travis.yml
2021-09-05 20:35:48 +02:00
af0a69f355
Add support for LOONGARCH64
2021-07-27 15:29:12 +08:00
b7da75e4fd
WiP CORTEX A55 support
2021-06-19 21:37:51 +02:00
0a535e58d8
getarch.c: define OPENBLAS_SUPPORTED for riscv64
2020-12-29 12:06:39 +00:00
be24c66a7c
Keep LOONGSON3A and LOONGSON3B for loongson
2020-12-10 10:53:13 +08:00
4b548857d6
Add msa support for loongson
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1. Using core loongson3r3 and loongson3r4 for loongson
2. Add DYNAMIC_ARCH for loongson
Change-Id: I1c6b54dbeca3a0cc31d1222af36a7e9bd6ab54c1
2020-12-09 10:28:46 +08:00
2e99e2699b
Add workaround for gcc 4.6 miscompiling assembly kernels with -mavx
2020-11-29 15:32:17 +01:00
11ebe5fa25
Avoid redefinition warning
2020-11-22 21:16:07 +01:00
fc35b72ae1
Refs #2899
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Merge branch 'openblas-open-910' of git://github.com/damonyu1989/OpenBLAS into damonyu1989-openblas-open-910
2020-11-10 09:38:04 +08:00
913cc9a4ca
Merge branch 'develop' into risc-v
2020-11-10 09:18:25 +08:00
ec088bf33a
Fix missing AVX2 and FMA3 capabilities in FORCE_target mode
2020-11-08 13:15:40 +01:00
e8cbf0fc50
Output predefined HAVE_ entries to Makefile.conf for ARM with specified TARGET
2020-10-27 23:01:19 +01:00
1a0c185122
Support cross-compiling for Apple Vortex
2020-10-18 18:54:54 +02:00
d7ba7679b6
Merge branch 'develop' into risc-v
2020-10-16 23:27:38 +08:00
ef8e7d0279
Add the support for RISC-V Vector.
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Change-Id: Iae7800a32f5af3903c330882cdf6f292d885f266
2020-10-15 16:09:02 +08:00
881c15179f
remove default support for FMA4 on zen architect
2020-09-27 09:35:50 +08:00
gxw
Martin Kroeker
Chip-Kerchner
Sergei Lewis
Andrey Sokolov
kseniyazaytseva
Dirreke
Octavian Maghiar
Guillaume Horel
Xianyi Zhang
Chris Sidebottom
Heller Zheng
Jiaxun Yang
gxw
Han Gao
Sunita Nadampalli
Bine Brank
Wangyang Guo
User User-User
Aurelien Jarno
Zhang Xianyi
damonyu
Qiyu8