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try to maintain cache line alignment for odd BLAS L1 work splits

This commit is contained in:
Andrew 2018-12-07 00:15:27 +01:00
parent 5839734284
commit 5f99b61aa7
1 changed files with 2 additions and 2 deletions
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4
driver/others/blas_l1_thread.c
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@ -65,7 +65,7 @@ int blas_level1_thread(int mode, BLASLONG m, BLASLONG n, BLASLONG k, void *alpha
/* Adjust Parameters */ /* Adjust Parameters */
width = blas_quickdivide(i + nthreads - num_cpu - 1, width = blas_quickdivide(i + nthreads - num_cpu - 1,
nthreads - num_cpu); nthreads - num_cpu);
width = MAX(width,((width-1)&~15)+16);
i -= width; i -= width;
if (i < 0) width = width + i; if (i < 0) width = width + i;
@ -136,7 +136,7 @@ int blas_level1_thread_with_return_value(int mode, BLASLONG m, BLASLONG n, BLASL
/* Adjust Parameters */ /* Adjust Parameters */
width = blas_quickdivide(i + nthreads - num_cpu - 1, width = blas_quickdivide(i + nthreads - num_cpu - 1,
nthreads - num_cpu); nthreads - num_cpu);
width = MAX(width,((width-1)&~15)+16);
i -= width; i -= width;
if (i < 0) width = width + i; if (i < 0) width = width + i;