forked from xuos/xiuos
support mm command for semc test
This commit is contained in:
wlyu
parent
55c8de20d9
commit
c4eaff938b
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#
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# This file is autogenerated: PLEASE DO NOT EDIT IT.
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#
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# You can use "make menuconfig" to make any modifications to the installed .config file.
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# You can then do "make savedefconfig" to generate a new defconfig file that includes your
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# modifications.
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#
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CONFIG_ADD_NUTTX_FETURES=y
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD="xidatong-arm32"
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CONFIG_ARCH_BOARD_XIDATONG_ARM32=y
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CONFIG_ARCH_CHIP="imxrt"
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CONFIG_ARCH_CHIP_IMXRT=y
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CONFIG_ARCH_CHIP_MIMXRT1052CVL5B=y
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CONFIG_ARCH_INTERRUPTSTACK=10240
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CONFIG_ARCH_STACKDUMP=y
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CONFIG_ARMV7M_DCACHE=y
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CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
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CONFIG_ARMV7M_ICACHE=y
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CONFIG_ARMV7M_USEBASEPRI=y
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CONFIG_BOARD_LOOPSPERMSEC=104926
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CONFIG_BUILTIN=y
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CONFIG_CLOCK_MONOTONIC=y
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CONFIG_EXAMPLES_HELLO=y
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CONFIG_IMXRT_GPIO_IRQ=y
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CONFIG_IMXRT_GPIO3_0_15_IRQ=y
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CONFIG_IDLETHREAD_STACKSIZE=2048
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CONFIG_IMXRT_LPUART1=y
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CONFIG_INTELHEX_BINARY=y
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CONFIG_LPUART1_SERIAL_CONSOLE=y
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CONFIG_NSH_ARCHINIT=y
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CONFIG_NSH_BUILTIN_APPS=y
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CONFIG_NSH_DISABLE_IFUPDOWN=y
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CONFIG_NSH_FILEIOSIZE=512
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CONFIG_NSH_LINELEN=64
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CONFIG_NSH_READLINE=y
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CONFIG_RAM_SIZE=524288
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CONFIG_RAM_START=0x20200000
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CONFIG_RAW_BINARY=y
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CONFIG_SCHED_HPWORK=y
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CONFIG_SCHED_WAITPID=y
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CONFIG_START_DAY=14
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CONFIG_START_MONTH=3
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CONFIG_SYSTEM_NSH=y
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CONFIG_DEV_GPIO=y
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CONFIG_READLINE_CMD_HISTORY=y
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CONFIG_READLINE_CMD_HISTORY_LEN=100
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CONFIG_READLINE_CMD_HISTORY_LINELEN=120
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CONFIG_READLINE_TABCOMPLETION=y
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CONFIG_FS_ROMFS=y
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CONFIG_NSH_ROMFSETC=y
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CONFIG_NSH_ARCHROMFS=y
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CONFIG_BOARDCTL_RESET=y
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CONFIG_INIT_ENTRYPOINT="nsh_main"
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CONFIG_IMXRT_SEMC=y
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CONFIG_ARM_MPU=y
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CONFIG_ARM_MPU_NREGIONS=16
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CONFIG_IMXRT_SEMC_SDRAM=y
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CONFIG_IMXRT_SDRAM_START=0x80000000
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CONFIG_IMXRT_SDRAM_SIZE=31457280
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CONFIG_IMXRT_SDRAM_HEAP=y
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CONFIG_IMXRT_SDRAM_HEAPOFFSET=0x0
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CONFIG_ARCH_USE_MPU=y
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CONFIG_MM_REGIONS=2
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CONFIG_TESTING_MM=y
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CONFIG_TESTING_MM_PROGNAME="mm"
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CONFIG_TESTING_MM_PRIORITY=100
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CONFIG_TESTING_MM_STACKSIZE=2048
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@ -0,0 +1,227 @@
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/****************************************************************************
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* arch/arm/src/imxrt/imxrt_mpuinit.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <assert.h>
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#include <nuttx/userspace.h>
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#include "mpu.h"
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#include "barriers.h"
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#include "hardware/imxrt_memorymap.h"
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#include "imxrt_mpuinit.h"
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#ifdef CONFIG_ARM_MPU
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifndef MAX
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# define MAX(a,b) a > b ? a : b
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#endif
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#ifndef MIN
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# define MIN(a,b) a < b ? a : b
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#endif
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#ifndef CONFIG_ARMV7M_DCACHE
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/* With Dcache off:
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* Cacheable (MPU_RASR_C) and Bufferable (MPU_RASR_B) needs to be off
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*/
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# undef MPU_RASR_B
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# define MPU_RASR_B 0
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# define RASR_B_VALUE 0
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# define RASR_C_VALUE 0
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#else
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# ifndef CONFIG_ARMV7M_DCACHE_WRITETHROUGH
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/* With Dcache on:
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* Cacheable (MPU_RASR_C) and Bufferable (MPU_RASR_B) needs to be on
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*/
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# define RASR_B_VALUE MPU_RASR_B
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# define RASR_C_VALUE MPU_RASR_C
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# else
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/* With Dcache in WRITETHROUGH Bufferable (MPU_RASR_B)
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* needs to be off, except for FLASH for alignment leniency
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*/
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# define RASR_B_VALUE 0
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# define RASR_C_VALUE MPU_RASR_C
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# endif
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: imxrt_mpu_initialize
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*
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* Description:
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* Configure the MPU to permit user-space access to only restricted i.MXRT
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* resources.
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*
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****************************************************************************/
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void imxrt_mpu_initialize(void)
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{
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#ifdef CONFIG_BUILD_PROTECTED
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uintptr_t datastart;
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uintptr_t dataend;
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#endif
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/* Show MPU information */
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mpu_showtype();
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#ifdef CONFIG_ARMV7M_DCACHE
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/* Memory barrier */
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ARM_DMB();
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#ifdef CONFIG_IMXFT_QSPI
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/* Make QSPI memory region strongly ordered */
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mpu_priv_stronglyordered(IMXRT_QSPIMEM_BASE, IMXRT_QSPIMEM_SIZE);
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#endif
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#endif
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#ifdef CONFIG_BUILD_PROTECTED
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/* Configure user flash and SRAM space */
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DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart);
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mpu_user_flash(USERSPACE->us_textstart,
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USERSPACE->us_textend - USERSPACE->us_textstart);
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datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart);
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dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend);
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DEBUGASSERT(dataend >= datastart);
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mpu_user_intsram(datastart, dataend - datastart);
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#else
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mpu_configure_region(0xc0000000, 512 * 1024 * 1024,
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MPU_RASR_TEX_DEV | /* Device
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* Not Cacheable
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* Not Bufferable
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* Not Shareable */
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MPU_RASR_AP_RWRW); /* P:RW U:RW
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* Instruction access */
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mpu_configure_region(IMXRT_EXTMEM_BASE, 1024 * 1024 * 1024,
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MPU_RASR_TEX_DEV | /* Device
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* Not Cacheable
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* Not Bufferable
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* Not Shareable */
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MPU_RASR_AP_RWRW); /* P:RW U:RW
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* Instruction access */
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mpu_configure_region(IMXRT_FLEXCIPHER_BASE, 8 * 1024 * 1024,
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MPU_RASR_TEX_NOR | /* Normal */
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RASR_C_VALUE | /* Cacheable */
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MPU_RASR_B | /* Bufferable
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* Not Shareable */
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MPU_RASR_AP_RORO); /* P:RO U:RO
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* Instruction access */
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mpu_configure_region(IMXRT_ITCM_BASE, 128 * 1024,
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MPU_RASR_TEX_NOR | /* Normal */
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RASR_C_VALUE | /* Cacheable */
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RASR_B_VALUE | /* Bufferable
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* Not Shareable */
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MPU_RASR_AP_RWRW); /* P:RW U:RW
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* Instruction access */
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mpu_configure_region(IMXRT_DTCM_BASE, 128 * 1024,
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MPU_RASR_TEX_NOR | /* Normal */
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RASR_C_VALUE | /* Cacheable */
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RASR_B_VALUE | /* Bufferable
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* Not Shareable */
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MPU_RASR_AP_RWRW); /* P:RW U:RW
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* Instruction access */
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#if 0
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mpu_configure_region(IMXRT_OCRAM2_BASE, 512 * 1024,
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MPU_RASR_TEX_NOR | /* Normal */
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RASR_C_VALUE | /* Cacheable */
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RASR_B_VALUE | /* Bufferable
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* Not Shareable */
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MPU_RASR_AP_RWRW); /* P:RW U:RW
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* Instruction access */
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#endif
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mpu_configure_region(IMXRT_OCRAM_BASE, 512 * 1024,
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MPU_RASR_TEX_NOR | /* Normal */
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RASR_C_VALUE | /* Cacheable */
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RASR_B_VALUE | /* Bufferable
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* Not Shareable */
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MPU_RASR_AP_RWRW); /* P:RW U:RW
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* Instruction access */
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mpu_configure_region(IMXRT_EXTMEM_BASE, 32 * 1024 * 1024,
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MPU_RASR_TEX_SO | /* Ordered */
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RASR_C_VALUE | /* Cacheable */
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RASR_B_VALUE | /* Bufferable
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* Not Shareable */
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MPU_RASR_AP_RWRW); /* P:RW U:RW
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* Instruction access */
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mpu_configure_region(0x81e00000, 2 * 1024 * 1024,
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MPU_RASR_TEX_NOR | /* Normal
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* Not Cacheable
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* Not Bufferable
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* Not Shareable */
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MPU_RASR_AP_RWRW); /* P:RW U:RW
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* Instruction access */
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mpu_control(true, true, true);
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return;
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#endif
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/* Then enable the MPU */
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mpu_control(true, false, true);
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}
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/****************************************************************************
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* Name: imxrt_mpu_uheap
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*
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* Description:
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* Map the user-heap region.
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*
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* This logic may need an extension to handle external SDRAM).
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*
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****************************************************************************/
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#ifdef CONFIG_BUILD_PROTECTED
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void imxrt_mpu_uheap(uintptr_t start, size_t size)
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{
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mpu_user_intsram(start, size);
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}
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#endif
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#endif /* CONFIG_ARM_MPU */
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