From c4eaff938bed6754fe5ab14784215426a9328825 Mon Sep 17 00:00:00 2001 From: wlyu Date: Thu, 22 Sep 2022 21:16:28 +0800 Subject: [PATCH] support mm command for semc test --- .../xidatong-arm32/configs/mmnsh/defconfig | 68 ++++++ .../nuttx/arch/arm/src/imxrt/imxrt_mpuinit.c | 227 ++++++++++++++++++ 2 files changed, 295 insertions(+) create mode 100755 Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/configs/mmnsh/defconfig create mode 100755 Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/imxrt_mpuinit.c diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/configs/mmnsh/defconfig b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/configs/mmnsh/defconfig new file mode 100755 index 000000000..2c6697e66 --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong-arm32/configs/mmnsh/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ADD_NUTTX_FETURES=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="xidatong-arm32" +CONFIG_ARCH_BOARD_XIDATONG_ARM32=y +CONFIG_ARCH_CHIP="imxrt" +CONFIG_ARCH_CHIP_IMXRT=y +CONFIG_ARCH_CHIP_MIMXRT1052CVL5B=y +CONFIG_ARCH_INTERRUPTSTACK=10240 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_ARMV7M_USEBASEPRI=y +CONFIG_BOARD_LOOPSPERMSEC=104926 +CONFIG_BUILTIN=y +CONFIG_CLOCK_MONOTONIC=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_IMXRT_GPIO_IRQ=y +CONFIG_IMXRT_GPIO3_0_15_IRQ=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_IMXRT_LPUART1=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=524288 +CONFIG_RAM_START=0x20200000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=3 +CONFIG_SYSTEM_NSH=y +CONFIG_DEV_GPIO=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_CMD_HISTORY_LEN=100 +CONFIG_READLINE_CMD_HISTORY_LINELEN=120 +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_FS_ROMFS=y +CONFIG_NSH_ROMFSETC=y +CONFIG_NSH_ARCHROMFS=y +CONFIG_BOARDCTL_RESET=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_IMXRT_SEMC=y +CONFIG_ARM_MPU=y +CONFIG_ARM_MPU_NREGIONS=16 +CONFIG_IMXRT_SEMC_SDRAM=y +CONFIG_IMXRT_SDRAM_START=0x80000000 +CONFIG_IMXRT_SDRAM_SIZE=31457280 +CONFIG_IMXRT_SDRAM_HEAP=y +CONFIG_IMXRT_SDRAM_HEAPOFFSET=0x0 +CONFIG_ARCH_USE_MPU=y +CONFIG_MM_REGIONS=2 +CONFIG_TESTING_MM=y +CONFIG_TESTING_MM_PROGNAME="mm" +CONFIG_TESTING_MM_PRIORITY=100 +CONFIG_TESTING_MM_STACKSIZE=2048 diff --git a/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/imxrt_mpuinit.c b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/imxrt_mpuinit.c new file mode 100755 index 000000000..55c4ff05f --- /dev/null +++ b/Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/imxrt_mpuinit.c @@ -0,0 +1,227 @@ +/**************************************************************************** + * arch/arm/src/imxrt/imxrt_mpuinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "mpu.h" +#include "barriers.h" + +#include "hardware/imxrt_memorymap.h" + +#include "imxrt_mpuinit.h" + +#ifdef CONFIG_ARM_MPU + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef MAX +# define MAX(a,b) a > b ? a : b +#endif + +#ifndef MIN +# define MIN(a,b) a < b ? a : b +#endif + +#ifndef CONFIG_ARMV7M_DCACHE + /* With Dcache off: + * Cacheable (MPU_RASR_C) and Bufferable (MPU_RASR_B) needs to be off + */ +# undef MPU_RASR_B +# define MPU_RASR_B 0 +# define RASR_B_VALUE 0 +# define RASR_C_VALUE 0 +#else +# ifndef CONFIG_ARMV7M_DCACHE_WRITETHROUGH + /* With Dcache on: + * Cacheable (MPU_RASR_C) and Bufferable (MPU_RASR_B) needs to be on + */ +# define RASR_B_VALUE MPU_RASR_B +# define RASR_C_VALUE MPU_RASR_C + +# else + /* With Dcache in WRITETHROUGH Bufferable (MPU_RASR_B) + * needs to be off, except for FLASH for alignment leniency + */ +# define RASR_B_VALUE 0 +# define RASR_C_VALUE MPU_RASR_C +# endif +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_mpu_initialize + * + * Description: + * Configure the MPU to permit user-space access to only restricted i.MXRT + * resources. + * + ****************************************************************************/ + +void imxrt_mpu_initialize(void) +{ +#ifdef CONFIG_BUILD_PROTECTED + uintptr_t datastart; + uintptr_t dataend; +#endif + + /* Show MPU information */ + + mpu_showtype(); + +#ifdef CONFIG_ARMV7M_DCACHE + /* Memory barrier */ + + ARM_DMB(); + +#ifdef CONFIG_IMXFT_QSPI + /* Make QSPI memory region strongly ordered */ + + mpu_priv_stronglyordered(IMXRT_QSPIMEM_BASE, IMXRT_QSPIMEM_SIZE); + +#endif +#endif + +#ifdef CONFIG_BUILD_PROTECTED + /* Configure user flash and SRAM space */ + + DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart); + + mpu_user_flash(USERSPACE->us_textstart, + USERSPACE->us_textend - USERSPACE->us_textstart); + + datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); + dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); + + DEBUGASSERT(dataend >= datastart); + + mpu_user_intsram(datastart, dataend - datastart); +#else + mpu_configure_region(0xc0000000, 512 * 1024 * 1024, + MPU_RASR_TEX_DEV | /* Device + * Not Cacheable + * Not Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Instruction access */ + + mpu_configure_region(IMXRT_EXTMEM_BASE, 1024 * 1024 * 1024, + MPU_RASR_TEX_DEV | /* Device + * Not Cacheable + * Not Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Instruction access */ + + mpu_configure_region(IMXRT_FLEXCIPHER_BASE, 8 * 1024 * 1024, + MPU_RASR_TEX_NOR | /* Normal */ + RASR_C_VALUE | /* Cacheable */ + MPU_RASR_B | /* Bufferable + * Not Shareable */ + MPU_RASR_AP_RORO); /* P:RO U:RO + * Instruction access */ + + mpu_configure_region(IMXRT_ITCM_BASE, 128 * 1024, + MPU_RASR_TEX_NOR | /* Normal */ + RASR_C_VALUE | /* Cacheable */ + RASR_B_VALUE | /* Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Instruction access */ + + mpu_configure_region(IMXRT_DTCM_BASE, 128 * 1024, + MPU_RASR_TEX_NOR | /* Normal */ + RASR_C_VALUE | /* Cacheable */ + RASR_B_VALUE | /* Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Instruction access */ +#if 0 + mpu_configure_region(IMXRT_OCRAM2_BASE, 512 * 1024, + MPU_RASR_TEX_NOR | /* Normal */ + RASR_C_VALUE | /* Cacheable */ + RASR_B_VALUE | /* Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Instruction access */ +#endif + mpu_configure_region(IMXRT_OCRAM_BASE, 512 * 1024, + MPU_RASR_TEX_NOR | /* Normal */ + RASR_C_VALUE | /* Cacheable */ + RASR_B_VALUE | /* Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Instruction access */ + + mpu_configure_region(IMXRT_EXTMEM_BASE, 32 * 1024 * 1024, + MPU_RASR_TEX_SO | /* Ordered */ + RASR_C_VALUE | /* Cacheable */ + RASR_B_VALUE | /* Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Instruction access */ + + mpu_configure_region(0x81e00000, 2 * 1024 * 1024, + MPU_RASR_TEX_NOR | /* Normal + * Not Cacheable + * Not Bufferable + * Not Shareable */ + MPU_RASR_AP_RWRW); /* P:RW U:RW + * Instruction access */ + + mpu_control(true, true, true); + return; +#endif + + /* Then enable the MPU */ + + mpu_control(true, false, true); +} + +/**************************************************************************** + * Name: imxrt_mpu_uheap + * + * Description: + * Map the user-heap region. + * + * This logic may need an extension to handle external SDRAM). + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void imxrt_mpu_uheap(uintptr_t start, size_t size) +{ + mpu_user_intsram(start, size); +} +#endif + +#endif /* CONFIG_ARM_MPU */