TODO: Port ok1028a-c.

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/Makefile

@@ -1,4 +1,10 @@
 # The following three platforms support compatiable instructions.
+ifneq ($(findstring $(BOARD), ok1028a-c), )
+SRC_DIR := armv8-a
+endif
+ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), )
 SRC_DIR := armv7-a
+endif
+
 
 include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/Makefile

@@ -0,0 +1,7 @@
+# The following three platforms support compatiable instructions.
+ifneq ($(findstring $(BOARD), ok1028a-c), )
+SRC_DIR := cortex-a72
+endif
+
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/Makefile

@@ -0,0 +1,4 @@
+SRC_DIR := preboot_for_$(BOARD)
+SRC_FILES := context_switch.S core.c
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/context_switch.S

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *        http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+/**
+ * @file context_switch.S
+ * @brief task context switch functions
+ * @version 1.0
+ * @author AIIT XUOS Lab
+ * @date 2024.4.10
+ */
+
+/*************************************************
+File name: context_switch.S
+Description: task context switch functions
+Others: 
+History:
+*************************************************/
+.global context_switch
+
+context_switch:
+    # Save  store original context to stack
+    stp x29, lr, [sp, #-16]!
+    stp x27, x28, [sp, #-16]!
+    stp x25, x26, [sp, #-16]!
+    stp x23, x24, [sp, #-16]!
+    stp x21, x22, [sp, #-16]!
+    stp x19, x20, [sp, #-16]!
+
+    # Switch stacks
+    mov x19, sp
+    str x19, [x0]
+    mov sp, x1
+
+    # restore context from stack
+    ldp x19, x20, [sp], #16
+    ldp x21, x22, [sp], #16
+    ldp x23, x24, [sp], #16
+    ldp x25, x26, [sp], #16
+    ldp x27, x28, [sp], #16
+    ldp x29, lr, [sp], #16
+
+    ret

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/core.c

@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *        http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+
+/**
+ * @file core.c
+ * @brief spl boot function
+ * @version 1.0
+ * @author AIIT XUOS Lab
+ * @date 2024.04.23
+ */
+
+/*************************************************
+File name: core.c
+Description: cortex-a9 core function, include cpu registers operations、core boot
+Others:
+History:
+1. Date: 2024-04-23
+Author: AIIT XUOS Lab
+Modification:
+1. first version
+*************************************************/
+
+/*********cortex-a72 general register************
+   EL0               |              EL1            |              EL2            |            EL3
+
+     x0;            
+     x1;
+     x2;
+      x3;
+     x4;
+     x5;
+     x6;
+     x7;
+     x8;
+     x9;
+     x10;
+     x11;
+     x12;
+     x13;
+     x14;
+     x15;
+     x16;
+     x17;
+     x18;
+     x19;
+     x20;
+     x21;
+     x22;
+     x23;
+     x24;
+     x25;    
+     x26;
+     x27;
+     x28;
+     x29;    
+     x30;
+/*********cortex-a72  special register************
+                                                XZR            
+                                                PC
+     SP_EL0              SP_EL1             SP_EL2              SP_EL3
+                                  SPSR_EL1        SPSR_EL2         SPSR_EL3
+                                  ELR_EL1           ELR_EL2            ELR_EL3
+************************************************/
+
+
+#include "core.h"

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/core.h

@@ -0,0 +1,232 @@
+/*
+ * Copyright (c) 2020 AIIT XUOS Lab
+ * XiUOS is licensed under Mulan PSL v2.
+ * You can use this software according to the terms and conditions of the Mulan PSL v2.
+ * You may obtain a copy of Mulan PSL v2 at:
+ *        http://license.coscl.org.cn/MulanPSL2
+ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
+ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
+ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
+ * See the Mulan PSL v2 for more details.
+ */
+
+/**
+ * @file core.h
+ * @brief cortex-a72 core function
+ * @version 1.0
+ * @author AIIT XUOS Lab
+ * @date 2024.04.11
+ */
+
+/*************************************************
+File name: core.h
+Description: cortex-a72 core function
+Others:
+History:
+Author: AIIT XUOS Lab
+Modification:
+*************************************************/
+
+#pragma once
+
+// Interrupt control bits
+#define NO_INT 0x80 // disable IRQ.
+#define DIS_INT 0xc0 // disable both IRQ and FIQ.
+
+//! @name SPSR fields
+//@{
+#define SPSR_EL1_N (1 << 31) //!< Negative
+#define SPSR_EL1_Z (1 << 30) //!< Zero
+#define SPSR_EL1_C (1 << 29) //!< Carry
+#define SPSR_EL1_V (1 << 28) //!< Overflow
+#define SPSR_EL1_SS (1 << 21) //!< Software Step
+#define SPSR_EL1_IL (1 << 20) //!< Illegal Exception
+#define SPSR_EL1_D (1 << 9) //!< Debug mask
+#define SPSR_EL1_A (1 << 8) //!< SError mask
+#define SPSR_EL1_I (1 << 7) //!< IRQ mask
+#define SPSR_EL1_F (1 << 6) //!< FIQ mask
+#define SPSR_EL1_M (1 << 4) //!< Execution state    0=64-bit  1=32-bit
+#define SPSR_EL1_MODE (0x7) //!< Current processor mode
+//@}
+
+//! @name Interrupt enable bits in SPSR
+//@{
+#define I_BIT 0x80 //!< When I bit is set, IRQ is disabled
+#define F_BIT 0x40 //!< When F bit is set, FIQ is disabled
+//@}
+
+// ARM Modes         t indicates selecting  sp_el0 pointer, h indicates selecting  sp_eln pointer
+#define SPSR_MODE_MASK 0x0f
+#define ARM_MODE_EL0_t 0x00
+#define ARM_MODE_EL1_t 0x04
+#define ARM_MODE_EL1_h 0x05
+#define ARM_MODE_EL2_t 0x08
+#define ARM_MODE_EL2_h 0x09
+#define ARM_MODE_EL3_t 0x0c
+#define ARM_MODE_EL3_h 0x0d
+
+#ifndef __ASSEMBLER__
+#include <stdint.h>
+#include <string.h>
+
+#include "cortex_a72.h"
+
+#define NR_CPU 4 // maximum number of CPUs
+#define NR_PROC 64 // maximum number of processes
+#define NOFILE 16 // open files per process
+#define NFILE 100 // open files per system
+#define NINODE 50 // maximum number of active i-nodes
+#define NDEV 10 // maximum major device number
+#define ROOTDEV 1 // device number of file system root disk
+#define MAXARG 32 // max exec arguments
+#define MAXOPBLOCKS 10 // max # of blocks any FS op writes
+#define LOGSIZE (MAXOPBLOCKS * 3) // max data blocks in on-disk log
+#define NBUF (MAXOPBLOCKS * 3) // size of disk block cache
+#define FSSIZE 1000 // size of file system in blocks
+#define MAXPATH 128 // maximum file path name
+
+__attribute__((always_inline)) static inline uint64_t EL0_mode() // Set ARM mode to EL0
+{
+    uint64_t val;
+
+    __asm__ __volatile__(
+        "mrs %0, spsr_el1"
+        : "=r"(val)
+        :
+        :);
+    val &= ~DIS_INT;
+    val &= ~SPSR_MODE_MASK;
+    val |= ARM_MODE_EL0_t;
+
+    return val;
+}
+
+struct context {
+    // callee-saved Registers
+    uint64_t x19;
+    uint64_t x20;
+    uint64_t x21;
+    uint64_t x22;
+    uint64_t x23;
+    uint64_t x24;
+    uint64_t x25;
+    uint64_t x26;
+    uint64_t x27;
+    uint64_t x28;
+    uint64_t x29;
+    uint64_t x30;
+};
+
+/// @brief init task context, set return address to trap return
+/// @param  ctx
+extern void trap_return(void);
+__attribute__((__always_inline__)) static inline void arch_init_context(struct context* ctx)
+{
+    memset(ctx, 0, sizeof(*ctx));
+    ctx->x30 = (uint64_t)(trap_return);
+}
+
+struct trapframe {
+    // Additional registers used to support musl
+    uint64_t _padding; // for 16-byte aligned
+    uint64_t tpidr_el0;
+    __uint128_t q0;
+    // Special Registers
+    uint64_t sp_el0; // stack pointer
+    uint64_t spsr_el1; // program status register
+    uint64_t elr_el1; // exception link register
+    uint64_t pc; // program counter
+    // general purpose registers
+    uint64_t x0;
+    uint64_t x1;
+    uint64_t x2;
+    uint64_t x3;
+    uint64_t x4;
+    uint64_t x5;
+    uint64_t x6;
+    uint64_t x7;
+    uint64_t x8;
+    uint64_t x9;
+    uint64_t x10;
+    uint64_t x11;
+    uint64_t x12;
+    uint64_t x13;
+    uint64_t x14;
+    uint64_t x15;
+    uint64_t x16;
+    uint64_t x17;
+    uint64_t x18;
+    uint64_t x19;
+    uint64_t x20;
+    uint64_t x21;
+    uint64_t x22;
+    uint64_t x23;
+    uint64_t x24;
+    uint64_t x25;
+    uint64_t x26;
+    uint64_t x27;
+    uint64_t x28;
+    uint64_t x29;
+    uint64_t x30;
+};
+
+/// @brief init task trapframe
+/// @param tf
+/// @param sp
+/// @param pc
+__attribute__((__always_inline__)) static inline void arch_init_trapframe(struct trapframe* tf, uintptr_t sp, uintptr_t pc)
+{
+    memset(tf, 0, sizeof(*tf));
+    tf->sp_el0 = sp;
+    tf->spsr_el1 = EL0_mode();
+    tf->elr_el1 = 0;
+    tf->pc = pc;
+}
+
+/// @brief set pc and sp to trapframe
+/// @param tf
+/// @param sp
+/// @param pc
+__attribute__((__always_inline__)) static inline void arch_trapframe_set_sp_pc(struct trapframe* tf, uintptr_t sp, uintptr_t pc)
+{
+    tf->sp_el0 = sp;
+    tf->pc = pc;
+}
+
+/// @brief set params of main(int argc, char** argv) to trapframe (argc, argv)
+/// @param tf
+/// @param argc
+/// @param argv
+__attribute__((__always_inline__)) static inline void arch_set_main_params(struct trapframe* tf, int argc, uintptr_t argv)
+{
+    tf->x0 = (uint64_t)argc;
+    tf->x1 = (uint64_t)argv;
+}
+
+/// @brief retrieve params to trapframe (up to max number of 6) and pass it to syscall()
+/// @param sys_num
+/// @param param1
+/// @param param2
+/// @param param3
+/// @param param4
+/// @param param5
+/// @return
+extern int syscall(int sys_num, uintptr_t param1, uintptr_t param2, uintptr_t param3, uintptr_t param4, uintptr_t param5);
+__attribute__((__always_inline__)) static inline int arch_syscall(struct trapframe* tf, int* syscall_num)
+{
+    // call syscall
+    *syscall_num = tf->x8;
+    return syscall(*syscall_num, tf->x1, tf->x2, tf->x3, tf->x4, tf->x5);
+}
+
+/// @brief set return reg to trapframe
+/// @param tf
+/// @param ret
+__attribute__((__always_inline__)) static inline void arch_set_return(struct trapframe* tf, int ret)
+{
+    tf->x0 = (uint64_t)ret;
+}
+
+void cpu_start_secondary(uint8_t cpu_id);
+void start_smp_cache_broadcast(int cpu_id);
+#endif

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/Makefile

@@ -0,0 +1,4 @@
+SRC_FILES := boot.S \
+			start.c
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/boot.S

@@ -0,0 +1,152 @@
+#include "memlayout.h"
+#include "core.h"
+#include "registers.h"
+#include "cortex_a72.h"
+        // qemu -kernel loads the kernel at 0x40000000
+        // and causes each CPU to jump there.
+        // kernel.ld causes the following code to
+        // be placed at 0x40000000.
+.section ".text"
+.global _entry
+_entry:
+        mrs x1, mpidr_el1
+        and x1, x1, #0x3
+        cbz x1, entry         // primary
+        # b entryothers         // secondary
+
+entry:
+        // clear .bss
+        adrp x1, bss_start
+        ldr w2, =bss_size
+1:
+        cbz w2, 2f
+        str xzr, [x1], #8
+        sub w2, w2, #1
+        b 1b
+2:
+        // set up entry pagetable
+        //
+        // Phase 1.
+        // map the kernel code identically.
+        // map [0x40000000,PA(end)) to [0x40000000,PA(end))
+        // memory type is normal
+        //
+        // Phase 2.
+        // map the kernel code.
+        // map [0xffffff8040000000,VA(end)) to [0x40000000,PA(end))
+        // memory type is normal.
+
+        // Phase 1
+        // map [0x40000000,PA(end)) to [0x40000000,PA(end))
+        adrp x0, l2entrypgt
+
+        mov x1, #0x00000000
+        ldr x2, =V2P_WO(end)-1
+
+        lsr x3, x1, #PXSHIFT(2)
+        and x3, x3, #PXMASK   // PX(2, x1)
+        lsr x4, x2, #PXSHIFT(2)
+        and x4, x4, #PXMASK   // PX(2, x2)
+        mov x5, #(PTE_AF | PTE_INDX(AI_NORMAL_NC_IDX) | PTE_VALID) // entry attr
+        orr x6, x1, x5      // block entry
+l2epgt_loop:
+        str x6, [x0, x3, lsl #3]  // l2entrypgt[l2idx] = block entry
+        add x3, x3, #1          // next index
+        add x6, x6, #0x200000   // next block, block size is 2MB
+        cmp x3, x4
+        b.ls l2epgt_loop    // if start va idx <= end va idx
+
+        adrp x0, l1entrypgt
+
+        lsr x3, x1, #PXSHIFT(1)
+        and x3, x3, #PXMASK     // start va level1 index
+
+        mov x4, #(PTE_TABLE | PTE_VALID)  // entry attr
+        adrp x5, l2entrypgt
+        orr x6, x4, x5    // table entry
+
+        str x6, [x0, x3, lsl #3]    // l1entrypgt[l1idx] = table entry
+
+        // Phase 2
+        // map [0xffffff8040000000,VA(end)) to [0x40000000,PA(end))
+        adrp x0, l2kpgt
+
+        mov x1, #0x00000000   // start pa
+        ldr x2, =V2P_WO(end)-1   // end pa
+        mov x3, #KERN_MEM_BASE
+        add x4, x1, x3    // start va
+        add x5, x2, x3    // end va
+
+        lsr x6, x4, #PXSHIFT(2)
+        and x6, x6, #PXMASK   // x6 = PX(2,x4)
+        lsr x7, x5, #PXSHIFT(2)
+        and x7, x7, #PXMASK   // x7 = PX(2,x5)
+        mov x8, #(PTE_AF | PTE_INDX(AI_NORMAL_NC_IDX) | PTE_VALID) // entry attr
+        orr x9, x1, x8      // block entry
+l2kpgt_loop:
+        str x9, [x0, x6, lsl #3]  // l2entrypgt[l2idx] = block entry
+        add x6, x6, #1          // next index
+        add x9, x9, #0x200000   // next block, block size is 2MB
+        cmp x6, x7
+        b.ls l2kpgt_loop    // if start va idx <= end va idx
+
+        adrp x0, l1kpgt
+
+        lsr x5, x4, #PXSHIFT(1)
+        and x5, x5, #PXMASK  // x5 = PX(1,x4)
+
+        mov x6, #(PTE_TABLE | PTE_VALID)  // entry attr
+        adrp x7, l2kpgt
+        orr x8, x6, x7    // table entry
+
+        str x8, [x0, x5, lsl #3]    // l1kpgt[l1idx] = table entry
+
+entryothers:  // secondary CPU starts here
+        // load pagetable
+        adrp x0, l1entrypgt
+        adrp x1, l1kpgt
+        msr ttbr0_el1, x0
+        msr ttbr1_el1, x1
+
+        // setup tcr
+        ldr x0, =(TCR_T0SZ(25)|TCR_T1SZ(25)|TCR_TG0(0)|TCR_TG1(2)|TCR_IPS(0))
+        msr tcr_el1, x0
+
+        // setup mair
+        ldr x1, =((MT_DEVICE_nGnRnE<<(8*AI_DEVICE_nGnRnE_IDX)) | (MT_NORMAL_NC<<(8*AI_NORMAL_NC_IDX)))
+        msr mair_el1, x1
+
+        ISB
+
+        ldr x1, =_start   // x1 = VA(_start)
+
+        // enable paging
+        mrs x0, sctlr_el1
+        orr x0, x0, #1
+        msr sctlr_el1, x0
+
+        br x1       // jump to higher address (0xffffff8000000000~)
+
+_start:
+        // set up a stack for C.
+        // stack0 is declared in start.c,
+        // with a 4096-byte stack per CPU.
+        // sp = stack0 + ((cpuid+1) * 4096)
+        // cpuid = mpidr_el1 & 0xff
+        ldr x0, =stack0
+        mov x1, #1024*4
+        mrs x2, mpidr_el1
+        and x2, x2, #0x3
+        add x2, x2, #1
+        mul x1, x1, x2
+        add x0, x0, x1
+        mov sp, x0
+        // jump to main()
+        b main
+
+        b .   // spin
+
+.global psci_call
+psci_call:
+        hvc #0
+        ret

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/config.mk

@@ -0,0 +1,18 @@
+export CROSS_COMPILE ?= aarch64-linux-gnu-
+export DEVICE = -march=armv8-a -mtune=cortex-a72  -ftree-vectorize -ffast-math 
+export CFLAGS := $(DEVICE) -Wall -O0 -g -gdwarf-2
+export AFLAGS := -c $(DEVICE) -x assembler-with-cpp -D__ASSEMBLY__ -gdwarf-2
+# export LFLAGS := $(DEVICE) -Wl,-Map=XiZi-imx6q-sabrelite.map,-cref,-u,_boot_start -T $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_imx6q-sabrelite/nxp_imx6q_sabrelite.lds
+export LFLAGS := $(DEVICE) --specs=nosys.specs -Wl,-Map=XiZi-ok1028a-c.map,-cref,-u,_start -T $(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds
+export CXXFLAGS := 
+
+ifeq ($(CONFIG_LIB_MUSLLIB), y)
+export LFLAGS += -nostdlib -nostdinc -fno-builtin -nodefaultlibs
+export LIBCC := -lgcc
+export LINK_MUSLLIB := $(KERNEL_ROOT)/lib/musllib/libmusl.a
+endif
+
+export DEFINES := -DHAVE_CCONFIG_H -DCHIP_LS1028
+
+export ARCH = arm
+export ARCH_ARMV = armv8-a

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/include/cortex_a72.h

@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * @file cortex_a72.h
+ * @brief some cortex A72 core functions
+ * @version 1.0
+ * @author AIIT XUOS Lab
+ * @date 2024.04.24
+ */
+
+/*************************************************
+File name: cortex_a72.h
+Description: some cortex A72 core functions
+Others:
+History:
+Author: AIIT XUOS Lab
+Modification:
+1. No modifications
+*************************************************/
+
+#if !defined(__CORTEX_A72_H__)
+#define __CORTEX_A72_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdlib.h>
+
+//! @name Instruction macros
+//@{
+#define NOP() __asm__ volatile("nop\n\t")
+#define WFI() __asm__ volatile("wfi\n\t")
+#define WFE() __asm__ volatile("wfe\n\t")
+#define SEV() __asm__ volatile("sev\n\t")
+#define DMB() __asm__ volatile("dmb\n\t")
+#define DSB() __asm__ volatile("dsb\n\t")
+#define ISB() __asm__ volatile("isb\n\t")
+
+#define _ARM_MRS(coproc, opcode1, Rt, CRn, CRm, opcode2) \
+    asm volatile("mrc p" #coproc ", " #opcode1 ", %[output], c" #CRn ", c" #CRm ", " #opcode2 "\n" : [output] "=r"(Rt))
+
+#define _ARM_MSR(coproc, opcode1, Rt, CRn, CRm, opcode2) \
+    asm volatile("mcr p" #coproc ", " #opcode1 ", %[input], c" #CRn ", c" #CRm ", " #opcode2 "\n" ::[input] "r"(Rt))
+
+#define WriteReg(value, address) (*(volatile unsigned int*)(address) = (value))
+#define ReadReg(address) (*(volatile unsigned int*)(address))
+
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+//! @name Misc
+//@{
+//! @brief Enable or disable the IRQ and FIQ state.
+bool arm_set_interrupt_state(bool enable);
+
+//! @brief Get current CPU ID.
+int cpu_get_current(void);
+
+//! @brief Enable the NEON MPE.
+void enable_neon_fpu(void);
+
+//! @brief Disable aborts on unaligned accesses.
+void disable_strict_align_check(void);
+
+//! @brief Get base address of private perpherial space.
+//!
+//! @return The address of the ARM CPU's private peripherals.
+// uint32_t get_arm_private_peripheral_base(void);
+//@}
+
+//! @name Data cache operations
+//@{
+
+//! @brief Check if dcache is enabled or disabled.
+int arm_dcache_state_query();
+
+//! @brief Enables data cache at any available cache level.
+//!
+//! Works only if MMU is enabled!
+void arm_dcache_enable();
+
+//! @brief Disables the data cache at any available cache level.
+void arm_dcache_disable();
+
+//! @brief Invalidates the entire data cache.
+void arm_dcache_invalidate();
+
+//! @brief Invalidate a line of data cache.
+void arm_dcache_invalidate_line(const void * addr);
+
+//! @brief Invalidate a number of lines of data cache.
+//!
+//! Number of lines depends on length parameter and size of line.
+//! Size of line for A9 L1 cache is 32B.
+void arm_dcache_invalidate_mlines(const void * addr, size_t length);
+
+//! @brief Flush (clean) all lines of cache (all sets in all ways).
+void arm_dcache_flush();
+
+//! @brief Flush (clean) one line of cache.
+void arm_dcache_flush_line(const void * addr);
+
+// @brief Flush (clean) multiple lines of cache.
+//!
+//! Number of lines depends on length parameter and size of line.
+void arm_dcache_flush_mlines(const void * addr, size_t length);
+//@}
+
+//! @name Instrution cache operations
+//@{
+
+//! @brief Check if icache is enabled or disabled.
+int arm_icache_state_query();
+
+//! @brief Enables instruction cache at any available cache level.
+//!
+//! Works without enabled MMU too!
+void arm_icache_enable();
+
+//! @brief Disables the instruction cache at any available cache level.
+void arm_icache_disable();
+
+//! @brief Invalidates the entire instruction cache.
+void arm_icache_invalidate();
+
+//! @brief Invalidates the entire instruction cache inner shareable.
+void arm_icache_invalidate_is();
+
+//! @brief Invalidate a line of the instruction cache.
+void arm_icache_invalidate_line(const void * addr);
+
+//! @brief Invalidate a number of lines of instruction cache.
+//!
+//! Number of lines depends on length parameter and size of line.
+void arm_icache_invalidate_mlines(const void * addr, size_t length);
+//@}
+
+//! @name TLB operations
+//@{
+//! @brief Invalidate entire unified TLB.
+void arm_unified_tlb_invalidate(void);
+
+//! @brief Invalidate entire unified TLB Inner Shareable.
+void arm_unified_tlb_invalidate_is(void);
+//@}
+
+//! @name Branch predictor operations
+//@{
+//! @brief Enable branch prediction.
+void arm_branch_prediction_enable(void);
+
+//! @brief Disable branch prediction.
+void arm_branch_prediction_disable(void);
+
+//! @brief Invalidate entire branch predictor array.
+void arm_branch_target_cache_invalidate(void);
+
+//! @brief Invalidate entire branch predictor array Inner Shareable
+void arm_branch_target_cache_invalidate_is(void);
+//@}
+
+//! @name SCU
+//@{
+//! @brief Enables the SCU.
+void scu_enable(void);
+
+//! @brief Set this CPU as participating in SMP.
+void scu_join_smp(void);
+
+//! @brief Set this CPU as not participating in SMP.
+void scu_leave_smp(void);
+
+//! @brief Determine which CPUs are participating in SMP.
+//!
+//! The return value is 1 bit per core:
+//! - bit 0 - CPU 0
+//! - bit 1 - CPU 1
+//! - etc...
+unsigned int scu_get_cpus_in_smp(void);
+
+//! @brief Enable the broadcasting of cache & TLB maintenance operations.
+//!
+//! When enabled AND in SMP, broadcast all "inner sharable"
+//! cache and TLM maintenance operations to other SMP cores
+void scu_enable_maintenance_broadcast(void);
+
+//! @brief Disable the broadcasting of cache & TLB maintenance operations.
+void scu_disable_maintenance_broadcast(void);
+
+//! @brief Invalidates the SCU copy of the tag rams for the specified core.
+//!
+//! Typically only done at start-up.
+//! Possible flow:
+//! - Invalidate L1 caches
+//! - Invalidate SCU copy of TAG RAMs
+//! - Join SMP
+//!
+//! @param cpu 0x0=CPU 0, 0x1=CPU 1, etc...
+//! @param ways The ways to invalidate. Pass 0xf to invalidate all ways.
+void scu_secure_invalidate(unsigned int cpu, unsigned int ways);
+//@}
+
+#if defined(__cplusplus)
+}
+#endif
+#endif//__CORTEX_A72_H__

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/include/registers.h

@@ -0,0 +1,105 @@
+#ifndef INC_SYSREGS_H_
+#define INC_SYSREGS_H_
+
+/* SCTLR_EL1, System Control Register (EL1). */
+#define SCTLR_RESERVED                                                         \
+    ((3 << 28) | (3 << 22) | (1 << 20) | (1 << 11) | (1 << 8) | (1 << 7))
+#define SCTLR_EE_LITTLE_ENDIAN  (0 << 25)
+#define SCTLR_E0E_LITTLE_ENDIAN (0 << 24)
+#define SCTLR_I_CACHE           (1 << 12)
+#define SCTLR_D_CACHE           (1 << 2)
+#define SCTLR_MMU_DISABLED      (0 << 0)
+#define SCTLR_MMU_ENABLED       (1 << 0)
+
+#define SCTLR_VALUE_MMU_DISABLED                                               \
+    (SCTLR_RESERVED | SCTLR_EE_LITTLE_ENDIAN | SCTLR_E0E_LITTLE_ENDIAN         \
+     | SCTLR_I_CACHE | SCTLR_D_CACHE | SCTLR_MMU_DISABLED)
+
+/* HCR_EL2, Hypervisor Configuration Register (EL2). */
+#define HCR_RW    (1 << 31)
+#define HCR_VALUE HCR_RW
+
+/* CPACR_EL1, Architectural Feature Access Control Register. */
+#define CPACR_FP_EN    (3 << 20)
+#define CPACR_TRACE_EN (0 << 28)
+#define CPACR_VALUE    (CPACR_FP_EN | CPACR_TRACE_EN)
+
+/* SCR_EL3, Secure Configuration Register (EL3). */
+#define SCR_RESERVED (3 << 4)
+#define SCR_RW       (1 << 10)
+#define SCR_HCE      (1 << 8)
+#define SCR_SMD      (1 << 7)
+#define SCR_NS       (1 << 0)
+#define SCR_VALUE    (SCR_RESERVED | SCR_RW | SCR_HCE | SCR_SMD | SCR_NS)
+
+/* SPSR_EL1/2/3, Saved Program Status Register. */
+#define SPSR_MASK_ALL  (7 << 6)
+#define SPSR_EL1h      (5 << 0)
+#define SPSR_EL2h      (9 << 0)
+#define SPSR_EL3_VALUE (SPSR_MASK_ALL | SPSR_EL2h)
+#define SPSR_EL2_VALUE (SPSR_MASK_ALL | SPSR_EL1h)
+
+/* Exception Class in ESR_EL1. */
+#define EC_SHIFT   26
+#define EC_UNKNOWN 0x00
+#define EC_SVC64   0x15
+#define EC_DABORT  0x24
+#define EC_IABORT  0x20
+
+#define PGSIZE 4096 // bytes per page
+#define PGSHIFT 12  // bits of offset within a page
+
+#define PGROUNDUP(sz)  (((sz)+PGSIZE-1) & ~(PGSIZE-1))
+#define PGROUNDDOWN(a) (((a)) & ~(PGSIZE-1))
+
+#define PTE_VALID 1  // level 0,1,2 descriptor: valid
+#define PTE_TABLE 2  // level 0,1,2 descriptor: table
+#define PTE_V     3  // level 3 descriptor: valid
+// PTE_AF(Access Flag)
+//
+// 0 -- this block entry has not yet.
+// 1 -- this block entry has been used.
+#define PTE_AF  (1 << 10)
+// PTE_AP(Access Permission) is 2bit field.
+//        EL0   EL1
+// 00 --   x    RW
+// 01 --  RW    RW
+// 10 --   x    RO
+// 11 --  RO    RO
+#define PTE_AP(ap)  (((ap) & 3) << 6)
+#define PTE_U   PTE_AP(1)
+#define PTE_RO  PTE_AP(2)
+#define PTE_URO PTE_AP(3)
+#define PTE_PXN (1UL << 53)   // Privileged eXecute Never
+#define PTE_UXN (1UL << 54)   // Unprivileged(user) eXecute Never
+#define PTE_XN (PTE_PXN|PTE_UXN)  // eXecute Never
+
+// attribute index
+// index is set by mair_el1
+#define AI_DEVICE_nGnRnE_IDX  0x0
+#define AI_NORMAL_NC_IDX      0x1
+
+// memory type
+#define MT_DEVICE_nGnRnE  0x0
+#define MT_NORMAL_NC      0x44
+
+#define PTE_INDX(i) (((i) & 7) << 2)
+#define PTE_DEVICE  PTE_INDX(AI_DEVICE_nGnRnE_IDX)
+#define PTE_NORMAL  PTE_INDX(AI_NORMAL_NC_IDX)
+
+// shift a physical address to the right place for a PTE.
+#define PA2PTE(pa)  ((uint64)(pa) & 0xfffffffff000)
+#define PTE2PA(pte) ((uint64)(pte) & 0xfffffffff000)
+
+#define PTE_FLAGS(pte)  ((pte) & (0x600000000003ff))
+
+// translation control register
+#define TCR_T0SZ(n)   ((n) & 0x3f)
+#define TCR_TG0(n)    (((n) & 0x3) << 14)
+#define TCR_T1SZ(n)   (((n) & 0x3f) << 16)
+#define TCR_TG1(n)    (((n) & 0x3) << 30)
+#define TCR_IPS(n)    (((n) & 0x7) << 32)
+
+#define ISS_MASK 0xFFFFFF
+
+#endif  // INC_SYSREGS_H_

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds

@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2010-2012, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY  OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file nxp_ls1028.lds
+ * @brief nxp ls1028 lds function
+ * @version 1.0
+ * @author AIIT XUOS Lab
+ * @date 2024.04.10
+ */ 
+OUTPUT_FORMAT("elf64-littleaarch64")
+OUTPUT_ARCH( "aarch64" )
+ENTRY( _entry )
+
+SECTIONS
+{
+  /*
+   * ensure that entry.S / _entry is at 0x40000000(physical address),
+   * where qemu's -kernel jumps.
+   * 0x40000000(PA) is 0xffffff8040000000(VA);
+   */
+/*
+  . = 0x40000000;
+  */
+  . = 0xffffff0000000000;
+
+.start_sec : {
+		. = ALIGN(0x1000);
+		/* initialization start checkpoint. */
+
+  boot.o(.text)
+  boot.o(.rodata .rodata.*)
+  boot.o(.data .data.*)
+    
+	PROVIDE(boot_start_addr = .);
+
+  boot.o(.bss .bss.* COMMON)
+
+		/* stack for booting code. */
+		. = ALIGN(0x1000);
+		PROVIDE(stacks_start = .);
+		. += BOOT_STACK_SIZE;
+		PROVIDE(stacks_end = .);
+		PROVIDE(stacks_top = .);
+
+		/* initialization end checkpoint. */
+		PROVIDE(boot_end_addr = .);
+	}
+
+  .text : AT(0x0000000) {
+    *(.text .text.*)
+    . = ALIGN(0x1000);
+    PROVIDE(etext = .);
+  }
+
+  .rodata : {
+    . = ALIGN(16);
+    *(.srodata .srodata.*) /* do not need to distinguish this from .rodata */
+    . = ALIGN(16);
+    *(.rodata .rodata.*)
+  }
+
+  .data : {
+    . = ALIGN(16);
+    *(.sdata .sdata.*) /* do not need to distinguish this from .data */
+    . = ALIGN(16);
+    *(.data .data.*)
+  }
+
+  .bss : {
+    . = ALIGN(16);
+    PROVIDE(bss_start = .);
+    *(.sbss .sbss.*) /* do not need to distinguish this from .bss */
+    . = ALIGN(16);
+    *(.bss .bss.*)
+    . = ALIGN(16);
+    PROVIDE(bss_end = .);
+  }
+
+  PROVIDE(end = .);
+}
+
+bss_size = (bss_end - bss_start) >> 3;

Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/start.c

@@ -0,0 +1,23 @@
+#include "core.h"
+#include "memlayout.h"
+#include "cortexa72.h"
+
+void _entry();
+void main();
+extern char end[];
+
+// entry.S needs one stack per CPU.
+__attribute__ ((aligned (16))) char stack0[4096 * NR_CPU];
+
+// entry.S jumps here in supervisor mode (EL1) on stack0.
+// in qemu-system-aarch64, default EL (Exeception Level) is 1.
+void
+start()
+{
+  main();
+}
+
+__attribute__((aligned(PGSIZE))) pte_t l1entrypgt[512];
+__attribute__((aligned(PGSIZE))) pte_t l2entrypgt[512];
+__attribute__((aligned(PGSIZE))) pte_t l1kpgt[512];
+__attribute__((aligned(PGSIZE))) pte_t l2kpgt[512];