diff --git a/Ubiquitous/XiZi_AIoT/Makefile b/Ubiquitous/XiZi_AIoT/Makefile index 4a560ba9c..65ec7a2b8 100755 --- a/Ubiquitous/XiZi_AIoT/Makefile +++ b/Ubiquitous/XiZi_AIoT/Makefile @@ -4,7 +4,7 @@ MAKEFLAGS += --no-print-directory .PHONY:COMPILE_APP COMPILE_KERNEL riscv_support := -arm_support += imx6q-sabrelite zynq7000-zc702 +arm_support += imx6q-sabrelite zynq7000-zc702 ok1028a-c emulator_support += support := $(riscv_support) $(arm_support) $(emulator_support) SRC_DIR := @@ -34,6 +34,9 @@ export UBIQUITOUS_ROOT ?= .. ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), ) include $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_$(BOARD)/config.mk endif +ifneq ($(findstring $(BOARD), ok1028a-c), ) +include $(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_$(BOARD)/config.mk +endif export BSP_BUILD_DIR := $(KERNEL_ROOT) export HOSTTOOLS_DIR ?= $(KERNEL_ROOT)/services/tools/hosttools export CONFIG2H_EXE ?= $(HOSTTOOLS_DIR)/xsconfig.sh diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/Makefile index ef8e8c1bc..05e53ecfe 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/Makefile @@ -1,4 +1,10 @@ # The following three platforms support compatiable instructions. +ifneq ($(findstring $(BOARD), ok1028a-c), ) +SRC_DIR := armv8-a +endif +ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), ) SRC_DIR := armv7-a +endif + include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/Makefile new file mode 100644 index 000000000..f0253e59d --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/Makefile @@ -0,0 +1,7 @@ +# The following three platforms support compatiable instructions. +ifneq ($(findstring $(BOARD), ok1028a-c), ) +SRC_DIR := cortex-a72 +endif + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/Makefile new file mode 100644 index 000000000..f4cbabfc4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/Makefile @@ -0,0 +1,4 @@ +SRC_DIR := preboot_for_$(BOARD) +SRC_FILES := context_switch.S core.c + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/context_switch.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/context_switch.S new file mode 100644 index 000000000..383aee1ab --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/context_switch.S @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file context_switch.S + * @brief task context switch functions + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.4.10 + */ + +/************************************************* +File name: context_switch.S +Description: task context switch functions +Others: +History: +*************************************************/ +.global context_switch + +context_switch: + # Save store original context to stack + stp x29, lr, [sp, #-16]! + stp x27, x28, [sp, #-16]! + stp x25, x26, [sp, #-16]! + stp x23, x24, [sp, #-16]! + stp x21, x22, [sp, #-16]! + stp x19, x20, [sp, #-16]! + + # Switch stacks + mov x19, sp + str x19, [x0] + mov sp, x1 + + # restore context from stack + ldp x19, x20, [sp], #16 + ldp x21, x22, [sp], #16 + ldp x23, x24, [sp], #16 + ldp x25, x26, [sp], #16 + ldp x27, x28, [sp], #16 + ldp x29, lr, [sp], #16 + + ret \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/core.c b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/core.c new file mode 100644 index 000000000..13d2ba824 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/core.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file core.c + * @brief spl boot function + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.23 + */ + +/************************************************* +File name: core.c +Description: cortex-a9 core function, include cpu registers operations、core boot +Others: +History: +1. Date: 2024-04-23 +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ + +/*********cortex-a72 general register************ + EL0 | EL1 | EL2 | EL3 + + x0; + x1; + x2; + x3; + x4; + x5; + x6; + x7; + x8; + x9; + x10; + x11; + x12; + x13; + x14; + x15; + x16; + x17; + x18; + x19; + x20; + x21; + x22; + x23; + x24; + x25; + x26; + x27; + x28; + x29; + x30; +/*********cortex-a72 special register************ + XZR + PC + SP_EL0 SP_EL1 SP_EL2 SP_EL3 + SPSR_EL1 SPSR_EL2 SPSR_EL3 + ELR_EL1 ELR_EL2 ELR_EL3 +************************************************/ + + +#include "core.h" \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/core.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/core.h new file mode 100644 index 000000000..797f0b4e5 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/core.h @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file core.h + * @brief cortex-a72 core function + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.11 + */ + +/************************************************* +File name: core.h +Description: cortex-a72 core function +Others: +History: +Author: AIIT XUOS Lab +Modification: +*************************************************/ + +#pragma once + +// Interrupt control bits +#define NO_INT 0x80 // disable IRQ. +#define DIS_INT 0xc0 // disable both IRQ and FIQ. + +//! @name SPSR fields +//@{ +#define SPSR_EL1_N (1 << 31) //!< Negative +#define SPSR_EL1_Z (1 << 30) //!< Zero +#define SPSR_EL1_C (1 << 29) //!< Carry +#define SPSR_EL1_V (1 << 28) //!< Overflow +#define SPSR_EL1_SS (1 << 21) //!< Software Step +#define SPSR_EL1_IL (1 << 20) //!< Illegal Exception +#define SPSR_EL1_D (1 << 9) //!< Debug mask +#define SPSR_EL1_A (1 << 8) //!< SError mask +#define SPSR_EL1_I (1 << 7) //!< IRQ mask +#define SPSR_EL1_F (1 << 6) //!< FIQ mask +#define SPSR_EL1_M (1 << 4) //!< Execution state 0=64-bit 1=32-bit +#define SPSR_EL1_MODE (0x7) //!< Current processor mode +//@} + +//! @name Interrupt enable bits in SPSR +//@{ +#define I_BIT 0x80 //!< When I bit is set, IRQ is disabled +#define F_BIT 0x40 //!< When F bit is set, FIQ is disabled +//@} + +// ARM Modes t indicates selecting sp_el0 pointer, h indicates selecting sp_eln pointer +#define SPSR_MODE_MASK 0x0f +#define ARM_MODE_EL0_t 0x00 +#define ARM_MODE_EL1_t 0x04 +#define ARM_MODE_EL1_h 0x05 +#define ARM_MODE_EL2_t 0x08 +#define ARM_MODE_EL2_h 0x09 +#define ARM_MODE_EL3_t 0x0c +#define ARM_MODE_EL3_h 0x0d + +#ifndef __ASSEMBLER__ +#include +#include + +#include "cortex_a72.h" + +#define NR_CPU 4 // maximum number of CPUs +#define NR_PROC 64 // maximum number of processes +#define NOFILE 16 // open files per process +#define NFILE 100 // open files per system +#define NINODE 50 // maximum number of active i-nodes +#define NDEV 10 // maximum major device number +#define ROOTDEV 1 // device number of file system root disk +#define MAXARG 32 // max exec arguments +#define MAXOPBLOCKS 10 // max # of blocks any FS op writes +#define LOGSIZE (MAXOPBLOCKS * 3) // max data blocks in on-disk log +#define NBUF (MAXOPBLOCKS * 3) // size of disk block cache +#define FSSIZE 1000 // size of file system in blocks +#define MAXPATH 128 // maximum file path name + +__attribute__((always_inline)) static inline uint64_t EL0_mode() // Set ARM mode to EL0 +{ + uint64_t val; + + __asm__ __volatile__( + "mrs %0, spsr_el1" + : "=r"(val) + : + :); + val &= ~DIS_INT; + val &= ~SPSR_MODE_MASK; + val |= ARM_MODE_EL0_t; + + return val; +} + +struct context { + // callee-saved Registers + uint64_t x19; + uint64_t x20; + uint64_t x21; + uint64_t x22; + uint64_t x23; + uint64_t x24; + uint64_t x25; + uint64_t x26; + uint64_t x27; + uint64_t x28; + uint64_t x29; + uint64_t x30; +}; + +/// @brief init task context, set return address to trap return +/// @param ctx +extern void trap_return(void); +__attribute__((__always_inline__)) static inline void arch_init_context(struct context* ctx) +{ + memset(ctx, 0, sizeof(*ctx)); + ctx->x30 = (uint64_t)(trap_return); +} + +struct trapframe { + // Additional registers used to support musl + uint64_t _padding; // for 16-byte aligned + uint64_t tpidr_el0; + __uint128_t q0; + // Special Registers + uint64_t sp_el0; // stack pointer + uint64_t spsr_el1; // program status register + uint64_t elr_el1; // exception link register + uint64_t pc; // program counter + // general purpose registers + uint64_t x0; + uint64_t x1; + uint64_t x2; + uint64_t x3; + uint64_t x4; + uint64_t x5; + uint64_t x6; + uint64_t x7; + uint64_t x8; + uint64_t x9; + uint64_t x10; + uint64_t x11; + uint64_t x12; + uint64_t x13; + uint64_t x14; + uint64_t x15; + uint64_t x16; + uint64_t x17; + uint64_t x18; + uint64_t x19; + uint64_t x20; + uint64_t x21; + uint64_t x22; + uint64_t x23; + uint64_t x24; + uint64_t x25; + uint64_t x26; + uint64_t x27; + uint64_t x28; + uint64_t x29; + uint64_t x30; +}; + +/// @brief init task trapframe +/// @param tf +/// @param sp +/// @param pc +__attribute__((__always_inline__)) static inline void arch_init_trapframe(struct trapframe* tf, uintptr_t sp, uintptr_t pc) +{ + memset(tf, 0, sizeof(*tf)); + tf->sp_el0 = sp; + tf->spsr_el1 = EL0_mode(); + tf->elr_el1 = 0; + tf->pc = pc; +} + +/// @brief set pc and sp to trapframe +/// @param tf +/// @param sp +/// @param pc +__attribute__((__always_inline__)) static inline void arch_trapframe_set_sp_pc(struct trapframe* tf, uintptr_t sp, uintptr_t pc) +{ + tf->sp_el0 = sp; + tf->pc = pc; +} + +/// @brief set params of main(int argc, char** argv) to trapframe (argc, argv) +/// @param tf +/// @param argc +/// @param argv +__attribute__((__always_inline__)) static inline void arch_set_main_params(struct trapframe* tf, int argc, uintptr_t argv) +{ + tf->x0 = (uint64_t)argc; + tf->x1 = (uint64_t)argv; +} + +/// @brief retrieve params to trapframe (up to max number of 6) and pass it to syscall() +/// @param sys_num +/// @param param1 +/// @param param2 +/// @param param3 +/// @param param4 +/// @param param5 +/// @return +extern int syscall(int sys_num, uintptr_t param1, uintptr_t param2, uintptr_t param3, uintptr_t param4, uintptr_t param5); +__attribute__((__always_inline__)) static inline int arch_syscall(struct trapframe* tf, int* syscall_num) +{ + // call syscall + *syscall_num = tf->x8; + return syscall(*syscall_num, tf->x1, tf->x2, tf->x3, tf->x4, tf->x5); +} + +/// @brief set return reg to trapframe +/// @param tf +/// @param ret +__attribute__((__always_inline__)) static inline void arch_set_return(struct trapframe* tf, int ret) +{ + tf->x0 = (uint64_t)ret; +} + +void cpu_start_secondary(uint8_t cpu_id); +void start_smp_cache_broadcast(int cpu_id); +#endif diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/Makefile new file mode 100644 index 000000000..b3b0d7606 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/Makefile @@ -0,0 +1,4 @@ +SRC_FILES := boot.S \ + start.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/boot.S new file mode 100644 index 000000000..38cb18233 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/boot.S @@ -0,0 +1,152 @@ +#include "memlayout.h" +#include "core.h" +#include "registers.h" +#include "cortex_a72.h" + // qemu -kernel loads the kernel at 0x40000000 + // and causes each CPU to jump there. + // kernel.ld causes the following code to + // be placed at 0x40000000. +.section ".text" +.global _entry +_entry: + mrs x1, mpidr_el1 + and x1, x1, #0x3 + cbz x1, entry // primary + # b entryothers // secondary + +entry: + // clear .bss + adrp x1, bss_start + ldr w2, =bss_size +1: + cbz w2, 2f + str xzr, [x1], #8 + sub w2, w2, #1 + b 1b +2: + // set up entry pagetable + // + // Phase 1. + // map the kernel code identically. + // map [0x40000000,PA(end)) to [0x40000000,PA(end)) + // memory type is normal + // + // Phase 2. + // map the kernel code. + // map [0xffffff8040000000,VA(end)) to [0x40000000,PA(end)) + // memory type is normal. + + // Phase 1 + // map [0x40000000,PA(end)) to [0x40000000,PA(end)) + adrp x0, l2entrypgt + + mov x1, #0x00000000 + ldr x2, =V2P_WO(end)-1 + + lsr x3, x1, #PXSHIFT(2) + and x3, x3, #PXMASK // PX(2, x1) + lsr x4, x2, #PXSHIFT(2) + and x4, x4, #PXMASK // PX(2, x2) + mov x5, #(PTE_AF | PTE_INDX(AI_NORMAL_NC_IDX) | PTE_VALID) // entry attr + orr x6, x1, x5 // block entry +l2epgt_loop: + str x6, [x0, x3, lsl #3] // l2entrypgt[l2idx] = block entry + add x3, x3, #1 // next index + add x6, x6, #0x200000 // next block, block size is 2MB + cmp x3, x4 + b.ls l2epgt_loop // if start va idx <= end va idx + + adrp x0, l1entrypgt + + lsr x3, x1, #PXSHIFT(1) + and x3, x3, #PXMASK // start va level1 index + + mov x4, #(PTE_TABLE | PTE_VALID) // entry attr + adrp x5, l2entrypgt + orr x6, x4, x5 // table entry + + str x6, [x0, x3, lsl #3] // l1entrypgt[l1idx] = table entry + + // Phase 2 + // map [0xffffff8040000000,VA(end)) to [0x40000000,PA(end)) + adrp x0, l2kpgt + + mov x1, #0x00000000 // start pa + ldr x2, =V2P_WO(end)-1 // end pa + mov x3, #KERN_MEM_BASE + add x4, x1, x3 // start va + add x5, x2, x3 // end va + + lsr x6, x4, #PXSHIFT(2) + and x6, x6, #PXMASK // x6 = PX(2,x4) + lsr x7, x5, #PXSHIFT(2) + and x7, x7, #PXMASK // x7 = PX(2,x5) + mov x8, #(PTE_AF | PTE_INDX(AI_NORMAL_NC_IDX) | PTE_VALID) // entry attr + orr x9, x1, x8 // block entry +l2kpgt_loop: + str x9, [x0, x6, lsl #3] // l2entrypgt[l2idx] = block entry + add x6, x6, #1 // next index + add x9, x9, #0x200000 // next block, block size is 2MB + cmp x6, x7 + b.ls l2kpgt_loop // if start va idx <= end va idx + + adrp x0, l1kpgt + + lsr x5, x4, #PXSHIFT(1) + and x5, x5, #PXMASK // x5 = PX(1,x4) + + mov x6, #(PTE_TABLE | PTE_VALID) // entry attr + adrp x7, l2kpgt + orr x8, x6, x7 // table entry + + str x8, [x0, x5, lsl #3] // l1kpgt[l1idx] = table entry + +entryothers: // secondary CPU starts here + // load pagetable + adrp x0, l1entrypgt + adrp x1, l1kpgt + msr ttbr0_el1, x0 + msr ttbr1_el1, x1 + + // setup tcr + ldr x0, =(TCR_T0SZ(25)|TCR_T1SZ(25)|TCR_TG0(0)|TCR_TG1(2)|TCR_IPS(0)) + msr tcr_el1, x0 + + // setup mair + ldr x1, =((MT_DEVICE_nGnRnE<<(8*AI_DEVICE_nGnRnE_IDX)) | (MT_NORMAL_NC<<(8*AI_NORMAL_NC_IDX))) + msr mair_el1, x1 + + ISB + + ldr x1, =_start // x1 = VA(_start) + + // enable paging + mrs x0, sctlr_el1 + orr x0, x0, #1 + msr sctlr_el1, x0 + + br x1 // jump to higher address (0xffffff8000000000~) + +_start: + // set up a stack for C. + // stack0 is declared in start.c, + // with a 4096-byte stack per CPU. + // sp = stack0 + ((cpuid+1) * 4096) + // cpuid = mpidr_el1 & 0xff + ldr x0, =stack0 + mov x1, #1024*4 + mrs x2, mpidr_el1 + and x2, x2, #0x3 + add x2, x2, #1 + mul x1, x1, x2 + add x0, x0, x1 + mov sp, x0 + // jump to main() + b main + + b . // spin + +.global psci_call +psci_call: + hvc #0 + ret diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/config.mk b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/config.mk new file mode 100644 index 000000000..9b3039c3b --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/config.mk @@ -0,0 +1,18 @@ +export CROSS_COMPILE ?= aarch64-linux-gnu- +export DEVICE = -march=armv8-a -mtune=cortex-a72 -ftree-vectorize -ffast-math +export CFLAGS := $(DEVICE) -Wall -O0 -g -gdwarf-2 +export AFLAGS := -c $(DEVICE) -x assembler-with-cpp -D__ASSEMBLY__ -gdwarf-2 +# export LFLAGS := $(DEVICE) -Wl,-Map=XiZi-imx6q-sabrelite.map,-cref,-u,_boot_start -T $(KERNEL_ROOT)/hardkernel/arch/arm/armv7-a/cortex-a9/preboot_for_imx6q-sabrelite/nxp_imx6q_sabrelite.lds +export LFLAGS := $(DEVICE) --specs=nosys.specs -Wl,-Map=XiZi-ok1028a-c.map,-cref,-u,_start -T $(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds +export CXXFLAGS := + +ifeq ($(CONFIG_LIB_MUSLLIB), y) +export LFLAGS += -nostdlib -nostdinc -fno-builtin -nodefaultlibs +export LIBCC := -lgcc +export LINK_MUSLLIB := $(KERNEL_ROOT)/lib/musllib/libmusl.a +endif + +export DEFINES := -DHAVE_CCONFIG_H -DCHIP_LS1028 + +export ARCH = arm +export ARCH_ARMV = armv8-a \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/include/cortex_a72.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/include/cortex_a72.h new file mode 100644 index 000000000..8ffc95898 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/include/cortex_a72.h @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/** + * @file cortex_a72.h + * @brief some cortex A72 core functions + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.24 + */ + +/************************************************* +File name: cortex_a72.h +Description: some cortex A72 core functions +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. No modifications +*************************************************/ + +#if !defined(__CORTEX_A72_H__) +#define __CORTEX_A72_H__ + +#include +#include +#include + +//! @name Instruction macros +//@{ +#define NOP() __asm__ volatile("nop\n\t") +#define WFI() __asm__ volatile("wfi\n\t") +#define WFE() __asm__ volatile("wfe\n\t") +#define SEV() __asm__ volatile("sev\n\t") +#define DMB() __asm__ volatile("dmb\n\t") +#define DSB() __asm__ volatile("dsb\n\t") +#define ISB() __asm__ volatile("isb\n\t") + +#define _ARM_MRS(coproc, opcode1, Rt, CRn, CRm, opcode2) \ + asm volatile("mrc p" #coproc ", " #opcode1 ", %[output], c" #CRn ", c" #CRm ", " #opcode2 "\n" : [output] "=r"(Rt)) + +#define _ARM_MSR(coproc, opcode1, Rt, CRn, CRm, opcode2) \ + asm volatile("mcr p" #coproc ", " #opcode1 ", %[input], c" #CRn ", c" #CRm ", " #opcode2 "\n" ::[input] "r"(Rt)) + +#define WriteReg(value, address) (*(volatile unsigned int*)(address) = (value)) +#define ReadReg(address) (*(volatile unsigned int*)(address)) + + +#if defined(__cplusplus) +extern "C" { +#endif + + +//! @name Misc +//@{ +//! @brief Enable or disable the IRQ and FIQ state. +bool arm_set_interrupt_state(bool enable); + +//! @brief Get current CPU ID. +int cpu_get_current(void); + +//! @brief Enable the NEON MPE. +void enable_neon_fpu(void); + +//! @brief Disable aborts on unaligned accesses. +void disable_strict_align_check(void); + +//! @brief Get base address of private perpherial space. +//! +//! @return The address of the ARM CPU's private peripherals. +// uint32_t get_arm_private_peripheral_base(void); +//@} + +//! @name Data cache operations +//@{ + +//! @brief Check if dcache is enabled or disabled. +int arm_dcache_state_query(); + +//! @brief Enables data cache at any available cache level. +//! +//! Works only if MMU is enabled! +void arm_dcache_enable(); + +//! @brief Disables the data cache at any available cache level. +void arm_dcache_disable(); + +//! @brief Invalidates the entire data cache. +void arm_dcache_invalidate(); + +//! @brief Invalidate a line of data cache. +void arm_dcache_invalidate_line(const void * addr); + +//! @brief Invalidate a number of lines of data cache. +//! +//! Number of lines depends on length parameter and size of line. +//! Size of line for A9 L1 cache is 32B. +void arm_dcache_invalidate_mlines(const void * addr, size_t length); + +//! @brief Flush (clean) all lines of cache (all sets in all ways). +void arm_dcache_flush(); + +//! @brief Flush (clean) one line of cache. +void arm_dcache_flush_line(const void * addr); + +// @brief Flush (clean) multiple lines of cache. +//! +//! Number of lines depends on length parameter and size of line. +void arm_dcache_flush_mlines(const void * addr, size_t length); +//@} + +//! @name Instrution cache operations +//@{ + +//! @brief Check if icache is enabled or disabled. +int arm_icache_state_query(); + +//! @brief Enables instruction cache at any available cache level. +//! +//! Works without enabled MMU too! +void arm_icache_enable(); + +//! @brief Disables the instruction cache at any available cache level. +void arm_icache_disable(); + +//! @brief Invalidates the entire instruction cache. +void arm_icache_invalidate(); + +//! @brief Invalidates the entire instruction cache inner shareable. +void arm_icache_invalidate_is(); + +//! @brief Invalidate a line of the instruction cache. +void arm_icache_invalidate_line(const void * addr); + +//! @brief Invalidate a number of lines of instruction cache. +//! +//! Number of lines depends on length parameter and size of line. +void arm_icache_invalidate_mlines(const void * addr, size_t length); +//@} + +//! @name TLB operations +//@{ +//! @brief Invalidate entire unified TLB. +void arm_unified_tlb_invalidate(void); + +//! @brief Invalidate entire unified TLB Inner Shareable. +void arm_unified_tlb_invalidate_is(void); +//@} + +//! @name Branch predictor operations +//@{ +//! @brief Enable branch prediction. +void arm_branch_prediction_enable(void); + +//! @brief Disable branch prediction. +void arm_branch_prediction_disable(void); + +//! @brief Invalidate entire branch predictor array. +void arm_branch_target_cache_invalidate(void); + +//! @brief Invalidate entire branch predictor array Inner Shareable +void arm_branch_target_cache_invalidate_is(void); +//@} + +//! @name SCU +//@{ +//! @brief Enables the SCU. +void scu_enable(void); + +//! @brief Set this CPU as participating in SMP. +void scu_join_smp(void); + +//! @brief Set this CPU as not participating in SMP. +void scu_leave_smp(void); + +//! @brief Determine which CPUs are participating in SMP. +//! +//! The return value is 1 bit per core: +//! - bit 0 - CPU 0 +//! - bit 1 - CPU 1 +//! - etc... +unsigned int scu_get_cpus_in_smp(void); + +//! @brief Enable the broadcasting of cache & TLB maintenance operations. +//! +//! When enabled AND in SMP, broadcast all "inner sharable" +//! cache and TLM maintenance operations to other SMP cores +void scu_enable_maintenance_broadcast(void); + +//! @brief Disable the broadcasting of cache & TLB maintenance operations. +void scu_disable_maintenance_broadcast(void); + +//! @brief Invalidates the SCU copy of the tag rams for the specified core. +//! +//! Typically only done at start-up. +//! Possible flow: +//! - Invalidate L1 caches +//! - Invalidate SCU copy of TAG RAMs +//! - Join SMP +//! +//! @param cpu 0x0=CPU 0, 0x1=CPU 1, etc... +//! @param ways The ways to invalidate. Pass 0xf to invalidate all ways. +void scu_secure_invalidate(unsigned int cpu, unsigned int ways); +//@} + +#if defined(__cplusplus) +} +#endif +#endif//__CORTEX_A72_H__ \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/include/registers.h b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/include/registers.h new file mode 100644 index 000000000..a510d4b22 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/include/registers.h @@ -0,0 +1,105 @@ +#ifndef INC_SYSREGS_H_ +#define INC_SYSREGS_H_ + +/* SCTLR_EL1, System Control Register (EL1). */ +#define SCTLR_RESERVED \ + ((3 << 28) | (3 << 22) | (1 << 20) | (1 << 11) | (1 << 8) | (1 << 7)) +#define SCTLR_EE_LITTLE_ENDIAN (0 << 25) +#define SCTLR_E0E_LITTLE_ENDIAN (0 << 24) +#define SCTLR_I_CACHE (1 << 12) +#define SCTLR_D_CACHE (1 << 2) +#define SCTLR_MMU_DISABLED (0 << 0) +#define SCTLR_MMU_ENABLED (1 << 0) + +#define SCTLR_VALUE_MMU_DISABLED \ + (SCTLR_RESERVED | SCTLR_EE_LITTLE_ENDIAN | SCTLR_E0E_LITTLE_ENDIAN \ + | SCTLR_I_CACHE | SCTLR_D_CACHE | SCTLR_MMU_DISABLED) + +/* HCR_EL2, Hypervisor Configuration Register (EL2). */ +#define HCR_RW (1 << 31) +#define HCR_VALUE HCR_RW + +/* CPACR_EL1, Architectural Feature Access Control Register. */ +#define CPACR_FP_EN (3 << 20) +#define CPACR_TRACE_EN (0 << 28) +#define CPACR_VALUE (CPACR_FP_EN | CPACR_TRACE_EN) + +/* SCR_EL3, Secure Configuration Register (EL3). */ +#define SCR_RESERVED (3 << 4) +#define SCR_RW (1 << 10) +#define SCR_HCE (1 << 8) +#define SCR_SMD (1 << 7) +#define SCR_NS (1 << 0) +#define SCR_VALUE (SCR_RESERVED | SCR_RW | SCR_HCE | SCR_SMD | SCR_NS) + +/* SPSR_EL1/2/3, Saved Program Status Register. */ +#define SPSR_MASK_ALL (7 << 6) +#define SPSR_EL1h (5 << 0) +#define SPSR_EL2h (9 << 0) +#define SPSR_EL3_VALUE (SPSR_MASK_ALL | SPSR_EL2h) +#define SPSR_EL2_VALUE (SPSR_MASK_ALL | SPSR_EL1h) + +/* Exception Class in ESR_EL1. */ +#define EC_SHIFT 26 +#define EC_UNKNOWN 0x00 +#define EC_SVC64 0x15 +#define EC_DABORT 0x24 +#define EC_IABORT 0x20 + +#define PGSIZE 4096 // bytes per page +#define PGSHIFT 12 // bits of offset within a page + +#define PGROUNDUP(sz) (((sz)+PGSIZE-1) & ~(PGSIZE-1)) +#define PGROUNDDOWN(a) (((a)) & ~(PGSIZE-1)) + +#define PTE_VALID 1 // level 0,1,2 descriptor: valid +#define PTE_TABLE 2 // level 0,1,2 descriptor: table +#define PTE_V 3 // level 3 descriptor: valid +// PTE_AF(Access Flag) +// +// 0 -- this block entry has not yet. +// 1 -- this block entry has been used. +#define PTE_AF (1 << 10) +// PTE_AP(Access Permission) is 2bit field. +// EL0 EL1 +// 00 -- x RW +// 01 -- RW RW +// 10 -- x RO +// 11 -- RO RO +#define PTE_AP(ap) (((ap) & 3) << 6) +#define PTE_U PTE_AP(1) +#define PTE_RO PTE_AP(2) +#define PTE_URO PTE_AP(3) +#define PTE_PXN (1UL << 53) // Privileged eXecute Never +#define PTE_UXN (1UL << 54) // Unprivileged(user) eXecute Never +#define PTE_XN (PTE_PXN|PTE_UXN) // eXecute Never + +// attribute index +// index is set by mair_el1 +#define AI_DEVICE_nGnRnE_IDX 0x0 +#define AI_NORMAL_NC_IDX 0x1 + +// memory type +#define MT_DEVICE_nGnRnE 0x0 +#define MT_NORMAL_NC 0x44 + +#define PTE_INDX(i) (((i) & 7) << 2) +#define PTE_DEVICE PTE_INDX(AI_DEVICE_nGnRnE_IDX) +#define PTE_NORMAL PTE_INDX(AI_NORMAL_NC_IDX) + +// shift a physical address to the right place for a PTE. +#define PA2PTE(pa) ((uint64)(pa) & 0xfffffffff000) +#define PTE2PA(pte) ((uint64)(pte) & 0xfffffffff000) + +#define PTE_FLAGS(pte) ((pte) & (0x600000000003ff)) + +// translation control register +#define TCR_T0SZ(n) ((n) & 0x3f) +#define TCR_TG0(n) (((n) & 0x3) << 14) +#define TCR_T1SZ(n) (((n) & 0x3f) << 16) +#define TCR_TG1(n) (((n) & 0x3) << 30) +#define TCR_IPS(n) (((n) & 0x7) << 32) + +#define ISS_MASK 0xFFFFFF + +#endif // INC_SYSREGS_H_ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds new file mode 100644 index 000000000..3de2afc81 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/nxp_ls1028.lds @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2010-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file nxp_ls1028.lds + * @brief nxp ls1028 lds function + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.10 + */ +OUTPUT_FORMAT("elf64-littleaarch64") +OUTPUT_ARCH( "aarch64" ) +ENTRY( _entry ) + +SECTIONS +{ + /* + * ensure that entry.S / _entry is at 0x40000000(physical address), + * where qemu's -kernel jumps. + * 0x40000000(PA) is 0xffffff8040000000(VA); + */ +/* + . = 0x40000000; + */ + . = 0xffffff0000000000; + +.start_sec : { + . = ALIGN(0x1000); + /* initialization start checkpoint. */ + + boot.o(.text) + boot.o(.rodata .rodata.*) + boot.o(.data .data.*) + + PROVIDE(boot_start_addr = .); + + boot.o(.bss .bss.* COMMON) + + /* stack for booting code. */ + . = ALIGN(0x1000); + PROVIDE(stacks_start = .); + . += BOOT_STACK_SIZE; + PROVIDE(stacks_end = .); + PROVIDE(stacks_top = .); + + /* initialization end checkpoint. */ + PROVIDE(boot_end_addr = .); + } + + .text : AT(0x0000000) { + *(.text .text.*) + . = ALIGN(0x1000); + PROVIDE(etext = .); + } + + .rodata : { + . = ALIGN(16); + *(.srodata .srodata.*) /* do not need to distinguish this from .rodata */ + . = ALIGN(16); + *(.rodata .rodata.*) + } + + .data : { + . = ALIGN(16); + *(.sdata .sdata.*) /* do not need to distinguish this from .data */ + . = ALIGN(16); + *(.data .data.*) + } + + .bss : { + . = ALIGN(16); + PROVIDE(bss_start = .); + *(.sbss .sbss.*) /* do not need to distinguish this from .bss */ + . = ALIGN(16); + *(.bss .bss.*) + . = ALIGN(16); + PROVIDE(bss_end = .); + } + + PROVIDE(end = .); +} + +bss_size = (bss_end - bss_start) >> 3; diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/start.c b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/start.c new file mode 100644 index 000000000..753dbdcf5 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_ok1028a-c/start.c @@ -0,0 +1,23 @@ +#include "core.h" +#include "memlayout.h" +#include "cortexa72.h" + +void _entry(); +void main(); +extern char end[]; + +// entry.S needs one stack per CPU. +__attribute__ ((aligned (16))) char stack0[4096 * NR_CPU]; + +// entry.S jumps here in supervisor mode (EL1) on stack0. +// in qemu-system-aarch64, default EL (Exeception Level) is 1. +void +start() +{ + main(); +} + +__attribute__((aligned(PGSIZE))) pte_t l1entrypgt[512]; +__attribute__((aligned(PGSIZE))) pte_t l2entrypgt[512]; +__attribute__((aligned(PGSIZE))) pte_t l1kpgt[512]; +__attribute__((aligned(PGSIZE))) pte_t l2kpgt[512]; \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/Makefile index 8362443e3..2e244bef0 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/Makefile @@ -1,3 +1,8 @@ +ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), ) SRC_DIR := cortex-a9 +endif +ifneq ($(findstring $(BOARD), ok1028a-c), ) +SRC_DIR := cortex-a72 +endif include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a72/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a72/Makefile new file mode 100644 index 000000000..23bc22506 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a72/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := l1_cache.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a72/l1_cache.c b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a72/l1_cache.c new file mode 100644 index 000000000..8ae141a0e --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a72/l1_cache.c @@ -0,0 +1,285 @@ +/** +* @file: l1_cache.c +* @brief: the general management of L1 cache +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2024/04/23 +* +*/ + +/************************************************* +File name: l1_cache.c +Description: the general management of L1 cache +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. implement the l1 cache operations +2. function names are modified to apply softkernel developement +3. function implementations are from modifications of imx6 SDK package +*************************************************/ + +#include "l1_cache.h" + +void InvalidateL1Dcache(uintptr_t start, uintptr_t end) +{ + uintptr_t length = end - start; + uintptr_t addr = start; + uint64_t ccsidr_el1; + uint64_t line_size; + uint64_t va; + // get the cache line size + __asm__ __volatile__("mrs %0, ccsidr_el1" : : "=r" (ccsidr_el1)); + line_size = 1 << ((ccsidr_el1 & 0x7) + 4); + + // align the address with line + const void * end_addr = (const void *)((uint64_t)addr + length); + + while (addr < end_addr){ + va = (uint64_t)addr & (~(line_size - 1)); + + //Invalidate data cache line to PoC (Point of Coherence) by va. + __asm__ __volatile__("dc ivac, %0 " : : "r" (va)); + + // increment addres to next line and decrement lenght + addr = (void*)((uint64_t)addr + line_size); + } + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + DSB(); +} + +void InvalidateL1DcacheAll(void) +{ + uint64_t ccsidr_el1; // Cache Size ID + int num_sets; // number of sets + int num_ways; // number of ways + uint32_t wayset; // wayset parameter + + __asm__ __volatile__("mrs %0, ccsidr_el1" : : "=r" (ccsidr_el1));// Read Cache Size ID + + // Fill number of sets and number of ways from ccsidr_el1 register + num_sets = ((ccsidr_el1 >> 32) & 0x7FFF) + 1; + num_ways = ((ccsidr_el1 >> 0) & 0x7FFF) + 1; + + // Invalidation all lines (all Sets in all ways) +for (int way = 0 ; way < num_ways; way++){ + for (int set = 0 ;set < num_sets; set++){ + wayset = (way << 30) | (set << 5); + __asm__ __volatile__("dc isw, %0" : : "r" (wayset)); + } +} + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + DSB(); +} + + +void CleanL1Dcache(uintptr_t start, uintptr_t end) +{ + void* addr = (void*)start; + uintptr_t length = end - start; + const void * end_addr = (const void *)((uint64_t)addr + length); + uint64_t ccsidr_el1; + uint64_t line_size; + uint64_t va; + + // get the cache line size + __asm__ __volatile__("mrs %0, ccsidr_el1" : "=r" (ccsidr_el1)); + line_size = 1 << ((ccsidr_el1 & 0x7) + 4); + + do + { + va = (uint64_t)addr & (~(line_size - 1)); + // Clean data cache line to PoC (Point of Coherence) by va. + __asm__ __volatile__("dc cvac, %0" : : "r" (va)); + + // increment addres to next line and decrement lenght + addr = (void*)((uint64_t)addr + line_size); + } while (addr < end_addr); + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + DSB(); +} + +void CleanL1DcacheAll(void) +{ + uint64_t ccsidr_el1; // Cache Size ID + int num_sets; // number of sets + int num_ways; // number of ways + uint32_t wayset; // wayset parameter + + __asm__ __volatile__("mrs %0, ccsidr_el1" : : "=r" (ccsidr_el1));// Read Cache Size ID + + // Fill number of sets and number of ways from ccsidr_el1 register This walues are decremented by 1 + num_sets = ((ccsidr_el1 >> 32) & 0x7FFF) + 1; + num_ways = ((ccsidr_el1 >> 0) & 0x7FFF) + 1; + + // clean all lines (all Sets in all ways) +for (int way = 0 ; way < num_ways; way++){ + for (int set = 0 ;set < num_sets; set++){ + wayset = (way << 30) | (set << 5); + __asm__ __volatile__("dc csw, %0" : : "r" (wayset)); + } +} + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + DSB(); +} + +void FlushL1Dcache(uintptr_t start, uintptr_t end) +{ + void* addr = (void*)start; + // size_t length=end-start; + uint64_t va; + uint64_t ccsidr_el1 = 0, line_size = 0; + const void * end_addr = (const void *)((uint64_t)end); + + // get the cache line size + __asm__ __volatile__("mrs %0, ccsidr_el1" : "=r" (ccsidr_el1)); + line_size = 1 << ((ccsidr_el1 & 0x7) + 4); + + do + { + // Clean data cache line to PoC (Point of Coherence) by va. + va = (uint64_t) ((uint64_t)addr & (~(line_size - 1))); //addr & va_VIRTUAL_ADDRESS_MASK + __asm__ __volatile__("dc civac, %0" : : "r" (va)); + + // increment addres to next line and decrement lenght + addr = (void*)((uint64_t)addr + line_size); + } while (addr < end_addr); + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + DSB(); +} + +void FlushL1DcacheAll(void) +{ + uint64_t ccsidr_el1; // Cache Size ID + int num_sets; // number of sets + int num_ways; // number of ways + uint32_t wayset; // wayset parameter + + __asm__ __volatile__("mrs %0, ccsidr_el1" : : "=r" (ccsidr_el1));// Read Cache Size ID + + // Fill number of sets and number of ways from ccsidr_el1 register This walues are decremented by 1 + num_sets = ((ccsidr_el1 >> 32) & 0x7FFF) + 1; + num_ways = ((ccsidr_el1 >> 0) & 0x7FFF) + 1; + + // clean and invalidate all lines (all Sets in all ways) +for (int way = 0 ; way < num_ways; way++){ + for (int set = 0 ;set < num_sets; set++){ + wayset = (way << 30) | (set << 5); + __asm__ __volatile__("dc cisw, %0" : : "r" (wayset)); + } +} + + // All Cache, Branch predictor and TLB maintenance operations before followed instruction complete + DSB(); +} + +void InvalidateL1IcacheAll() +{ + __asm__ __volatile__("ic iallu\n\t"); + // synchronize context on this processor + ISB(); +} + +void InvalidateL1Icache(uintptr_t start, uintptr_t end) +{ + uintptr_t length = end - start; + uintptr_t addr = start; + uint64_t ccsidr_el1; + uint64_t line_size; + uint64_t va; + // get the cache line size + __asm__ __volatile__("mrs %0, ccsidr_el1" : : "=r" (ccsidr_el1)); + line_size = 1 << ((ccsidr_el1 & 0x7) + 4); + + while (addr < end){ + va = (uint64_t)addr & (~(line_size - 1)); + + //Invalidate data cache line to PoC (Point of Coherence) by va. + __asm__ __volatile__("dc ivau, %0 " : : "r" (va)); + // increment addres to next line and decrement lenght + addr = (void*)((uint64_t)addr + line_size); + } + + // synchronize context on this processor + ISB(); +} + + +void EnableL1Dcache() +{ + uint64_t sctlr_el1; // System Control Register + + // read sctlr_el1 + __asm__ __volatile__("mrs %0, sctlr_el1" : :"=r" (sctlr_el1)); + + if (!(sctlr_el1 & SCTLR_EL1_DCACHE_ENABLE)) + { + // set C bit (data caching enable) + sctlr_el1 |= SCTLR_EL1_DCACHE_ENABLE; + + // write modified sctlr_el1 + __asm__ __volatile__("msr sctlr_el1, %0" : : "r" (sctlr_el1)); + + //data synchronization barrier + DSB(); + } +} + +void DisableL1Dcache() +{ + uint64_t sctlr_el1; // System Control Register + + // read sctlr_el1 + __asm__ __volatile__("mrs %0, sctlr_el1" : : "=r" (sctlr_el1)); + + // set C bit (data caching enable) + sctlr_el1 &= ~ SCTLR_EL1_DCACHE_ENABLE; + + // write modified sctlr_el1 + __asm__ __volatile__("msr sctlr_el1, %0" : : "r" (sctlr_el1)); + + //data synchronization barrier + DSB(); + } + +void EnableL1Icache() +{ + uint64_t sctlr_el1; // System Control Register + + // read sctlr_el1 + __asm__ __volatile__("mrs %0, sctlr_el1" : : "=r" (sctlr_el1)); + + if (!(sctlr_el1 & SCTLR_EL1_ICACHE_ENABLE)) + { + // set I bit (data caching enable) + sctlr_el1 |= SCTLR_EL1_ICACHE_ENABLE; + + // write modified sctlr_el1 + __asm__ __volatile__("msr sctlr_el1, %0" : : "r" (sctlr_el1)); + + //Instruction synchronization barrier + ISB(); + } +} + +void DisableL1Icache() +{ + uint64_t sctlr_el1; // System Control Register + + // read sctlr_el1 + __asm__ __volatile__("mrs %0, sctlr_el1" : : "=r" (sctlr_el1)); + + // set I bit (data caching enable) + sctlr_el1 &= ~ SCTLR_EL1_ICACHE_ENABLE; + + // write modified sctlr_el1 + __asm__ __volatile__("msr sctlr_el1, %0" : : "r" (sctlr_el1)); + + //Instruction synchronization barrier + ISB(); + } \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a72/l1_cache.h b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a72/l1_cache.h new file mode 100644 index 000000000..b6463bd38 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/cache/L1/arm/cortex-a72/l1_cache.h @@ -0,0 +1,78 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** +* @file: l1_cache.h +* @brief: the general management of L1 cache +* @version: 1.0 +* @author: AIIT XUOS Lab +* @date: 2024/4/23 +* +*/ + +/************************************************* +File name: l1_cache.h +Description: the general management of L1 cache +Others: +History: +Author: AIIT XUOS Lab +Modification: +1、define the l1 cache operations +*************************************************/ +#include "cortex-a72/core.h" +#include + +/* +* L1 Cache Operation: +* +* IVAC -Invalidate by Virtual Address, to Point of Coherency AArch32Equivalent :DCIMVAC +* +* ISW -Invalidate by Set/Way AArch32Equivalent :DCISW +* +*CVAC -Clean by Virtual Address to Point of Coherency AArch32Equivalent :DCCMVAC +* +*CSW -Clean by Set/Way AArch32Equivalent :DCCSW +* +*CVAU -Clean by Virtual Address to Point of Unification AArch32Equivalent :DCCMVAU +* +*CIVAC -Clean and invalidate data cache line by VA to PoC. AArch32Equivalent :DCCIMVAC +* +*ISW -Clean and invalidate data cache line by Set/Way. AArch32Equivalent :DCCISW + */ + +#define SCTLR_EL1_ICACHE_ENABLE(1 << 12) //!< Instruction cache enable +#define SCTLR_EL1_DCACHE_ENABLE (1 << 2) //!< Data cache enable + +void InvalidateL1Dcache(uintptr_t start, uintptr_t end); + +void InvalidateL1DcacheAll(void); + + +void CleanL1Dcache(uintptr_t start, uintptr_t end); + +void CleanL1DcacheAll(void); + +void FlushL1Dcache(uintptr_t start, uintptr_t end); + +void FlushL1DcacheAll(void); + + +void InvalidateL1IcacheAll(void); + +void InvalidateL1Icache(uintptr_t start, uintptr_t end); + +void EnableL1Icache(void); +void DisableL1Icache(); + +void EnableL1Dcache(); + +void DisableL1Dcache(); \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/Makefile index b199fd1e3..bd7075f60 100644 --- a/Ubiquitous/XiZi_AIoT/hardkernel/intr/Makefile +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/Makefile @@ -1,4 +1,4 @@ -SRC_DIR := arm/armv7-a/cortex-a9 +SRC_DIR := arm SRC_FILES := spinlock.c include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/Makefile new file mode 100644 index 000000000..dcf1ed644 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/Makefile @@ -0,0 +1,9 @@ +ifneq ($(findstring $(BOARD), ok1028a-c), ) +SRC_DIR := armv8-a +endif +ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), ) +SRC_DIR := armv7-a +endif + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/Makefile new file mode 100644 index 000000000..5f1c48123 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv7-a/Makefile @@ -0,0 +1,6 @@ +ifneq ($(findstring $(BOARD), imx6q-sabrelite zynq7000-zc702), ) +SRC_DIR := cortex-a9 +endif + + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/Makefile new file mode 100644 index 000000000..63683be72 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/Makefile @@ -0,0 +1,3 @@ +SRC_DIR := cortex-a72 + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/error_debug.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/error_debug.c new file mode 100644 index 000000000..c31a5e8db --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/error_debug.c @@ -0,0 +1,121 @@ +/* Copyright (c) 2006-2018 Frans Kaashoek, Robert Morris, Russ Cox, + * Massachusetts Institute of Technology + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE + * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +/** + * @file error_debug.c + * @brief handle program abort + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.4.25 + */ + +/************************************************* +File name: error_debug.c +Description: handle program abort +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. Take only armv8 abort reason part(_abort_reason). +2. Modify iabort and dabort handler(in dabort_handler() and iabort_handler()) +*************************************************/ + +#include "log.h" +#include "multicores.h" +#include "spinlock.h" +#include "syscall.h" + +__attribute__((always_inline)) static inline void _abort_reason(uint32_t fault_status) +{ + if ((fault_status & 0x3f) == 0x21) // Alignment failure + KPrintf("reason: alignment\n"); + else if ((fault_status & 0x3f) == 0x4) // Translation fault, level 0 + KPrintf("reason: sect. translation level 0\n"); + else if ((fault_status & 0x3f) == 0x5) // Translation fault, level 1 + KPrintf("reason: sect. translation level 1\n"); + else if ((fault_status & 0x3f) == 0x6) // Translation fault, level 2 + KPrintf("reason: sect. translation level 2\n"); + else if ((fault_status & 0x3f) == 0x7) // Translation fault, level 3 + KPrintf("reason: sect. translation level 3\n"); + else if ((fault_status & 0x3f) == 0x3d) //Section Domain fault + KPrintf("reason: sect. domain\n"); + else if ((fault_status & 0x3f) == 0x13) // Permission level 1 + KPrintf("reason: sect. permission level 1\n"); + else if ((fault_status & 0x3f) == 0x14) // Permission level 2 + KPrintf("reason: sect. permission level 2\n"); + else if ((fault_status & 0x3f) == 0x15) // Permission level 3 + KPrintf("reason: sect. permission level 3\n"); + else if ((fault_status & 0x3f) == 0x8) // External abort + KPrintf("reason: ext. abort\n"); + else if ((fault_status & 0x3f) == 0x9) // Access flag fault, level 1 + KPrintf("reason: sect. Access flag fault level 1\n"); + else if ((fault_status & 0x3f) == 0xa) // Access flag fault, level 2 + KPrintf("reason: sect. Access flag fault level 2\n"); + else if ((fault_status & 0x3f) == 0xb) // Access flag fault, level 3 + KPrintf("reason: sect. Access flag fault level 3\n"); + else + KPrintf("reason: unknown???\n"); +} + +void dump_tf(struct trapframe* tf) +{ + KPrintf(" elr_el1: 0x%x\n", tf->elr_el1); + KPrintf(" spsr_el1: 0x%x\n", tf->spsr_el1); + KPrintf(" x0: 0x%x\n", tf->x0); + KPrintf(" x1: 0x%x\n", tf->x1); + KPrintf(" x2: 0x%x\n", tf->x2); + KPrintf(" x3: 0x%x\n", tf->x3); + KPrintf(" x4: 0x%x\n", tf->x4); + KPrintf(" x5: 0x%x\n", tf->x5); + KPrintf(" x6: 0x%x\n", tf->x6); + KPrintf(" x7: 0x%x\n", tf->x7); + KPrintf(" x8: 0x%x\n", tf->x8); + KPrintf(" x9: 0x%x\n", tf->x9); + KPrintf(" x10: 0x%x\n", tf->x10); + KPrintf(" x11: 0x%x\n", tf->x11); + KPrintf(" x12: 0x%x\n", tf->x12); + KPrintf(" x13: 0x%x\n", tf->x13); + KPrintf(" x14: 0x%x\n", tf->x14); + KPrintf(" x15: 0x%x\n", tf->x15); + KPrintf(" x16: 0x%x\n", tf->x16); + KPrintf(" x17: 0x%x\n", tf->x17); + KPrintf(" x18: 0x%x\n", tf->x18); + KPrintf(" x19: 0x%x\n", tf->x19); + KPrintf(" x20: 0x%x\n", tf->x20); + KPrintf(" x21: 0x%x\n", tf->x21); + KPrintf(" x22: 0x%x\n", tf->x22); + KPrintf(" x23: 0x%x\n", tf->x23); + KPrintf(" x24: 0x%x\n", tf->x24); + KPrintf(" x25: 0x%x\n", tf->x25); + KPrintf(" x26: 0x%x\n", tf->x26); + KPrintf(" x27: 0x%x\n", tf->x27); + KPrintf(" x28: 0x%x\n", tf->x28); + KPrintf(" x29: 0x%x\n", tf->x29); + KPrintf(" pc: 0x%x\n", tf->pc); +} + +void handle_undefined_instruction(struct trapframe* tf) +{ + // unimplemented trap handler + KPrintf("undefined instruction at %x\n", tf->pc); + panic(""); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/arch_gicv3.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/arch_gicv3.h new file mode 100644 index 000000000..552885ac7 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/arch_gicv3.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file arch_gicv3.h + * @brief gicv3 operation + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.05.07 + */ +/************************************************* +File name: arch_gicv3.h +Description: gicv3 operation +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. Rename file +*************************************************/ diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/boot.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/gicv3.c similarity index 100% rename from Ubiquitous/XiZi_AIoT/hardkernel/arch/arm/armv8-a/cortex-a72/boot.S rename to Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/gicv3.c diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/gicv3.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/gicv3.h new file mode 100644 index 000000000..e69de29bb diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/sysreg.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/gicv3/sysreg.h new file mode 100644 index 000000000..e69de29bb diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/hard_spinlock.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/hard_spinlock.S new file mode 100644 index 000000000..32976c730 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/hard_spinlock.S @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2013, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/* + * Portions Copyright (c) 2011-2012 ARM Ltd. All rights reserved. + */ +/** + * @file hard_spinlock.S + * @brief spinlock implementation + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.11 + */ + +/************************************************* +File name: hard_spinlock.S +Description: spinlock implementation +Others: +History: +Author: AIIT XUOS Lab +Modification: +*************************************************/ + + .code 64 + .section ".text","ax" + + .global cpu_get_current + +#define UNLOCKED 0xFF +// int spinlock_lock(spinlock_t * lock, uint64_t timeout) + .global _spinlock_lock + .func _spinlock_lock +_spinlock_lock: + +ldxr x1, [x0] // check if the spinlock is currently unlocked +cmp x1, #UNLOCKED + +wfene // wait for an event signal +bne _spinlock_lock + +mrs x1, mpidr_el1 // get our CPU ID +and x1, x1, #3 +stxr x2, x1, [x0] +cbnz x2, _spinlock_lock // check if the write was successful, if the write failed, start over + +dmb // Ensure that accesses to shared resource have completed + +mov x0, #0 +ret + + .endfunc + + +// void spinlock_unlock(spinlock_t * lock) + .global _spinlock_unlock + .func _spinlock_unlock +_spinlock_unlock: + +mrs x1, mpidr_el1 // get our CPU ID +and x1, x1, #3 + +ldr x2, [x0] +cmp x1, x2 +bne 1f //doesn't match,jump to 1 + +dmb + +mov x1, #UNLOCKED +str x1, [x0] + +dsb //Ensure that no instructions following the barrier execute until + // all memory accesses prior to the barrier have completed. + + +sev // send event to wake up other cores waiting on spinlock + +mov x0, #0 // return success +ret + +1: +mov x0, #1 //doesn't match, so exit with failure +ret + diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/irq_numbers.h b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/irq_numbers.h new file mode 100644 index 000000000..7a0bc8e3d --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/irq_numbers.h @@ -0,0 +1,110 @@ +/** + * @file irq_numbers.c + * @brief irq numbers + * @version 3.0 + * @author AIIT XUOS Lab + * @date 2023.08.25 + */ + +/************************************************* +File name: irq_numbers.c +Description: irq numbers +Others: +History: +1. Date: 2023-08-28 +Author: AIIT XUOS Lab +Modification: +1. Add HW_NR_IRQS +*************************************************/ +#if !defined(__IRQ_NUMBERS_H__) +#define __IRQ_NUMBERS_H__ + +#define HW_NR_IRQS NR_OK1028_INTRS + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +//! @brief i.MX6 interrupt numbers. +//! +//! This enumeration lists the numbers for all of the interrupts available on the i.MX6 series. +//! Use these numbers when specifying an interrupt to the GIC. +//! +//! The first 16 interrupts are special in that they are reserved for software interrupts generated +//! by the SWI instruction. + +enum _ls_interrupts { + SW_INTERRUPT_0 = 0, //!< Software interrupt 0. + SW_INTERRUPT_1 = 1, //!< Software interrupt 1. + SW_INTERRUPT_2 = 2, //!< Software interrupt 2. + SW_INTERRUPT_3 = 3, //!< Software interrupt 3. + SW_INTERRUPT_4 = 4, //!< Software interrupt 4. + SW_INTERRUPT_5 = 5, //!< Software interrupt 5. + SW_INTERRUPT_6 = 6, //!< Software interrupt 6. + SW_INTERRUPT_7 = 7, //!< Software interrupt 7. + SW_INTERRUPT_8 = 8, //!< Software interrupt 8. + SW_INTERRUPT_9 = 9, //!< Software interrupt 9. + SW_INTERRUPT_10 = 10, //!< Software interrupt 10. + SW_INTERRUPT_11 = 11, //!< Software interrupt 11. + SW_INTERRUPT_12 = 12, //!< Software interrupt 12. + SW_INTERRUPT_13 = 13, //!< Software interrupt 13. + SW_INTERRUPT_14 = 14, //!< Software interrupt 14. + SW_INTERRUPT_15 = 15, //!< Software interrupt 15. + RSVD_INTERRUPT_16 = 16, //!< Reserved. + RSVD_INTERRUPT_17 = 17, //!< Reserved. + RSVD_INTERRUPT_18 = 18, //!< Reserved. + RSVD_INTERRUPT_19 = 19, //!< Reserved. + RSVD_INTERRUPT_20 = 20, //!< Reserved. + RSVD_INTERRUPT_21 = 21, //!< Reserved. + + LS_INT_DEBUG_CC = 22, //!<(cluster-internal) COMMIRQ - Debug communications channel + LS_INT_PMU = 23, //!<(cluster-internal) PMUIRQ - Perfmon* + LS_INT_CTI = 24, //!<(cluster-internal) CTIIRQ - Cross-trigger interface* + LS_INT_VMI = 25, //!<(cluster-internal) VCPUMNTIRQ -Virtual maintenance interface* + + LS_INT_WDOG = 28, //!< Watchdog timer + LS_INT_SEC_PHY_TIMER = 29, //!<(cluster-internal) CNTPSIRQ - EL1 Secure physical timer event* + LS_INT_NON_SEC_PHY_TIMER = 30, //!<(cluster-internal) CNTPNSIRQ - EL1 Non-secure physical timer event* + RSVD_INTERRUPT_31 = 31, //!< Reserved. + RSVD_INTERRUPT_32 = 32, //!< Reserved. + RSVD_INTERRUPT_33 = 33, //!< Reserved. + RSVD_INTERRUPT_34 = 34, //!< Reserved. + RSVD_INTERRUPT_35 = 35, //!< Reserved. + RSVD_INTERRUPT_36 = 36, //!< Reserved. + RSVD_INTERRUPT_37 = 37, //!< Reserved. + RSVD_INTERRUPT_38 = 38, //!< Reserved. + RSVD_INTERRUPT_39 = 39, //!< Reserved. + RSVD_INTERRUPT_40 = 40, //!< Reserved. + RSVD_INTERRUPT_41 = 41, //!< Reserved. + RSVD_INTERRUPT_42 = 42, //!< Reserved. + + LS_INT_DUART1 = 64, // Logical OR of DUART1 interrupt requests. + + LS_INT_I2C1_2 = 66, //!< I2C1 and I2C2 ORed + LS_INT_I2C3_4 = 67, //!< I2C3 and I2C4 ORed + LS_INT_GPIO1_2 = 68, //!< GPIO1 and GPIO2 ORed + LS_INT_GPIO3 = 69, //!< GPIO3 + + LS_INT_FLETIMER1 = 76, //!< ORed all Flextimer 1 interrupt signals + LS_INT_FLETIMER1 = 77, //!< ORed all Flextimer 2 interrupt signals + LS_INT_FLETIMER1 = 78, //!< ORed all Flextimer 3 interrupt signals + LS_INT_FLETIMER1 = 79, //!< ORed all Flextimer 4 interrupt signals + + LS_INT_I2C5_6 = 106, //!< I2C5 and I2C6 ORed + LS_INT_I2C7_8 = 107, //!< I2C7 and I2C8 ORed + + LS_INT_USB3_1 = 112, //!< USB1 ORed INT + LS_INT_USB3_2 = 113, //!< USB2 ORed INT + + LS_INT_LPUART1 = 264, //!< LPUART1 interrupt request. + LS_INT_LPUART2 = 265, //!< LPUART1 interrupt request. + LS_INT_LPUART3 = 266, //!< LPUART1 interrupt request. + LS_INT_LPUART4 = 267, //!< LPUART1 interrupt request. + LS_INT_LPUART5 = 268, //!< LPUART1 interrupt request. + LS_INT_LPUART6 = 269, //!< LPUART1 interrupt request. + + NR_OK1028_INTRS, + +}; + +#endif //__IRQ_NUMBERS_H__ \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/trap_common.c b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/trap_common.c new file mode 100644 index 000000000..e91e77f3c --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/ok1028a-c/trap_common.c @@ -0,0 +1,237 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file trap_common.c + * @brief trap interface of hardkernel + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2023.05.06 + */ + +/************************************************* +File name: trap_common.c +Description: trap interface of hardkernel +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include + +#include "core.h" +#include "gicv2_common_opa.h" +#include "trap_common.h" + +#include "log.h" +#include "multicores.h" + +extern void init_stack(uint64_t, uint64_t); +extern void user_trap_swi_enter(void); +extern void trap_iabort(void); +extern void trap_dabort(void); +extern void trap_irq_enter(void); +extern void trap_undefined_instruction(void); + +static struct XiziTrapDriver xizi_trap_driver; + +void panic(char* s) +{ + xizi_trap_driver.cpu_irq_disable(); + spinlock_unlock(&whole_kernel_lock); + KPrintf("panic: %s\n", s); + for (;;) + ; +} + +/* stack for different mode*/ +static char mode_stack_pages[NR_CPU][NR_MODE_STACKS][MODE_STACK_SIZE]; + +extern uint64_t _vector_jumper; +extern uint64_t _vector_start; +extern uint64_t _vector_end; + +void init_cpu_mode_stacks(int cpu_id) +{ + uint32_t modes[] = { ARM_MODE_EL0_t, ARM_MODE_EL1_t, ARM_MODE_EL2_t, ARM_MODE_EL3_t }; + // initialize the stacks for different mode + for (int i = 0; i < sizeof(modes) / sizeof(uint64_t); i++) { + memset(mode_stack_pages[cpu_id][i], 0, MODE_STACK_SIZE); + init_stack(modes[i], (uint64_t)mode_stack_pages[cpu_id][i]); + } +} + +void handle_reserved(void) +{ + // unimplemented trap handler + LOG("Unimplemented Reserved\n"); + panic(""); +} + +void handle_fiq(void) +{ + LOG("Unimplemented FIQ\n"); + panic(""); +} + +static void _sys_irq_init(int cpu_id) +{ + /* load exception vectors */ + init_cpu_mode_stacks(cpu_id); + if (cpu_id == 0) { + volatile uint64_t* vector_base = &_vector_start; + + // Set Interrupt handler start address + vector_base[1] = (uint64_t)trap_undefined_instruction; // Undefined Instruction + vector_base[2] = (uint64_t)user_trap_swi_enter; // Software Interrupt + vector_base[3] = (uint64_t)trap_iabort; // Prefetch Abort + vector_base[4] = (uint64_t)trap_dabort; // Data Abort + vector_base[5] = (uint64_t)handle_reserved; // Reserved + vector_base[6] = (uint64_t)trap_irq_enter; // IRQ + vector_base[7] = (uint64_t)handle_fiq; // FIQ + } + /* active hardware irq responser */ + gic_init(); + xizi_trap_driver.switch_hw_irqtbl((uint64_t*)&_vector_jumper); +} + +static void _cpu_irq_enable(void) +{ + arm_set_interrupt_state(true); +} + +static void _cpu_irq_disable(void) +{ + arm_set_interrupt_state(false); +} + +static void _single_irq_enable(int irq, int cpu, int prio) +{ + gic_set_irq_priority(irq, prio); + gic_set_irq_security(irq, false); // set IRQ as non-secure + gic_set_cpu_target(irq, cpu, true); + gic_enable_irq(irq, true); +} + +static void _single_irq_disable(int irq, int cpu) +{ + gic_enable_irq(irq, false); + gic_set_cpu_target(irq, cpu, false); +} + +#define VBAR +static inline uint64_t _switch_hw_irqtbl(uint64_t* new_tbl_base) +{ + uint64_t old_tbl_base = 0; + //get old irq table base addr + asm volatile("mrs %0, vbar_el1" : "=r" (old_tbl_base)); + + // set new irq table base addr + asm volatile("msr vbar_el1, %0" : : "r" (new_tbl_base)); + + return old_tbl_base; +} + +static void _bind_irq_handler(int irq, irq_handler_t handler) +{ + xizi_trap_driver.sw_irqtbl[irq].handler = handler; +} + +static bool _send_sgi(uint32_t irq, uint32_t bitmask, enum SgiFilterType type) +{ + if (bitmask > (1 << NR_CPU) - 1) { + return false; + } + + enum _gicd_sgi_filter sgi_filter; + switch (type) { + case SgiFilter_TargetList: + sgi_filter = kGicSgiFilter_UseTargetList; + break; + case SgiFilter_AllOtherCPUs: + sgi_filter = kGicSgiFilter_AllOtherCPUs; + break; + default: + sgi_filter = kGicSgiFilter_OnlyThisCPU; + break; + } + gic_send_sgi(irq, bitmask, sgi_filter); + + return true; +} + +static uint32_t _hw_before_irq() +{ + + uint32_t vectNum = gic_read_irq_ack(); + if (vectNum & 0x200) { + gic_write_end_of_irq(vectNum); + return 0; + } + return vectNum; +} + +static uint32_t _hw_cur_int_num(uint32_t int_info) +{ + return int_info & 0x1FF; +} + +static uint32_t _hw_cur_int_cpu(uint32_t int_info) +{ + return (int_info >> 10) & 0x7; +} + +static void _hw_after_irq(uint32_t int_info) +{ + gic_write_end_of_irq(int_info); +} + +static int _is_interruptable(void) +{ + uint32_t val; + + asm volatile("mrs %0, spsr_el1" : "=r"(val)); + + return !(val & DIS_INT); +} + +int _cur_cpu_id() +{ + return cpu_get_current(); +} + +static struct XiziTrapDriver xizi_trap_driver = { + .sys_irq_init = _sys_irq_init, + .cur_cpu_id = _cur_cpu_id, + + .cpu_irq_enable = _cpu_irq_enable, + .cpu_irq_disable = _cpu_irq_disable, + .single_irq_enable = _single_irq_enable, + .single_irq_disable = _single_irq_disable, + .switch_hw_irqtbl = _switch_hw_irqtbl, + + .bind_irq_handler = _bind_irq_handler, + .send_sgi = _send_sgi, + + .is_interruptable = _is_interruptable, + .hw_before_irq = _hw_before_irq, + .hw_cur_int_num = _hw_cur_int_num, + .hw_cur_int_cpu = _hw_cur_int_cpu, + .hw_after_irq = _hw_after_irq, +}; + +struct XiziTrapDriver* hardkernel_intr_init(struct TraceTag* hardkernel_tag) +{ + xizi_trap_driver.sys_irq_init(0); + xizi_trap_driver.cpu_irq_disable(); + return &xizi_trap_driver; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/trampoline.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/trampoline.S new file mode 100644 index 000000000..886ae1f86 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/trampoline.S @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file trampoline.S + * @brief trap in and out code + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024-04-22 + */ + +/************************************************* +File name: trampoline.S +Description: trap in and out code +Others: +History: +1. Date: 2024-04-22 +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ + +#include "memlayout.h" + +#include "core.h" + +.global trap_irq_enter +.global trap_return +.global usertrapret + +trap_return: + /* Restore registers. */ + ldp x1, x2, [sp], #16 + ldp x3, x0, [sp], #16 + msr sp_el0, x1 + msr spsr_el1, x2 + msr elr_el1, x3 + + ldp x1, x2, [sp], #16 + ldp x3, x4, [sp], #16 + ldp x5, x6, [sp], #16 + ldp x7, x8, [sp], #16 + ldp x9, x10, [sp], #16 + ldp x11, x12, [sp], #16 + ldp x13, x14, [sp], #16 + ldp x15, x16, [sp], #16 + ldp x17, x18, [sp], #16 + ldp x19, x20, [sp], #16 + ldp x21, x22, [sp], #16 + ldp x23, x24, [sp], #16 + ldp x25, x26, [sp], #16 + ldp x27, x28, [sp], #16 + ldp x29, x30, [sp], #16 + + eret + +user_trap_swi_enter: + // Save trapframe to swi stack + stp x29, x30, [sp, #-16]! + stp x27, x28, [sp, #-16]! + stp x25, x26, [sp, #-16]! + stp x23, x24, [sp, #-16]! + stp x21, x22, [sp, #-16]! + stp x19, x20, [sp, #-16]! + stp x17, x18, [sp, #-16]! + stp x15, x16, [sp, #-16]! + stp x13, x14, [sp, #-16]! + stp x11, x12, [sp, #-16]! + stp x9, x10, [sp, #-16]! + stp x7, x8, [sp, #-16]! + stp x5, x6, [sp, #-16]! + stp x3, x4, [sp, #-16]! + stp x1, x2, [sp, #-16]! + + mrs x2, spsr_el1 + str x2, [sp, #-8] + str x30, [sp, #-8] + stp sp, elr_el1, [sp, #-16]! + str sp, [sp, #-8] + + // Call syscall handler + mov x0, sp + bl software_irq_dispatch + b trap_return + +trap_irq_enter: + /* Build trapframe. */ + stp x29, x30, [sp, #-16]! + stp x27, x28, [sp, #-16]! + stp x25, x26, [sp, #-16]! + stp x23, x24, [sp, #-16]! + stp x21, x22, [sp, #-16]! + stp x19, x20, [sp, #-16]! + stp x17, x18, [sp, #-16]! + stp x15, x16, [sp, #-16]! + stp x13, x14, [sp, #-16]! + stp x11, x12, [sp, #-16]! + stp x9, x10, [sp, #-16]! + stp x7, x8, [sp, #-16]! + stp x5, x6, [sp, #-16]! + stp x3, x4, [sp, #-16]! + stp x1, x2, [sp, #-16]! + + mrs x3, elr_el1 + mrs x2, spsr_el1 + mrs x1, sp_el0 + stp x3, x0, [sp, #-16]! + stp x1, x2, [sp, #-16]! + + /* Call trap(struct trapframe*). */ + mov x0, sp + bl intr_irq_dispatch + b trap_return + + + +/* Help forkret to call trap_return in an expected way. */ +usertrapret: + /* Overlay stack pointer in trap_return. */ + mov sp, x0 + b trap_return diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/vector.S b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/vector.S new file mode 100644 index 000000000..ff7ae82d7 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/intr/arm/armv8-a/cortex-a72/vector.S @@ -0,0 +1,67 @@ +/* +* Copyright (c) 2020 AIIT XUOS Lab +* XiUOS is licensed under Mulan PSL v2. +* You can use this software according to the terms and conditions of the Mulan PSL v2. +* You may obtain a copy of Mulan PSL v2 at: +* http://license.coscl.org.cn/MulanPSL2 +* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, +* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, +* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +* See the Mulan PSL v2 for more details. +*/ + +/** + * @file vector.S + * @brief define vector table function + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.4.22 + */ + +/************************************************* +File name: vector.S +Description: cortex-a9 vector table +Others: +History: +1. Date: 2024.4.22 +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ + +#include "memlayout.h" + +#define ventry .align 7; b trap_irq_enter + +#define verror(type) .align 7; mov x0, #(type); b irq_error + +.globl vectors + +.align 11 +vectors: +el1_sp0: + verror(0) + verror(1) + verror(2) + verror(3) + +el1_spx: + /* Current EL with SPx */ + verror(4) + verror(5) + verror(6) + verror(7) + +el0_aarch64: + /* Lower EL using AArch64 */ + ventry + ventry + verror(10) + verror(11) + +el0_aarch32: + /* Lower EL using AArch32 */ + verror(12) + verror(13) + verror(14) + verror(15) diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/Makefile new file mode 100644 index 000000000..7a9b17009 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/Makefile @@ -0,0 +1,3 @@ +SRC_DIR := cortex-a72 + +include $(KERNEL_ROOT)/compiler.mk diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/Makefile b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/Makefile new file mode 100644 index 000000000..6b8df00e5 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/Makefile @@ -0,0 +1,3 @@ +SRC_FILES := bootmmu.c mmu.c pagetable_attr.c + +include $(KERNEL_ROOT)/compiler.mk \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/bootmmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/bootmmu.c new file mode 100644 index 000000000..1739178b4 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/bootmmu.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file bootmmu.c + * @brief build pagetable and enable mmu in boot time + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.26 + */ + +/************************************************* +File name: bootmmu.c +Description: build pagetable and enable mmu in boot time +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include "core.h" +#include "memlayout.h" +#include "mmu.h" + +#include "mmio_access.h" + +#include +#include + +extern uint64_t kernel_data_end[]; +extern uint64_t kernel_data_begin[]; + +#define NR_PDE_ENTRIES 512 +#define L1_TYPE_SEC (2 << 0) +#define L1_SECT_DEV ((0B00)<<2) //Device memory +#define L1_SECT_AP0 (1 << 6) //Data Access Permissions +uint64_t boot_ptable[NR_PTE_ENTRIES] __attribute__((aligned(0x4000))) = { 0 }; + +static void build_boot_pgdir() +{ + // dev mem + uint64_t dev_mem_end_idx = (DEV_PHYMEM_BASE + DEV_MEM_SZ) >> LEVEL3_PDE_SHIFT; + for (uint64_t i = DEV_PHYMEM_BASE >> LEVEL3_PDE_SHIFT; i < dev_mem_end_idx; i++) { + boot_pgdir[i] = (i << LEVEL3_PDE_SHIFT) | L1_TYPE_SEC | L1_SECT_DEV | L1_SECT_AP0; + boot_pgdir[MMIO_P2V_WO(i << LEVEL3_PDE_SHIFT) >> LEVEL3_PDE_SHIFT] = (i << LEVEL3_PDE_SHIFT) | L1_TYPE_SEC | L1_SECT_DEV | L1_SECT_AP0; + } + + // identical mem + uint64_t idn_mem_start_idx = PHY_MEM_BASE >> LEVEL3_PDE_SHIFT; + uint64_t idn_mem_end_idx = PHY_MEM_STOP >> LEVEL3_PDE_SHIFT; + for (uint64_t i = idn_mem_start_idx; i < idn_mem_end_idx; i++) { + boot_pgdir[i] = i << LEVEL3_PDE_SHIFT | L1_TYPE_SEC | L1_SECT_AP0; + } + + // kern mem + uint64_t kern_mem_start_idx = KERN_MEM_BASE >> LEVEL3_PDE_SHIFT; + uint64_t kern_mem_end_idx = (KERN_MEM_BASE + (PHY_MEM_STOP - PHY_MEM_BASE)) >> LEVEL3_PDE_SHIFT; + for (uint64_t i = kern_mem_start_idx; i < kern_mem_end_idx; i++) { + boot_pgdir[i] = V2P(i << LEVEL3_PDE_SHIFT) | L1_TYPE_SEC | L1_SECT_AP0; + } +} + + + +static void load_boot_pgdir() +{ + uint64_t val; + + // DACR_W(0x55555555); // set domain access control as client + TTBCR_W(0x0); + TTBR0_W((uint64_t)boot_pgdir); + + // Enable paging using read/modify/write + SCTLR_R(val); + val |= (1 << 0); //EL1 and EL0 stage 1 address translation enabled. + val |= (1 << 1); //Alignment check enable + val |= (1 << 2); // Cacheability control, for data caching. + val |= (1 << 12); // Instruction access Cacheability control + val |= (1 << 19); //forced to XN for the EL1&0 translation regime. + + SCTLR_W(val); + + // flush all TLB + DSB(); + CLEARTLB(0); + ISB(); +} + +extern void main(void); +static bool _bss_inited = false; +void bootmain() +{ + build_boot_pgdir(); + load_boot_pgdir(); + __asm__ __volatile__("add sp, sp, %0" ::"r"(KERN_MEM_BASE - PHY_MEM_BASE)); + if (!_bss_inited) { + memset(&kernel_data_begin, 0x00, (uint64_t)kernel_data_end - (uint64_t)kernel_data_begin); + _bss_inited = true; + } + + main(); +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/include/mmu.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/include/mmu.h new file mode 100644 index 000000000..ff8ff1fe3 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/include/mmu.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file mmu.h + * @brief mmu related configure and registers + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024-04-26 + */ +/************************************************* +File name: mmu.h +Description: mmu related configure and registers +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#pragma once + +#include + +#include "memlayout.h" +#include "page_table_entry.h" + + +#define TCR_IPS (0 << 32) +#define TCR_TG1_4K (0b10 << 30) +#define TCR_SH1_INNER (0b11 << 28) +#define TCR_ORGN1_IRGN1_WRITEBACK_WRITEALLOC ((0b01 << 26) | (0b01 << 24)) +#define TCR_TG0_4K (0 << 14) +#define TCR_SH0_INNER (0b11 << 12) +#define TCR_ORGN0_IRGN0_WRITEBACK_WRITEALLOC ((0b01 << 10) | (0b01 << 8)) +#define TCR_VALUE \ + (TCR_IPS | \ + TCR_TG1_4K | TCR_SH1_INNER | TCR_ORGN1_IRGN1_WRITEBACK_WRITEALLOC | \ + TCR_TG0_4K | TCR_SH0_INNER | TCR_ORGN0_IRGN0_WRITEBACK_WRITEALLOC) + +enum AccessPermission { + AccessPermission_NoAccess = 0, + AccessPermission_KernelOnly = 1, //EL1 + AccessPermission_Reserved = 2, + AccessPermission_KernelUser = 3, //EL1&EL0 +}; + +void GetDevPteAttr(uintptr_t* attr); +void GetUsrPteAttr(uintptr_t* attr); +void GetUsrDevPteAttr(uintptr_t* attr); +void GetKernPteAttr(uintptr_t* attr); +void GetPdeAttr(uintptr_t* attr); + + +/* +Enable MMU, cache, write buffer, etc. +*/ +#define SCTLR_R(val) __asm__ volatile("mrs %0, sctlr_el1" : "=r"(val)) +#define SCTLR_W(val) __asm__ volatile("msr sctlr_el1, %0" :: "r"(val)) + +/* +Read and write mmu pagetable register base addr +*/ +#define TTBR0_R(val) __asm__ volatile("mrs %0, ttbr0_el1" : "=r"(val)) +#define TTBR0_W(val) __asm__ volatile("msr ttbr0_el1, %0" :: "r"(val)) + +/* +TTBCR is used for choosing TTBR0 and TTBR1 as page table register. +When TTBCR is set to 0, TTBR0 is selected by default. +*/ +#define TTBCR_R(val) __asm__ volatile("mrs %0, ttbcr_el1" : "=r"(val)) +#define TTBCR_W(val) __asm__ volatile("msr ttbcr_el1, %0" :: "r"(val)) + +/* +DACR registers are used to control memory privilage. +The domain value is usually 0x01. The memory privilage will be controled by pte AP/APX +*/ +//#define DACR_R(val) __asm__ volatile("mrs %0, dacr_el1" : "=r"(val)) +//#define DACR_W(val) __asm__ volatile("msr dacr_el1, %0" :: "r"(val)) + +/* +Flush TLB when loading a new page table. +@note If nG is not set in the pte attribute, process switching need flush tlb. +*/ +#define CLEARTLB(val) __asm__ volatile("tlbi vmalle1") + +/* +When nG is set in the pte attribute, the process is assigned an ASID, which is stored in the lower 8 bits of the CONTEXTIDR register. +When the process switches, the flush TLB is no longer required anymore. +*/ +#define CONTEXTIDR_R(val) __asm__ volatile("mrs %0, contextidr_el1" : "=r"(val)) +#define CONTEXTIDR_W(val) __asm__ volatile("msr contextidr_el1, %0" :: "r"(val)) + + +/* virtual and physical addr translate */ +#define V2P(a) ((uint64_t)((uint64_t)(a)-KERN_OFFSET)) +#define P2V(a) ((void*)((void*)(a) + KERN_OFFSET)) + +#define V2P_WO(x) ((x)-KERN_OFFSET) // same as V2P, but without casts +#define P2V_WO(x) ((x) + KERN_OFFSET) // same as V2P, but without casts + +#ifndef __ASSEMBLER__ +#include +__attribute__((always_inline)) static inline uint64_t v2p(void* a) { return ((uint64_t)(a)) - KERN_MEM_BASE; } +__attribute__((always_inline)) static inline void* p2v(uint64_t a) { return (void*)((a) + KERN_MEM_BASE); } +#endif \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/include/page_table_entry.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/include/page_table_entry.h new file mode 100644 index 000000000..2742e3452 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/include/page_table_entry.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2008-2012, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file page_table_entry.h + * @brief mmu related configure and registers + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024-04-25 + */ + +/************************************************* +File name: page_table_entry.h +Description: mmu related configure and registers +Others: take imx_platform_sdk sdk/core/src/mmu.c for references + https://github.com/flit/imx6_platform_sdk +History: +Author: AIIT XUOS Lab +Modification: +1. modify the L1-level page table name and properties name to apply hardkernel implementation +*************************************************/ +#pragma once + +#include + +typedef union { + uintptr_t entry; + struct { + uint64_t desc_type : 2; // (Invalid, PageTable, Section, SuperSection)/(Invalid, Table, Block) + //uint64_t B : 1; // Bufferable + // uint64_t C : 1; // Cacheable + uint64_t XN : 1; // Execute-not + //uint64_t Domain : 4; // Domain + uint64_t _impl_defined : 1; // Implementation defined, should be zero. + uint64_t AP1_0 : 2; // Access permissions AP + uint64_t TEX : 3; // TEX remap ==attr_idx The memory type, Device or Normal. + uint64_t AP2 : 1; // Access permissions AP[2] + uint64_t S : 1; // Shareable + uint64_t NG : 1; // Not-global + uint64_t _zero : 1; // Should be zero. + uint64_t NS : 1; // Non-secure + uint64_t section_addr :36 ; // Section Physical base address + uint64_t AF : 1; // Access flag + }; +} __attribute__((packed)) PageDirEntry; + +typedef union { + uint64_t entry; + struct { + uint64_t desc_type : 2; // (Invalid, Reserved,4kb, 16kb 64kb ) + // uint64_t B : 1; // Bufferable + //uint64_t C : 1; // Cacheable + uint64_t AP1_0 : 2;//Access permissions + uint64_t TEX : 3;//TEX remap ==attr_idx The memory type, Device or Normal. + uint64_t AP2 : 1; + uint64_t S : 1; // Shareable + uint64_t NG : 1; // Not-global + uint64_t page_addr :36 ; + uint64_t AF : 1; // Access flag + }; +} __attribute__((packed)) PageTblEntry; diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/mmu.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/mmu.c new file mode 100644 index 000000000..70acd7fa8 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/mmu.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file mmu.c + * @brief mmu operations + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024.04.26 + */ + +/************************************************* +File name: mmu.c +Description: mmu operations +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ + +#include + +#include "mmu.h" + +#include "cache_common_ope.h" +#include "mmu_common.h" +#include "trap_common.h" + +// extern struct MmuCommonDone mmu_common_done; +static struct MmuDriverRightGroup right_group; + +void load_pgdir_critical(uintptr_t pgdir_paddr, struct TraceTag* intr_driver_tag) +{ + + /* get cache driver */ + struct ICacheDone* p_icache_done = AchieveResource(&right_group.icache_driver_tag); + struct DCacheDone* p_dcache_done = AchieveResource(&right_group.dcache_driver_tag); + + /* get intr driver */ + struct XiziTrapDriver* p_intr_driver = AchieveResource(intr_driver_tag); + + p_intr_driver->cpu_irq_disable(); + TTBR0_W((uint64_t)pgdir_paddr); + CLEARTLB(0); + p_icache_done->invalidateall(); + p_dcache_done->flushall(); + p_intr_driver->cpu_irq_enable(); +} + +void load_pgdir(uintptr_t pgdir_paddr) +{ + /* get cache driver */ + struct ICacheDone* p_icache_done = AchieveResource(&right_group.icache_driver_tag); + struct DCacheDone* p_dcache_done = AchieveResource(&right_group.dcache_driver_tag); + + TTBR0_W((uint64_t)pgdir_paddr); + CLEARTLB(0); + p_icache_done->invalidateall(); + p_dcache_done->flushall(); +} + +__attribute__((always_inline)) inline static void _tlb_flush(uintptr_t va) +{ + __asm__ volatile("tlbi vae1is, %0" :: "r"(va) ); +} + +static void tlb_flush_range(uintptr_t vstart, int len) +{ + uintptr_t vaddr = vstart; + uintptr_t vend = vaddr + len; + for (; vaddr < vend; vaddr += PAGE_SIZE) { + _tlb_flush(vaddr); + } +} + +static void tlb_flush_all() +{ + CLEARTLB(0); +} + +static struct MmuCommonDone mmu_common_done = { + .MmuDevPteAttr = GetDevPteAttr, + .MmuPdeAttr = GetPdeAttr, + .MmuUsrPteAttr = GetUsrPteAttr, + .MmuUsrDevPteAttr = GetUsrDevPteAttr, + .MmuKernPteAttr = GetKernPteAttr, + + .LoadPgdirCrit = load_pgdir_critical, + .LoadPgdir = load_pgdir, + .TlbFlushAll = tlb_flush_all, + .TlbFlush = tlb_flush_range, +}; + +struct MmuCommonDone* hardkernel_mmu_init(struct TraceTag* hardkernel_tag, char* icache_name, char* dcache_name) +{ + /* init right group for mmu driver */ + AchieveResourceTag(&right_group.icache_driver_tag, hardkernel_tag, icache_name); + AchieveResourceTag(&right_group.dcache_driver_tag, hardkernel_tag, dcache_name); + + return &mmu_common_done; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/ok1028a-c/memlayout.h b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/ok1028a-c/memlayout.h new file mode 100644 index 000000000..164ef2241 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/ok1028a-c/memlayout.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ + +/** + * @file memlayout.h + * @brief virtual memory and physical memory layout + * @version 1.0 + * @author AIIT XUOS Lab + * @date 2024-04-25 + */ +/************************************************* +File name: memlayout.h +Description: virtual memory and physical memory layout +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#pragma once + +// Memory layout +// clang-format off + +#define ARCH_BIT 64 + +/* A72 physical memory layout */ +#define PHY_MEM_BASE (0x00000000) +#define PHY_USER_FREEMEM_BASE (0x30000000) +#define PHY_USER_FREEMEM_TOP (0x80000000) +#define PHY_MEM_STOP (0x80000000) + + +/* PTE-PAGE_SIZE */ +#define LEVEL4_PTE_SHIFT 12 +#define LEVEL4_PTE_SIZE (1 << LEVEL4_PTE_SHIFT) + +/* PDE-SECTION_SIZE */ +#define LEVEL3_PDE_SHIFT 21 +#define LEVEL3_PDE_SIZE (1 << LEVEL3_PDE_SHIFT) + +#define LEVEL2_PTE_SHIFT 30 + +#define LEVEL1_PTE_SHIFT 39 + +#define NUM_LEVEL3_PDE (1 << (ARCH_BIT - LEVEL3_PDE_SHIFT)) // how many PTE in a PT +#define NUM_LEVEL4_PTE (1 << (LEVEL3_PDE_SHIFT - LEVEL4_PTE_SHIFT)) // how many PTE in a PT +#define NUM_TOPLEVEL_PDE NUM_LEVEL3_PDE + +#define PAGE_SIZE LEVEL4_PTE_SIZE +#define MAX_NR_FREE_PAGES ((PHY_MEM_STOP - PHY_MEM_BASE) >> LEVEL4_PTE_SHIFT) + +/* Deivce memory layout */ +#define DEV_PHYMEM_BASE (0x0000000000000000) +#define DEV_VRTMEM_BASE (0x0000ffffffffffff) +#define DEV_MEM_SZ (0x10000000) + +/* User memory layout */ +#define USER_STACK_SIZE PAGE_SIZE +#define USER_MEM_BASE (0x0000000000000000) +#define USER_MEM_TOP DEV_VRTMEM_BASE +#define USER_IPC_SPACE_BASE (0x7000000000000000) +#define USER_IPC_SPACE_TOP (USER_MEM_TOP - USER_STACK_SIZE) + +/* Kernel memory layout */ +#define KERN_MEM_BASE (0xffff000000000000) // First kernel virtual address +#define KERN_OFFSET (KERN_MEM_BASE - PHY_MEM_BASE) + +#define V2P(a) (((uint64)(a)) - KERN_MEM_BASE) +#define P2V(a) ((void *)(((char *)(a)) + KERN_MEM_BASE)) + +#define V2P_WO(x) ((x) - KERN_MEM_BASE) // same as V2P, but without casts +#define P2V_WO(x) ((x) + KERN_MEM_BASE) // same as P2V, but without casts + +// one beyond the highest possible virtual address. +#define MAXVA (KERN_MEM_BASE + (1ULL<<38)) + +// qemu puts UART registers here in physical memory. +#define UART0 (KERN_MEM_BASE + 0x09000000L) +#define UART0_IRQ 33 + +// virtio mmio interface +#define VIRTIO0 (KERN_MEM_BASE + 0x0a000000L) +#define VIRTIO0_IRQ 48 + +#define TIMER0_IRQ 27 + +// interrupt controller GICv3 +#define GICV3 (KERN_MEM_BASE + 0x08000000L) +#define GICV3_REDIST (KERN_MEM_BASE + 0x080a0000L) + +// map kernel stacks beneath the trampoline, +// each surrounded by invalid guard pages. +#define PGSIZE 4096 // bytes per page +#define KSTACK(p) (MAXVA - ((p)+1) * 2*PGSIZE) + + +// extract the three 9-bit page table indices from a virtual address. +#define PXMASK 0x1FF // 9 bits +#define PXSHIFT(level) (39-(level)*9) +#define PX(level, va) ((((uint64)(va)) >> PXSHIFT(level)) & PXMASK) + +// clang-format on \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/pagetable_attr.c b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/pagetable_attr.c new file mode 100644 index 000000000..cd2ab20c5 --- /dev/null +++ b/Ubiquitous/XiZi_AIoT/hardkernel/mmu/arm/armv8-a/cortex-a72/pagetable_attr.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2020 AIIT XUOS Lab + * XiUOS is licensed under Mulan PSL v2. + * You can use this software according to the terms and conditions of the Mulan PSL v2. + * You may obtain a copy of Mulan PSL v2 at: + * http://license.coscl.org.cn/MulanPSL2 + * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, + * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, + * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. + * See the Mulan PSL v2 for more details. + */ +/** + * @file pagetable_attr.c + * @brief mmu entry attributes + * @version 1. + * @author AIIT XUOS Lab + * @date 2023.04.26 + */ + +/************************************************* +File name: pagetable_attr.c +Description: mmu entry attributes +Others: +History: +Author: AIIT XUOS Lab +Modification: +1. first version +*************************************************/ +#include "mmu.h" +#include "mmu_common.h" + +void GetUsrPteAttr(uintptr_t* attr) +{ + static char init = 0; + static PageTblEntry usr_pte_attr; + if (init == 0) { + init = 1; + + usr_pte_attr.entry = 0; + usr_pte_attr.desc_type = PAGE_4K; + usr_pte_attr.B = 1; + usr_pte_attr.C = 1; + usr_pte_attr.S = 1; + usr_pte_attr.AP1_0 = AccessPermission_KernelUser; + } + *attr = usr_pte_attr.entry; +} + +void GetUsrDevPteAttr(uintptr_t* attr) +{ + static char init = 0; + static PageTblEntry usr_pte_attr; + if (init == 0) { + init = 1; + + usr_pte_attr.entry = 0; + usr_pte_attr.desc_type = PAGE_4K; + usr_pte_attr.AP1_0 = AccessPermission_KernelUser; + } + *attr = usr_pte_attr.entry; +} + +void GetDevPteAttr(uintptr_t* attr) +{ + static char init = 0; + static PageTblEntry dev_pte_attr; + if (init == 0) { + init = 1; + + dev_pte_attr.entry = 0; + dev_pte_attr.desc_type = PAGE_4K; + dev_pte_attr.AP1_0 = AccessPermission_KernelOnly; + } + *attr = dev_pte_attr.entry; +} + +void GetKernPteAttr(uintptr_t* attr) +{ + static char init = 0; + static PageTblEntry kern_pte_attr; + if (init == 0) { + init = 1; + + kern_pte_attr.entry = 0; + kern_pte_attr.desc_type = PAGE_4K; + kern_pte_attr.B = 1; + kern_pte_attr.C = 1; + kern_pte_attr.S = 1; + kern_pte_attr.AP1_0 = AccessPermission_KernelOnly; + } + *attr = kern_pte_attr.entry; +} + +void GetPdeAttr(uintptr_t* attr) +{ + *attr = PAGE_DIR_COARSE; +} \ No newline at end of file diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/include/uart.c b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/include/uart.c new file mode 100644 index 000000000..e69de29bb diff --git a/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/include/uart.h b/Ubiquitous/XiZi_AIoT/hardkernel/uart/arm/armv8-a/cortex-a72/uart_io_for_ok1028a-c/include/uart.h new file mode 100644 index 000000000..e69de29bb diff --git a/Ubiquitous/XiZi_AIoT/path_kernel.mk b/Ubiquitous/XiZi_AIoT/path_kernel.mk index 33d069622..0c5d0c58e 100755 --- a/Ubiquitous/XiZi_AIoT/path_kernel.mk +++ b/Ubiquitous/XiZi_AIoT/path_kernel.mk @@ -38,6 +38,16 @@ KERNELPATHS += \ -I$(KERNEL_ROOT)/hardkernel/cache/L2/pl310/ endif +ifeq ($(BOARD), ok1028a-c) +KERNELPATHS += \ + -I$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/preboot_for_$(BOARD)/include \ + -I$(KERNEL_ROOT)/hardkernel/arch/arm/armv8-a/cortex-a72/ \ + -I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv8-a/cortex-a72/$(BOARD) \ + -I$(KERNEL_ROOT)/hardkernel/mmu/arm/armv8-a/cortex-a72/include \ + -I$(KERNEL_ROOT)/hardkernel/intr/arm/armv8-a/cortex-a72/ \ + -I$(KERNEL_ROOT)/hardkernel/intr/arm/armv8-a/cortex-a72/$(BOARD) +endif + KERNELPATHS += \ -I$(KERNEL_ROOT)/hardkernel \ -I$(KERNEL_ROOT)/hardkernel/clock/ \