add hal ethernet driver

Ubiquitous/XiZi_AIoT/services/app/Makefile

@@ -43,7 +43,7 @@ INC_DIR = 	-I$(KERNEL_ROOT)/services/shell/letter-shell \
 			-I$(KERNEL_ROOT)/services/app 
 
 ifeq ($(BOARD), imx6q-sabrelite)
-all: init test_fault simple_client simple_server shell fs_server semaphore_server test_semaphore test_ipc_null test_thread test_irq_hdlr test_irq_block test_irq_send eth_driver epit_server test_net lwip readme.txt | bin
+all: init test_fault simple_client simple_server shell fs_server semaphore_server test_semaphore test_ipc_null test_thread test_irq_hdlr test_irq_block test_irq_send eth_driver epit_server test_net lwip ethernet readme.txt | bin
 else 
 all: init test_fault simple_client simple_server shell fs_server semaphore_server test_ipc_null test_thread test_semaphore readme.txt | bin
 endif
@@ -64,6 +64,10 @@ eth_driver: enet_drv.o enet_test.o board_network.o enet_iomux_config.o imx6dq_gp
 	@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
 	@${objdump} -S $@ > $@.asm
 
+ethernet: test_gmac.o gmac.o gmac_3568.o hal_base.o hal_bsp.o hal_pinctrl_v2.o hal_cru.o hal_cache.o hal_gpio.o hal_timer.o hal_cru_rk3568.o libserial.o printf.o libmem.o usyscall.o arch_usyscall.o session.o libipc.o 
+	@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
+	@${objdump} -S $@ > $@.asm
+
 epit_server: timer.o epit.o ccm_pll.o usyscall.o arch_usyscall.o libserial.o printf.o libipc.o session.o
 	@${ld} ${user_ldflags} -e main -o $@ $^ ${board_specs}
 	@${objdump} -S $@ > $@.asm

Ubiquitous/XiZi_AIoT/services/drivers/Makefile

@@ -1,4 +1,4 @@
 
-SRC_DIR :=  $(BOARD)
+SRC_DIR :=  $(BOARD) rk-3568
 
 include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/Makefile

@@ -0,0 +1,4 @@
+
+SRC_DIR := ethernet
+
+include $(KERNEL_ROOT)/compiler.mk

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/Makefile

@@ -0,0 +1,37 @@
+ifeq ($(BOARD), imx6q-sabrelite)
+toolchain ?= arm-none-eabi-
+endif
+ifeq ($(BOARD), zynq7000-zc702)
+toolchain ?= arm-xilinx-eabi-
+endif
+cc = ${toolchain}gcc
+ld = ${toolchain}g++
+objdump = ${toolchain}objdump
+user_ldflags = -N -Ttext 0
+
+cflags = -std=c11  -g \
+	-Wno-unused -Wno-format -fno-common -ffreestanding -fno-builtin -static \
+	-Wno-unaligned-access -fdce -Wall -Werror -Wno-uninitialized -Wno-strict-aliasing -fdiagnostics-show-option \
+	-mapcs -marm -mfpu=neon -ftree-vectorize -fno-math-errno -funsafe-math-optimizations -fno-signed-zeros -mfloat-abi=softfp \
+	-fno-omit-frame-pointer -fno-stack-protector -fno-pie 
+
+# cflags = -std=c11 -march=armv7-a -mtune=cortex-a9 -nostdlib -nodefaultlibs -mfloat-abi=soft -fno-pic \
+# 	-static -fno-builtin -fno-strict-aliasing -Wall -ggdb -Wno-unused -Werror -fno-omit-frame-pointer -fno-stack-protector -fno-pie 
+
+c_useropts = -O0
+
+INC_DIR = 	-I$(KERNEL_ROOT)/services/app \
+		  	-I$(KERNEL_ROOT)/services/boards/$(BOARD) \
+			-I$(KERNEL_ROOT)/services/lib/serial \
+			-I$(KERNEL_ROOT)/services/drivers/rk-3568/include \
+			-I$(KERNEL_ROOT)/services/lib/usyscall \
+		  	-I$(KERNEL_ROOT)/services/lib/ipc \
+		  	-I$(KERNEL_ROOT)/services/lib/memory 
+
+
+all: gmac.o gmac_3568.o test_gmac.o hal_base.o hal_bsp.o hal_pinctrl_v2.o hal_cru.o hal_cache.o hal_gpio.o hal_timer.o hal_cru_rk3568.o
+	@mv $^ $(KERNEL_ROOT)/services/app
+
+%.o: %.c
+	@echo "cc $^"
+	@${cc} ${cflags} ${c_useropts} ${INC_DIR} -o $@ -c $^

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/gmac_3568.c

@@ -0,0 +1,199 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include "hal_base.h"
+#include "hal_gmac.h"
+#include "hal_debug.h"
+#include "hal_cru.h"
+
+/** @addtogroup RK_HAL_Driver
+ *  @{
+ */
+
+/** @addtogroup GMAC
+ *  @{
+ */
+
+/** @defgroup GMAC_Private_Definition Private Definition
+ *  @{
+ */
+/********************* Private MACRO Definition ******************************/
+
+#define HIWORD_UPDATE(val, mask, shift) \
+        ((val) << (shift) | (mask) << ((shift) + 16))
+
+#define GRF_BIT(nr)     (1 << (nr) | 1 << (nr+16))
+#define GRF_CLR_BIT(nr) (1 << (nr+16))
+
+#define DELAY_ENABLE(soc, tx, rx)                                          \
+    (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
+     ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
+
+#define RK3568_GRF_GMAC0_CON0 0X0380
+#define RK3568_GRF_GMAC0_CON1 0X0384
+#define RK3568_GRF_GMAC1_CON0 0X0388
+#define RK3568_GRF_GMAC1_CON1 0X038c
+
+/* RK3568_GRF_GMAC0_CON1 && RK3568_GRF_GMAC1_CON1 */
+#define RK3568_GMAC_GMII_MODE GRF_BIT(7)
+#define RK3568_GMAC_PHY_INTF_SEL_RGMII \
+        (GRF_BIT(4) | GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
+#define RK3568_GMAC_PHY_INTF_SEL_RMII \
+        (GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
+#define RK3568_GMAC_FLOW_CTRL         GRF_BIT(3)
+#define RK3568_GMAC_FLOW_CTRL_CLR     GRF_CLR_BIT(3)
+#define RK3568_GMAC_RXCLK_DLY_ENABLE  GRF_BIT(1)
+#define RK3568_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
+#define RK3568_GMAC_TXCLK_DLY_ENABLE  GRF_BIT(0)
+#define RK3568_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
+
+/* RK3568_GRF_GMAC0_CON0 && RK3568_GRF_GMAC1_CON0 */
+#define RK3568_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
+#define RK3568_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+
+/********************* Private Structure Definition **************************/
+
+/********************* Private Variable Definition ***************************/
+
+/********************* Private Function Definition ***************************/
+
+/** @} */
+/********************* Public Function Definition ****************************/
+
+/** @defgroup GMAC_Exported_Functions_Group5 Other Functions
+ *  @{
+ */
+
+/**
+ * @brief  Set RGMII Mode.
+ * @param  pGMAC: pointer to a GMAC_HANDLE structure that contains
+ *                the information for GMAC module.
+ * @param  txDelay: RGMII tx delayline
+ * @param  rxDelay: RGMII rx delayline
+ */
+void HAL_GMAC_SetToRGMII(struct GMAC_HANDLE *pGMAC,
+                         int32_t txDelay, int32_t rxDelay)
+{
+    uint32_t *con0, *con1;
+
+    con0 = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(GRF->MAC1_CON0) :
+                                                 &(GRF->MAC0_CON0));
+    con1 = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(GRF->MAC1_CON1) :
+                                                 &(GRF->MAC0_CON1));
+
+    WRITE_REG(*con1,
+              RK3568_GMAC_PHY_INTF_SEL_RGMII |
+              RK3568_GMAC_RXCLK_DLY_ENABLE |
+              RK3568_GMAC_TXCLK_DLY_ENABLE);
+
+    WRITE_REG(*con0,
+              RK3568_GMAC_CLK_RX_DL_CFG(rxDelay) |
+              RK3568_GMAC_CLK_TX_DL_CFG(txDelay));
+}
+
+/**
+ * @brief  Set RMII Mode.
+ * @param  pGMAC: pointer to a GMAC_HANDLE structure that contains
+ *                the information for GMAC module.
+ */
+void HAL_GMAC_SetToRMII(struct GMAC_HANDLE *pGMAC)
+{
+    uint32_t *con1, *cruCon, val;
+
+    con1 = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(GRF->MAC1_CON1) :
+                                                 &(GRF->MAC0_CON1));
+
+    WRITE_REG(*con1, RK3568_GMAC_PHY_INTF_SEL_RMII);
+
+    cruCon = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(CRU->CRU_CLKSEL_CON[33]) :
+                                                   &(CRU->CRU_CLKSEL_CON[31]));
+    /* RMII mode */
+    val = HIWORD_UPDATE(0x1, 0x3, 0);
+    /* clock from io if it was */
+    /* val |= HIWORD_UPDATE(0x1, 0x1, 2);  */
+    /* ref clock sel 50M */
+    val |= HIWORD_UPDATE(0x1, 0x3, 8);
+    /* clock speed 25M */
+    val |= HIWORD_UPDATE(0x1, 0x1, 3);
+    WRITE_REG(*cruCon, val);
+}
+
+/**
+ * @brief  Set external clock source select.
+ * @param  pGMAC: pointer to a GMAC_HANDLE structure that contains
+ *                the information for GMAC module.
+ * @param  extClk: 0: select clk_mac as the clock of mac
+ *                 1: select external phy clock as the clock of mac
+ */
+void HAL_GMAC_SetExtclkSrc(struct GMAC_HANDLE *pGMAC, bool extClk)
+{
+    uint32_t *cruCon, val;
+    uint32_t clksel = 0;
+
+    cruCon = (uint32_t *)((pGMAC->pReg == GMAC1) ? &(CRU->CRU_CLKSEL_CON[33]) :
+                                                   &(CRU->CRU_CLKSEL_CON[31]));
+
+    if (extClk) {
+        clksel = 1;
+    }
+
+    val = HIWORD_UPDATE(clksel, 0x1, 2);
+    WRITE_REG(*cruCon, val);
+}
+
+/**
+ * @brief  Set RGMII speed.
+ * @param  pGMAC: pointer to a GMAC_HANDLE structure that contains
+ *                the information for GMAC module.
+ * @param  speed: RGMII speed 10/100/1000
+ */
+void HAL_GMAC_SetRGMIISpeed(struct GMAC_HANDLE *pGMAC, int32_t speed)
+{
+    eCLOCK_Name clkID;
+    uint32_t rate;
+    int32_t ret;
+
+    switch (speed) {
+    case 10:
+        rate = 2500000;
+        break;
+    case 100:
+        rate = 25000000;
+        break;
+    case 1000:
+        rate = 125000000;
+        break;
+    default:
+        HAL_DBG_ERR("unknown speed value for GMAC speed=%ld", speed);
+
+        return;
+    }
+
+    if (pGMAC->phyStatus.interface == PHY_INTERFACE_MODE_RMII) {
+        clkID = (pGMAC->pReg == GMAC1) ? SCLK_GMAC1_RMII_SPEED :
+                                         SCLK_GMAC0_RMII_SPEED;
+    } else {
+        clkID = (pGMAC->pReg == GMAC1) ? SCLK_GMAC1_RGMII_SPEED :
+                                         SCLK_GMAC0_RGMII_SPEED;
+    }
+
+    ret = HAL_CRU_ClkSetFreq(clkID, rate);
+    if (ret) {
+        HAL_DBG_ERR("%s: set clk_mac_speed rate %ld failed %ld\n",
+                    __func__, rate, ret);
+    }
+}
+
+/**
+ * @brief  Set RGMII speed.
+ * @param  pGMAC: pointer to a GMAC_HANDLE structure that contains
+ *                the information for GMAC module.
+ * @param  speed: RGMII speed 10/100
+ */
+void HAL_GMAC_SetRMIISpeed(struct GMAC_HANDLE *pGMAC, int32_t speed)
+{
+    HAL_GMAC_SetRGMIISpeed(pGMAC, speed);
+}
+

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_base.c

@@ -0,0 +1,333 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include "hal_base.h"
+#include "hal_def.h"
+#include "hal_bsp.h"
+#include "hal_timer.h"
+/** @addtogroup RK_HAL_Driver
+ *  @{
+ */
+
+/** @addtogroup HAL_BASE
+ *  @{
+ */
+
+/** @defgroup HAL_BASE_How_To_Use How To Use
+ *  @{
+
+ HAL system support is including delay system, HAL tick system and global system clock,
+
+ HAL system tick setting:
+
+ - Attach HAL_IncTick() to system tick interrupt handler;
+ - Notify the HAL system the system's tick frequency by calling HAL_SetTickFreq() unless
+    it is the same as default value HAL_TICK_FREQ_1KHZ;
+ - If you need a more accurate delay system, specify SYS_TIMER in hal_conf.h.
+
+ Init HAL system:
+
+ - Initialize the HAL system by calling HAL_Init():
+
+ Reset when SOC system is changed:
+
+ - Update system with new core clock and new SysTick clock source by calling HAL_SystemCoreClockUpdate();
+
+ APIs:
+
+ - Get system time by calling HAL_GetTick().
+ - Delay for a certain length of time, HAL_DelayMs(), HAL_DelayUs(), and HAL_CPUDelayUs().
+ - Blocking for a certain period of time to continuously query HW status, use HAL_GetTick()
+ to do timeout, this will be more accurate.
+ - Get current cpu usage by calling HAL_GetCPUUsage().
+
+ @} */
+
+/** @defgroup HAL_BASE_Private_Definition Private Definition
+ *  @{
+ */
+/********************* Private MACRO Definition ******************************/
+
+#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ
+#define  SYSTEM_CLOCK  816000000U
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = SYSTEM_CLOCK;
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+{
+    SystemCoreClock = SYSTEM_CLOCK;
+}
+/********************* Private Structure Definition **************************/
+
+/********************* Private Variable Definition ***************************/
+
+static __IO uint32_t uwTick;
+static eHAL_tickFreq uwTickFreq = HAL_TICK_FREQ_DEFAULT;
+
+/********************* Private Function Definition ***************************/
+
+static void CPUCycleLoop(uint32_t cycles)
+{
+    __asm volatile (
+        "mov  r0, %0\n\t"
+        "adds r0, r0, #2\n\t"   //    1    2    Round to the nearest multiple of 4.
+        "lsrs r0, r0, #2\n\t"   //    1    2    Divide by 4 and set flags.
+        "beq  2f\n\t"           //    2    2    Skip if 0.
+        ".align 4\n\t"
+        "1:\n\t"
+        "adds r0, r0, #1\n\t"   //    1    2    Increment the counter.
+        "subs r0, r0, #2\n\t"   //    1    2    Decrement the counter by 2.
+        "bne  1b\n\t"           //   (1)2  2    2 CPU cycles (if branch is taken).
+        "nop\n\t"               //    1    2    Loop alignment padding.
+        "2:"
+        : : "r" (cycles)
+        );
+}
+
+static inline HAL_Status TimerDelayUs(uint32_t us)
+{
+    uint64_t count, from, now, pass;
+
+    from = HAL_TIMER_GetCount(SYS_TIMER);
+    count = PLL_INPUT_OSC_RATE / 1000000 * us;
+
+    do {
+        now = HAL_TIMER_GetCount(SYS_TIMER);
+        pass = now > from ? now - from : from - now;
+    } while (pass < count);
+
+    return HAL_OK;
+}
+
+
+/** @} */
+/********************* Public Function Definition ***************************/
+/** @defgroup HAL_BASE_Exported_Functions_Group4 Init and DeInit Functions
+
+ This section provides functions allowing to init and deinit the module:
+
+ *  @{
+ */
+
+/**
+ * @brief  Init HAL driver basic code.
+ * @return HAL_OK.
+ */
+
+/**
+ * @brief  HAL system update with new core clock and systick clock source.
+ * @param  hz: new core clock.
+ * @param  clkSource: new systick clock source.
+ * @return HAL_OK.
+ */
+HAL_Status HAL_SystemCoreClockUpdate(uint32_t hz, eHAL_systickClkSource clkSource)
+{
+    uint32_t rate = hz;
+    HAL_Status ret = HAL_OK;
+
+#if defined(__CORTEX_M) && defined(HAL_SYSTICK_MODULE_ENABLED)
+    ret = HAL_SYSTICK_CLKSourceConfig(clkSource);
+    if (ret == HAL_OK && clkSource == HAL_SYSTICK_CLKSRC_EXT) {
+        rate = PLL_INPUT_OSC_RATE;
+    }
+    HAL_SYSTICK_Config(rate / (1000 / HAL_GetTickFreq()));
+    ret = HAL_OK;
+#endif
+
+    if (ret == HAL_OK) {
+        SystemCoreClock = rate;   /* Update global SystemCoreClock */
+    }
+
+    return ret;
+}
+
+
+
+/** @} */
+
+/** @defgroup HAL_BASE_Exported_Functions_Group5 Other Functions
+ *  @{
+ */
+
+/**
+ * @brief  Count plus tickFreq when interrupt occurs.
+ * @return HAL_Status: HAL_OK.
+ */
+HAL_Status HAL_IncTick(void)
+{
+    uwTick += uwTickFreq;
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Provides tick value in millisecond.
+ * @return uint32_t: tick value in millisecond.
+ * @attention this API allow direct use in the HAL layer.
+ */
+uint32_t HAL_GetTick(void)
+{
+
+    uint64_t tick = HAL_TIMER_GetCount(SYS_TIMER);
+    uint32_t base = PLL_INPUT_OSC_RATE / 1000;
+
+    if (tick >> 62) {
+        tick = ~tick;
+    }
+
+    return (uint32_t)HAL_DivU64(tick, base);
+
+
+}
+
+/**
+ * @brief  Provides system timer count.
+ * @return uint64_t: timer count.
+ * @attention this API allow direct use in the HAL layer.
+ */
+uint64_t HAL_GetSysTimerCount(void)
+{
+
+    uint64_t count = HAL_TIMER_GetCount(SYS_TIMER);
+    if (count >> 62) {
+        count = ~count;
+    }
+
+    return count;
+
+
+}
+
+/**
+  * @brief Set new tick frequency.
+  * @return HAL_Status.
+  */
+HAL_Status HAL_SetTickFreq(eHAL_tickFreq freq)
+{
+    // HAL_ASSERT(IS_TICKFREQ(freq));
+
+    uwTickFreq = freq;
+
+    return HAL_OK;
+}
+
+/**
+  * @brief Return tick frequency.
+  * @return uint32_t: tick period in Hz.
+  * @attention this API allow direct use in the HAL layer.
+  */
+eHAL_tickFreq HAL_GetTickFreq(void)
+{
+    return uwTickFreq;
+}
+
+/**
+ * @brief  SysTick mdelay.
+ * @param  ms: mdelay count.
+ * @return HAL_Status: HAL_OK.
+ * @attention this API allow direct use in the HAL layer. Blocking for a
+ *  certain period of time to continuously query HW status, use HAL_GetTick
+ *  to do timeout, that will be more accurate.
+ */
+__attribute__((weak)) HAL_Status HAL_DelayMs(uint32_t ms)
+{
+    for (uint32_t i = 0; i < ms; i++) {
+        HAL_DelayUs(1000);
+    }
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  SysTick udelay.
+ * @param  us: udelay count.
+ * @return HAL_Status: HAL_OK.
+ * @attention this API allow direct use in the HAL layer. The longer the delay,
+ *  the more accurate. Actual delay is greater than the parameter.
+ */
+HAL_Status HAL_DelayUs(uint32_t us)
+{
+#if defined(SYS_TIMER) && defined(HAL_TIMER_MODULE_ENABLED)
+
+    return TimerDelayUs(us);
+#else
+
+    return HAL_CPUDelayUs(us);
+#endif
+}
+
+/**
+ * @brief  CPU loop udelay.
+ * @param  us: udelay count.
+ * @return HAL_Status: HAL_OK.
+ * @attention this API allow direct use in the HAL layer. The longer the delay,
+ *  the more accurate. Actual delay is greater than the parameter.
+ *  During delay, CPU rate change result in delay imprecise, so call it in
+ *  following case:
+ *    1.IRQ disable
+ *    2.CRU code
+ */
+HAL_Status HAL_CPUDelayUs(uint32_t us)
+{
+    volatile uint32_t cycles;
+
+#if (__CORTEX_M == 0)
+    cycles = (uint32_t)HAL_DivU64((uint64_t)SystemCoreClock, 1000000) * us; /* Add few cycles penalty */
+#else
+    cycles = SystemCoreClock / 1000000 * us; /* Add few cycles penalty */
+#endif
+
+    CPUCycleLoop(cycles);
+
+    return HAL_OK;
+}
+
+uint64_t HAL_DivU64Rem(uint64_t numerator, uint32_t denominator, uint32_t *pRemainder)
+{
+    uint64_t remainder = numerator;
+    uint64_t b = denominator;
+    uint64_t result;
+    uint64_t d = 1;
+    uint32_t high = numerator >> 32;
+
+    result = 0;
+    if (high >= denominator) {
+        high /= denominator;
+        result = (uint64_t)high << 32;
+        remainder -= (uint64_t)(high * denominator) << 32;
+    }
+
+    while ((int64_t)b > 0 && b < remainder) {
+        b = b + b;
+        d = d + d;
+    }
+
+    do {
+        if (remainder >= b) {
+            remainder -= b;
+            result += d;
+        }
+        b >>= 1;
+        d >>= 1;
+    } while (d);
+
+    if (pRemainder) {
+        *pRemainder = remainder;
+    }
+
+    return result;
+}
+
+/** @} */
+
+/** @} */
+
+/** @} */

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_bsp.c

@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include "hal_bsp.h"
+#include "rk3568.h"
+#include "soc.h"
+#include "hal_gmac.h"
+
+const struct HAL_GMAC_DEV g_gmac0Dev =
+{
+    .pReg = GMAC0,
+    .clkID = CLK_MAC0_2TOP,
+    .clkGateID = CLK_MAC0_2TOP_GATE,
+    .pclkID = PCLK_PHP,
+    .pclkGateID = PCLK_GMAC0_GATE,
+    .irqNum = GMAC0_IRQn,
+};
+
+const struct HAL_GMAC_DEV g_gmac1Dev =
+{
+    .pReg = GMAC1,
+    .clkID = CLK_MAC1_2TOP,
+    .clkGateID = CLK_MAC1_2TOP_GATE,
+    .pclkID = PCLK_USB,
+    .pclkGateID = PCLK_GMAC1_GATE,
+    .irqNum = GMAC1_IRQn,
+};
+
+void BSP_Init(void)
+{
+}

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_debug.c

@@ -0,0 +1,228 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ */
+
+/** @addtogroup RK_HAL_Driver
+ *  @{
+ */
+
+/** @addtogroup DEBUG
+ *  @{
+ */
+
+/** @defgroup DEBUG_How_To_Use How To Use
+ *  @{
+
+ The DEBUG driver can be used as follows:
+
+ Implement DBG hook:
+
+ - printf func: define new HAL_SYSLOG in hal_conf.h or use HAL_DBG_Printf() in default;
+ - assert func: redefine AssertFailed().
+
+ Define debug level in hal_conf.h:
+
+ - HAL_DBG_ON: print master switch;
+ - HAL_DBG_INFO_ON: information printing switch;
+ - HAL_DBG_WRN_ON: information printing switch;
+ - HAL_DBG_ERR_ON: information printing switch;
+ - HAL_ASSERT_ON: Support assert.
+
+ APIS:
+
+ - printf information by calling HAL_DBG();
+ - printf warning by calling HAL_DBG_WRN();
+ - printf error by calling HAL_DBG_ERR();
+ - do assert by calling HAL_ASSERT().
+
+ @} */
+
+#include "hal_base.h"
+#include "hal_debug.h"
+
+/** @defgroup DEBUG_Private_Definition Private Definition
+ *  @{
+ */
+/********************* Private MACRO Definition ******************************/
+
+/********************* Private Structure Definition **************************/
+
+/********************* Private Variable Definition ***************************/
+
+/********************* Private Function Definition ***************************/
+
+/** @} */
+/********************* Public Function Definition ****************************/
+
+/** @defgroup DEBUG_Exported_Functions_Group5 Other Functions
+
+ This section provides functions allowing to init and deinit module as follows:
+
+ *  @{
+ */
+
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the HAL_ASSERT error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: HAL_ASSERT error line source number
+  */
+ __attribute__((weak)) void HAL_AssertFailed(const char *file, uint32_t line)
+{
+    HAL_DBG_ERR("assert failed at %s %lu\n", file, line);
+    while (1) {
+        ;
+    }
+}
+
+/**
+ * @brief  format hex print.
+ * @param  s: head tag for every new line.
+ * @param  buf: buffer for printing.
+ * @param  width: every single printed object width.
+ * @param  len: the number of printed objects.
+ * @return HAL_Status: HAL_OK.
+ * sum = width * len (BYTE).
+ */
+HAL_Status HAL_DBG_HEX(char *s, void *buf, uint32_t width, uint32_t len)
+{
+#ifdef HAL_DBG_ON
+    uint32_t i, j;
+    unsigned char *p8 = (unsigned char *)buf;
+    unsigned short *p16 = (unsigned short *)buf;
+    uint32_t *p32 = (uint32_t *)buf;
+
+    j = 0;
+    for (i = 0; i < len; i++) {
+        if (j == 0) {
+            HAL_SYSLOG("[HAL_DBG_HEX] %s %p + 0x%lx:", s, buf, i * width);
+        }
+
+        if (width == 4) {
+            HAL_SYSLOG("0x%08lx,", p32[i]);
+        } else if (width == 2) {
+            HAL_SYSLOG("0x%04x,", p16[i]);
+        } else {
+            HAL_SYSLOG("0x%02x,", p8[i]);
+        }
+
+        if (++j >= 16) {
+            j = 0;
+            HAL_SYSLOG("\n");
+        }
+    }
+    HAL_SYSLOG("\n");
+#endif
+
+    return HAL_OK;
+}
+
+#ifdef HAL_DBG_USING_HAL_PRINTF
+static void reverse(char *start, char *end)
+{
+    while (start < end) {
+        char temp = *start;
+        *start = *end;
+        *end = temp;
+        start++;
+        end--;
+    }
+}
+
+#ifdef __GNUC__
+extern int _write(int fd, char *ptr, int len);
+#endif
+
+/**
+ * @brief  format and print data
+ * @param  format: format printf param. only support: \%d, \%s, \%ld, \%lld
+ * @return int32_t.
+ */
+ __attribute__((weak)) int32_t HAL_DBG_Printf(const char *format, ...)
+{
+    static char g_printf_buf[HAL_PRINTF_BUF_SIZE];
+    char *str = g_printf_buf;
+    int32_t len = 0;
+    va_list args;
+
+    va_start(args, format);
+
+    while (*format != '\0') {
+        if (*format == '%') {
+            format++;
+            if (*format == 'd') {
+                int i = va_arg(args, int);
+                char *start = str;
+                do {
+                    *str++ = '0' + (i % 10);
+                    i /= 10;
+                } while (i > 0);
+                reverse(start, str - 1);
+            } else if (*format == 's') {
+                char *s = va_arg(args, char *);
+                while (*s) {
+                    *str++ = *s++;
+                }
+            } else if (*format == 'l') {
+                format++;
+                if (*format == 'd') {
+                    long i = va_arg(args, long);
+                    char *start = str;
+                    do {
+                        *str++ = '0' + (i % 10);
+                        i /= 10;
+                    } while (i > 0);
+                    reverse(start, str - 1);
+                } else if (*format == 'l') {
+                    format++;
+                    if (*format == 'd') {
+                        long long int i = va_arg(args, long long int);
+                        char *start = str;
+                        do {
+                            *str++ = '0' + (i % 10);
+                            i /= 10;
+                        } while (i > 0);
+                        reverse(start, str - 1);
+                    }
+                }
+            }
+        } else {
+            *str++ = *format;
+        }
+        format++;
+    }
+
+    *str = '\0';
+
+    va_end(args);
+    len = str - g_printf_buf;
+
+#ifdef __GNUC__
+
+    return _write(2, g_printf_buf, len);
+#else
+    for (int i = 0; i < len; i++) {
+        fputc(g_printf_buf[i], stdout);
+    }
+
+    return len;
+#endif
+}
+#else
+/**
+ * @brief  format and print data
+ * @param  format: format printf param.
+ * @return int32_t.
+ */
+ __attribute__((weak)) int32_t HAL_DBG_Printf(const char *format, ...)
+{
+    return 0;
+}
+#endif /* HAL_DBG_USING_HAL_PRINTF */
+
+/** @} */
+
+/** @} */
+
+/** @} */

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_gpio.c

@@ -0,0 +1,577 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include "hal_base.h"
+#include "hal_pinctrl.h"
+#include "hal_gpio.h"
+
+/** @addtogroup RK_HAL_Driver
+ *  @{
+ */
+
+/** @addtogroup GPIO
+ *  @{
+ */
+
+/** @defgroup GPIO_How_To_Use How To Use
+ *  @{
+
+ The GPIO driver can be used as follows:
+
+ APIs for GPIO io read write:
+
+   1. HAL_GPIO_GetPinLevel() to get EXT port level.
+   2. HAL_GPIO_SetPinLevel() to set io level.
+   3. HAL_GPIO_SetPinDirection() to set io direction.
+
+ APIs for GPIO IRQ:
+
+   1. HAL_GPIO_EnableIRQ() to enable a GPIO IRQ.
+   2. HAL_GPIO_DisableIRQ() to disable a GPIO IRQ.
+   3. HAL_GPIO_IRQHandler() to handle GPIO IRQ isr.
+   4. HAL_GPIO_IRQDispatch() to dispatch GPIO IRQ, should be implemented by User.
+
+ Please open the macro definition HAL_GPIO_VIRTUAL_MODEL_FEATURE_ENABLED to support
+
+ APIs for GPIO virtual model:
+
+   1. HAL_GPIO_EnableVirtualModel() to enable a GPIO virtual model.
+   2. HAL_GPIO_DisableVirtualModel() to disable a GPIO virtual model.
+   3. HAL_GPIO_SetVirtualModel() to configure GPIO pins virtual model.
+
+ @} */
+
+/** @defgroup GPIO_Private_Definition Private Definition
+ *  @{
+ */
+/********************* Private MACRO Definition ******************************/
+#define UNUSED(X) (void)(X)      /* To avoid gcc/g++ warnings */
+
+/********************* Private Function Definition ***************************/
+
+/**
+ * @brief  Set the GPIO IRQ end of interrupt(EOI).
+ * @param  pGPIO: The pointer of GPIO struct.
+ * @param  pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
+ */
+static void GPIO_SetEOI(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
+{
+#if (GPIO_VER_ID == 0x01000C2BU)
+    if (IS_GPIO_HIGH_PIN(pin)) {
+        pin &= 0xFFFF0000;
+        pGPIO->PORT_EOI_H = pin | (pin >> 16);
+    } else {
+        pin &= 0x0000FFFF;
+        pGPIO->PORT_EOI_L = pin | (pin << 16);
+    }
+#else
+    {
+        pGPIO->PORTA_EOI = pin;
+    }
+#endif
+}
+
+/**
+ * @brief  Get GPIO all pins irq type.
+ * @param  pGPIO: the GPIO struct.
+ * @return uint32_t: type value.
+ */
+static uint32_t GPIO_GetIntType(struct GPIO_REG *pGPIO)
+{
+    uint32_t type;
+
+#if (GPIO_VER_ID == 0x01000C2BU)
+    type = (pGPIO->INT_TYPE_L & 0xffff);
+    type |= ((pGPIO->INT_TYPE_H & 0xffff) << 16);
+    type |= (pGPIO->INT_BOTHEDGE_L & 0xffff);
+    type |= ((pGPIO->INT_BOTHEDGE_H & 0xffff) << 16);
+#else
+    type = pGPIO->INTTYPE_LEVEL;
+    #ifdef GPIO_INT_BOTHEDGE_OFFSET
+    type |= pGPIO->INT_BOTHEDGE;
+    #endif
+#endif
+
+    return type;
+}
+
+/**
+ * @brief  Get GPIO all pins irq status.
+ * @param  pGPIO: the GPIO struct.
+ * @return uint32_t: status value.
+ */
+static uint32_t GPIO_GetIntStatus(struct GPIO_REG *pGPIO)
+{
+    return pGPIO->INT_STATUS;
+}
+
+/** @} */
+/********************* Public Function Definition ***************************/
+
+/** @defgroup GPIO_Exported_Functions_Group1 State and Errors Functions
+
+ This section provides functions allowing to get the status of the module:
+
+ *  @{
+ */
+
+/**
+ * @brief  GPIO Configure IRQ trigger type.
+ * @param  pGPIO: The pointer of GPIO struct.
+ * @param  pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
+ * @param  mode: The value defined in @ref eGPIO_intType.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_GPIO_SetIntType(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_intType mode)
+{
+    uint32_t both = 0, type = 0, plar = 0;
+
+    UNUSED(both);
+
+    switch (mode) {
+    case GPIO_INT_TYPE_EDGE_RISING:
+        type = 1;
+        plar = 1;
+        both = 0;
+        break;
+    case GPIO_INT_TYPE_EDGE_FALLING:
+        type = 1;
+        plar = 0;
+        both = 0;
+        break;
+    case GPIO_INT_TYPE_LEVEL_HIGH:
+        type = 0;
+        plar = 1;
+        both = 0;
+        break;
+    case GPIO_INT_TYPE_LEVEL_LOW:
+        type = 0;
+        plar = 0;
+        both = 0;
+        break;
+    case GPIO_INT_TYPE_EDGE_BOTH:
+        type = 0;
+        plar = 0;
+        both = 1;
+        break;
+    default:
+
+        return HAL_INVAL;
+    }
+
+#if (GPIO_VER_ID == 0x01000C2BU)
+    if (IS_GPIO_HIGH_PIN(pin)) {
+        pin &= 0xFFFF0000;
+        pGPIO->INT_TYPE_H = (type) ? (pin | (pin >> 16)) : (pin);
+        pGPIO->INT_POLARITY_H = (plar) ? (pin | (pin >> 16)) : (pin);
+        pGPIO->INT_BOTHEDGE_H = (both) ? (pin | (pin >> 16)) : (pin);
+    } else {
+        pin &= 0x0000FFFF;
+        pGPIO->INT_TYPE_L = (type) ? (pin | (pin << 16)) : (pin << 16);
+        pGPIO->INT_POLARITY_L = (plar) ? (pin | (pin << 16)) : (pin << 16);
+        pGPIO->INT_BOTHEDGE_L = (both) ? (pin | (pin << 16)) : (pin << 16);
+    }
+#else
+    {
+        pGPIO->INTTYPE_LEVEL = (type) ? (pin) : (pGPIO->INTTYPE_LEVEL & ~(pin));
+        pGPIO->INT_POLARITY = (plar) ? (pin) : (pGPIO->INT_POLARITY & ~(pin));
+        #ifdef GPIO_INT_BOTHEDGE_OFFSET
+        pGPIO->INT_BOTHEDGE = (both) ? (pin) : (pGPIO->INT_BOTHEDGE & ~(pin));
+        #endif
+    }
+#endif
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Set GPIO direction.
+ * @param  pGPIO: the GPIO struct.
+ * @param  pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
+ * @param  direction: direction value defined in @ref eGPIO_pinDirection.
+ * @return HAL_Status: HAL_OK if success.
+ */
+HAL_Status HAL_GPIO_SetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinDirection direction)
+{
+#if (GPIO_VER_ID == 0x01000C2BU)
+    if (IS_GPIO_HIGH_PIN(pin)) {
+        pin &= 0xFFFF0000;
+        pGPIO->SWPORT_DDR_H = (direction == GPIO_OUT) ? (pin | (pin >> 16)) : (pin);
+    } else {
+        pin &= 0x0000FFFF;
+        pGPIO->SWPORT_DDR_L = (direction == GPIO_OUT) ? (pin | (pin << 16)) : (pin << 16);
+    }
+#else
+    if (direction == GPIO_OUT) {
+        pGPIO->SWPORTA_DDR |= pin;
+    } else {
+        pGPIO->SWPORTA_DDR &= ~pin;
+    }
+#endif
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Set GPIO direction.
+ * @param  pGPIO: the GPIO struct.
+ * @param  mPins: The pins defined in @ref ePINCTRL_GPIO_PINS.
+ * @param  direction: value defined in @ref eGPIO_pinDirection.
+ * @return HAL_Status: HAL_OK if success.
+ */
+HAL_Status HAL_GPIO_SetPinsDirection(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinDirection direction)
+{
+    uint8_t pin;
+    HAL_Status rc;
+
+    HAL_ASSERT(IS_GPIO_INSTANCE(pGPIO));
+
+    for (pin = 0; pin < 32; pin++) {
+        if (mPins & (1 << pin)) {
+            rc = HAL_GPIO_SetPinDirection(pGPIO, (1 << pin), direction);
+            if (rc) {
+                return rc;
+            }
+        }
+    }
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Get GPIO Pin data direction value.
+ * @param  pGPIO: the GPIO struct.
+ * @param  pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
+ * @retval eGPIO_pinDirection: data direction value.
+ */
+eGPIO_pinDirection HAL_GPIO_GetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
+{
+    eGPIO_pinDirection direction;
+    uint32_t value;
+
+#if (GPIO_VER_ID == 0x01000C2BU)
+    value = IS_GPIO_HIGH_PIN(pin) ? (pGPIO->SWPORT_DDR_H & (pin >> 16)) : (pGPIO->SWPORT_DDR_L & pin);
+#else
+    value = pGPIO->SWPORTA_DDR & pin;
+#endif
+
+    if (value != (uint32_t)GPIO_IN) {
+        direction = GPIO_OUT;
+    } else {
+        direction = GPIO_IN;
+    }
+
+    return direction;
+}
+
+/**
+ * @brief  Set GPIO pin level.
+ * @param  pGPIO: The pointer of GPIO struct.
+ * @param  pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
+ * @param  level: The level defined in @ref eGPIO_pinLevel.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_GPIO_SetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinLevel level)
+{
+#if (GPIO_VER_ID == 0x01000C2BU)
+    if (IS_GPIO_HIGH_PIN(pin)) {
+        pin &= 0xFFFF0000;
+        pGPIO->SWPORT_DR_H = (level == GPIO_HIGH) ? (pin | (pin >> 16)) : (pin);
+    } else {
+        pin &= 0x0000FFFF;
+        pGPIO->SWPORT_DR_L = (level == GPIO_HIGH) ? (pin | (pin << 16)) : (pin << 16);
+    }
+#else
+    if (level == GPIO_HIGH) {
+        pGPIO->SWPORTA_DR |= pin;
+    } else {
+        pGPIO->SWPORTA_DR &= ~pin;
+    }
+#endif
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Set GPIO pin level.
+ * @param  pGPIO: The pointer of GPIO struct.
+ * @param  mPins: The pins defined in @ref ePINCTRL_GPIO_PINS.
+ * @param  level: The level defined in @ref eGPIO_pinLevel.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_GPIO_SetPinsLevel(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinLevel level)
+{
+    uint8_t pin;
+    HAL_Status rc;
+
+    HAL_ASSERT(IS_GPIO_INSTANCE(pGPIO));
+
+    for (pin = 0; pin < 32; pin++) {
+        if (mPins & (1 << pin)) {
+            rc = HAL_GPIO_SetPinLevel(pGPIO, (1 << pin), level);
+            if (rc) {
+                return rc;
+            }
+        }
+    }
+
+    return HAL_OK;
+}
+
+/** @} */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO Functions
+
+ This section provides functions allowing to IO controlling:
+
+ *  @{
+ */
+
+/**
+ * @brief  Get GPIO Pin data value.
+ * @param  pGPIO: the GPIO struct.
+ * @param  pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
+ * @retval eGPIO_pinLevel: data value.
+ */
+eGPIO_pinLevel HAL_GPIO_GetPinData(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
+{
+    eGPIO_pinLevel level;
+    uint32_t value;
+
+#if (GPIO_VER_ID == 0x01000C2BU)
+    value = IS_GPIO_HIGH_PIN(pin) ? (pGPIO->SWPORT_DR_H & (pin >> 16)) : (pGPIO->SWPORT_DR_L & pin);
+#else
+    value = pGPIO->SWPORTA_DR & pin;
+#endif
+
+    if (value != (uint32_t)GPIO_LOW) {
+        level = GPIO_HIGH;
+    } else {
+        level = GPIO_LOW;
+    }
+
+    return level;
+}
+
+/**
+ * @brief  Get GPIO Pin ext bank level.
+ * @param  pGPIO: the GPIO struct.
+ * @param  pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
+ * @retval GPIO_PinState: ext bank value.
+ */
+eGPIO_pinLevel HAL_GPIO_GetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
+{
+    uint32_t value;
+
+#if (GPIO_VER_ID == 0x01000C2BU)
+    value = (pGPIO->EXT_PORT & pin);
+#else
+    value = (pGPIO->EXT_PORTA & pin);
+#endif
+
+    return (value == (uint32_t)GPIO_LOW) ? GPIO_LOW : GPIO_HIGH;
+}
+
+/**
+ * @brief  Get GPIO Pin ext bank level.
+ * @param  pGPIO: the GPIO struct.
+ * @retval uint32_t: ext bank value.
+ */
+uint32_t HAL_GPIO_GetBankLevel(struct GPIO_REG *pGPIO)
+{
+    uint32_t value;
+
+#if (GPIO_VER_ID == 0x01000C2BU)
+    value = (pGPIO->EXT_PORT);
+#else
+    value = (pGPIO->EXT_PORTA);
+#endif
+
+    return value;
+}
+/** @} */
+
+/** @defgroup GPIO_Exported_Functions_Group3 Other Functions
+ *  @{
+ */
+
+/**
+ * @brief  Set GPIO irq enable.
+ * @param  pGPIO: The pointer of GPIO struct.
+ * @param  pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
+ */
+void HAL_GPIO_EnableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
+{
+#if (GPIO_VER_ID == 0x01000C2BU)
+    if (IS_GPIO_HIGH_PIN(pin)) {
+        pin &= 0xFFFF0000;
+#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED
+        pGPIO->INT_MASK_H = pin;
+#endif
+        pGPIO->INT_EN_H = pin | (pin >> 16);
+    } else {
+        pin &= 0x0000FFFF;
+#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED
+        pGPIO->INT_MASK_L = pin << 16;
+#endif
+        pGPIO->INT_EN_L = pin | (pin << 16);
+    }
+#else
+    {
+        pGPIO->INTEN |= pin;
+        pGPIO->INTMASK &= ~pin;
+    }
+#endif
+}
+
+/**
+ * @brief  Set GPIO irq disable.
+ * @param  pGPIO: The pointer of GPIO struct.
+ * @param  pin: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
+ */
+void HAL_GPIO_DisableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin)
+{
+#if (GPIO_VER_ID == 0x01000C2BU)
+    if (IS_GPIO_HIGH_PIN(pin)) {
+        pin &= 0xFFFF0000;
+        pGPIO->INT_EN_H = pin;
+#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED
+        pGPIO->INT_MASK_H = pin | (pin >> 16);
+#endif
+    } else {
+        pin &= 0x0000FFFF;
+        pGPIO->INT_EN_L = pin << 16;
+#ifndef HAL_GPIO_IRQ_GROUP_MODULE_ENABLED
+        pGPIO->INT_MASK_L = pin | (pin << 16);
+#endif
+    }
+#else
+    {
+        pGPIO->INTEN &= ~pin;
+        pGPIO->INTMASK |= pin;
+    }
+#endif
+}
+
+/**
+ * @brief  GPIO IRQ callbacks.
+ * @param  bank: The bank id.
+ * @param  pin: The true pin index, 0~31.
+ * NOTE: This function Should not be modified, when the callback is needed,
+ *       the HAL_GPIO_IRQDispatch could be implemented in the user file.
+ */
+__attribute__((weak)) void HAL_GPIO_IRQDispatch(eGPIO_bankId bank, uint32_t pin)
+{
+    UNUSED(bank);
+    UNUSED(pin);
+}
+
+/**
+ * @brief  GPIO IRQ hanlder.
+ * @param  pGPIO: The pointer of GPIO struct.
+ * @param  bank: The bank id.
+ */
+void HAL_GPIO_IRQHandler(struct GPIO_REG *pGPIO, eGPIO_bankId bank)
+{
+    uint32_t stat, type, clear;
+    uint32_t i;
+    uint32_t pin;
+
+    stat = GPIO_GetIntStatus(pGPIO);
+    type = GPIO_GetIntType(pGPIO);
+
+    /* Then process each pending GPIO interrupt */
+    for (i = 0x0U; i < PIN_NUMBER_PER_BANK && stat != 0; i++) {
+        clear = 0x1U << i;
+        pin = HAL_BIT(i);
+
+        if ((stat & clear) != 0x0U) {
+            /* If gpio is Edge-sensitive triggered, clear eoi */
+            if (type & clear) {
+                GPIO_SetEOI(pGPIO, pin);
+            }
+
+            /* Remove the pending interrupt bit from the clear */
+            stat &= ~clear;
+
+            /* And disptach the GPIO interrupt to the handler */
+            HAL_GPIO_IRQDispatch(bank, i);
+        }
+    }
+}
+
+#ifdef HAL_GPIO_VIRTUAL_MODEL_FEATURE_ENABLED
+
+/**
+ * @brief  GPIO virtual model enable.
+ * @param  pGPIO: The pointer of GPIO struct.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_GPIO_EnableVirtualModel(struct GPIO_REG *pGPIO)
+{
+#if (GPIO_VER_ID == 0x01000C2BU)
+    pGPIO->GPIO_VIRTUAL_EN = 0x10001;
+
+    return HAL_OK;
+#endif
+
+    return HAL_ERROR;
+}
+
+/**
+ * @brief  GPIO virtual model disable.
+ * @param  pGPIO: The pointer of GPIO struct.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_GPIO_DisableVirtualModel(struct GPIO_REG *pGPIO)
+{
+#if (GPIO_VER_ID == 0x01000C2BU)
+    pGPIO->GPIO_VIRTUAL_EN = 0x10000;
+
+    return HAL_OK;
+#endif
+
+    return HAL_ERROR;
+}
+
+/**
+ * @brief  GPIO Configure pins for virtual model.
+ * @param  pGPIO: The pointer of GPIO struct.
+ * @param  pins: The pin bit defined in @ref ePINCTRL_GPIO_PINS.
+ * @param  vmode: The value defined in @ref eGPIO_VirtualModel.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_GPIO_SetVirtualModel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_VirtualModel vmodel)
+{
+#if (GPIO_VER_ID == 0x01000C2BU)
+    uint32_t low_pins, high_pins;
+
+    low_pins = pin & 0x0000ffff;
+    high_pins = (pin & 0xffff0000) >> 16;
+
+    /* Support OS_A and OS_B */
+    if (vmodel == GPIO_VIRTUAL_MODEL_OS_B) {
+        pGPIO->GPIO_REG_GROUP_L = low_pins << 16;
+        pGPIO->GPIO_REG_GROUP_H = high_pins << 16;
+    } else {
+        pGPIO->GPIO_REG_GROUP_L = low_pins | (low_pins << 16);
+        pGPIO->GPIO_REG_GROUP_H = high_pins | (high_pins << 16);
+    }
+
+    return HAL_OK;
+#endif
+
+    return HAL_ERROR;
+}
+
+#endif /* HAL_GPIO_VIRTUAL_MODEL_FEATURE_ENABLED */
+
+/** @} */
+
+/** @} */
+
+/** @} */
+
+

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_pinctrl_v2.c

@@ -0,0 +1,565 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include "hal_base.h"
+#include "hal_def.h"
+#include "hal_pinctrl.h"
+
+/** @addtogroup RK_HAL_Driver
+ *  @{
+ */
+
+/** @addtogroup PINCTRL
+ *  @{
+ */
+
+/** @defgroup PINCTRL_How_To_Use How To Use
+ *  @{
+
+ The pinctrl setting registers actually is bus grf registers, which include
+ iomux, drive strength, pull mode, slew rate and schmitt trigger.
+
+ The pinctrl driver provides APIs:
+   - HAL_PINCTRL_SetIOMUX() to set pin iomux
+   - HAL_PINCTRL_SetParam() to set pin iomux/drive/pull/slewrate/schmitt/ie
+
+ Example:
+
+     HAL_PINCTRL_SetIOMUX(GPIO_BANK0,
+                          GPIO_PIN_A0 | // I2S_IN_SCLK
+                          GPIO_PIN_A1 | // I2S_IN_LRCK
+                          GPIO_PIN_A2 | // I2S_IN_SDI0
+                          GPIO_PIN_A3,  // I2S_IN_SDI1
+                          PIN_CONFIG_MUX_FUNC2);
+
+     HAL_PINCTRL_SetParam(GPIO_BANK0,
+                          GPIO_PIN_A0 | // I2S_IN_SCLK
+                          GPIO_PIN_A1 | // I2S_IN_LRCK
+                          GPIO_PIN_A2 | // I2S_IN_SDI0
+                          GPIO_PIN_A3,  // I2S_IN_SDI1
+                          PIN_CONFIG_MUX_FUNC2 |
+                          PIN_CONFIG_PUL_DOWN |
+                          PIN_CONFIG_DRV_LEVEL2 |
+                          PIN_CONFIG_SRT_FAST |
+                          PIN_CONFIG_SMT_ENABLE);
+ @} */
+
+/** @defgroup PINCTRL_Private_Definition Private Definition
+ *  @{
+ */
+/********************* Private MACRO Definition ******************************/
+
+#define _TO_MASK(w)         ((1U << (w)) - 1U)
+#define _TO_OFFSET(p, w)    ((p) * (w))
+#define RK_GEN_VAL(p, v, w) ((_TO_MASK(w) << (_TO_OFFSET(p, w) + 16)) | (((v) & _TO_MASK(w)) << _TO_OFFSET(p, w)))
+
+/*
+ * Use HAL_DBG("pinctrl: write val = 0x%lx to register %p\n", VAL, &REG);
+ * and HAL_DBG("pinctrl: readback register %p = 0x%lx\n", &REG, REG);
+ * for debug
+ */
+#define _PINCTRL_WRITE(REG, DATA) \
+{                                 \
+    REG = DATA;                   \
+}
+
+#if defined(GRF_GPIO0A_IOMUX_OFFSET)
+#define IOMUX_BIT_PER_PIN                 (2)
+#define IOMUX_PIN_PER_REG                 (16 / IOMUX_BIT_PER_PIN)
+#define IOMUX_0(__B, __P)                 (GRF->GPIO##__B##__P##_IOMUX)
+#define SET_IOMUX_0(_B, _P, p, v, w)      _PINCTRL_WRITE(IOMUX_0(_B, _P), RK_GEN_VAL(p, v, w))
+#define RK_SET_IOMUX_0(B, P, p, v)        SET_IOMUX_0(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
+#define SET_IOMUX(_GPIO, _PORT, pin, val) RK_SET_IOMUX_0(_GPIO, _PORT, pin, val)
+
+#elif defined(GRF_GPIO0A_IOMUX_H_OFFSET)
+#define IOMUX_BIT_PER_PIN            (4)
+#define IOMUX_PIN_PER_REG            (16 / IOMUX_BIT_PER_PIN)
+#define IOMUX_0(__B, __P)            (GRF->GPIO##__B##__P##_IOMUX_L)
+#define IOMUX_1(__B, __P)            (GRF->GPIO##__B##__P##_IOMUX_H)
+#define SET_IOMUX_0(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_0(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_IOMUX_1(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_1(_B, _P), RK_GEN_VAL(p, v, w))
+#define RK_SET_IOMUX_0(B, P, p, v)   SET_IOMUX_0(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
+#define RK_SET_IOMUX_1(B, P, p, v)   SET_IOMUX_1(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
+#define SET_IOMUX(_GPIO, _PORT, pin, val)       \
+{                                               \
+    if ((pin % 8) < 4) {                        \
+        RK_SET_IOMUX_0(_GPIO, _PORT, pin, val); \
+    } else {                                    \
+        RK_SET_IOMUX_1(_GPIO, _PORT, pin, val); \
+    }                                           \
+}
+
+#elif defined(GRF_GPIO0A_IOMUX_0_OFFSET)
+#define IOMUX_BIT_PER_PIN            (8)
+#define IOMUX_PIN_PER_REG            (16 / IOMUX_BIT_PER_PIN)
+#define IOMUX_0(__B, __P)            (GRF->GPIO##__B##__P##_IOMUX_0)
+#define IOMUX_1(__B, __P)            (GRF->GPIO##__B##__P##_IOMUX_1)
+#define IOMUX_2(__B, __P)            (GRF->GPIO##__B##__P##_IOMUX_2)
+#define IOMUX_3(__B, __P)            (GRF->GPIO##__B##__P##_IOMUX_3)
+#define SET_IOMUX_0(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_0(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_IOMUX_1(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_1(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_IOMUX_2(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_2(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_IOMUX_3(_B, _P, p, v, w) _PINCTRL_WRITE(IOMUX_3(_B, _P), RK_GEN_VAL(p, v, w))
+#define RK_SET_IOMUX_0(B, P, p, v)   SET_IOMUX_0(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
+#define RK_SET_IOMUX_1(B, P, p, v)   SET_IOMUX_1(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
+#define RK_SET_IOMUX_2(B, P, p, v)   SET_IOMUX_2(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
+#define RK_SET_IOMUX_3(B, P, p, v)   SET_IOMUX_3(B, P, p % IOMUX_PIN_PER_REG, v, IOMUX_BIT_PER_PIN)
+#define SET_IOMUX(_GPIO, _PORT, pin, val)       \
+{                                               \
+    if ((pin % 8) < 2) {                        \
+        RK_SET_IOMUX_0(_GPIO, _PORT, pin, val); \
+    } else if ((pin % 8) < 4) {                 \
+        RK_SET_IOMUX_1(_GPIO, _PORT, pin, val); \
+    } else if ((pin % 8) < 6) {                 \
+        RK_SET_IOMUX_2(_GPIO, _PORT, pin, val); \
+    } else {                                    \
+        RK_SET_IOMUX_3(_GPIO, _PORT, pin, val); \
+    }                                           \
+}
+#endif
+
+#if defined(GRF_GPIO0A_DS_OFFSET)
+#define DS_BIT_PER_PIN                 (2)
+#define DS_PIN_PER_REG                 (16 / DS_BIT_PER_PIN)
+#define DS_0(__B, __P)                 (GRF->GPIO##__B##__P##_DS)
+#define SET_DS_0(_B, _P, p, v, w)      _PINCTRL_WRITE(DS_0(_B, _P), RK_GEN_VAL(p, v, w))
+#define RK_SET_DS_0(B, P, p, v)        SET_DS_0(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
+#define SET_DS(_GPIO, _PORT, pin, val) RK_SET_DS_0(_GPIO, _PORT, pin, val)
+
+#elif defined(GRF_GPIO0A_DS_H_OFFSET)
+#define DS_BIT_PER_PIN            (4)
+#define DS_PIN_PER_REG            (16 / DS_BIT_PER_PIN)
+#define DS_0(__B, __P)            (GRF->GPIO##__B##__P##_DS_L)
+#define DS_1(__B, __P)            (GRF->GPIO##__B##__P##_DS_L)
+#define SET_DS_0(_B, _P, p, v, w) _PINCTRL_WRITE(DS_0(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_DS_1(_B, _P, p, v, w) _PINCTRL_WRITE(DS_1(_B, _P), RK_GEN_VAL(p, v, w))
+#define RK_SET_DS_0(B, P, p, v)   SET_DS_0(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
+#define RK_SET_DS_1(B, P, p, v)   SET_DS_1(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
+#define SET_DS(_GPIO, _PORT, pin, val)       \
+{                                            \
+    if ((pin % 8) < 4) {                     \
+        RK_SET_DS_0(_GPIO, _PORT, pin, val); \
+    } else {                                 \
+        RK_SET_DS_1(_GPIO, _PORT, pin, val); \
+    }                                        \
+}
+
+#elif defined(GRF_GPIO0A_DS_0_OFFSET)
+#define DS_BIT_PER_PIN            (8)
+#define DS_PIN_PER_REG            (16 / DS_BIT_PER_PIN)
+#define DS_0(__B, __P)            (GRF->GPIO##__B##__P##_DS_0)
+#define DS_1(__B, __P)            (GRF->GPIO##__B##__P##_DS_1)
+#define DS_2(__B, __P)            (GRF->GPIO##__B##__P##_DS_2)
+#define DS_3(__B, __P)            (GRF->GPIO##__B##__P##_DS_3)
+#define SET_DS_0(_B, _P, p, v, w) _PINCTRL_WRITE(DS_0(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_DS_1(_B, _P, p, v, w) _PINCTRL_WRITE(DS_1(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_DS_2(_B, _P, p, v, w) _PINCTRL_WRITE(DS_2(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_DS_3(_B, _P, p, v, w) _PINCTRL_WRITE(DS_3(_B, _P), RK_GEN_VAL(p, v, w))
+#define RK_SET_DS_0(B, P, p, v)   SET_DS_0(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
+#define RK_SET_DS_1(B, P, p, v)   SET_DS_1(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
+#define RK_SET_DS_2(B, P, p, v)   SET_DS_2(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
+#define RK_SET_DS_3(B, P, p, v)   SET_DS_3(B, P, p % DS_PIN_PER_REG, v, DS_BIT_PER_PIN)
+#define SET_DS(_GPIO, _PORT, pin, val)       \
+{                                            \
+    if ((pin % 8) < 2) {                     \
+        RK_SET_DS_0(_GPIO, _PORT, pin, val); \
+    } else if ((pin % 8) < 4) {              \
+        RK_SET_DS_1(_GPIO, _PORT, pin, val); \
+    } else if ((pin % 8) < 6) {              \
+        RK_SET_DS_2(_GPIO, _PORT, pin, val); \
+    } else {                                 \
+        RK_SET_DS_3(_GPIO, _PORT, pin, val); \
+    }                                        \
+}
+#endif
+
+#if defined(GRF_GPIO0A_P_OFFSET)
+#define P_BIT_PER_PIN                 (2)
+#define P_PIN_PER_REG                 (16 / P_BIT_PER_PIN)
+#define P_0(__B, __P)                 (GRF->GPIO##__B##__P##_P)
+#define SET_P_0(_B, _P, p, v, w)      _PINCTRL_WRITE(P_0(_B, _P), RK_GEN_VAL(p, v, w))
+#define RK_SET_P_0(B, P, p, v)        SET_P_0(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
+#define SET_P(_GPIO, _PORT, pin, val) RK_SET_P_0(_GPIO, _PORT, pin, val)
+
+#elif defined(GRF_GPIO0A_P_H_OFFSET)
+#define P_BIT_PER_PIN            (4)
+#define P_PIN_PER_REG            (16 / P_BIT_PER_PIN)
+#define P_0(__B, __P)            (GRF->GPIO##__B##__P##_P_L)
+#define P_1(__B, __P)            (GRF->GPIO##__B##__P##_P_L)
+#define SET_P_0(_B, _P, p, v, w) _PINCTRL_WRITE(P_0(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_P_1(_B, _P, p, v, w) _PINCTRL_WRITE(P_1(_B, _P), RK_GEN_VAL(p, v, w))
+#define RK_SET_P_0(B, P, p, v)   SET_P_0(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
+#define RK_SET_P_1(B, P, p, v)   SET_P_1(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
+#define SET_P(_GPIO, _PORT, pin, val)       \
+{                                           \
+    if ((pin % 8) < 4) {                    \
+        RK_SET_P_0(_GPIO, _PORT, pin, val); \
+    } else {                                \
+        RK_SET_P_3(_GPIO, _PORT, pin, val); \
+    }                                       \
+}
+
+#elif defined(GRF_GPIO0A_P_0_OFFSET)
+#define P_BIT_PER_PIN            (8)
+#define P_PIN_PER_REG            (16 / P_BIT_PER_PIN)
+#define P_0(__B, __P)            (GRF->GPIO##__B##__P##_P_0)
+#define P_1(__B, __P)            (GRF->GPIO##__B##__P##_P_1)
+#define P_2(__B, __P)            (GRF->GPIO##__B##__P##_P_2)
+#define P_3(__B, __P)            (GRF->GPIO##__B##__P##_P_3)
+#define SET_P_0(_B, _P, p, v, w) _PINCTRL_WRITE(P_0(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_P_1(_B, _P, p, v, w) _PINCTRL_WRITE(P_1(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_P_2(_B, _P, p, v, w) _PINCTRL_WRITE(P_2(_B, _P), RK_GEN_VAL(p, v, w))
+#define SET_P_3(_B, _P, p, v, w) _PINCTRL_WRITE(P_3(_B, _P), RK_GEN_VAL(p, v, w))
+#define RK_SET_P_0(B, P, p, v)   SET_P_0(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
+#define RK_SET_P_1(B, P, p, v)   SET_P_1(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
+#define RK_SET_P_2(B, P, p, v)   SET_P_2(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
+#define RK_SET_P_3(B, P, p, v)   SET_P_3(B, P, p % P_PIN_PER_REG, v, P_BIT_PER_PIN)
+#define SET_P(_GPIO, _PORT, pin, val)       \
+{                                           \
+    if ((pin % 8) < 2) {                    \
+        RK_SET_P_0(_GPIO, _PORT, pin, val); \
+    } else if ((pin % 8) < 4) {             \
+        RK_SET_P_1(_GPIO, _PORT, pin, val); \
+    } else if ((pin % 8) < 6) {             \
+        RK_SET_P_2(_GPIO, _PORT, pin, val); \
+    } else {                                \
+        RK_SET_P_3(_GPIO, _PORT, pin, val); \
+    }                                       \
+}
+#endif
+
+#ifdef SET_IOMUX
+#define PINCTRL_SET_IOMUX(bank, pin, val) \
+{                                         \
+    if (pin < 8) {                        \
+        SET_IOMUX(bank, A, pin, val);     \
+    } else if (pin < 16) {                \
+        SET_IOMUX(bank, B, pin, val);     \
+    } else if (pin < 24) {                \
+        SET_IOMUX(bank, C, pin, val);     \
+    } else {                              \
+        SET_IOMUX(bank, D, pin, val);     \
+    }                                     \
+}
+#endif
+
+#ifdef SET_DS
+#define PINCTRL_SET_DS(bank, pin, val) \
+{                                      \
+    if (pin < 8) {                     \
+        SET_DS(bank, A, pin, val);     \
+    } else if (pin < 16) {             \
+        SET_DS(bank, B, pin, val);     \
+    } else if (pin < 24) {             \
+        SET_DS(bank, C, pin, val);     \
+    } else {                           \
+        SET_DS(bank, D, pin, val);     \
+    }                                  \
+}
+#endif
+
+#ifdef SET_P
+#define PINCTRL_SET_P(bank, pin, val) \
+{                                     \
+    if (pin < 8) {                    \
+        SET_P(bank, A, pin, val);     \
+    } else if (pin < 16) {            \
+        SET_P(bank, B, pin, val);     \
+    } else if (pin < 24) {            \
+        SET_P(bank, C, pin, val);     \
+    } else {                          \
+        SET_P(bank, D, pin, val);     \
+    }                                 \
+}
+#endif
+
+/********************* Private Variable Definition ***************************/
+
+/********************* Private Function Definition ***************************/
+
+/**
+ * @brief  Private function to set iomux for one pin.
+ * @param  bank: pin bank channel.
+ * @param  pin: pin index, 0~31.
+ * @param  param: value to write.
+ * @return HAL_Status.
+ */
+static HAL_Status PINCTRL_SetIOMUX(eGPIO_bankId bank, uint8_t pin, uint32_t data)
+{
+#ifdef PINCTRL_SET_IOMUX
+    switch (bank) {
+#ifdef GPIO0
+    case 0:
+        PINCTRL_SET_IOMUX(0, pin, data);
+        break;
+#endif
+#ifdef GPIO1
+    case 1:
+        PINCTRL_SET_IOMUX(1, pin, data);
+        break;
+#endif
+#ifdef GPIO2
+    case 2:
+        PINCTRL_SET_IOMUX(2, pin, data);
+        break;
+#endif
+#ifdef GPIO3
+    case 3:
+        PINCTRL_SET_IOMUX(3, pin, data);
+        break;
+#endif
+#ifdef GPIO4
+    case 4:
+    #ifdef SOC_RV1126
+        if (pin < 2) {
+            GRF->GPIO4A_IOMUX_L = RK_GEN_VAL(pin % IOMUX_PIN_PER_REG, data, IOMUX_BIT_PER_PIN);
+        }
+    #else
+        PINCTRL_SET_IOMUX(4, pin, data);
+    #endif
+        break;
+#endif
+    default:
+        HAL_DBG("unknown gpio%d\n", bank);
+        break;
+    }
+
+    return HAL_OK;
+#else
+
+    return HAL_ERROR;
+#endif
+}
+
+/**
+ * @brief  Private function to set drive strength for one pin.
+ * @param  bank: pin bank channel.
+ * @param  pin: pin index, 0~31.
+ * @param  param: value to write.
+ * @return HAL_Status.
+ */
+static HAL_Status PINCTRL_SetDS(eGPIO_bankId bank, uint8_t pin, uint32_t data)
+{
+#ifdef PINCTRL_SET_DS
+    switch (bank) {
+#ifdef GPIO0
+    case 0:
+        PINCTRL_SET_DS(0, pin, data);
+        break;
+#endif
+#ifdef GPIO1
+    case 1:
+        PINCTRL_SET_DS(1, pin, data);
+        break;
+#endif
+#ifdef GPIO2
+    case 2:
+        PINCTRL_SET_DS(2, pin, data);
+        break;
+#endif
+#ifdef GPIO3
+    case 3:
+        PINCTRL_SET_DS(3, pin, data);
+        break;
+#endif
+#ifdef GPIO4
+    case 4:
+    #ifdef SOC_RV1126
+        if (pin < 2) {
+            GRF->GPIO4A_DS_L = RK_GEN_VAL(pin % DS_PIN_PER_REG, data, DS_BIT_PER_PIN);
+        }
+    #else
+        PINCTRL_SET_DS(4, pin, data);
+    #endif
+        break;
+#endif
+    default:
+        HAL_DBG("unknown gpio%d\n", bank);
+        break;
+    }
+
+    return HAL_OK;
+#else
+
+    return HAL_ERROR;
+#endif
+}
+
+/**
+ * @brief  Private function to set pupd for one pin.
+ * @param  bank: pin bank channel.
+ * @param  pin: pin index, 0~31.
+ * @param  param: value to write.
+ * @return HAL_Status.
+ */
+static HAL_Status PINCTRL_SetPUPD(eGPIO_bankId bank, uint8_t pin, uint32_t data)
+{
+#ifdef PINCTRL_SET_P
+    switch (bank) {
+#ifdef GPIO0
+    case 0:
+    #ifdef SOC_RV1126
+        if (pin < 8) {
+            SET_P(0, A, pin, data);
+        } else if (pin < 16) {
+            SET_P(0, B, pin, data);
+        } else if (pin < 20) {
+            GRF->GPIO0C_P_L = RK_GEN_VAL(pin % P_PIN_PER_REG, data, P_BIT_PER_PIN);
+        } else if (pin < 24) {
+            GRF->GPIO0C_P_H = RK_GEN_VAL(pin % P_PIN_PER_REG, data, P_BIT_PER_PIN);
+        } else {
+            SET_P(0, D, pin, data);
+        }
+    #else
+        PINCTRL_SET_P(0, pin, data);
+    #endif
+        break;
+#endif
+#ifdef GPIO1
+    case 1:
+        PINCTRL_SET_P(1, pin, data);
+        break;
+#endif
+#ifdef GPIO2
+    case 2:
+        PINCTRL_SET_P(2, pin, data);
+        break;
+#endif
+#ifdef GPIO3
+    case 3:
+        PINCTRL_SET_P(3, pin, data);
+        break;
+#endif
+#ifdef GPIO4
+    case 4:
+        #ifdef SOC_RV1126
+        if (pin < 2) {
+            GRF->GPIO4A_P = RK_GEN_VAL(pin % P_PIN_PER_REG, data, P_BIT_PER_PIN);
+        }
+        #else
+        PINCTRL_SET_P(4, pin, data);
+        #endif
+        break;
+#endif
+    default:
+        HAL_DBG("unknown gpio%d\n", bank);
+        break;
+    }
+
+    return HAL_OK;
+#else
+
+    return HAL_ERROR;
+#endif
+}
+
+/**
+ * @brief  Private function to configure one pin.
+ * @param  bank: pin bank channel defined in @ref eGPIO_bankId.
+ * @param  pin: pin index, 0~31.
+ * @param  param: multi params defined in @ref ePINCTRL_configParam,
+ * @return HAL_Status.
+ */
+static HAL_Status PINCTRL_SetPinParam(eGPIO_bankId bank, uint8_t pin, uint32_t param)
+{
+    HAL_Status rc = HAL_OK;
+
+    if (param & FLAG_MUX) {
+        rc |= PINCTRL_SetIOMUX(bank, pin, (uint8_t)((param & MASK_MUX) >> SHIFT_MUX));
+    }
+
+    if (param & FLAG_PUL) {
+        rc |= PINCTRL_SetPUPD(bank, pin, (uint8_t)((param & MASK_PUL) >> SHIFT_PUL));
+    }
+
+    if (param & FLAG_DRV) {
+        rc |= PINCTRL_SetDS(bank, pin, (uint8_t)((param & MASK_DRV) >> SHIFT_DRV));
+    }
+
+    return rc;
+}
+/** @} */
+
+/********************* Public Function Definition ****************************/
+
+/** @defgroup PINCTRL_Exported_Functions_Group1 Suspend and Resume Functions
+
+ This section provides functions allowing to suspend and resume the module:
+
+ *  @{
+ */
+
+/** @} */
+
+/** @defgroup PINCTRL_Exported_Functions_Group2 Init and DeInit Functions
+
+ This section provides functions allowing to init and deinit the module:
+
+ *  @{
+ */
+HAL_Status HAL_PINCTRL_Init(void)
+{
+    return HAL_OK;
+}
+
+HAL_Status HAL_PINCTRL_DeInit(void)
+{
+    return HAL_OK;
+}
+/** @} */
+
+/** @defgroup PINCTRL_Exported_Functions_Group3 IO Functions
+
+ *  @{
+ */
+
+/**
+ * @brief  Public function to configure for multi pins.
+ * @param  bank: pin bank channel defined in eGPIO_bankId.
+ * @param  mPins: multi pins defined in @ref ePINCTRL_GPIO_PINS.
+ * @param  param: multi params defined in @ref ePINCTRL_configParam.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_PINCTRL_SetParam(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param)
+{
+    uint8_t pin;
+    HAL_Status rc;
+
+    HAL_ASSERT(bank < GPIO_BANK_NUM);
+
+    if (!(param & (FLAG_MUX | FLAG_PUL | FLAG_DRV | FLAG_SRT | FLAG_SMT))) {
+        return HAL_OK;
+    }
+
+    for (pin = 0; pin < 32; pin++) {
+        if (mPins & (1 << pin)) {
+            rc = PINCTRL_SetPinParam(bank, pin, param);
+            if (rc) {
+                return rc;
+            }
+        }
+    }
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Public function to set iomux for multi pins.
+ * @param  bank: pin bank channel defined in eGPIO_bankId.
+ * @param  mPins: multi pins defined in @ref ePINCTRL_GPIO_PINS.
+ * @param  param: multi params defined in @ref ePINCTRL_configParam.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_PINCTRL_SetIOMUX(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param)
+{
+    return HAL_PINCTRL_SetParam(bank, mPins, param);
+}
+/** @} */
+
+/** @} */
+
+/** @} */
+
+

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/hal_timer.c

@@ -0,0 +1,306 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include "hal_base.h"
+#include "hal_def.h"
+#include "hal_timer.h"
+
+/** @addtogroup RK_HAL_Driver
+ *  @{
+ */
+
+/** @addtogroup TIMER
+ *  @{
+ */
+
+/** @defgroup TIMER_How_To_Use How To Use
+ *  @{
+
+ The TIMER driver can be used as follows:
+
+ - IT mode: Resgister TIMER handler.
+ - Initialize the TIMER by calling HAL_TIMER_Init():
+ - Set TIMER count by calling HAL_TIMER_SetCount().
+ - Start the TIMER by calling HAL_TIMER_Start() or HAL_TIMER_Start_IT().
+ - Stop the TIMER by calling HAL_TIMER_Stop() or HAL_TIMER_Stop_IT().
+
+ SYS_TIMER
+
+ - SYS_TIMER is a rk timer fixed to serve the delay system. Invoke HAL_TIMER_SysTimerInit() to init.
+
+ @} */
+
+/** @defgroup TIMER_Private_Definition Private Definition
+ *  @{
+ */
+/********************* Private MACRO Definition ******************************/
+#define TIMER_CONTROLREG_TIMER_MODE_FREE_RUNNING (0x0U << TIMER_CONTROLREG_TIMER_MODE_SHIFT)
+
+#define TIMER_CONTROLREG_TIMER_ENABLE_ENABLED  (0x1U << TIMER_CONTROLREG_TIMER_ENABLE_SHIFT)
+#define TIMER_CONTROLREG_TIMER_ENABLE_DISABLED (0x0U << TIMER_CONTROLREG_TIMER_ENABLE_SHIFT)
+
+#define TIMER_CONTROLREG_TIMER_INT_MASK_UNMASK (0x1U << TIMER_CONTROLREG_TIMER_INT_MASK_SHIFT)
+
+/********************* Private Structure Definition **************************/
+
+/********************* Private Variable Definition ***************************/
+
+/********************* Private Function Definition ***************************/
+
+/** @} */
+/********************* Public Function Definition ****************************/
+
+/** @defgroup TIMER_Exported_Functions_Group4 Init and DeInit Functions
+
+ This section provides functions allowing to init and deinit module as follows:
+
+ *  @{
+ */
+
+/**
+ * @brief  Timer init.
+ * @param  pReg: Choose TIMER.
+ * @param  mode: Choose TIMER mode.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_TIMER_Init(struct TIMER_REG *pReg, eTIMER_MODE mode)
+{
+    HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
+#ifdef SYS_TIMER
+    if (pReg == SYS_TIMER) {
+        return HAL_BUSY;
+    }
+#endif
+
+    WRITE_REG(pReg->CONTROLREG, mode << TIMER_CONTROLREG_TIMER_MODE_SHIFT);
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  System Timer init.
+ * @return HAL_Status.
+ * @attention this API allow direct use in the HAL layer. SYS_TTIMER is used for delay system.
+ */
+HAL_Status HAL_TIMER_SysTimerInit(struct TIMER_REG *pReg)
+{
+    HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
+
+    if (READ_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK)) {
+        return HAL_OK;
+    }
+
+    WRITE_REG(pReg->CONTROLREG, TIMER_FREE_RUNNING);
+    pReg->LOAD_COUNT[0] = 0xFFFFFFFFU;
+    pReg->LOAD_COUNT[1] = 0xFFFFFFFFU;
+    CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_INT_MASK_MASK);
+    SET_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK);
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Timer deinit.
+ * @param  pReg: Choose TIMER.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_TIMER_DeInit(struct TIMER_REG *pReg)
+{
+    HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
+#ifdef SYS_TIMER
+    if (pReg == SYS_TIMER) {
+        return HAL_BUSY;
+    }
+#endif
+
+    WRITE_REG(pReg->CONTROLREG, 0);
+
+    return HAL_OK;
+}
+
+/** @} */
+
+/** @defgroup TIMER_Exported_Functions_Group5 Other Functions
+ *  @{
+ */
+
+/**
+ * @brief  Start TIMER counter.
+ * @param  pReg: Choose TIMER.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_TIMER_Start(struct TIMER_REG *pReg)
+{
+    HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
+#ifdef SYS_TIMER
+    if (pReg == SYS_TIMER) {
+        return HAL_BUSY;
+    }
+#endif
+
+    CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_INT_MASK_MASK);
+    SET_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK);
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Stop TIMER counter.
+ * @param  pReg: Choose TIMER.
+ * @return HAL_Status.
+ * Just disable TIMER, and keep TIMER configuration.
+ */
+HAL_Status HAL_TIMER_Stop(struct TIMER_REG *pReg)
+{
+    HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
+#ifdef SYS_TIMER
+    if (pReg == SYS_TIMER) {
+        return HAL_BUSY;
+    }
+#endif
+
+    CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK);
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Start TIMER counter in interrupt mode.
+ * @param  pReg: Choose TIMER.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_TIMER_Start_IT(struct TIMER_REG *pReg)
+{
+    HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
+#ifdef SYS_TIMER
+    if (pReg == SYS_TIMER) {
+        return HAL_BUSY;
+    }
+#endif
+
+    SET_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_ENABLED | TIMER_CONTROLREG_TIMER_INT_MASK_UNMASK);
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Stop TIMER counter in interrupt mode.
+ * @param  pReg: Choose TIMER.
+ * @return HAL_Status.
+ * Just disable TIMER, and keep TIMER configuration.
+ */
+HAL_Status HAL_TIMER_Stop_IT(struct TIMER_REG *pReg)
+{
+    HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
+#ifdef SYS_TIMER
+    if (pReg == SYS_TIMER) {
+        return HAL_BUSY;
+    }
+#endif
+
+    CLEAR_BIT(pReg->CONTROLREG, TIMER_CONTROLREG_TIMER_ENABLE_MASK);
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Set TIMER count number.
+ * @param  pReg: Choose TIMER.
+ * @param  timerCount: TIMER counter loading number.
+ * @return HAL_Status.
+ * Set timer count number.
+ */
+HAL_Status HAL_TIMER_SetCount(struct TIMER_REG *pReg, uint64_t timerCount)
+{
+    uint64_t loadCount = 0;
+
+    HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
+#ifdef SYS_TIMER
+    if (pReg == SYS_TIMER) {
+        return HAL_BUSY;
+    }
+#endif
+
+    loadCount = timerCount;
+    pReg->LOAD_COUNT[0] = (loadCount & 0xffffffff);
+    pReg->LOAD_COUNT[1] = ((loadCount >> 32) & 0xffffffff);
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  Get TIMER count number.
+ * @param  pReg: Choose TIMER.
+ * @return uint64_t: Current conut number.
+ */
+HAL_SECTION_SRAM_CODE
+uint64_t HAL_TIMER_GetCount(struct TIMER_REG *pReg)
+{
+    uint32_t high, low, temp;
+
+    HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
+
+    do {
+        high = pReg->CURRENT_VALUE[1];
+        low = pReg->CURRENT_VALUE[0];
+        temp = pReg->CURRENT_VALUE[1];
+    } while (high != temp);
+
+    return ((uint64_t)high << 32) | low;
+}
+
+/**
+ * @brief  Clear TIMER interrupt status.
+ * @param  pReg: Choose TIMER.
+ * @return HAL_Status: HAL_OK.
+ */
+HAL_Status HAL_TIMER_ClrInt(struct TIMER_REG *pReg)
+{
+    uint32_t timeOut = 1000;
+
+    HAL_ASSERT(IS_TIMER_INSTANCE(pReg));
+
+    pReg->INTSTATUS = 0x1;
+    while (pReg->INTSTATUS && timeOut) {
+        timeOut--;
+    }
+
+    if (timeOut == 0) {
+        return HAL_TIMEOUT;
+    } else {
+        return HAL_OK;
+    }
+}
+
+/**
+ * @brief  TIMER0 interrupt handler.
+ * @return HAL_Status: HAL_OK.
+ * Clear interrupt status.
+ */
+__attribute__((weak)) HAL_Status HAL_TIMER0_Handler(void)
+{
+    HAL_TIMER_ClrInt(TIMER0);
+
+    return HAL_OK;
+}
+
+/**
+ * @brief  TIMER1 interrupt handler.
+ * @return HAL_Status: HAL_OK.
+ * Clear interrupt status.
+ */
+__attribute__((weak)) HAL_Status HAL_TIMER1_Handler(void)
+{
+    HAL_TIMER_ClrInt(TIMER1);
+
+    return HAL_OK;
+}
+
+/** @} */
+
+/** @} */
+
+/** @} */
+

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/ethernet/test_gmac.c

@@ -0,0 +1,800 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include "hal_bsp.h"
+#include "hal_base.h"
+#include "hal_gmac.h"
+#include "hal_pinctrl.h"
+#include "hal_debug.h"
+#include "hal_timer.h"
+#include "hal_cache.h"
+#include "hal_gpio.h"
+#include "hal_cru.h"
+#include "libserial.h"
+#include "stdlib.h"
+
+
+/*************************** GMAC DRIVER ****************************/
+
+/***************************** MACRO Definition ******************************/
+#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
+
+#define CONFIG_SYS_NONCACHED_MEMORY (4 << 20) /* 4M */
+
+/* 1MB granularity */
+#define MMU_SECTION_SIZE (1 << 20)
+
+/***************************** Structure Definition **************************/
+
+/***************************** Function Declare ******************************/
+
+/********************* Private MACRO Definition ******************************/
+#define GMAC_BUS_MAX 2
+
+#define ARCH_DMA_MINALIGN 64
+
+#define GMAC_DESCRIPTOR_SIZE 16
+#define GMAC_DESCRIPTORS_TX  8
+#define GMAC_DESCRIPTORS_RX  8
+#define GMAC_DESC_TX_SIZE    HAL_GMAC_ALIGN(GMAC_DESCRIPTORS_TX * GMAC_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
+#define GMAC_DESC_RX_SIZE    HAL_GMAC_ALIGN(GMAC_DESCRIPTORS_RX * GMAC_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
+
+#define GMAC_RX_BUFFER_SIZE (GMAC_DESCRIPTORS_RX * HAL_GMAC_MAX_PACKET_SIZE)
+#define GMAC_TX_BUFFER_SIZE (GMAC_DESCRIPTORS_TX * HAL_GMAC_MAX_PACKET_SIZE)
+
+/* Basic mode control register. */
+#define BMCR_RESV      0x003f      /* Unused...                   */
+#define BMCR_SPEED1000 0x0040     /* MSB of Speed (1000)         */
+#define BMCR_CTST      0x0080     /* Collision test              */
+#define BMCR_FULLDPLX  0x0100     /* Full duplex                 */
+#define BMCR_ANRESTART 0x0200     /* Auto negotiation restart    */
+#define BMCR_ISOLATE   0x0400     /* Isolate data paths from MII */
+#define BMCR_PDOWN     0x0800     /* Enable low power state      */
+#define BMCR_ANENABLE  0x1000     /* Enable auto negotiation     */
+#define BMCR_SPEED100  0x2000     /* Select 100Mbps              */
+#define BMCR_LOOPBACK  0x4000     /* TXD loopback bits           */
+#define BMCR_RESET     0x8000     /* Reset to default state      */
+#define BMCR_SPEED10   0x0000     /* Select 10Mbps               */
+
+#define GMAC_TEST_TIMES 1600
+
+/********************* Private Structure Definition **************************/
+/* GMAC consumer config data. */
+struct GMAC_ETH_CONFIG {
+    struct GMAC_HANDLE instance;
+    const struct HAL_GMAC_DEV *halDev;
+    eGMAC_PHY_Interface mode;
+    uint32_t speed;
+    uint32_t maxSpeed;
+    uint16_t phyAddr;
+
+    bool extClk;
+
+    /* phy reset gpio */
+    struct GPIO_REG *resetGpioBank;
+    ePINCTRL_GPIO_PINS resetGpioNum;
+    uint32_t resetDelayMs[3];
+
+    int32_t txDelay;
+    int32_t rxDelay;
+
+    struct GMAC_Desc *txDescs;
+    struct GMAC_Desc *rxDescs;
+
+    uint8_t *txBuff;
+    uint8_t *rxBuff;
+
+    /* MAC address info, hw address */
+    uint8_t macAddr[6];
+};
+
+/********************* Private Variable Definition ***************************/
+#ifdef NC_MEM_BASE
+static const unsigned long os_no_cache_start = (unsigned long)NC_MEM_BASE;
+#else
+static const unsigned long os_no_cache_start = 0;
+#endif
+
+/*
+ * Reserve one MMU section worth of address space below the malloc() area that
+ * will be mapped uncached.
+ */
+static unsigned long noncached_start;
+static unsigned long noncached_end;
+static unsigned long noncached_next;
+
+static unsigned int m_nocachemem_inited = 0;
+
+static uint8_t dstAddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+
+static struct GMAC_ETH_CONFIG ethConfigTable[] =
+{
+
+    {
+        .halDev = &g_gmac0Dev,
+        .mode = PHY_INTERFACE_MODE_RGMII,
+        .maxSpeed = 1000,
+        .phyAddr = 1,
+
+        .extClk = false,
+
+        .resetGpioBank = GPIO2,
+        .resetGpioNum = GPIO_PIN_D3,
+        .resetDelayMs = { 0, 20, 100 },
+
+        .txDelay = 0x3C,
+        .rxDelay = 0x2f,
+    },
+
+    // {
+    //     .halDev = &g_gmac1Dev,
+    //     .mode = PHY_INTERFACE_MODE_RGMII,
+    //     .maxSpeed = 1000,
+    //     .phyAddr = 1,
+
+    //     .extClk = false,
+
+    //     .resetGpioBank = GPIO2,
+    //     .resetGpioNum = GPIO_PIN_D1,
+    //     .resetDelayMs = { 0, 20, 100 },
+
+    //     .txDelay = 0x4f,
+    //     .rxDelay = 0x26,
+    // },
+};
+
+
+
+/********************* Private Function Definition ***************************/
+
+static void Dump_Hex(char *message, uint8_t *ptr, uint16_t buflen)
+{
+    unsigned char *buf = (unsigned char *)ptr;
+    int i, j;
+
+    printf("%s package at %p, len: %d: \n", message, ptr, buflen);
+    for (i = 0; i < buflen; i += 16) {
+        printf("%08X: ", i);
+
+        for (j = 0; j < 16; j++) {
+            if (i + j < buflen) {
+                printf("%02X ", buf[i + j]);
+            } else {
+                printf("   ");
+            }
+        }
+        printf(" ");
+
+        for (j = 0; j < 16; j++) {
+            if (i + j < buflen) {
+                printf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
+            }
+        }
+        printf("\n");
+    }
+}
+
+static void print_desc(struct GMAC_HANDLE *pGMAC)
+{
+    struct GMAC_Desc *desc;
+    int nIndex;
+
+    printf("\n");
+
+    if (pGMAC->rxDescs) {
+        desc = pGMAC->rxDescs;
+        for (nIndex = 0; nIndex < pGMAC->rxSize; nIndex++) {
+            desc = pGMAC->rxDescs + nIndex;
+            printf("rx_desc[%d]@0x%08lx={0x%lx, 0x%lx, 0x%lx, 0x%lx};\n",
+                   nIndex, (uint32_t)desc, desc->des0, desc->des1, desc->des2, desc->des3);
+        }
+    }
+
+    if (pGMAC->txDescs) {
+        desc = pGMAC->txDescs;
+        for (nIndex = 0; nIndex < pGMAC->txSize; nIndex++) {
+            desc = pGMAC->txDescs + nIndex;
+            printf("tx_desc[%d]@0x%08lx={0x%lx, 0x%lx, 0x%lx, 0x%lx};\n",
+                   nIndex, (uint32_t)desc, desc->des0, desc->des1, desc->des2, desc->des3);
+        }
+    }
+}
+
+static void Dump_Regs(struct GMAC_HANDLE *pGMAC)
+{
+    uint32_t *reg = (uint32_t *)pGMAC->pReg;
+    int i;
+
+    printf("\n");
+
+    for (i = 0; i < (0x200 / 0x4); i++) {
+        printf("offset_0x%08x: %08lx %08lx %08lx %08lx\n", i * 0x10,
+               *((volatile const uint32_t *)(reg + 0x4 * i)), *(volatile const uint32_t *)((reg + 0x4 * i + 1)),
+               *((volatile const uint32_t *)(reg + 0x4 * i + 2)), *((volatile const uint32_t *)(reg + 0x4 * i + 3)));
+    }
+
+    reg = reg + 0x1000 / 4;
+
+    for (i = 0; i < (0x100 / 0x4); i++) {
+        printf("offset_0x%08x: %08lx %08lx %08lx %08lx\n", i * 0x10 + 0x1000,
+               *((volatile const uint32_t *)(reg + 0x4 * i)), *((volatile const uint32_t *)(reg + 0x4 * i + 1)),
+               *((volatile const uint32_t *)(reg + 0x4 * i + 2)), *((volatile const uint32_t *)(reg + 0x4 * i + 3)));
+    }
+}
+
+static void PHY_Read(struct GMAC_HANDLE *pGMAC, uint32_t phyReg)
+{
+    int data;
+
+    data = HAL_GMAC_MDIORead(pGMAC, pGMAC->phyConfig.phyAddress, phyReg);
+    if (data >= 0) {
+        printf("PHY_Read: %02lX --> %08X\n", phyReg, data);
+    } else {
+        printf("PHY_Read: %02lX --> faild\n", phyReg);
+    }
+}
+
+static void PHY_Write(uint32_t phyReg, uint32_t data)
+{
+    struct GMAC_HANDLE *pGMAC;
+    int status;
+
+    status = HAL_GMAC_MDIOWrite(pGMAC, pGMAC->phyConfig.phyAddress, phyReg, data);
+    if (!status) {
+        printf("PHY_Write: %02lX --> %08lX\n", phyReg, data);
+    } else {
+        printf("PHY_Write: %02lX --> faild\n", phyReg);
+    }
+}
+
+static void PHY_Dump(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC)
+{
+    int data, i;
+
+    for (i = 0; i < 32; i++) {
+        data = HAL_GMAC_MDIORead(pGMAC, eth->phyAddr, i);
+        if (data < 0) {
+            printf("phy_dump: %d --> faild\n", i);
+            break;
+        }
+
+        if (i % 8 == 7) {
+            printf("%d --> %08X\n ", i, data);
+        } else {
+            printf("%d --> %08X\n\n", i, data);
+        }
+    }
+    printf("\n");
+}
+
+static void GMAC_PHY_Reset(struct GMAC_ETH_CONFIG *config)
+{
+    if (config->resetGpioBank) {
+        HAL_GPIO_SetPinDirection(config->resetGpioBank,
+                                 config->resetGpioNum,
+                                 GPIO_OUT);
+        HAL_GPIO_SetPinLevel(config->resetGpioBank,
+                             config->resetGpioNum,
+                             GPIO_HIGH);
+
+        HAL_DelayMs(config->resetDelayMs[0]);
+
+        HAL_GPIO_SetPinLevel(config->resetGpioBank,
+                             config->resetGpioNum,
+                             GPIO_LOW);
+        HAL_DelayMs(config->resetDelayMs[1]);
+
+        HAL_GPIO_SetPinLevel(config->resetGpioBank,
+                             config->resetGpioNum,
+                             GPIO_HIGH);
+        HAL_DelayMs(config->resetDelayMs[2]);
+    }
+}
+
+static inline void NET_Random_ETHAddr(uint8_t *addr)
+{
+    unsigned int seed = HAL_TIMER_GetCount(SYS_TIMER) | 0xffffffff;
+    uint8_t i;
+
+    for (i = 0; i < 6; i++) {
+        addr[i] = 0xae;
+    }
+
+    addr[0] &= 0xfe;    /* clear multicast bit */
+    addr[0] |= 0x02;    /* set local assignment bit (IEEE802) */
+}
+
+static inline void NET_Random_Package(uint8_t *addr, uint16_t len)
+{
+    unsigned int seed = HAL_TIMER_GetCount(SYS_TIMER) | 0xffffffff;
+    uint16_t i;
+
+    for (i = 0; i < len; i++) {
+        addr[i] = 0xae;
+    }
+}
+
+static void PHY_Update_Links(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC,
+                             uint8_t id)
+{
+    HAL_Status status;
+
+    status = HAL_GMAC_PHYStartup(pGMAC);
+    if (status) {
+        printf("HAL_PHY_Startup() failed: %d\n", status);
+
+        return;
+    }
+    HAL_DelayMs(7000);
+
+    status = HAL_GMAC_PHYUpdateLink(pGMAC);
+    if (status == HAL_OK) {
+        if (pGMAC->phyStatus.link) {
+            status = HAL_GMAC_PHYParseLink(pGMAC);
+            if (PHY_SPEED_1000M == pGMAC->phyStatus.speed) {
+                printf("Phy%d: 1000M link speed\n", id);
+            } else if (PHY_SPEED_100M == pGMAC->phyStatus.speed) {
+                printf("Phy%d: 100M link speed\n", id);
+            } else {
+                printf("Phy%d: 10M link speed\n", id);
+            }
+
+            if (PHY_DUPLEX_HALF == pGMAC->phyStatus.duplex) {
+                printf("Phy%d: half dumplex\n", id);
+            } else {
+                printf("Phy%d: full dumplex\n", id);
+            }
+
+            if (pGMAC->phyStatus.pause) {
+                printf("Phy%d: flow control rx/tx\n", id);
+            } else {
+                printf("Phy%d: flow control off\n", id);
+            }
+
+            status = HAL_GMAC_AdjustLink(pGMAC, eth->txDelay, eth->rxDelay);
+            if (status != HAL_OK) {
+                printf("HAL_GMAC_AdjustLink() failed: %d\n", status);
+            }
+
+            printf("Phy%d: link up.\n", id);
+        } else {
+            printf("Phy%d: link down.\n", id);
+        }
+    }
+}
+
+/* interrupt service routine polling */
+static HAL_Status GMAC_ETH_IRQ(struct GMAC_HANDLE *pGMAC)
+{
+    HAL_Status status;
+
+    /* enter interrupt */
+    /* rt_interrupt_enter(); */
+    status = HAL_GMAC_IRQHandler(pGMAC);
+
+    if (status & DMA_HANLE_RX) {
+        /* a frame has been received */
+        return 1;
+    }
+
+    return 0;
+    /* leave interrupt */
+    /* rt_interrupt_leave(); */
+}
+
+static HAL_Status noncached_init(void)
+{
+    unsigned long start, end;
+    size_t size;
+
+    if (os_no_cache_start <= 0) {
+	printf("Noncached_init failed, plase defined no cached memort\n");
+	return -1;
+    }
+
+    start = HAL_GMAC_ALIGN(os_no_cache_start, 64);
+    size = HAL_GMAC_ALIGN(CONFIG_SYS_NONCACHED_MEMORY, MMU_SECTION_SIZE);
+    end = start + size;
+
+    noncached_start = start;
+    noncached_end = end;
+    noncached_next = start;
+    m_nocachemem_inited = 1;
+
+    return 0;
+}
+
+static unsigned long noncached_alloc(size_t size, size_t align)
+{
+    if (!m_nocachemem_inited) {
+        if (noncached_init())
+	    return (unsigned long)NULL;
+    }
+
+    unsigned long next = HAL_GMAC_ALIGN(noncached_next, align);
+
+    if (next >= noncached_end || (noncached_end - next) < size) {
+        return 0;
+    }
+
+    noncached_next = next + size;
+
+    return next;
+}
+
+static void *malloc_align(size_t size, size_t align)
+{
+    void *align_ptr;
+    void *ptr;
+    size_t align_size;
+
+    /* align the alignment size to 4 byte */
+    align = ((align + 0x03) & ~0x03);
+
+    /* get total aligned size */
+    align_size = ((size + 0x03) & ~0x03) + align;
+    /* allocate memory block from heap */
+    ptr = malloc(align_size);
+    if (ptr != NULL) {
+        /* the allocated memory block is aligned */
+        if (((uint32_t)ptr & (align - 1)) == 0) {
+            align_ptr = (void *)((uint32_t)ptr + align);
+        } else {
+            align_ptr = (void *)(((uint32_t)ptr + (align - 1)) & ~(align - 1));
+        }
+
+        /* set the pointer before alignment pointer to the real pointer */
+        *((uint32_t *)((uint32_t)align_ptr - sizeof(void *))) = (uint32_t)ptr;
+
+        ptr = align_ptr;
+    }
+
+    return ptr;
+}
+
+static void free_align(void *ptr)
+{
+    void *real_ptr;
+
+    real_ptr = (void *)*(uint32_t *)((uint32_t)ptr - sizeof(void *));
+    free(real_ptr);
+}
+
+/********************* Public Function Definition ****************************/
+
+static HAL_Status GMAC_Send_Test(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC,
+                                 uint16_t len)
+{
+    uint8_t *ptr = NULL;
+    HAL_Status status;
+
+    if (!pGMAC->phyStatus.link) {
+        return -1;
+    }
+
+    /* Check the frame length. */
+    if (len > HAL_GMAC_MAX_FRAME_SIZE) {
+        return -1;
+    }
+
+    ptr = (uint8_t *)HAL_GMAC_GetTXBuffer(pGMAC);
+    memcpy(ptr, dstAddr, 6);
+    memcpy(ptr + 6, eth->macAddr, 6);
+    ptr[12] = 0x40;
+    ptr[13] = 0x06;
+    ptr[14] = 0x00;
+    ptr[15] = 0x01;
+    NET_Random_Package(ptr + 16, len - 16);
+
+    if (len > 60) {
+        /* index */
+        ptr[50] = pGMAC->txDescIdx;
+    }
+
+    /* dump packages */
+    Dump_Hex("Tx", ptr, len);
+
+    HAL_DCACHE_CleanByRange((uint32_t)ptr, len);
+    status = HAL_GMAC_Send(pGMAC, ptr, len);
+    if (status) {
+        printf("GMAC send failed: %d\n", status);
+    }
+
+    return status;
+}
+
+static uint16_t GMAC_Recv_Test(struct GMAC_HANDLE *pGMAC)
+{
+    uint8_t *ptr = NULL;
+    HAL_Status status;
+    int32_t size;
+
+    if (!pGMAC->phyStatus.link) {
+        return -1;
+    }
+
+    status = GMAC_ETH_IRQ(pGMAC);
+    ptr = HAL_GMAC_Recv(pGMAC, &size);
+    while (status && ptr) {
+        if (size > 0 && ptr) {
+            /* dump packages */
+            Dump_Hex("Rx", ptr, size);
+            HAL_DCACHE_InvalidateByRange((uint32_t)ptr, size);
+            HAL_GMAC_CleanRX(pGMAC);
+        } else {
+            printf("GMAC recv failed: %ld\n", size);
+
+            return -1;
+        }
+        ptr = HAL_GMAC_Recv(pGMAC, &size);
+    }
+
+    return 0;
+}
+
+static HAL_Status GMAC_Memory_Init(struct GMAC_ETH_CONFIG *eth, struct GMAC_HANDLE *pGMAC)
+{
+    eth->rxDescs = (struct GMAC_Desc *)noncached_alloc(GMAC_DESC_RX_SIZE, ARCH_DMA_MINALIGN);
+    eth->txDescs = (struct GMAC_Desc *)noncached_alloc(GMAC_DESC_TX_SIZE, ARCH_DMA_MINALIGN);
+
+    if (!eth->rxDescs || !eth->txDescs)
+        return -1;
+
+    eth->rxBuff = malloc_align(GMAC_RX_BUFFER_SIZE, ARCH_DMA_MINALIGN);
+    eth->txBuff = malloc_align(GMAC_TX_BUFFER_SIZE, ARCH_DMA_MINALIGN);
+
+    if (!eth->rxBuff || !eth->txBuff)
+        return -1;
+
+    memset(eth->rxDescs, 0, GMAC_DESC_RX_SIZE);
+    memset(eth->txDescs, 0, GMAC_DESC_TX_SIZE);
+
+    memset(eth->rxBuff, 0, GMAC_RX_BUFFER_SIZE);
+    HAL_DCACHE_InvalidateByRange((uint32_t)eth->rxBuff, GMAC_RX_BUFFER_SIZE);
+
+    memset(eth->txBuff, 0, GMAC_TX_BUFFER_SIZE);
+    HAL_DCACHE_CleanByRange((uint32_t)eth->txBuff, GMAC_TX_BUFFER_SIZE);
+
+    HAL_GMAC_DMARxDescInit(pGMAC, eth->rxDescs, eth->rxBuff, GMAC_DESCRIPTORS_RX);
+    HAL_GMAC_DMATxDescInit(pGMAC, eth->txDescs, eth->txBuff, GMAC_DESCRIPTORS_TX);
+
+    print_desc(pGMAC);
+
+    return 0;
+}
+
+static HAL_Status GMAC_Init(uint8_t id)
+{
+    struct GMAC_ETH_CONFIG *eth;
+    struct GMAC_HANDLE *pGMAC;
+    const struct HAL_GMAC_DEV *gmacDev;
+    struct GMAC_PHY_Config config;
+    eGMAC_PHY_Interface interface;
+    HAL_Status status;
+    uint32_t freq;
+
+    HAL_ASSERT(id < GMAC_BUS_MAX);
+
+    eth = &ethConfigTable[id];
+    if (!eth) {
+        return HAL_ERROR;
+    }
+
+    pGMAC = &eth->instance;
+    gmacDev = eth->halDev;
+
+    /* MAC init */
+    interface = eth->mode;
+
+    if (interface == PHY_INTERFACE_MODE_RGMII) {
+        HAL_CRU_ClkSetFreq(gmacDev->clkID, 125000000);
+    } else {
+        HAL_CRU_ClkSetFreq(gmacDev->clkID, 50000000);
+    }
+
+    freq = HAL_CRU_ClkGetFreq(gmacDev->pclkID);
+    HAL_GMAC_Init(pGMAC, gmacDev->pReg, freq, interface, eth->extClk);
+
+    /* PHY Init */
+    config.speed = eth->speed;
+    config.maxSpeed = eth->maxSpeed;
+    config.duplexMode = PHY_DUPLEX_FULL;
+    config.neg = PHY_AUTONEG_ENABLE;
+    config.interface = interface;
+    config.phyAddress = eth->phyAddr;
+    config.features = 0;
+    status = HAL_GMAC_PHYInit(pGMAC, &config);
+    if (status) {
+        printf("HAL_PHY_Init() failed: %d\n", status);
+
+        return status;
+    }
+
+    /* MAC Address */
+    NET_Random_ETHAddr(eth->macAddr);
+    HAL_GMAC_WriteHWAddr(&eth->instance, eth->macAddr);
+
+    return 0;
+}
+
+/*************************** GMAC TEST ****************************/
+#define GMAC_MAX_DEVICES 2
+
+
+
+/**
+ * @brief  Config iomux for GMAC0
+ */
+static void GMAC0_Iomux_Config(void)
+{
+    /* GMAC0 iomux */
+    HAL_PINCTRL_SetIOMUX(GPIO_BANK2,
+                         GPIO_PIN_B6, /* gmac0_rxd0 */
+                         PIN_CONFIG_MUX_FUNC1);
+
+    HAL_PINCTRL_SetIOMUX(GPIO_BANK2,
+                         GPIO_PIN_C3 | /* gmac0_mdc */
+                         GPIO_PIN_C4 | /* gmac0_mdio */
+                         GPIO_PIN_C0 | /* gmac0_rxdvcrs */
+                         GPIO_PIN_B7 | /* gmac0_rxd1 */
+                         GPIO_PIN_A3 | /* gmac0_rxd2 */
+                         GPIO_PIN_A4 | /* gmac0_rxd3 */
+                         GPIO_PIN_A6 | /* gmac0_txd2 */
+                         GPIO_PIN_A7 | /* gmac0_txd3 */
+                         GPIO_PIN_A5,  /* gmac0_rxclk */
+                         PIN_CONFIG_MUX_FUNC2);
+
+    HAL_PINCTRL_SetIOMUX(GPIO_BANK2,
+                         GPIO_PIN_B3 | /* gmac0_txd0 */
+                         GPIO_PIN_B4 | /* gmac0_txd1 */
+                         GPIO_PIN_B5,  /* gmac0_txen */
+                         PIN_CONFIG_MUX_FUNC1 | PIN_CONFIG_DRV_LEVEL2);
+
+    HAL_PINCTRL_SetIOMUX(GPIO_BANK2,
+                         GPIO_PIN_A7 | /* gmac0_txd3 */
+                         GPIO_PIN_A6,  /* gmac0_txd2 */
+                         PIN_CONFIG_MUX_FUNC2 | PIN_CONFIG_DRV_LEVEL2);
+    HAL_PINCTRL_SetIOMUX(GPIO_BANK2,   /* gmac0_txclk */
+                         GPIO_PIN_B0,
+                         PIN_CONFIG_MUX_FUNC2 | PIN_CONFIG_DRV_LEVEL1);
+
+#if 0
+    /* io-domian: 1.8v or 3.3v for vccio4 */
+	WRITE_REG_MASK_WE(GRF->IO_VSEL0,
+	                  GRF_IO_VSEL0_POC_VCCIO4_SEL18_MASK,
+	                  (1 << GRF_IO_VSEL0_POC_VCCIO4_SEL18_SHIFT));
+
+	WRITE_REG_MASK_WE(GRF->IO_VSEL1,
+	                  GRF_IO_VSEL1_POC_VCCIO4_SEL33_MASK,
+	                  (0 << GRF_IO_VSEL1_POC_VCCIO4_SEL33_SHIFT));
+#endif
+}
+
+
+
+/**
+ * @brief  Config iomux for GMAC1
+ */
+// static void GMAC1_M1_Iomux_Config(void)
+// {
+//     /* GMAC1 M1 iomux */
+//     HAL_PINCTRL_SetIOMUX(GPIO_BANK4,
+//                          GPIO_PIN_B6 | /* gmac1_mdcm1 */
+//                          GPIO_PIN_B7 | /* gmac1_mdiom1 */
+//                          GPIO_PIN_B1 | /* gmac1_rxdvcrsm1 */
+//                          GPIO_PIN_A7 | /* gmac1_rxd0m1 */
+//                          GPIO_PIN_B0 | /* gmac1_rxd1m1 */
+//                          GPIO_PIN_A1 | /* gmac1_rxd2m1 */
+//                          GPIO_PIN_A2 | /* gmac1_rxd3m1 */
+//                          GPIO_PIN_A6 | /* gmac1_txenm1 */
+//                          GPIO_PIN_A3,  /* gmac1_rxclkm1 */
+//                          PIN_CONFIG_MUX_FUNC3);
+
+//     HAL_PINCTRL_SetIOMUX(GPIO_BANK4,
+//                          GPIO_PIN_A0,  /* gmac1_txd1m1 */
+//                          PIN_CONFIG_MUX_FUNC3 | PIN_CONFIG_DRV_LEVEL3);
+
+//     HAL_PINCTRL_SetIOMUX(GPIO_BANK4,
+//                          GPIO_PIN_A4 | /* gmac1_txd0m1 */
+//                          GPIO_PIN_A5,  /* gmac1_txd1m1 */
+//                          PIN_CONFIG_MUX_FUNC3 | PIN_CONFIG_DRV_LEVEL2);
+
+//     /* GMAC1 M1 iomux */
+//     HAL_PINCTRL_SetIOMUX(GPIO_BANK3,
+//                          GPIO_PIN_D6 | /* gmac1_txd2m1 */
+//                          GPIO_PIN_D7,  /* gmac1_txd3m1 */
+//                          PIN_CONFIG_MUX_FUNC3 | PIN_CONFIG_DRV_LEVEL2);
+
+//     HAL_PINCTRL_IOFuncSelForGMAC1(IOFUNC_SEL_M1);
+
+// #if 0
+//     /* io-domian: 1.8v or 3.3v for vccio6 */
+//     WRITE_REG_MASK_WE(GRF->IO_VSEL0,
+// 	              GRF_IO_VSEL0_POC_VCCIO6_SEL18_MASK,
+// 	              (1 << GRF_IO_VSEL0_POC_VCCIO6_SEL18_SHIFT));
+
+//     WRITE_REG_MASK_WE(GRF->IO_VSEL1,
+// 	              GRF_IO_VSEL1_POC_VCCIO6_SEL33_MASK,
+// 	              (0 << GRF_IO_VSEL1_POC_VCCIO6_SEL33_SHIFT));
+// #endif
+// }
+
+
+static void GMAC_Iomux_Config(uint8_t id)
+{
+    // if (id == 1) {
+    //     GMAC1_M1_Iomux_Config();
+    // } else if (id == 0) {
+        GMAC0_Iomux_Config();
+    // }
+}
+
+
+/*************************** GMAC TEST MAIN ****************************/
+
+void main(){
+    struct GMAC_ETH_CONFIG *eth;
+    struct GMAC_HANDLE *pGMAC;
+    int32_t bus, num = 0, i;
+
+    HAL_DBG("\n");
+    HAL_DBG("%s\n", __func__);
+    HAL_DBG("    GMAC Test:\n");
+
+    num = sizeof(ethConfigTable) / sizeof(struct GMAC_ETH_CONFIG);
+    HAL_DBG("    GMAC Num: %ld\n", num);
+    for (bus = 0; bus < num; bus++) {
+        eth = &ethConfigTable[bus];
+        if (eth) {
+            pGMAC = &eth->instance;
+        } else {
+            return;
+        }
+
+        /* ionmux */
+        GMAC_Iomux_Config(bus);
+
+        HAL_CRU_ClkEnable(eth->halDev->pclkGateID);
+        HAL_CRU_ClkEnable(eth->halDev->clkGateID);
+
+        /* Register irq */
+
+        /* PHY reset */
+        GMAC_PHY_Reset(eth);
+
+        /* GMAC Init */
+        GMAC_Init(bus);
+
+        GMAC_Memory_Init(eth, pGMAC);
+
+        /* Enable GMAC and DMA transmission and reception */
+        HAL_GMAC_Start(pGMAC, eth->macAddr);
+
+        /* Update links information */
+        PHY_Update_Links(eth, pGMAC, bus);
+
+        /* Dump MAC Regs */
+        Dump_Regs(pGMAC);
+        /* Dump PHY Regs */
+        PHY_Dump(eth, pGMAC);
+
+        for (i = 0; i < GMAC_TEST_TIMES; i++) {
+            /* GMAC Send 64 bytes */
+            GMAC_Send_Test(eth, pGMAC, 64);
+            /* GMAC Send 1500 bytes */
+            GMAC_Send_Test(eth, pGMAC, 1500);
+            HAL_DelayMs(1000);
+
+            /* GMAC Recv */
+            GMAC_Recv_Test(pGMAC);
+        }
+
+        HAL_CRU_ClkDisable(eth->halDev->pclkGateID);
+        HAL_CRU_ClkDisable(eth->halDev->clkGateID);
+
+        free_align(eth->txBuff);
+        free_align(eth->rxBuff);
+    }
+}

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_base.h

@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ */
+
+/** @addtogroup RK_HAL_Driver
+ *  @{
+ */
+
+/** @addtogroup HAL_BASE
+ *  @{
+ */
+
+#ifndef _HAL_BASE_H_
+#define _HAL_BASE_H_
+
+#include "stdint.h"
+#include "hal_def.h"
+#include "hal_debug.h"
+
+/***************************** MACRO Definition ******************************/
+
+/** @defgroup HAL_BASE_Exported_Definition_Group1 Basic Definition
+ *  @{
+ */
+
+/** enter markrom usb upgrade */
+#define SYS_UPGRADE_FLAG (0xEF08A53C)
+/** enter loader usb upgrade */
+#define LDR_UPGRADE_FLAG (0x5242C301)
+
+#define IS_TICKFREQ(f) (((f) == HAL_TICK_FREQ_1KHZ)  || ((f) == HAL_TICK_FREQ_100HZ) || ((f) == HAL_TICK_FREQ_10HZ))
+
+/***************************** Structure Definition **************************/
+typedef enum {
+    HAL_TICK_FREQ_10HZ    = 100U,    /**< 10 ticks per second, so it's 100ms/tick */
+    HAL_TICK_FREQ_100HZ   = 10U,     /**< 100 ticks per second, so it's 10ms/tick */
+    HAL_TICK_FREQ_1KHZ    = 1U,      /**< 1000 ticks per second, so it's 1ms/tick */
+    HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
+} eHAL_tickFreq;
+
+/** @} */
+
+/***************************** Function Declare ******************************/
+/** @defgroup HAL_BASE_Public_Function_Declare Public Function Declare
+ *  @{
+ */
+
+
+HAL_Status HAL_InitTick(uint32_t tickPriority);
+HAL_Status HAL_IncTick(void);
+uint32_t HAL_GetTick(void);
+HAL_Status HAL_SetTickFreq(eHAL_tickFreq freq);
+eHAL_tickFreq HAL_GetTickFreq(void);
+
+HAL_Status HAL_DelayUs(uint32_t us);
+HAL_Status HAL_DelayMs(uint32_t ms);
+HAL_Status HAL_CPUDelayUs(uint32_t us);
+HAL_Status HAL_SystemCoreClockUpdate(uint32_t hz, eHAL_systickClkSource clkSource);
+
+uint64_t HAL_DivU64Rem(uint64_t numerator, uint32_t denominator, uint32_t *pRemainder);
+uint64_t HAL_GetSysTimerCount(void);
+
+
+/** @} */
+
+/********************* Public Function Definition ***************************/
+/** @defgroup HAL_BASE_Exported_Functions_Group5 Other Functions
+ *  @{
+ */
+
+/**
+ * @brief  uint64_t numerator / uint32_t denominator
+ * @param  numerator
+ * @param  denominator
+ * @return uint64_t result
+ */
+static inline uint64_t HAL_DivU64(uint64_t numerator, uint32_t denominator)
+{
+    return HAL_DivU64Rem(numerator, denominator, NULL);
+}
+
+/**
+ * @brief  uint32_t numerator / uint32_t denominator rounded to nearest integer
+ * @param  numerator
+ * @param  denominator
+ * @return uint32_t result rounded to nearest integer
+ */
+static inline uint32_t HAL_DivRoundClosest(uint32_t numerator, uint32_t denominator)
+{
+    return (numerator + (denominator / 2)) / denominator;
+}
+
+/** @} */
+
+#endif
+
+/** @} */
+
+/** @} */

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_bsp.h

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __BSP_H__
+#define __BSP_H__
+
+#include "hal_base.h"
+
+/***************************** MACRO Definition ******************************/
+
+/***************************** Structure Definition **************************/
+
+#define SYS_TIMER TIMER5
+extern const struct HAL_GMAC_DEV g_gmac0Dev;
+extern const struct HAL_GMAC_DEV g_gmac1Dev;
+
+/***************************** Function Declare ******************************/
+void BSP_Init(void);
+
+#endif

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_cache.h

@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ */
+
+/** @addtogroup RK_HAL_Driver
+ *  @{
+ */
+
+/** @addtogroup CACHE
+ *  @{
+ */
+
+#ifndef _HAL_CACHE_H_
+#define _HAL_CACHE_H_
+
+#include "hal_def.h"
+#include "hal_debug.h"
+
+/***************************** MACRO Definition ******************************/
+/** @defgroup CACHE_Exported_Definition_Group1 Basic Definition
+ *  @{
+ */
+
+/***************************** Structure Definition **************************/
+
+/**
+ *  performance measurement count for icache & dcache
+ *
+ */
+struct CACHE_PMU_CNT {
+    uint32_t rdNum; /**< PMU read number counter */
+    uint32_t wrNum; /**< PMU write number counter */
+    uint32_t sramRdHit; /**< PMU SRAM hit counter */
+    uint32_t hbRdHit; /**< PMU hot buffer hit */
+    uint32_t stbRdHit; /**< PMU store buffer hit */
+    uint32_t rdHit; /**< PMU read hit counter */
+    uint32_t wrHit; /**< PMU write hit counter */
+    uint32_t rdMissPenalty; /**< PMU read miss penalty counter */
+    uint32_t wrMissPenalty; /**< PMU write miss penalty counter */
+    uint32_t rdLat; /**< PMU read latency */
+    uint32_t wrLat; /**< PMU write latency */
+};
+
+/** @} */
+/********************* Public Function Definition ****************************/
+/** @defgroup CACHE_Exported_Functions_Group5 Other Functions
+ *  @attention these APIs allow direct use in the HAL layer
+ *  @{
+ */
+
+uint32_t HAL_CpuAddrToDmaAddr(uint32_t cpuAddr);
+HAL_Status HAL_ICACHE_Enable(void);
+HAL_Status HAL_ICACHE_Disable(void);
+HAL_Status HAL_ICACHE_Invalidate(void);
+HAL_Status HAL_ICACHE_InvalidateByRange(uint32_t address, uint32_t sizeByte);
+HAL_Status HAL_ICACHE_EnablePMU(void);
+HAL_Status HAL_ICACHE_DisablePMU(void);
+HAL_Status HAL_ICACHE_GetPMU(struct CACHE_PMU_CNT *stat);
+HAL_Status HAL_ICACHE_EnableInt(void);
+HAL_Status HAL_ICACHE_DisableInt(void);
+HAL_Check HAL_ICACHE_GetInt(void);
+uint32_t HAL_ICACHE_GetErrAddr(void);
+HAL_Status HAL_ICACHE_ClearInt(void);
+HAL_Status HAL_DCACHE_Enable(void);
+HAL_Status HAL_DCACHE_Disable(void);
+HAL_Status HAL_DCACHE_Invalidate(void);
+HAL_Status HAL_DCACHE_InvalidateByRange(uint32_t address, uint32_t sizeByte);
+HAL_Status HAL_DCACHE_CleanByRange(uint32_t address, uint32_t sizeByte);
+HAL_Status HAL_DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t sizeByte);
+HAL_Status HAL_DCACHE_CleanInvalidate(void);
+HAL_Status HAL_DCACHE_EnablePMU(void);
+HAL_Status HAL_DCACHE_DisablePMU(void);
+HAL_Status HAL_DCACHE_GetPMU(struct CACHE_PMU_CNT *stat);
+HAL_Status HAL_DCACHE_EnableInt(void);
+HAL_Status HAL_DCACHE_DisableInt(void);
+HAL_Check HAL_DCACHE_GetInt(void);
+HAL_Status HAL_DCACHE_ClearInt(void);
+uint32_t HAL_DCACHE_GetErrAddr(void);
+
+/** @} */
+
+#endif
+
+/** @} */
+
+/** @} */

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_cru.h

@@ -0,0 +1,474 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ */
+
+
+/** @addtogroup RK_HAL_Driver
+ *  @{
+ */
+
+/** @addtogroup CRU
+ *  @{
+ */
+
+#ifndef _HAL_CRU_H_
+#define _HAL_CRU_H_
+
+#include "hal_def.h"
+
+/*************************** MACRO Definition ****************************/
+/** @defgroup CRU_Exported_Definition_Group1 Basic Definition
+ *  @{
+ */
+
+#ifdef HAL_CRU_DBG_ON
+#define HAL_CRU_DBG(fmt, arg...) HAL_SYSLOG("[HAL CRU] " fmt, ##arg)
+#else
+#define HAL_CRU_DBG(fmt, arg...) do { if (0) HAL_SYSLOG("[HAL CRU] " fmt, ##arg); } while (0)
+#endif
+
+#define MHZ 1000000
+#define KHZ 1000
+
+#ifndef PLL_INPUT_OSC_RATE
+#define PLL_INPUT_OSC_RATE (24 * MHZ)
+#endif
+
+#define GENVAL_D16(x, h, l)     ((uint32_t)(((x) & HAL_GENMASK(h, l)) / 16))
+#define GENVAL_D16_REM(x, h, l) ((uint32_t)(((x) & HAL_GENMASK(h, l)) % 16))
+#define WIDTH_TO_MASK(w)        ((1 << (w)) - 1)
+
+/*
+ * RESET/GATE fields:
+ *   [31:16]: reserved
+ *   [15:12]: bank
+ *   [11:0]:  id
+ */
+#define CLK_RESET_GET_REG_OFFSET(x) GENVAL_D16(x, 11, 0)
+#define CLK_RESET_GET_BITS_SHIFT(x) GENVAL_D16_REM(x, 11, 0)
+#define CLK_RESET_GET_REG_BANK(x)   HAL_GENVAL(x, 15, 12)
+
+#define CLK_GATE_GET_REG_OFFSET(x) CLK_RESET_GET_REG_OFFSET(x)
+#define CLK_GATE_GET_BITS_SHIFT(x) CLK_RESET_GET_BITS_SHIFT(x)
+#define CLK_GATE_GET_REG_BANK(x)   CLK_RESET_GET_REG_BANK(x)
+
+/*
+ * MUX/DIV fields:
+ *   [31:24]: width
+ *   [23:16]: shift
+ *   [15:12]: reserved
+ *   [11:8]:  bank
+ *   [7:0]:   reg
+ */
+#define CLK_MUX_GET_REG_OFFSET(x) HAL_GENVAL(x, 7,  0)
+#define CLK_MUX_GET_BANK(x)       HAL_GENVAL(x, 11, 8)
+#define CLK_MUX_GET_BITS_SHIFT(x) HAL_GENVAL(x, 23, 16)
+#define CLK_MUX_GET_WIDTH(x)      HAL_GENVAL(x, 31, 24)
+#define CLK_MUX_GET_MASK(x)       (WIDTH_TO_MASK(CLK_MUX_GET_WIDTH(x)) << CLK_MUX_GET_BITS_SHIFT(x))
+
+#define CLK_DIV_GET_REG_OFFSET(x) CLK_MUX_GET_REG_OFFSET(x)
+#define CLK_DIV_GET_BANK(x)       CLK_MUX_GET_BANK(x)
+#define CLK_DIV_GET_BITS_SHIFT(x) CLK_MUX_GET_BITS_SHIFT(x)
+#define CLK_DIV_GET_WIDTH(x)      CLK_MUX_GET_WIDTH(x)
+#define CLK_DIV_GET_MASK(x)       CLK_MUX_GET_MASK(x)
+#define CLK_DIV_GET_MAXDIV(x)     ((1 << CLK_DIV_GET_WIDTH(x)) - 1)
+
+/*
+ * v64 mux = v32 | bank(in bit[35:32])
+ * v64 div = v32 | bank(in bit[39:36])
+ */
+#ifdef CRU_CLK_USE_CON_BANK
+#define CLK_GET_MUX(v64) ((uint32_t)(((v64) & 0xFFFFFFFF00000000) >> 32))
+#define CLK_GET_DIV(v64) ((uint32_t)((v64) & 0x00000000FFFFFFFF))
+#else
+#define CLK_GET_MUX(v32) ((uint32_t)((v32) & 0x0F0F00FFU))
+#define CLK_GET_DIV(v32) ((uint32_t)((((v32) & 0x0000FF00U) >> 8) | \
+                                     (((v32) & 0xF0F00000U) >> 4)))
+#endif
+
+#define RK_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, \
+                    _frac)                                                \
+    {                                                                     \
+        .rate = _rate##U, .fbDiv = _fbdiv, .postDiv1 = _postdiv1,         \
+        .refDiv = _refdiv, .postDiv2 = _postdiv2, .dsmpd = _dsmpd,        \
+        .frac = _frac,                                                    \
+    }
+
+#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \
+    {                                          \
+        .rate = _rate##U, .p = _p, .m = _m,    \
+        .s = _s, .k = _k,                      \
+    }
+
+#define CRU_BANK_CFG_FLAGS(reg, sel, gate, soft) \
+    {                                            \
+        .cruBase = reg,                          \
+        .selOffset = sel,                        \
+        .gateOffset = gate,                      \
+        .softOffset = soft,                      \
+    }
+
+struct PLL_CONFIG {
+    uint32_t rate;
+
+    union {
+        struct {
+            uint32_t fbDiv;
+            uint32_t postDiv1;
+            uint32_t refDiv;
+            uint32_t postDiv2;
+            uint32_t dsmpd;
+            uint32_t frac;
+        };
+        struct {
+            uint32_t m;
+            uint32_t p;
+            uint32_t s;
+            uint32_t k;
+        };
+    };
+};
+
+struct PLL_SETUP {
+    __IO uint32_t *conOffset0;
+    __IO uint32_t *conOffset1;
+    __IO uint32_t *conOffset2;
+    __IO uint32_t *conOffset3;
+    __IO uint32_t *conOffset6;
+    __IO uint32_t *modeOffset;
+    __I uint32_t *stat0;
+    uint32_t modeShift;
+    uint32_t lockShift;
+    uint32_t modeMask;
+    const struct PLL_CONFIG *rateTable;
+};
+
+typedef enum {
+    GLB_SRST_FST = 0xfdb9,
+    GLB_SRST_SND = 0xeca8,
+} eCRU_GlbSrstType;
+
+typedef enum {
+    GLB_RST_FST_WDT0 = 0U,
+    GLB_RST_SND_WDT0,
+    GLB_RST_FST_WDT1,
+    GLB_RST_SND_WDT1,
+    GLB_RST_FST_WDT2,
+    GLB_RST_SND_WDT2,
+} eCRU_WdtRstType;
+
+struct CRU_BANK_INFO {
+    uint32_t cruBase;
+    uint32_t selOffset;
+    uint32_t gateOffset;
+    uint32_t softOffset;
+};
+
+struct HAL_CRU_DEV {
+    const struct CRU_BANK_INFO *banks;
+    uint8_t banksNum;
+};
+
+extern const struct HAL_CRU_DEV g_cruDev;
+
+/***************************** Structure Definition **************************/
+
+/** @} */
+/***************************** Function Declare ******************************/
+/** @defgroup CRU_Private_Function_Declare Private Function Declare
+ *  @{
+ */
+
+#define _MHZ(n) ((n) * 1000000)
+#define DIV_NO_REM(pFreq, freq, maxDiv) \
+    ((!((pFreq) % (freq))) && ((pFreq) / (freq) <= (maxDiv)))
+
+int HAL_CRU_FreqGetMux4(uint32_t freq, uint32_t freq0, uint32_t freq1,
+                        uint32_t freq2, uint32_t freq3);
+int HAL_CRU_FreqGetMux3(uint32_t freq, uint32_t freq0, uint32_t freq1,
+                        uint32_t freq2);
+int HAL_CRU_FreqGetMux2(uint32_t freq, uint32_t freq0, uint32_t freq1);
+
+uint32_t HAL_CRU_MuxGetFreq4(uint32_t muxName, uint32_t freq0, uint32_t freq1,
+                             uint32_t freq2, uint32_t freq3);
+uint32_t HAL_CRU_MuxGetFreq3(uint32_t muxName, uint32_t freq0, uint32_t freq1,
+                             uint32_t freq2);
+uint32_t HAL_CRU_MuxGetFreq2(uint32_t muxName, uint32_t freq0, uint32_t freq1);
+
+int HAL_CRU_RoundFreqGetMux4(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1,
+                             uint32_t pFreq2, uint32_t pFreq3, uint32_t *pFreqOut);
+int HAL_CRU_RoundFreqGetMux3(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1,
+                             uint32_t pFreq2, uint32_t *pFreqOut);
+int HAL_CRU_RoundFreqGetMux2(uint32_t freq, uint32_t pFreq0, uint32_t pFreq1,
+                             uint32_t *pFreqOut);
+
+/** @} */
+
+/** @defgroup CRU_Public_Function_Declare Public Function Declare
+ *  @{
+ */
+
+/**
+ * @brief Get pll freq.
+ * @param  pSetup: Contains PLL register parameters
+ * @return pll rate.
+ */
+uint32_t HAL_CRU_GetPllFreq(struct PLL_SETUP *pSetup);
+
+/**
+ * @brief Set pll freq.
+ * @param  pSetup: Contains PLL register parameters
+ * @param  rate: pll set
+ * @return HAL_Status.
+ */
+HAL_Status HAL_CRU_SetPllFreq(struct PLL_SETUP *pSetup, uint32_t rate);
+
+/**
+ * @brief Set pll power up.
+ * @param  pSetup: Contains PLL register parameters
+ * @return HAL_Status.
+ */
+HAL_Status HAL_CRU_SetPllPowerUp(struct PLL_SETUP *pSetup);
+
+/**
+ * @brief Set pll power down.
+ * @param  pSetup: Contains PLL register parameters
+ * @return HAL_Status.
+ */
+HAL_Status HAL_CRU_SetPllPowerDown(struct PLL_SETUP *pSetup);
+
+/**
+ * @brief Check if clk is enabled
+ * @param  clk: clock to check
+ * @return HAL_Check.
+ */
+HAL_Check HAL_CRU_ClkIsEnabled(uint32_t clk);
+
+/**
+ * @brief Enable clk
+ * @param  clk: clock to set
+ * @return HAL_Status.
+ */
+HAL_Status HAL_CRU_ClkEnable(uint32_t clk);
+
+/**
+ * @brief Disable unused clk
+ * @param  bank: cru bank id
+ * @param  index: gate con offset
+ * @param  val: gate value
+ * @return HAL_Status.
+ */
+HAL_Status HAL_CRU_ClkDisableUnused(uint32_t bank, uint32_t index, uint32_t val);
+
+/**
+ * @brief Disable clk
+ * @param  clk: clock to set
+ * @return HAL_Status.
+ */
+HAL_Status HAL_CRU_ClkDisable(uint32_t clk);
+
+/**
+ * @brief Check if clk is reset
+ * @param  clk: clock to check
+ * @return HAL_Check.
+ */
+HAL_Check HAL_CRU_ClkIsReset(uint32_t clk);
+
+/**
+ * @brief Assert the reset to the clk
+ * @param  clk: clock to assert
+ * @return HAL_Status.
+ */
+HAL_Status HAL_CRU_ClkResetAssert(uint32_t clk);
+
+/**
+ * @brief Deassert the reset to the clk
+ * @param  clk: clock to deassert
+ * @return HAL_Status.
+ */
+HAL_Status HAL_CRU_ClkResetDeassert(uint32_t clk);
+
+/**
+ * @brief Sync Assert the resets to the clk
+ * @param  numClks: num clocks to assert
+ * @param  clks: clocks to assert
+ * @return HAL_Status.
+ */
+HAL_Status HAL_CRU_ClkResetSyncAssert(int numClks, uint32_t *clks);
+
+/**
+ * @brief Sync Deassert the resets to the clk
+ * @param  numClks: num clocks to assert
+ * @param  clks: clocks to deassert
+ * @return HAL_Status.
+ */
+HAL_Status HAL_CRU_ClkResetSyncDeassert(int numClks, uint32_t *clks);
+
+/**
+ * @brief  Set frac div
+ * @param  fracDivName: frac div id(Contains div offset, shift, mask information)
+ * @param  numerator: the numerator to set.
+ * @param  denominator: the denominator to set.
+ * @return HAL_Status
+ */
+HAL_Status HAL_CRU_ClkSetFracDiv(uint32_t fracDivName,
+                                 uint32_t numerator,
+                                 uint32_t denominator);
+
+/**
+ * @brief  Get frac div
+ * @param  fracDivName: frac div id(Contains div offset, shift, mask information)
+ * @param  numerator: the returned numerator.
+ * @param  denominator: the returned denominator.
+ * @return HAL_Status
+ */
+HAL_Status HAL_CRU_ClkGetFracDiv(uint32_t fracDivName,
+                                 uint32_t *numerator,
+                                 uint32_t *denominator);
+
+/**
+ * @brief  Set integer div
+ * @param  divName: div id(Contains div offset, shift, mask information)
+ * @param  divValue: div value
+ * @return NONE
+ */
+HAL_Status HAL_CRU_ClkSetDiv(uint32_t divName, uint32_t divValue);
+
+/**
+ * @brief  Get integer div
+ * @param  divName: div id (Contains div offset, shift, mask information)
+ * @return div value
+ */
+uint32_t HAL_CRU_ClkGetDiv(uint32_t divName);
+
+/**
+ * @brief  Set mux
+ * @param  muxName: mux id (Contains mux offset, shift, mask information)
+ * @param  muxValue: mux value
+ * @return NONE
+ */
+HAL_Status HAL_CRU_ClkSetMux(uint32_t muxName, uint32_t muxValue);
+
+/**
+ * @brief  Get mux
+ * @param  muxName: mux id (Contains mux offset, shift, mask information)
+ * @return mux value
+ */
+uint32_t HAL_CRU_ClkGetMux(uint32_t muxName);
+
+/**
+ * @brief  Get frac div config.
+ * @param  rateOut: clk out rate.
+ * @param  rate: clk src rate.
+ * @param  numerator: the returned numerator.
+ * @param  denominator: the returned denominator.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_CRU_FracdivGetConfig(uint32_t rateOut, uint32_t rate,
+                                    uint32_t *numerator,
+                                    uint32_t *denominator);
+/**
+ * @brief Get clk freq.
+ * @param  clockName: CLOCK_Name id.
+ * @return rate.
+ * @attention these APIs allow direct use in the HAL layer.
+ */
+uint32_t HAL_CRU_ClkGetFreq(eCLOCK_Name clockName);
+
+/**
+ * @brief Set clk freq.
+ * @param  clockName: CLOCK_Name id.
+ * @param  rate: clk rate.
+ * @return HAL_Status.
+ * @attention these APIs allow direct use in the HAL layer.
+ */
+HAL_Status HAL_CRU_ClkSetFreq(eCLOCK_Name clockName, uint32_t rate);
+
+/**
+ * @brief vop dclk enable.
+ * @param  gateId: gate id
+ * @return HAL_Status.
+ * @attention these APIs allow direct use in the HAL layer.
+ */
+HAL_Status HAL_CRU_VopDclkEnable(uint32_t gateId);
+
+/**
+ * @brief vop dclk disable.
+ * @param  gateId: gate id
+ * @return HAL_Status.
+ * @attention these APIs allow direct use in the HAL layer.
+ */
+HAL_Status HAL_CRU_VopDclkDisable(uint32_t gateId);
+
+/**
+ * @brief  Get Np5 best div.
+ * @param  clockName: clk id.
+ * @param  rate: clk rate.
+ * @param  pRate: clk parent rate
+ * @param  bestdiv: the returned bestdiv.
+ * @return HAL_Status.
+ */
+HAL_Status HAL_CRU_ClkNp5BestDiv(eCLOCK_Name clockName, uint32_t rate, uint32_t pRate, uint32_t *bestdiv);
+
+/**
+ * @brief  assert CRU global software reset.
+ * @param  type: global software reset type.
+ * @return HAL_INVAL if the SoC does not support.
+ */
+HAL_Status HAL_CRU_SetGlbSrst(eCRU_GlbSrstType type);
+
+/**
+ * @brief wdt glbrst enable.
+ * @param  wdtType: wdt reset type.
+ * @return HAL_OK.
+ * @attention these APIs allow direct use in the HAL layer.
+ */
+HAL_Status HAL_CRU_WdtGlbRstEnable(eCRU_WdtRstType wdtType);
+
+/**
+ * @brief pll output freq Compensation.
+ * @param  clockName: CLOCK_Name id.
+ * @param  ppm: Efforts to compensate.
+ * @return HAL_OK.
+ * @attention these APIs allow direct use in the HAL layer.
+ */
+HAL_Status HAL_CRU_PllCompensation(eCLOCK_Name clockName, int ppm);
+
+/**
+ * @brief CRU suspend.
+ * @return HAL_Status.
+ * @attention these APIs allow direct use in the HAL layer.
+ */
+HAL_Status HAL_CRU_Suspend(void);
+
+/**
+ * @brief CRU resume.
+ * @return HAL_Status.
+ * @attention these APIs allow direct use in the HAL layer.
+ */
+HAL_Status HAL_CRU_Resume(void);
+
+#ifdef HAL_CRU_AS_FEATURE_ENABLED
+/**
+ * @brief  it is for AS init.
+ */
+void HAL_CRU_AsInit(void);
+
+/**
+ * @brief  it is for AS enable.
+ * @param  ch: channel
+ * @param  en: 1 is enable, 0 is disable.
+ */
+void HAL_CRU_AsEnable(uint8_t ch, uint8_t en);
+#endif
+
+/** @} */
+
+#endif
+
+/** @} */
+
+/** @} */
+
+

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_debug.h

@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2018-2021 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _HAL_DEBUG_H_
+#define _HAL_DEBUG_H_
+
+#include "hal_def.h"
+#include "libserial.h"
+/** @addtogroup RK_HAL_Driver
+ *  @{
+ */
+
+/** @addtogroup DEBUG
+ *  @{
+ */
+
+/***************************** MACRO Definition ******************************/
+
+/* Run only for debugging, please refer to how-to-use for the definition of the specification. */
+//#define HAL_DBG_USING_RTT_SERIAL
+//#define HAL_DBG_USING_LIBC_PRINTF
+//#define HAL_DBG_USING_HAL_PRINTF
+
+#define HAL_SYSLOG printf
+
+/** @defgroup DEBUG_Exported_Definition_Group1 Basic Definition
+ *  @{
+ */
+
+#ifndef HAL_SYSLOG
+#define HAL_SYSLOG HAL_DBG_Printf
+#endif
+
+#if defined(HAL_DBG_ON) && defined(HAL_DBG_INFO_ON)
+#define HAL_DBG(fmt, arg...) HAL_SYSLOG("[HAL INFO] " fmt, ##arg)
+#else
+#define HAL_DBG(fmt, arg...) do { if (0) HAL_SYSLOG("[HAL INFO] " fmt, ##arg); } while (0)
+#endif
+
+#if defined(HAL_DBG_ON) && defined(HAL_DBG_WRN_ON)
+#define HAL_DBG_WRN(fmt, arg...) HAL_SYSLOG("[HAL WARNING] " fmt, ##arg)
+#else
+#define HAL_DBG_WRN(fmt, arg...) do { if (0) HAL_SYSLOG("[HAL WARNING] " fmt, ##arg); } while (0)
+#endif
+
+#if defined(HAL_DBG_ON) && defined(HAL_DBG_ERR_ON)
+#define HAL_DBG_ERR(fmt, arg...) HAL_SYSLOG("[HAL ERROR] " fmt, ##arg)
+#else
+#define HAL_DBG_ERR(fmt, arg...) do { if (0) HAL_SYSLOG("[HAL ERROR] " fmt, ##arg); } while (0)
+#endif
+
+#if defined(HAL_DBG_ON) && defined(HAL_ASSERT_ON)
+#define HAL_ASSERT(expr)                                        \
+    do {                                                        \
+        if (!(expr))                                            \
+            HAL_AssertFailed((const char *)__FILE__, __LINE__); \
+    } while (0)
+#else
+#define HAL_ASSERT(expr)
+#endif
+
+/***************************** Structure Definition **************************/
+
+/** @} */
+/***************************** Function Declare ******************************/
+/** @defgroup DEBUG_Public_Function_Declare Public Function Declare
+ *  @{
+ */
+
+void HAL_AssertFailed(const char *file, uint32_t line);
+HAL_Status HAL_DBG_HEX(char *s, void *buf, uint32_t width, uint32_t len);
+#ifdef __GNUC__
+__attribute__((__format__(printf, 1, 2)))
+#endif
+int32_t HAL_DBG_Printf(const char *format, ...);
+
+/** @} */
+
+#endif
+
+/** @} */
+
+/** @} */

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_def.h

@@ -0,0 +1,205 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ */
+
+/** @addtogroup RK_HAL_Driver
+ *  @{
+ */
+
+/** @addtogroup HAL_DEF
+ *  @{
+ */
+
+#ifndef _HAL_DEF_H_
+#define _HAL_DEF_H_
+
+// #include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdarg.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "soc.h"
+#include "hal_list.h"
+
+/***************************** MACRO Definition ******************************/
+/** @defgroup HAL_DEF_Exported_Definition_Group1 Basic Definition
+ *  @{
+ */
+
+#define SET_BIT(REG, BIT)    ((*(volatile uint32_t *)&(REG)) |= (BIT))        /**< Set 1 to the register specific bit field */
+#define CLEAR_BIT(REG, MASK) ((*(volatile uint32_t *)&(REG)) &= ~(MASK))      /**< Clear the specific bits filed from the register */
+#define READ_BIT(REG, MASK)  ((*(volatile const uint32_t *)&(REG)) & (MASK))  /**< Read the value of a specific bits field from the register */
+#define CLEAR_REG(REG)       ((*(volatile uint32_t *)&(REG)) = (0x0))         /**< Write 0 to the register */
+#define WRITE_REG(REG, VAL)  ((*(volatile uint32_t *)&(REG)) = (VAL))         /**< Write the register */
+#define READ_REG(REG)        ((*(volatile const uint32_t *)&(REG)))           /**< Read the register */
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) \
+        WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))    /**< Clear and set the value of a specific bits field from the register */
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+
+#if defined(__GNUC__) || defined(__CC_ARM)
+#define MASK_TO_WE(msk) (__builtin_constant_p(msk) ? ((msk) > 0xFFFFU ? 0 : ((msk) << 16)) : ((msk) << 16))
+#else
+#define MASK_TO_WE(msk) ((msk) << 16)
+#endif
+#define VAL_MASK_WE(msk, val)            ((MASK_TO_WE(msk)) | (val))
+#define WRITE_REG_MASK_WE(reg, msk, val) WRITE_REG(reg, (VAL_MASK_WE(msk, val)))
+
+/* Misc OPS Marco */
+#define HAL_MAX_DELAY 0xFFFFFFFFU
+
+#define RESET                     0
+#define HAL_IS_BIT_SET(REG, MASK) (((*(volatile uint32_t *)&(REG)) & (MASK)) != RESET)  /**< Check if the the specific bits filed from the register is valid */
+#define HAL_IS_BIT_CLR(REG, MASK) (((*(volatile uint32_t *)&(REG)) & (MASK)) == RESET)  /**< Check if the the specific bits filed from the register is isvalid */
+
+#define HAL_BIT(nr)       (1UL << (nr))
+#define HAL_ARRAY_SIZE(a) (sizeof((a)) / sizeof((a)[0]))
+#define HAL_MAX(x, y)     ((x) > (y) ? (x) : (y))
+#define HAL_MIN(x, y)     ((x) < (y) ? (x) : (y))
+
+#define HAL_DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
+
+#define HAL_IS_ALIGNED(x, a) (((x) & (a - 1)) == 0)
+#ifdef CACHE_LINE_SIZE
+#define HAL_IS_CACHELINE_ALIGNED(x) HAL_IS_ALIGNED((uint32_t)(x), CACHE_LINE_SIZE)
+#else
+#define HAL_IS_CACHELINE_ALIGNED(x) HAL_IS_ALIGNED((uint32_t)(x), 4)
+#endif
+
+/* Compiller Macro */
+#if defined(__GNUC__) || defined(__clang__) || defined(__CC_ARM) || defined(__ICCARM__)
+#define HAL_UNUSED __attribute__((__unused__))
+#else
+#define HAL_UNUSED
+#endif
+
+#ifdef CACHE_LINE_SIZE
+#define HAL_CACHELINE_ALIGNED __ALIGNED(CACHE_LINE_SIZE)
+#else
+#define HAL_CACHELINE_ALIGNED
+#endif
+
+#ifdef HAL_SRAM_SECTION_ENABLED
+#define HAL_SECTION_SRAM_CODE   __attribute__((section(".sram_code")))
+#define HAL_SECTION_SRAM_RODATA __attribute__((section(".sram_rodata")))
+#define HAL_SECTION_SRAM_DATA   __attribute__((section(".sram_data")))
+#define HAL_SECTION_SRAM_BSS    __attribute__((section(".sram_bss")))
+#else
+#define HAL_SECTION_SRAM_CODE
+#define HAL_SECTION_SRAM_RODATA
+#define HAL_SECTION_SRAM_DATA
+#define HAL_SECTION_SRAM_BSS
+#endif
+
+#ifdef HAL_PSRAM_SECTION_ENABLED
+#define HAL_SECTION_PSRAM_CODE   __attribute__((section(".psram_code")))
+#define HAL_SECTION_PSRAM_RODATA __attribute__((section(".psram_rodata")))
+#define HAL_SECTION_PSRAM_DATA   __attribute__((section(".psram_data")))
+#define HAL_SECTION_PSRAM_BSS    __attribute__((section(".psram_bss")))
+#else
+#define HAL_SECTION_PSRAM_CODE
+#define HAL_SECTION_PSRAM_RODATA
+#define HAL_SECTION_PSRAM_DATA
+#define HAL_SECTION_PSRAM_BSS
+#endif
+
+#ifdef HAL_XIP_SECTION_ENABLED
+#define HAL_SECTION_XIP_CODE   __attribute__((section(".xip_code")))
+#define HAL_SECTION_XIP_RODATA __attribute__((section(".xip_rodata")))
+#else
+#define HAL_SECTION_XIP_CODE
+#define HAL_SECTION_XIP_RODATA
+#endif
+
+#define HAL_GENMASK(h, l)       (((~0U) << (l)) & (~0U >> (32 - 1 - (h))))
+#define HAL_GENVAL(x, h, l)     ((uint32_t)(((x) & HAL_GENMASK(h, l)) >> (l)))
+#define HAL_GENMASK_ULL(h, l)   (((~0ULL) << (l)) & (~0ULL >> (64 - 1 - (h))))
+#define HAL_GENVAL_ULL(x, h, l) ((uint64_t)(((x) & HAL_GENMASK_ULL(h, l)) >> (l)))
+
+/** MCU systick clock source */
+typedef enum {
+    HAL_SYSTICK_CLKSRC_CORE,
+    HAL_SYSTICK_CLKSRC_EXT
+} eHAL_systickClkSource;
+
+/** Check if is MCU systick clock source */
+#define IS_SYSTICK_SOURCE(s) (((s) == HAL_SYSTICK_CLKSRC_CORE) || ((s) == HAL_SYSTICK_CLKSRC_EXT))
+
+/***************************** Structure Definition **************************/
+/** HAL boolean type definition */
+typedef enum {
+    HAL_FALSE = 0x00U,
+    HAL_TRUE  = 0x01U
+} HAL_Check;
+
+/** HAL error code definition */
+typedef enum {
+    HAL_OK      = 0x00U,
+    HAL_ERROR   = (-1),
+    HAL_BUSY    = (-16),
+    HAL_NODEV   = (-19),
+    HAL_INVAL   = (-22),
+    HAL_NOSYS   = (-38),
+    HAL_TIMEOUT = (-110)
+} HAL_Status;
+
+/** HAL functional status definition */
+typedef enum {
+    HAL_DISABLE = 0x00U,
+    HAL_ENABLE  = 0x01U
+} HAL_FuncStatus;
+
+/** HAL lock structures definition */
+typedef enum {
+    HAL_UNLOCKED = 0x00U,
+    HAL_LOCKED   = 0x01U
+} HAL_LockStatus;
+
+/** RK GPIO bank definition */
+typedef enum {
+#ifdef GPIO0
+    GPIO_BANK0 = 0,
+#endif
+#ifdef GPIO1
+    GPIO_BANK1 = 1,
+#endif
+#ifdef GPIO2
+    GPIO_BANK2 = 2,
+#endif
+#ifdef GPIO3
+    GPIO_BANK3 = 3,
+#endif
+#ifdef GPIO4
+    GPIO_BANK4 = 4,
+#endif
+#ifdef GPIO0_EXP
+    GPIO_BANK0_EXP = 5,
+#endif
+#ifdef GPIO1_EXP
+    GPIO_BANK1_EXP = 6,
+#endif
+#ifdef GPIO2_EXP
+    GPIO_BANK2_EXP = 7,
+#endif
+#ifdef GPIO3_EXP
+    GPIO_BANK3_EXP = 8,
+#endif
+#ifdef GPIO4_EXP
+    GPIO_BANK4_EXP = 9,
+#endif
+    GPIO_BANK_NUM
+} eGPIO_bankId;
+
+/** HAL function type definition */
+typedef void (*pFunc)(void);
+
+/** @} */
+/***************************** Function Declare ******************************/
+
+#endif
+
+/** @} */
+
+/** @} */

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_gmac.h

@@ -0,0 +1,425 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ */
+
+/** @addtogroup RK_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GMAC
+  * @{
+  */
+
+#ifndef __HAL_GMAC_H
+#define __HAL_GMAC_H
+
+#include "hal_def.h"
+#include "hal_base.h"
+
+/***************************** MACRO Definition ******************************/
+/** @defgroup GMAC_Exported_Definition_Group1 Basic Definition
+ *  @{
+ */
+
+/* GMAC PHY indicates what features are supported by the interface. */
+#define HAL_GMAC_PHY_SUPPORTED_10baseT_Half      (1 << 0)
+#define HAL_GMAC_PHY_SUPPORTED_10baseT_Full      (1 << 1)
+#define HAL_GMAC_PHY_SUPPORTED_100baseT_Half     (1 << 2)
+#define HAL_GMAC_PHY_SUPPORTED_100baseT_Full     (1 << 3)
+#define HAL_GMAC_PHY_SUPPORTED_1000baseT_Half    (1 << 4)
+#define HAL_GMAC_PHY_SUPPORTED_1000baseT_Full    (1 << 5)
+#define HAL_GMAC_PHY_SUPPORTED_Autoneg           (1 << 6)
+#define HAL_GMAC_PHY_SUPPORTED_TP                (1 << 7)
+#define HAL_GMAC_PHY_SUPPORTED_AUI               (1 << 8)
+#define HAL_GMAC_PHY_SUPPORTED_MII               (1 << 9)
+#define HAL_GMAC_PHY_SUPPORTED_FIBRE             (1 << 10)
+#define HAL_GMAC_PHY_SUPPORTED_BNC               (1 << 11)
+#define HAL_GMAC_PHY_SUPPORTED_10000baseT_Full   (1 << 12)
+#define HAL_GMAC_PHY_SUPPORTED_Pause             (1 << 13)
+#define HAL_GMAC_PHY_SUPPORTED_Asym_Pause        (1 << 14)
+#define HAL_GMAC_PHY_SUPPORTED_2500baseX_Full    (1 << 15)
+#define HAL_GMAC_PHY_SUPPORTED_Backplane         (1 << 16)
+#define HAL_GMAC_PHY_SUPPORTED_1000baseKX_Full   (1 << 17)
+#define HAL_GMAC_PHY_SUPPORTED_10000baseKX4_Full (1 << 18)
+#define HAL_GMAC_PHY_SUPPORTED_10000baseKR_Full  (1 << 19)
+#define HAL_GMAC_PHY_SUPPORTED_10000baseR_FEC    (1 << 20)
+#define HAL_GMAC_PHY_SUPPORTED_1000baseX_Half    (1 << 21)
+#define HAL_GMAC_PHY_SUPPORTED_1000baseX_Full    (1 << 22)
+
+#define HAL_GMAC_PHY_DEFAULT_FEATURES (HAL_GMAC_PHY_SUPPORTED_Autoneg | \
+                                       HAL_GMAC_PHY_SUPPORTED_TP |      \
+                                       HAL_GMAC_PHY_SUPPORTED_MII)
+
+#define HAL_GMAC_PHY_10BT_FEATURES (HAL_GMAC_PHY_SUPPORTED_10baseT_Half | \
+                                    HAL_GMAC_PHY_SUPPORTED_10baseT_Full)
+
+#define HAL_GMAC_PHY_100BT_FEATURES (HAL_GMAC_PHY_SUPPORTED_100baseT_Half | \
+                                     HAL_GMAC_PHY_SUPPORTED_100baseT_Full)
+
+#define HAL_GMAC_PHY_1000BT_FEATURES (HAL_GMAC_PHY_SUPPORTED_1000baseT_Half | \
+                                      HAL_GMAC_PHY_SUPPORTED_1000baseT_Full)
+
+#define HAL_GMAC_PHY_BASIC_FEATURES (HAL_GMAC_PHY_10BT_FEATURES |  \
+                                     HAL_GMAC_PHY_100BT_FEATURES | \
+                                     HAL_GMAC_PHY_DEFAULT_FEATURES)
+
+#define HAL_GMAC_PHY_GBIT_FEATURES (HAL_GMAC_PHY_BASIC_FEATURES | \
+                                    HAL_GMAC_PHY_1000BT_FEATURES)
+
+/* GMAC flow ctrl Definition */
+#define HAL_GMAC_FLOW_OFF  0
+#define HAL_GMAC_FLOW_RX   1
+#define HAL_GMAC_FLOW_TX   2
+#define HAL_GMAC_FLOW_AUTO (HAL_GMAC_FLOW_TX | HAL_GMAC_FLOW_RX)
+
+/* GMAC descriptions and buffers Definition */
+#define HAL_GMAC_ALIGN(x, a)      (((x) + (a) - 1) & ~((a) - 1))
+#define HAL_GMAC_DESCRIPTOR_WORDS 4
+#define HAL_GMAC_DESCRIPTOR_SIZE  (HAL_GMAC_DESCRIPTOR_WORDS * 4)
+#define HAL_GMAC_BUFFER_ALIGN     64
+#define HAL_GMAC_MAX_FRAME_SIZE   1518
+#define HAL_GMAC_MAX_PACKET_SIZE  HAL_GMAC_ALIGN(HAL_GMAC_MAX_FRAME_SIZE, HAL_GMAC_BUFFER_ALIGN)
+
+/***************************** Structure Definition **************************/
+struct GMAC_HANDLE;
+
+/**
+  * @brief  GMAC PHY Speed
+  */
+typedef enum {
+    PHY_SPEED_10M   = 10,
+    PHY_SPEED_100M  = 100,
+    PHY_SPEED_1000M = 1000,
+} eGMAC_PHY_SPEED;
+
+/**
+ * @brief  GMAC PHY Duplex
+ */
+typedef enum {
+    PHY_DUPLEX_HALF = 0,
+    PHY_DUPLEX_FULL = 1,
+} eGMAC_PHY_DUPLEX;
+
+/**
+ * @brief  GMAC PHY Auto Negrotetion
+ */
+typedef enum {
+    PHY_AUTONEG_DISABLE = 0,
+    PHY_AUTONEG_ENABLE  = 1,
+} eGMAC_PHY_NEGROTETION;
+
+/**
+  * @brief  GMAC PHY Interface Mode
+  */
+typedef enum {
+    PHY_INTERFACE_MODE_MII,
+    PHY_INTERFACE_MODE_RMII,
+    PHY_INTERFACE_MODE_RGMII,
+    PHY_INTERFACE_MODE_NONE,
+} eGMAC_PHY_Interface;
+
+/**
+  * @brief  GMAC DMA IRQ Status
+  */
+typedef enum {
+    DMA_UNKNOWN  = 0x0,
+    DMA_HANLE_RX = 0x1,
+    DMA_HANLE_TX = 0x2,
+    DMA_TX_ERROR = 0x10,
+    DMA_RX_ERROR = 0x20,
+} eGMAC_IRQ_Status;
+
+/**
+  * @brief  GMAC PHY OPS Structure Definition
+  */
+struct GMAC_PHY_OPS {
+    HAL_Status (*init)(struct GMAC_HANDLE *pGMAC);     /**< Will be called during HAL_GMAC_PHYInit(). */
+    HAL_Status (*config)(struct GMAC_HANDLE *pGMAC);   /**< Called to configure the PHY, and modify the PHY,
+                                                            based on the results. Should be called after HAL_GMAC_PHYInit(). */
+    HAL_Status (*startup)(struct GMAC_HANDLE *pGMAC);  /**< Called when starting up the PHY */
+    HAL_Status (*shutdown)(struct GMAC_HANDLE *pGMAC); /**< Called when bringing down the PHY */
+    HAL_Status (*reset)(struct GMAC_HANDLE *pGMAC);    /**< Called when hardware reset */
+    HAL_Status (*softreset)(struct GMAC_HANDLE *pGMAC);/**< Called when soft reset */
+};
+
+/**
+  * @brief  GMAC PHY Config Structure Definition
+  */
+struct GMAC_PHY_Config {
+    eGMAC_PHY_Interface interface;/**< Ethernet interface mode. */
+    int16_t phyAddress;           /**< Ethernet PHY address,
+                                       This parameter must be a number between Min = 0 and Max = 31 */
+    eGMAC_PHY_NEGROTETION neg;    /**< Selects or disable the AutoNegotiation mode for the external PHY,
+                                       The AutoNegotiation allows an automatic setting of the Speed
+                                       (10/100/1000 Mbps) and the mode (half/full-duplex). */
+    eGMAC_PHY_SPEED speed;        /**< Sets the Ethernet speed: 10/100/1000 Mbps
+                                       while disable AutoNegotiation. */
+    eGMAC_PHY_DUPLEX duplexMode;  /**< Selects the Ethernet duplex mode: Half-Duplex or
+                                       Full-Duplex mode while disable AutoNegotiation. */
+    eGMAC_PHY_SPEED maxSpeed;     /**< Sets the Ethernet max speed: 10/100/1000 Mbps. */
+    uint32_t features;            /**< Sets the Ethernet PHY features. */
+};
+
+/**
+  * @brief  GMAC PHY Status Structure Definition
+  */
+struct GMAC_PHY_STATUS {
+    eGMAC_PHY_Interface interface;    /**< Ethernet interface mode. */
+
+    /* forced speed & duplex (no autoneg)
+     * partner speed & duplex & pause (autoneg)
+     */
+    eGMAC_PHY_SPEED speed;            /**< Ethernet speed. */
+    eGMAC_PHY_DUPLEX duplex;          /**< Ethernet duplex. */
+    eGMAC_PHY_SPEED maxSpeed;         /**< Ethernet max speed. */
+    eGMAC_PHY_NEGROTETION neg;        /**< Ethernet AutoNegotiation or not. */
+
+    /* The most recently read link state */
+    int link;                         /**< Ethernet current link. */
+    int oldLink;                      /**< Store the Ethernet last link. */
+
+    uint32_t features;                /**< Ethernet PHY actual features. */
+    uint32_t advertising;             /**< Ethernet PHY advertising features. */
+    uint32_t supported;               /**< Ethernet PHY supported features. */
+
+    int16_t addr;                     /**< Ethernet PHY address. */
+    int16_t pause;                    /**< Ethernet PHY address. */
+    uint32_t phyID;                   /**< Ethernet PHY ID. */
+};
+
+/**
+  * @brief  GMAC Link Config Structure Definition
+  */
+struct GMAC_Link {
+    uint32_t speedMask;
+    uint32_t speed10;
+    uint32_t speed100;
+    uint32_t speed1000;
+    uint32_t duplex;
+};
+
+/**
+  * @brief  GMAC DMA Descriptors Data Structure Definition
+  */
+struct GMAC_Desc {
+    uint32_t des0; /**< DMA Descriptors first word */
+    uint32_t des1; /**< DMA Descriptors second word */
+    uint32_t des2; /**< DMA Descriptors third word */
+    uint32_t des3; /**< DMA Descriptors four word */
+};
+
+/**
+  * @brief  GMAC DMA Transfer Status Structure Definition
+  */
+struct GMAC_DMAStats {
+    uint32_t txUndeflowIRQ;
+    uint32_t txProcessStoppedIRQ;
+    uint32_t txJabberIRQ;
+    uint32_t rxOverflowIRQ;
+    uint32_t rxBufUnavIRQ;
+    uint32_t rxProcessStoppedIRQ;
+    uint32_t rxWatchdogIRQ;
+    uint32_t txEarlyIRQ;
+    uint32_t fatalBusErrorIRQ;
+    uint32_t normalIRQN;
+    uint32_t rxNormalIRQN;
+    uint32_t txNormallIRQN;
+
+    uint32_t rxEarlyIRQ;
+    uint32_t thresHold;
+    uint32_t txPktN;
+    uint32_t rxPktN;
+    uint32_t txBytesN;
+    uint32_t rxBytesN;
+    uint32_t txErrors;
+    uint32_t rxErrors;
+};
+
+/**
+  * @brief  GMAC device information Structure Definition
+  */
+struct GMAC_DEVICE_INFO {
+    uint32_t miiAddrShift;
+    uint32_t miiAddrMask;
+    uint32_t miiRegShift;
+    uint32_t miiRegMask;
+    uint32_t clkCsrShift;
+    uint32_t clkCsrMask;
+};
+
+/**
+  * @brief  GMAC Handle Structure Definition
+  */
+struct GMAC_HANDLE {
+    struct GMAC_REG *pReg;                /**< Register base address */
+    uint32_t clkCSR;                      /**< clock csr value, div for MDC clock */
+
+    struct GMAC_DEVICE_INFO mac;          /**< MAC information */
+
+    struct GMAC_PHY_OPS phyOps;           /**< phy ops callback function */
+    struct GMAC_PHY_Config phyConfig;     /**< phy config provied by user */
+    struct GMAC_PHY_STATUS phyStatus;     /**< phy status */
+
+    struct GMAC_Link link;                /**< GMAC link config */
+    struct GMAC_DMAStats extraStatus;     /**< GMAC DMA transfer status */
+
+    struct GMAC_Desc *rxDescs;            /**< First Rx descriptor pointer */
+    struct GMAC_Desc *txDescs;            /**< First Tx descriptor pointer */
+    uint8_t *txBuf;                       /**< First Tx buffer pointer */
+    uint8_t *rxBuf;                       /**< First Tx buffer pointer */
+    uint32_t txDescIdx;                   /**< Current Tx descriptor index */
+    uint32_t rxDescIdx;                   /**< Current Rx descriptor pointer */
+    uint32_t txSize;                      /**< Tx descriptor size*/
+    uint32_t rxSize;                      /**< Rx descriptor size */
+};
+
+
+#define PM_RUNTIME_TYPE_MUTI_SFT (3)
+#define PM_RUNTIME_PER_TYPE_NUM  (8)
+
+#define PM_RUNTIME_TYPE_TO_FIRST_ID(type) ((type) << PM_RUNTIME_TYPE_MUTI_SFT)
+#define PM_RUNTIME_ID_TO_TYPE(id)         ((id) >> PM_RUNTIME_TYPE_MUTI_SFT)
+#define PM_RUNTIME_ID_TO_TYPE_OFFSET(id)  ((id) % PM_RUNTIME_PER_TYPE_NUM)
+#define PM_RUNTIME_ID_TYPE_BIT_MSK(id)    HAL_BIT(((id) % PM_RUNTIME_PER_TYPE_NUM))
+
+#define PM_DISPLAY_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_DISPLAY])
+#define PM_UART_REQUESTED(pdata)    ((pdata)->bits[PM_RUNTIME_TYPE_UART])
+#define PM_I2C_REQUESTED(pdata)     ((pdata)->bits[PM_RUNTIME_TYPE_I2C])
+#define PM_INTF_REQUESTED(pdata)    ((pdata)->bits[PM_RUNTIME_TYPE_INTF])
+#define PM_HS_INTF_REQUESTED(pdata) ((pdata)->bits[PM_RUNTIME_TYPE_HS_INTF])
+#define PM_SPI_REQUESTED(pdata)     ((pdata)->bits[PM_RUNTIME_TYPE_SPI])
+#define PM_CIF_REQUESTED(pdata)     ((pdata)->bits[PM_RUNTIME_TYPE_CIF])
+
+/* suspend config id */
+#define PM_SLEEP_MODE_CONFIG   0x01
+#define PM_SLEEP_WAKEUP_SOURCE 0x02
+
+enum {
+    PM_RUNTIME_TYPE_INTF = 0, /**< normal interface */
+    PM_RUNTIME_TYPE_DISPLAY,
+    PM_RUNTIME_TYPE_AUDIO,
+    PM_RUNTIME_TYPE_HS_INTF, /**< high speed interface */
+    PM_RUNTIME_TYPE_STORAGE,
+    PM_RUNTIME_TYPE_UART,
+    PM_RUNTIME_TYPE_I2C,
+    PM_RUNTIME_TYPE_SPI,
+    PM_RUNTIME_TYPE_CIF,
+    PM_RUNTIME_TYPE_DEVICE,
+    PM_RUNTIME_TYPE_END,
+};
+
+typedef enum {
+    PM_RUNTIME_IDLE_ONLY = 0,
+    PM_RUNTIME_IDLE_NORMAL,
+    PM_RUNTIME_IDLE_DEEP,
+    PM_RUNTIME_IDLE_DEEP1,
+    PM_RUNTIME_IDLE_DEEP2,
+} ePM_RUNTIME_idleMode;
+
+typedef enum {
+    PM_RUNTIME_ID_INTF_INVLD = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_INTF), /**< the id = 0, is means invalid */
+    PM_RUNTIME_ID_SPI_APB,
+    PM_RUNTIME_ID_VOP = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_DISPLAY),
+    PM_RUNTIME_ID_MIPI,
+
+    PM_RUNTIME_ID_I2S = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_AUDIO),
+    PM_RUNTIME_ID_I2S1,
+    PM_RUNTIME_ID_I2S2,
+    PM_RUNTIME_ID_ADC,
+    PM_RUNTIME_ID_DMA,
+
+    PM_RUNTIME_ID_USB = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_HS_INTF),
+    PM_RUNTIME_ID_SDIO,
+
+    PM_RUNTIME_ID_UART0 = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_UART),
+    PM_RUNTIME_ID_UART1,
+    PM_RUNTIME_ID_UART2,
+    PM_RUNTIME_ID_UART3,
+    PM_RUNTIME_ID_UART4,
+    PM_RUNTIME_ID_UART5,
+    PM_RUNTIME_ID_UART6,
+    PM_RUNTIME_ID_UART7,
+    PM_RUNTIME_ID_UART8,
+    PM_RUNTIME_ID_UART9,
+
+    PM_RUNTIME_ID_I2C0 = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_I2C),
+    PM_RUNTIME_ID_I2C1,
+    PM_RUNTIME_ID_I2C2,
+    PM_RUNTIME_ID_I2C3,
+    PM_RUNTIME_ID_I2C4,
+    PM_RUNTIME_ID_I2C5,
+
+    PM_RUNTIME_ID_SPI = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_SPI),
+    PM_RUNTIME_ID_CIF = PM_RUNTIME_TYPE_TO_FIRST_ID(PM_RUNTIME_TYPE_CIF),
+
+    PM_RUNTIME_ID_END,
+} ePM_RUNTIME_ID;
+/**
+  * @brief  GMAC HW Information Definition
+  */
+struct HAL_GMAC_DEV {
+    struct GMAC_REG *pReg;
+    eCLOCK_Name clkID;
+    uint32_t clkGateID;
+    eCLOCK_Name pclkID;
+    uint32_t pclkGateID;
+    IRQn_Type irqNum;
+    ePM_RUNTIME_ID runtimeID;
+};
+
+/** @} */
+
+/***************************** Function Declare ******************************/
+/** @defgroup GMAC_Public_Function_Declare Public Function Declare
+ *  @{
+ */
+HAL_Status HAL_GMAC_Init(struct GMAC_HANDLE *pGMAC, struct GMAC_REG *pReg,
+                         uint32_t freq, eGMAC_PHY_Interface interface,
+                         bool extClk);
+HAL_Status HAL_GMAC_DeInit(struct GMAC_HANDLE *pGMAC);
+HAL_Status HAL_GMAC_Start(struct GMAC_HANDLE *pGMAC, uint8_t *addr);
+HAL_Status HAL_GMAC_Stop(struct GMAC_HANDLE *pGMAC);
+void HAL_GMAC_EnableDmaIRQ(struct GMAC_HANDLE *pGMAC);
+void HAL_GMAC_DisableDmaIRQ(struct GMAC_HANDLE *pGMAC);
+HAL_Status HAL_GMAC_DMATxDescInit(struct GMAC_HANDLE *pGMAC,
+                                  struct GMAC_Desc *txDescs,
+                                  uint8_t *txBuff, uint32_t txBuffCount);
+HAL_Status HAL_GMAC_DMARxDescInit(struct GMAC_HANDLE *pGMAC,
+                                  struct GMAC_Desc *rxDescs,
+                                  uint8_t *rxBuff, uint32_t rxBuffCount);
+eGMAC_IRQ_Status HAL_GMAC_IRQHandler(struct GMAC_HANDLE *pGMAC);
+HAL_Status HAL_GMAC_AdjustLink(struct GMAC_HANDLE *pGMAC, int32_t txDelay,
+                               int32_t rxDelay);
+uint32_t HAL_GMAC_GetTXIndex(struct GMAC_HANDLE *pGMAC);
+uint32_t HAL_GMAC_GetRXIndex(struct GMAC_HANDLE *pGMAC);
+uint8_t *HAL_GMAC_GetTXBuffer(struct GMAC_HANDLE *pGMAC);
+uint8_t *HAL_GMAC_GetRXBuffer(struct GMAC_HANDLE *pGMAC);
+HAL_Status HAL_GMAC_Send(struct GMAC_HANDLE *pGMAC,
+                         void *packet, uint32_t length);
+uint8_t *HAL_GMAC_Recv(struct GMAC_HANDLE *pGMAC, int32_t *length);
+void HAL_GMAC_CleanRX(struct GMAC_HANDLE *pGMAC);
+void HAL_GMAC_WriteHWAddr(struct GMAC_HANDLE *pGMAC, uint8_t *enetAddr);
+HAL_Status HAL_GMAC_PHYInit(struct GMAC_HANDLE *pGMAC,
+                            struct GMAC_PHY_Config *config);
+HAL_Status HAL_GMAC_PHYStartup(struct GMAC_HANDLE *pGMAC);
+HAL_Status HAL_GMAC_PHYUpdateLink(struct GMAC_HANDLE *pGMAC);
+HAL_Status HAL_GMAC_PHYParseLink(struct GMAC_HANDLE *pGMAC);
+int32_t HAL_GMAC_MDIORead(struct GMAC_HANDLE *pGMAC, int32_t mdioAddr,
+                          int32_t mdioReg);
+HAL_Status HAL_GMAC_MDIOWrite(struct GMAC_HANDLE *pGMAC, int32_t mdioAddr,
+                              int32_t mdioReg, uint16_t mdioVal);
+void HAL_GMAC_SetToRGMII(struct GMAC_HANDLE *pGMAC,
+                         int32_t txDelay, int32_t rxDelay);
+void HAL_GMAC_SetToRMII(struct GMAC_HANDLE *pGMAC);
+void HAL_GMAC_SetRGMIISpeed(struct GMAC_HANDLE *pGMAC, int32_t speed);
+void HAL_GMAC_SetRMIISpeed(struct GMAC_HANDLE *pGMAC, int32_t speed);
+void HAL_GMAC_SetExtclkSrc(struct GMAC_HANDLE *pGMAC, bool extClk);
+
+/** @} */
+
+#endif
+
+/** @} */
+
+/** @} */

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_gpio.h

@@ -0,0 +1,169 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ */
+
+
+/** @addtogroup RK_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+
+#ifndef __HAL_GPIO_H
+#define __HAL_GPIO_H
+
+#include "hal_def.h"
+#include "hal_pinctrl.h"
+
+/***************************** MACRO Definition ******************************/
+/** @defgroup GPIO_Exported_Definition_Group1 Basic Definition
+ *  @{
+ */
+
+#ifndef GPIO_VER_ID
+#define GPIO_VER_ID (0U)
+#endif
+
+#define PIN_NUMBER_PER_BANK (32)
+
+#define GPIO_PIN_SHIFT  (0) /**< Bits 0-4: GPIO Pin number: 0 - 31 */
+#define GPIO_PIN_MASK   (0x1f << GPIO_PIN_SHIFT)
+#define GPIO_BANK_SHIFT (5) /**< Bits 5-7: GPIO Port number: 0 - 7 */
+#define GPIO_BANK_MASK  (0x7 << GPIO_BANK_SHIFT)
+
+#define BANK_PIN(BANK, PIN) ((((BANK) << GPIO_BANK_SHIFT) & GPIO_BANK_MASK) + (((PIN) << GPIO_PIN_SHIFT) & GPIO_PIN_MASK))
+
+/***************************** Structure Definition **************************/
+/** GPIO pin level definition */
+typedef enum {
+    GPIO_LOW,
+    GPIO_HIGH
+} eGPIO_pinLevel;
+
+/** GPIO pin direction definition */
+typedef enum {
+    GPIO_IN,
+    GPIO_OUT
+} eGPIO_pinDirection;
+
+/** GPIO pin debounce definition */
+typedef enum {
+    GPIO_DEBOUNCE_DIS,
+    GPIO_DEBOUNCE_EN
+} eGPIO_pinDebounce;
+
+/** GPIO pin interrupt enable definition */
+typedef enum {
+    GPIO_INT_DISABLE,
+    GPIO_INT_ENABLE
+} eGPIO_intEnable;
+
+/** GPIO pin interrupt type definition */
+typedef enum {
+    GPIO_INT_TYPE_NONE         = 0x00000000,
+    GPIO_INT_TYPE_EDGE_RISING  = 0x00000001,
+    GPIO_INT_TYPE_EDGE_FALLING = 0x00000002,
+    GPIO_INT_TYPE_EDGE_BOTH    = (GPIO_INT_TYPE_EDGE_FALLING | GPIO_INT_TYPE_EDGE_RISING),
+    GPIO_INT_TYPE_LEVEL_HIGH   = 0x00000004,
+    GPIO_INT_TYPE_LEVEL_LOW    = 0x00000008,
+    GPIO_INT_TYPE_LEVEL_MASK   = (GPIO_INT_TYPE_LEVEL_LOW | GPIO_INT_TYPE_LEVEL_HIGH),
+    GPIO_INT_TYPE_SENSE_MASK   = 0x0000000f,
+    GPIO_INT_TYPE_DEFAULT      = GPIO_INT_TYPE_SENSE_MASK,
+} eGPIO_intType;
+
+/** GPIO pin interrupt mode definition */
+typedef enum {
+    GPIO_INT_MODE_EDGE_RISING,
+    GPIO_INT_MODE_EDGE_FALLING,
+    GPIO_INT_MODE_EDGE_RISING_FALLING,
+    GPIO_INT_MODE_LEVEL_HIGH,
+    GPIO_INT_MODE_LEVEL_LOW,
+    GPIO_INT_MODE_INVALID
+} eGPIO_intMode;
+
+/** GPIO pin virtual model definition */
+typedef enum {
+    GPIO_VIRTUAL_MODEL_OS_A,
+    GPIO_VIRTUAL_MODEL_OS_B,
+    GPIO_VIRTUAL_MODEL_OS_C,
+    GPIO_VIRTUAL_MODEL_OS_D,
+} eGPIO_VirtualModel;
+
+#define IS_GPIO_PIN_DIR(ACTION)   (((ACTION) == GPIO_IN) || ((ACTION) == GPIO_OUT))
+#define IS_GPIO_PIN_LEVEL(ACTION) (((ACTION) == GPIO_LOW) || ((ACTION) == GPIO_HIGH))
+
+#define IS_GPIO_PIN(PIN)      ((PIN) != 0x00000000U)
+#define IS_GPIO_HIGH_PIN(PIN) IS_GPIO_PIN(((PIN) & 0xFFFF0000U))
+
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_PIN_A0) || \
+                              ((PIN) == GPIO_PIN_A1) || \
+                              ((PIN) == GPIO_PIN_A2) || \
+                              ((PIN) == GPIO_PIN_A3) || \
+                              ((PIN) == GPIO_PIN_A4) || \
+                              ((PIN) == GPIO_PIN_A5) || \
+                              ((PIN) == GPIO_PIN_A6) || \
+                              ((PIN) == GPIO_PIN_A7) || \
+                              ((PIN) == GPIO_PIN_B0) || \
+                              ((PIN) == GPIO_PIN_B1) || \
+                              ((PIN) == GPIO_PIN_B2) || \
+                              ((PIN) == GPIO_PIN_B3) || \
+                              ((PIN) == GPIO_PIN_B4) || \
+                              ((PIN) == GPIO_PIN_B5) || \
+                              ((PIN) == GPIO_PIN_B6) || \
+                              ((PIN) == GPIO_PIN_B7) || \
+                              ((PIN) == GPIO_PIN_C0) || \
+                              ((PIN) == GPIO_PIN_C1) || \
+                              ((PIN) == GPIO_PIN_C2) || \
+                              ((PIN) == GPIO_PIN_C3) || \
+                              ((PIN) == GPIO_PIN_C4) || \
+                              ((PIN) == GPIO_PIN_C5) || \
+                              ((PIN) == GPIO_PIN_C6) || \
+                              ((PIN) == GPIO_PIN_C7) || \
+                              ((PIN) == GPIO_PIN_D0) || \
+                              ((PIN) == GPIO_PIN_D1) || \
+                              ((PIN) == GPIO_PIN_D2) || \
+                              ((PIN) == GPIO_PIN_D3) || \
+                              ((PIN) == GPIO_PIN_D4) || \
+                              ((PIN) == GPIO_PIN_D5) || \
+                              ((PIN) == GPIO_PIN_D6) || \
+                              ((PIN) == GPIO_PIN_D7))
+
+/** @} */
+/***************************** Function Declare ******************************/
+/** @defgroup GPIO_Exported_Definition_Group2 Public Functions Declare.
+ *  @{
+ */
+eGPIO_pinDirection HAL_GPIO_GetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin);
+eGPIO_pinLevel HAL_GPIO_GetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin);
+eGPIO_pinLevel HAL_GPIO_GetPinData(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin);
+uint32_t HAL_GPIO_GetBankLevel(struct GPIO_REG *pGPIO);
+
+HAL_Status HAL_GPIO_SetPinLevel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinLevel level);
+HAL_Status HAL_GPIO_SetPinDirection(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_pinDirection direction);
+HAL_Status HAL_GPIO_SetIntType(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_intType mode);
+
+HAL_Status HAL_GPIO_SetPinsLevel(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinLevel level);
+HAL_Status HAL_GPIO_SetPinsDirection(struct GPIO_REG *pGPIO, uint32_t mPins, eGPIO_pinDirection direction);
+
+void HAL_GPIO_EnableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin);
+void HAL_GPIO_DisableIRQ(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin);
+void HAL_GPIO_IRQHandler(struct GPIO_REG *pGPIO, eGPIO_bankId bank);
+
+#ifdef HAL_GPIO_VIRTUAL_MODEL_FEATURE_ENABLED
+HAL_Status HAL_GPIO_EnableVirtualModel(struct GPIO_REG *pGPIO);
+HAL_Status HAL_GPIO_DisableVirtualModel(struct GPIO_REG *pGPIO);
+HAL_Status HAL_GPIO_SetVirtualModel(struct GPIO_REG *pGPIO, ePINCTRL_GPIO_PINS pin, eGPIO_VirtualModel vmodel);
+#endif
+
+/* The parameter pin for this function is special, it's 0~31. */
+void HAL_GPIO_IRQDispatch(eGPIO_bankId bank, uint32_t pin);
+
+/** @} */
+
+#endif
+/** @} */
+
+/** @} */

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_list.h

@@ -0,0 +1,181 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _HAL_LIST_H_
+#define _HAL_LIST_H_
+
+/***************************** Structure Definition **************************/
+
+/** double list struct */
+struct HAL_LIST_NODE {
+    struct HAL_LIST_NODE *next;
+    struct HAL_LIST_NODE *prev;
+};
+
+typedef struct HAL_LIST_NODE HAL_LIST;
+
+/***************************** Function Declare ******************************/
+/**
+ * @brief cast a member of a structure out to the containing structure
+ * @param ptr:    the pointer to the member.
+ * @param type:   the type of the container struct this is embedded in.
+ * @param member: the name of the member within the struct.
+ */
+#define HAL_CONTAINER_OF(ptr, type, member) \
+    ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member)))
+
+/**
+ * @brief initialize a list object
+ * @param object: object itself.
+ */
+#define HAL_LIST_OBJECT_INIT(object) { &(object), &(object) }
+
+#define HAL_LIST_HEAD_INIT(name) { &(name), &(name) }
+
+/**
+ * @brief initialize a list head
+ * @param name: list name..
+ */
+#define HAL_LIST_HEAD(name) \
+    struct HAL_LIST_NODE name = HAL_LIST_HEAD_INIT(name)
+
+/**
+ * @brief initialize a list
+ * @param l: list to be initialized
+ */
+static inline void HAL_LIST_Init(HAL_LIST *l)
+{
+    l->next = l->prev = l;
+}
+
+/**
+ * @brief insert a node after a list
+ * @param l: list to insert it
+ * @param n: new node to be inserted
+ */
+static inline void HAL_LIST_InsertAfter(HAL_LIST *l, HAL_LIST *n)
+{
+    l->next->prev = n;
+    n->next = l->next;
+
+    l->next = n;
+    n->prev = l;
+}
+
+/**
+ * @brief insert a node before a list
+ * @param n: new node to be inserted
+ * @param l: list to insert it
+ */
+static inline void HAL_LIST_InsertBefore(HAL_LIST *l, HAL_LIST *n)
+{
+    l->prev->next = n;
+    n->prev = l->prev;
+
+    l->prev = n;
+    n->next = l;
+}
+
+/**
+ * @brief remove node from list.
+ * @param n: the node to remove from the list.
+ */
+static inline void HAL_LIST_Remove(HAL_LIST *n)
+{
+    n->next->prev = n->prev;
+    n->prev->next = n->next;
+
+    n->next = n->prev = n;
+}
+
+/**
+ * @brief tests whether a list is empty
+ * @param l: the list to test.
+ */
+static inline int HAL_LIST_IsEmpty(const HAL_LIST *l)
+{
+    return l->next == l;
+}
+
+/**
+ * @brief get the list length
+ * @param l: the list to get.
+ */
+static inline uint32_t HAL_LIST_Len(const HAL_LIST *l)
+{
+    uint32_t len = 0;
+    const HAL_LIST *p = l;
+
+    while (p->next != l) {
+        p = p->next;
+        len++;
+    }
+
+    return len;
+}
+
+/**
+ * @brief get the struct for this entry
+ * @param node: the entry point
+ * @param type: the type of structure
+ * @param member: the name of list in structure
+ */
+#define HAL_LIST_ENTRY(node, type, member) \
+    HAL_CONTAINER_OF(node, type, member)
+
+/**
+ * @brief iterate over a list
+ * @param pos:  the rt_list_t * to use as a loop cursor.
+ * @param head: the head for your list.
+ */
+#define HAL_LIST_FOR_EACH(pos, head) \
+    for (pos = (head)->next; pos != (head); pos = pos->next)
+
+/**
+ * @brief iterate over a list safe against removal of list entry
+ * @param pos:  the rt_list_t * to use as a loop cursor.
+ * @param n:    another rt_list_t * to use as temporary storage
+ * @param head: the head for your list.
+ */
+#define HAL_LIST_FOR_EACH_SAFE(pos, n, head)               \
+    for (pos = (head)->next, n = pos->next; pos != (head); \
+        pos = n, n = pos->next)
+
+/**
+ * @brief   iterate over list of given type
+ * @param   pos:    the type * to use as a loop cursor.
+ * @param   head:   the head for your list.
+ * @param   member: the name of the list_struct within the struct.
+ */
+#define HAL_LIST_FOR_EACH_ENTRY(pos, head, member)                     \
+    for (pos = HAL_LIST_ENTRY((head)->next, __typeof__(*pos), member); \
+         &pos->member != (head);                                       \
+         pos = HAL_LIST_ENTRY(pos->member.next, __typeof__(*pos), member))
+
+/**
+ * @brief   iterate over list of given type safe against removal of list entry
+ * @param   pos:    the type * to use as a loop cursor.
+ * @param   n:      another type * to use as temporary storage
+ * @param   head:   the head for your list.
+ * @param   member: the name of the list_struct within the struct.
+ */
+#define HAL_LIST_FOR_EACH_ENTRY_SAFE(pos, n, head, member)               \
+    for (pos = HAL_LIST_ENTRY((head)->next, __typeof__(*pos), member),   \
+         n = HAL_LIST_ENTRY(pos->member.next, __typeof__(*pos), member); \
+         &pos->member != (head);                                         \
+         pos = n, n = HAL_LIST_ENTRY(n->member.next, __typeof__(*n), member))
+
+/**
+ * @brief   get the first element from a list
+ * @param   ptr:    the list head to take the element from.
+ * @param   type:   the type of the struct this is embedded in.
+ * @param   member: the name of the list_struct within the struct.
+ *
+ * Note, that list is expected to be not empty.
+ */
+#define HAL_LIST_FIRST_ENTRY(ptr, type, member) \
+    HAL_LIST_ENTRY((ptr)->next, type, member)
+
+#endif

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_pinctrl.h

@@ -0,0 +1,697 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ */
+
+
+
+/** @addtogroup RK_HAL_Driver
+ *  @{
+ */
+
+/** @addtogroup PINCTRL
+ *  @{
+ */
+
+#ifndef __HAL_PINCTRL_H__
+#define __HAL_PINCTRL_H__
+
+#include "hal_def.h"
+
+/***************************** MACRO Definition ******************************/
+/** @defgroup PINCTRL_Exported_Definition_Group1 Basic Definition
+ *  @{
+ */
+
+/** PINCTRL IOFUNC Select definition */
+typedef enum {
+    IOFUNC_SEL_M0,
+    IOFUNC_SEL_M1,
+    IOFUNC_SEL_M2,
+} eIOFUNC_SEL;
+
+typedef enum {
+#if defined(GPIO0)
+    GPIO0_A0 = 0,
+    GPIO0_A1,
+    GPIO0_A2,
+    GPIO0_A3,
+    GPIO0_A4,
+    GPIO0_A5,
+    GPIO0_A6,
+    GPIO0_A7,
+    GPIO0_B0 = 8,
+    GPIO0_B1,
+    GPIO0_B2,
+    GPIO0_B3,
+    GPIO0_B4,
+    GPIO0_B5,
+    GPIO0_B6,
+    GPIO0_B7,
+    GPIO0_C0 = 16,
+    GPIO0_C1,
+    GPIO0_C2,
+    GPIO0_C3,
+    GPIO0_C4,
+    GPIO0_C5,
+    GPIO0_C6,
+    GPIO0_C7,
+    GPIO0_D0 = 24,
+    GPIO0_D1,
+    GPIO0_D2,
+    GPIO0_D3,
+    GPIO0_D4,
+    GPIO0_D5,
+    GPIO0_D6,
+    GPIO0_D7,
+#endif
+#if defined(GPIO1)
+    GPIO1_A0 = 32,
+    GPIO1_A1,
+    GPIO1_A2,
+    GPIO1_A3,
+    GPIO1_A4,
+    GPIO1_A5,
+    GPIO1_A6,
+    GPIO1_A7,
+    GPIO1_B0 = 40,
+    GPIO1_B1,
+    GPIO1_B2,
+    GPIO1_B3,
+    GPIO1_B4,
+    GPIO1_B5,
+    GPIO1_B6,
+    GPIO1_B7,
+    GPIO1_C0 = 48,
+    GPIO1_C1,
+    GPIO1_C2,
+    GPIO1_C3,
+    GPIO1_C4,
+    GPIO1_C5,
+    GPIO1_C6,
+    GPIO1_C7,
+    GPIO1_D0 = 56,
+    GPIO1_D1,
+    GPIO1_D2,
+    GPIO1_D3,
+    GPIO1_D4,
+    GPIO1_D5,
+    GPIO1_D6,
+    GPIO1_D7,
+#endif
+#if defined(GPIO2)
+    GPIO2_A0 = 64,
+    GPIO2_A1,
+    GPIO2_A2,
+    GPIO2_A3,
+    GPIO2_A4,
+    GPIO2_A5,
+    GPIO2_A6,
+    GPIO2_A7,
+    GPIO2_B0 = 72,
+    GPIO2_B1,
+    GPIO2_B2,
+    GPIO2_B3,
+    GPIO2_B4,
+    GPIO2_B5,
+    GPIO2_B6,
+    GPIO2_B7,
+    GPIO2_C0 = 80,
+    GPIO2_C1,
+    GPIO2_C2,
+    GPIO2_C3,
+    GPIO2_C4,
+    GPIO2_C5,
+    GPIO2_C6,
+    GPIO2_C7,
+    GPIO2_D0 = 88,
+    GPIO2_D1,
+    GPIO2_D2,
+    GPIO2_D3,
+    GPIO2_D4,
+    GPIO2_D5,
+    GPIO2_D6,
+    GPIO2_D7,
+#endif
+#if defined(GPIO3)
+    GPIO3_A0 = 96,
+    GPIO3_A1,
+    GPIO3_A2,
+    GPIO3_A3,
+    GPIO3_A4,
+    GPIO3_A5,
+    GPIO3_A6,
+    GPIO3_A7,
+    GPIO3_B0 = 104,
+    GPIO3_B1,
+    GPIO3_B2,
+    GPIO3_B3,
+    GPIO3_B4,
+    GPIO3_B5,
+    GPIO3_B6,
+    GPIO3_B7,
+    GPIO3_C0 = 112,
+    GPIO3_C1,
+    GPIO3_C2,
+    GPIO3_C3,
+    GPIO3_C4,
+    GPIO3_C5,
+    GPIO3_C6,
+    GPIO3_C7,
+    GPIO3_D0 = 120,
+    GPIO3_D1,
+    GPIO3_D2,
+    GPIO3_D3,
+    GPIO3_D4,
+    GPIO3_D5,
+    GPIO3_D6,
+    GPIO3_D7,
+#endif
+#if defined(GPIO4)
+    GPIO4_A0 = 128,
+    GPIO4_A1,
+    GPIO4_A2,
+    GPIO4_A3,
+    GPIO4_A4,
+    GPIO4_A5,
+    GPIO4_A6,
+    GPIO4_A7,
+    GPIO4_B0 = 136,
+    GPIO4_B1,
+    GPIO4_B2,
+    GPIO4_B3,
+    GPIO4_B4,
+    GPIO4_B5,
+    GPIO4_B6,
+    GPIO4_B7,
+    GPIO4_C0 = 144,
+    GPIO4_C1,
+    GPIO4_C2,
+    GPIO4_C3,
+    GPIO4_C4,
+    GPIO4_C5,
+    GPIO4_C6,
+    GPIO4_C7,
+    GPIO4_D0 = 152,
+    GPIO4_D1,
+    GPIO4_D2,
+    GPIO4_D3,
+    GPIO4_D4,
+    GPIO4_D5,
+    GPIO4_D6,
+    GPIO4_D7,
+#endif
+#if defined(GPIO0_EXP)
+    GPIO0_EXP_A0 = 160,
+    GPIO0_EXP_A1,
+    GPIO0_EXP_A2,
+    GPIO0_EXP_A3,
+    GPIO0_EXP_A4,
+    GPIO0_EXP_A5,
+    GPIO0_EXP_A6,
+    GPIO0_EXP_A7,
+    GPIO0_EXP_B0 = 168,
+    GPIO0_EXP_B1,
+    GPIO0_EXP_B2,
+    GPIO0_EXP_B3,
+    GPIO0_EXP_B4,
+    GPIO0_EXP_B5,
+    GPIO0_EXP_B6,
+    GPIO0_EXP_B7,
+    GPIO0_EXP_C0 = 176,
+    GPIO0_EXP_C1,
+    GPIO0_EXP_C2,
+    GPIO0_EXP_C3,
+    GPIO0_EXP_C4,
+    GPIO0_EXP_C5,
+    GPIO0_EXP_C6,
+    GPIO0_EXP_C7,
+    GPIO0_EXP_D0 = 184,
+    GPIO0_EXP_D1,
+    GPIO0_EXP_D2,
+    GPIO0_EXP_D3,
+    GPIO0_EXP_D4,
+    GPIO0_EXP_D5,
+    GPIO0_EXP_D6,
+    GPIO0_EXP_D7,
+#endif
+#if defined(GPIO1_EXP)
+    GPIO1_EXP_A0 = 192,
+    GPIO1_EXP_A1,
+    GPIO1_EXP_A2,
+    GPIO1_EXP_A3,
+    GPIO1_EXP_A4,
+    GPIO1_EXP_A5,
+    GPIO1_EXP_A6,
+    GPIO1_EXP_A7,
+    GPIO1_EXP_B0 = 200,
+    GPIO1_EXP_B1,
+    GPIO1_EXP_B2,
+    GPIO1_EXP_B3,
+    GPIO1_EXP_B4,
+    GPIO1_EXP_B5,
+    GPIO1_EXP_B6,
+    GPIO1_EXP_B7,
+    GPIO1_EXP_C0 = 208,
+    GPIO1_EXP_C1,
+    GPIO1_EXP_C2,
+    GPIO1_EXP_C3,
+    GPIO1_EXP_C4,
+    GPIO1_EXP_C5,
+    GPIO1_EXP_C6,
+    GPIO1_EXP_C7,
+    GPIO1_EXP_D0 = 216,
+    GPIO1_EXP_D1,
+    GPIO1_EXP_D2,
+    GPIO1_EXP_D3,
+    GPIO1_EXP_D4,
+    GPIO1_EXP_D5,
+    GPIO1_EXP_D6,
+    GPIO1_EXP_D7,
+#endif
+#if defined(GPIO2_EXP)
+    GPIO2_EXP_A0 = 224,
+    GPIO2_EXP_A1,
+    GPIO2_EXP_A2,
+    GPIO2_EXP_A3,
+    GPIO2_EXP_A4,
+    GPIO2_EXP_A5,
+    GPIO2_EXP_A6,
+    GPIO2_EXP_A7,
+    GPIO2_EXP_B0 = 232,
+    GPIO2_EXP_B1,
+    GPIO2_EXP_B2,
+    GPIO2_EXP_B3,
+    GPIO2_EXP_B4,
+    GPIO2_EXP_B5,
+    GPIO2_EXP_B6,
+    GPIO2_EXP_B7,
+    GPIO2_EXP_C0 = 240,
+    GPIO2_EXP_C1,
+    GPIO2_EXP_C2,
+    GPIO2_EXP_C3,
+    GPIO2_EXP_C4,
+    GPIO2_EXP_C5,
+    GPIO2_EXP_C6,
+    GPIO2_EXP_C7,
+    GPIO2_EXP_D0 = 248,
+    GPIO2_EXP_D1,
+    GPIO2_EXP_D2,
+    GPIO2_EXP_D3,
+    GPIO2_EXP_D4,
+    GPIO2_EXP_D5,
+    GPIO2_EXP_D6,
+    GPIO2_EXP_D7,
+#endif
+#if defined(GPIO3_EXP)
+    GPIO3_EXP_A0 = 256,
+    GPIO3_EXP_A1,
+    GPIO3_EXP_A2,
+    GPIO3_EXP_A3,
+    GPIO3_EXP_A4,
+    GPIO3_EXP_A5,
+    GPIO3_EXP_A6,
+    GPIO3_EXP_A7,
+    GPIO3_EXP_B0 = 264,
+    GPIO3_EXP_B1,
+    GPIO3_EXP_B2,
+    GPIO3_EXP_B3,
+    GPIO3_EXP_B4,
+    GPIO3_EXP_B5,
+    GPIO3_EXP_B6,
+    GPIO3_EXP_B7,
+    GPIO3_EXP_C0 = 272,
+    GPIO3_EXP_C1,
+    GPIO3_EXP_C2,
+    GPIO3_EXP_C3,
+    GPIO3_EXP_C4,
+    GPIO3_EXP_C5,
+    GPIO3_EXP_C6,
+    GPIO3_EXP_C7,
+    GPIO3_EXP_D0 = 280,
+    GPIO3_EXP_D1,
+    GPIO3_EXP_D2,
+    GPIO3_EXP_D3,
+    GPIO3_EXP_D4,
+    GPIO3_EXP_D5,
+    GPIO3_EXP_D6,
+    GPIO3_EXP_D7,
+#endif
+#if defined(GPIO4_EXP)
+    GPIO4_EXP_A0 = 288,
+    GPIO4_EXP_A1,
+    GPIO4_EXP_A2,
+    GPIO4_EXP_A3,
+    GPIO4_EXP_A4,
+    GPIO4_EXP_A5,
+    GPIO4_EXP_A6,
+    GPIO4_EXP_A7,
+    GPIO4_EXP_B0 = 296,
+    GPIO4_EXP_B1,
+    GPIO4_EXP_B2,
+    GPIO4_EXP_B3,
+    GPIO4_EXP_B4,
+    GPIO4_EXP_B5,
+    GPIO4_EXP_B6,
+    GPIO4_EXP_B7,
+    GPIO4_EXP_C0 = 304,
+    GPIO4_EXP_C1,
+    GPIO4_EXP_C2,
+    GPIO4_EXP_C3,
+    GPIO4_EXP_C4,
+    GPIO4_EXP_C5,
+    GPIO4_EXP_C6,
+    GPIO4_EXP_C7,
+    GPIO4_EXP_D0 = 312,
+    GPIO4_EXP_D1,
+    GPIO4_EXP_D2,
+    GPIO4_EXP_D3,
+    GPIO4_EXP_D4,
+    GPIO4_EXP_D5,
+    GPIO4_EXP_D6,
+    GPIO4_EXP_D7,
+#endif
+    GPIO_NUM_MAX
+} ePINCTRL_PIN;
+
+/** PINCTRL IOMUX definition */
+typedef enum {
+    PINCTRL_IOMUX_FUNC0,
+    PINCTRL_IOMUX_FUNC1,
+    PINCTRL_IOMUX_FUNC2,
+    PINCTRL_IOMUX_FUNC3,
+    PINCTRL_IOMUX_FUNC4,
+    PINCTRL_IOMUX_FUNC5,
+    PINCTRL_IOMUX_FUNC6,
+    PINCTRL_IOMUX_FUNC7,
+    PINCTRL_IOMUX_FUNC8,
+    PINCTRL_IOMUX_FUNC9,
+    PINCTRL_IOMUX_FUNC10,
+    PINCTRL_IOMUX_FUNC11,
+    PINCTRL_IOMUX_FUNC12,
+    PINCTRL_IOMUX_FUNC13,
+    PINCTRL_IOMUX_FUNC14,
+    PINCTRL_IOMUX_FUNC15
+} ePINCTRL_iomuxFunc;
+
+/** PINCTRL PULL definition */
+typedef enum {
+    PINCTRL_PULL_OD,
+    PINCTRL_PULL_UP,
+    PINCTRL_PULL_DOWN,
+    PINCTRL_PULL_KEEP
+} ePINCTRL_pullMode;
+
+/** PINCTRL Drive Strength definition */
+typedef enum {
+    PINCTRL_DRIVE_LEVEL0,
+    PINCTRL_DRIVE_LEVEL1,
+    PINCTRL_DRIVE_LEVEL2,
+    PINCTRL_DRIVE_LEVEL3,
+    PINCTRL_DRIVE_LEVEL4,
+    PINCTRL_DRIVE_LEVEL5,
+    PINCTRL_DRIVE_LEVEL6,
+    PINCTRL_DRIVE_LEVEL7
+} ePINCTRL_driveLevel;
+
+/** PINCTRL Slew Rate definition */
+typedef enum {
+    PINCTRL_SLEWRATE_SLOW,
+    PINCTRL_SLEWRATE_FAST
+} ePINCTRL_slewRate;
+
+/** PINCTRL Schmitt enable definition */
+typedef enum {
+    PINCTRL_SCHMITT_DIS,
+    PINCTRL_SCHMITT_EN
+} ePINCTRL_schmitt;
+
+#define FLAG_MUX  HAL_BIT(31)
+#define FLAG_PUL  HAL_BIT(30)
+#define FLAG_DRV  HAL_BIT(29)
+#define FLAG_SRT  HAL_BIT(28)
+#define FLAG_SMT  HAL_BIT(27)
+#define SHIFT_MUX (0)
+#define SHIFT_PUL (4)
+#define SHIFT_DRV (8)
+#define SHIFT_SRT (16)
+#define SHIFT_SMT (18)
+#define MASK_MUX  (0xFU << SHIFT_MUX)
+#define MASK_PUL  (0xFU << SHIFT_PUL)
+#define MASK_DRV  (0xFFU << SHIFT_DRV)
+#define MASK_SRT  (0x3U << SHIFT_SRT)
+#define MASK_SMT  (0x3U << SHIFT_SMT)
+
+/** @brief  PIN Configuration Mode
+ *  Elements values convention: gggg g000 0000 ttrr dddd dddd pppp xxxx
+ *      - ggggg  : Flag to set Mux/Pull/Drive/Slewrate/Schmitt
+ *      - tt  : Schmitt value
+ *      - rr  : Slewrate value
+ *      - dddddddd  : Drive value
+ *      - pppp  : Pull value
+ *      - xxxx  : Mux mode value
+ */
+typedef enum {
+    PIN_CONFIG_MUX_FUNC0   = (0x0 << SHIFT_MUX | FLAG_MUX),
+    PIN_CONFIG_MUX_FUNC1   = (0x1 << SHIFT_MUX | FLAG_MUX),
+    PIN_CONFIG_MUX_FUNC2   = (0x2 << SHIFT_MUX | FLAG_MUX),
+    PIN_CONFIG_MUX_FUNC3   = (0x3 << SHIFT_MUX | FLAG_MUX),
+    PIN_CONFIG_MUX_FUNC4   = (0x4 << SHIFT_MUX | FLAG_MUX),
+    PIN_CONFIG_MUX_FUNC5   = (0x5 << SHIFT_MUX | FLAG_MUX),
+    PIN_CONFIG_MUX_FUNC6   = (0x6 << SHIFT_MUX | FLAG_MUX),
+    PIN_CONFIG_MUX_FUNC7   = (0x7 << SHIFT_MUX | FLAG_MUX),
+    PIN_CONFIG_MUX_FUNC8   = (0x8 << SHIFT_MUX | FLAG_MUX),
+    PIN_CONFIG_MUX_FUNC9   = (0x9 << SHIFT_MUX | FLAG_MUX),
+    PIN_CONFIG_MUX_FUNC10  = (0xa << SHIFT_MUX | FLAG_MUX),
+    PIN_CONFIG_MUX_FUNC11  = (0xb << SHIFT_MUX | FLAG_MUX),
+    PIN_CONFIG_MUX_FUNC12  = (0xc << SHIFT_MUX | FLAG_MUX),
+    PIN_CONFIG_MUX_FUNC13  = (0xd << SHIFT_MUX | FLAG_MUX),
+    PIN_CONFIG_MUX_FUNC14  = (0xe << SHIFT_MUX | FLAG_MUX),
+    PIN_CONFIG_MUX_FUNC15  = (0xf << SHIFT_MUX | FLAG_MUX),
+    PIN_CONFIG_MUX_DEFAULT = PIN_CONFIG_MUX_FUNC0,
+
+
+    PIN_CONFIG_PUL_NORMAL  = (0x1 << SHIFT_PUL | FLAG_PUL),
+    PIN_CONFIG_PUL_DEFAULT = (0x0 << SHIFT_PUL | FLAG_PUL),
+    PIN_CONFIG_PUL_UP      = PIN_CONFIG_PUL_DEFAULT,
+    PIN_CONFIG_PUL_DOWN    = PIN_CONFIG_PUL_DEFAULT,
+    PIN_CONFIG_PUL_KEEP    = PIN_CONFIG_PUL_DEFAULT,
+
+
+    PIN_CONFIG_DRV_LEVEL0        = (0x1 << SHIFT_DRV | FLAG_DRV),
+    PIN_CONFIG_DRV_LEVEL1        = (0x3 << SHIFT_DRV | FLAG_DRV),
+    PIN_CONFIG_DRV_LEVEL2        = (0x7 << SHIFT_DRV | FLAG_DRV),
+    PIN_CONFIG_DRV_LEVEL3        = (0xf << SHIFT_DRV | FLAG_DRV),
+    PIN_CONFIG_DRV_LEVEL4        = (0x1f << SHIFT_DRV | FLAG_DRV),
+    PIN_CONFIG_DRV_LEVEL5        = (0x3f << SHIFT_DRV | FLAG_DRV),
+    PIN_CONFIG_DRV_LEVEL_DEFAULT = PIN_CONFIG_DRV_LEVEL2,
+
+    PIN_CONFIG_SRT_SLOW    = (0x0 << SHIFT_SRT | FLAG_SRT),
+    PIN_CONFIG_SRT_FAST    = (0x1 << SHIFT_SRT | FLAG_SRT),
+    PIN_CONFIG_SRT_DEFAULT = PIN_CONFIG_SRT_SLOW,
+
+    PIN_CONFIG_SMT_DISABLE = (0x0 << SHIFT_SMT | FLAG_SMT),
+    PIN_CONFIG_SMT_ENABLE  = (0x1 << SHIFT_SMT | FLAG_SMT),
+    PIN_CONFIG_SMT_DEFAULT = PIN_CONFIG_SMT_DISABLE,
+
+    PIN_CONFIG_MAX = 0xFFFFFFFFU,
+} ePINCTRL_configParam;
+
+typedef enum {
+    GRF_MUX_INFO = 0,
+    GRF_PUL_INFO,
+    GRF_DRV_INFO,
+    GRF_SRT_INFO,
+    GRF_SMT_INFO,
+    GRF_INFO_NUM
+} ePIN_GRF_INFO_ID;
+
+#define PIN_BANK_CFG_FLAGS(chn, cnt, reg,                                                       \
+                           offset0, bpp0, ppr0,                                                 \
+                           offset1, bpp1, ppr1,                                                 \
+                           offset2, bpp2, ppr2,                                                 \
+                           offset3, bpp3, ppr3,                                                 \
+                           offset4, bpp4, ppr4)                                                 \
+    {                                                                                           \
+        .channel = chn,                                                                         \
+        .pinCount = cnt,                                                                        \
+        .grfBase = reg,                                                                         \
+        .GRFInfo[GRF_MUX_INFO] = { .offset = offset0, .bitsPerPin = bpp0, .pinsPerReg = ppr0 }, \
+        .GRFInfo[GRF_PUL_INFO] = { .offset = offset1, .bitsPerPin = bpp1, .pinsPerReg = ppr1 }, \
+        .GRFInfo[GRF_DRV_INFO] = { .offset = offset2, .bitsPerPin = bpp2, .pinsPerReg = ppr2 }, \
+        .GRFInfo[GRF_SRT_INFO] = { .offset = offset3, .bitsPerPin = bpp3, .pinsPerReg = ppr3 }, \
+        .GRFInfo[GRF_SMT_INFO] = { .offset = offset4, .bitsPerPin = bpp4, .pinsPerReg = ppr4 }, \
+    }
+
+/** @defgroup ePINCTRL_GPIO_PINS Pins Definition
+ *  @{
+ */
+typedef enum {
+    GPIO_PIN_A0 = 0x00000001U,  /*!< Pin 0 selected    */
+    GPIO_PIN_A1 = 0x00000002U,  /*!< Pin 1 selected    */
+    GPIO_PIN_A2 = 0x00000004U,  /*!< Pin 2 selected    */
+    GPIO_PIN_A3 = 0x00000008U,  /*!< Pin 3 selected    */
+    GPIO_PIN_A4 = 0x00000010U,  /*!< Pin 4 selected    */
+    GPIO_PIN_A5 = 0x00000020U,  /*!< Pin 5 selected    */
+    GPIO_PIN_A6 = 0x00000040U,  /*!< Pin 6 selected    */
+    GPIO_PIN_A7 = 0x00000080U,  /*!< Pin 7 selected    */
+    GPIO_PIN_B0 = 0x00000100U,  /*!< Pin 8 selected    */
+    GPIO_PIN_B1 = 0x00000200U,  /*!< Pin 9 selected    */
+    GPIO_PIN_B2 = 0x00000400U,  /*!< Pin 10 selected   */
+    GPIO_PIN_B3 = 0x00000800U,  /*!< Pin 11 selected   */
+    GPIO_PIN_B4 = 0x00001000U,  /*!< Pin 12 selected   */
+    GPIO_PIN_B5 = 0x00002000U,  /*!< Pin 13 selected   */
+    GPIO_PIN_B6 = 0x00004000U,  /*!< Pin 14 selected   */
+    GPIO_PIN_B7 = 0x00008000U,  /*!< Pin 15 selected   */
+    GPIO_PIN_C0 = 0x00010000U,  /*!< Pin 16 selected   */
+    GPIO_PIN_C1 = 0x00020000U,  /*!< Pin 17 selected   */
+    GPIO_PIN_C2 = 0x00040000U,  /*!< Pin 18 selected   */
+    GPIO_PIN_C3 = 0x00080000U,  /*!< Pin 19 selected   */
+    GPIO_PIN_C4 = 0x00100000U,  /*!< Pin 20 selected   */
+    GPIO_PIN_C5 = 0x00200000U,  /*!< Pin 21 selected   */
+    GPIO_PIN_C6 = 0x00400000U,  /*!< Pin 22 selected   */
+    GPIO_PIN_C7 = 0x00800000U,  /*!< Pin 23 selected   */
+    GPIO_PIN_D0 = 0x01000000U,  /*!< Pin 24 selected   */
+    GPIO_PIN_D1 = 0x02000000U,  /*!< Pin 25 selected   */
+    GPIO_PIN_D2 = 0x04000000U,  /*!< Pin 26 selected   */
+    GPIO_PIN_D3 = 0x08000000U,  /*!< Pin 27 selected   */
+    GPIO_PIN_D4 = 0x10000000U,  /*!< Pin 28 selected   */
+    GPIO_PIN_D5 = 0x20000000U,  /*!< Pin 29 selected   */
+    GPIO_PIN_D6 = 0x40000000U,  /*!< Pin 30 selected   */
+    GPIO_PIN_D7 = 0x80000000U,  /*!< Pin 31 selected   */
+} ePINCTRL_GPIO_PINS;
+
+#define GPIO_PIN_ALL (0xFFFFFFFFU)  /*!< All pins selected */
+
+/** @} */
+
+#define ROUTE_VAL(v, s, m) (((v) << (s)) | (m) << ((s) + 16))
+
+/***************************** Structure Definition **************************/
+
+struct PINCTRL_GRF_INFO {
+    uint16_t offset;
+    uint8_t bitsPerPin;
+    uint8_t pinsPerReg;
+};
+
+struct PINCTRL_MUX_RECAL_DATA {
+    uint32_t reg;
+    uint8_t bank;
+    uint8_t pin;
+    uint8_t bit;
+    uint8_t mask;
+};
+
+struct PINCTRL_MUX_ROUTE_DATA {
+    uint32_t routeReg;
+    uint32_t routeVal;
+    uint32_t pin;
+    uint8_t bank;
+    uint8_t func;
+};
+
+struct PINCTRL_BANK_INFO {
+    struct PINCTRL_GRF_INFO GRFInfo[GRF_INFO_NUM];
+    uint32_t grfBase;
+    uint8_t pinCount;
+    uint8_t channel;
+};
+
+struct HAL_PINCTRL_DEV {
+    const struct PINCTRL_BANK_INFO *banks;
+    const struct PINCTRL_MUX_RECAL_DATA *muxRecalData;
+    const struct PINCTRL_MUX_ROUTE_DATA *muxRouteData;
+    uint8_t banksNum;
+    uint8_t muxRecalDataNum;
+    uint8_t muxRouteDataNum;
+};
+
+/** @brief  Rockchip pinctrl device struct define
+ * Define a struct for pinctrl, including banks info, bank number,
+ * and grf info about iomux offset, iomux bit info, drive/pull/
+ * slewrate/schmitt offset and bit info.
+ */
+extern const struct HAL_PINCTRL_DEV g_pinDev;
+
+/** @} */
+
+/***************************** Function Declare ******************************/
+/** @defgroup PINCTRL_Public_Function_Declare Public Function Declare
+ *  @{
+ */
+
+HAL_Status HAL_PINCTRL_Suspend(void);
+HAL_Status HAL_PINCTRL_Resume(void);
+
+HAL_Status HAL_PINCTRL_Init(void);
+HAL_Status HAL_PINCTRL_DeInit(void);
+
+HAL_Status HAL_PINCTRL_SetParam(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param);
+HAL_Status HAL_PINCTRL_SetIOMUX(eGPIO_bankId bank, uint32_t mPins, ePINCTRL_configParam param);
+
+HAL_Status HAL_PINCTRL_IOFuncSelForCIF(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForEMMC(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForFLASH(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForFSPI(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForLCDC(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForMIPICSI(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForRGMII(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForGMAC0(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForGMAC1(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForSDIO(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForSDMMC0(eIOFUNC_SEL mode);
+
+HAL_Status HAL_PINCTRL_IOFuncSelForCAN0(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForCAN1(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForCAN2(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForCAN3(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForCAN4(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForCAN5(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForI2C0(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForI2C1(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForI2C2(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForI2C3(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForI2C4(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForI2C5(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForI2S0(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForI2S1(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForI2S2(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForPWM0(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForPWM1(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForPWM2(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForPWM3(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForPWM4(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForPWM5(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForPWM6(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForPWM7(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForPWM8(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForPWM9(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForPWM10(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForPWM11(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForSPI0(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForSPI1(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForSPI2(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForSPI3(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForSPI4(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForSPI5(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForUART0(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForUART1(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForUART2(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForUART3(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForUART4(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForUART5(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForUART6(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForUART7(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForUART8(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForUART9(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForUART10(eIOFUNC_SEL mode);
+HAL_Status HAL_PINCTRL_IOFuncSelForUART11(eIOFUNC_SEL mode);
+
+/** @} */
+
+#endif /* __HAL_PINCTRL_H__ */
+
+/** @} */
+
+/** @} */

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/hal_timer.h

@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
+ */
+
+
+
+
+/** @addtogroup RK_HAL_Driver
+ *  @{
+ */
+
+/** @addtogroup TIMER
+ *  @{
+ */
+
+#ifndef _HAL_TIMER_H_
+#define _HAL_TIMER_H_
+
+#include "hal_def.h"
+
+/***************************** MACRO Definition ******************************/
+
+/** @defgroup TIMER_Exported_Definition_Group1 Basic Definition
+ *  @{
+ */
+
+typedef enum {
+    TIMER_FREE_RUNNING = 0,
+    TIMER_USER_DEFINED,
+    TIMER_MODE_MAX
+} eTIMER_MODE;
+
+/***************************** Structure Definition **************************/
+
+/** @} */
+/***************************** Function Declare ******************************/
+/** @defgroup TIMER_Public_Function_Declare Public Function Declare
+ *  @{
+ */
+
+HAL_Status HAL_TIMER_Stop(struct TIMER_REG *pReg);
+HAL_Status HAL_TIMER_Start(struct TIMER_REG *pReg);
+HAL_Status HAL_TIMER_Stop_IT(struct TIMER_REG *pReg);
+HAL_Status HAL_TIMER_Start_IT(struct TIMER_REG *pReg);
+HAL_Status HAL_TIMER_SetCount(struct TIMER_REG *pReg, uint64_t usTick);
+uint64_t HAL_TIMER_GetCount(struct TIMER_REG *pReg);
+HAL_Status HAL_TIMER0_Handler(void);
+HAL_Status HAL_TIMER1_Handler(void);
+HAL_Status HAL_TIMER_Init(struct TIMER_REG *pReg, eTIMER_MODE mode);
+HAL_Status HAL_TIMER_SysTimerInit(struct TIMER_REG *pReg);
+HAL_Status HAL_TIMER_DeInit(struct TIMER_REG *pReg);
+HAL_Status HAL_TIMER_ClrInt(struct TIMER_REG *pReg);
+
+/** @} */
+
+#endif
+
+/** @} */
+
+/** @} */
+

Ubiquitous/XiZi_AIoT/services/drivers/rk-3568/include/soc.h

@@ -0,0 +1,443 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __SOC_H
+#define __SOC_H
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+#define     __I     volatile             /*!< brief Defines 'read only' permissions */
+#else
+#define     __I     volatile const       /*!< brief Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< brief Defines 'write only' permissions */
+#define     __IO    volatile             /*!< brief Defines 'read / write' permissions */
+
+/* ================================================================================ */
+/* ================                    DMA REQ                      =============== */
+/* ================================================================================ */
+typedef enum {
+    DMA_REQ_UART0_TX = 0,
+    DMA_REQ_UART0_RX = 1,
+    DMA_REQ_UART1_TX = 2,
+    DMA_REQ_UART1_RX = 3,
+    DMA_REQ_UART2_TX = 4,
+    DMA_REQ_UART2_RX = 5,
+    DMA_REQ_UART3_TX = 6,
+    DMA_REQ_UART3_RX = 7,
+    DMA_REQ_UART4_TX = 8,
+    DMA_REQ_UART4_RX = 9,
+    DMA_REQ_UART5_TX = 10,
+    DMA_REQ_UART5_RX = 11,
+    DMA_REQ_UART6_TX = 12,
+    DMA_REQ_UART6_RX = 13,
+    DMA_REQ_UART7_TX = 14,
+    DMA_REQ_UART7_RX = 15,
+    DMA_REQ_UART8_TX = 16,
+    DMA_REQ_UART8_RX = 17,
+    DMA_REQ_UART9_TX = 18,
+    DMA_REQ_UART9_RX = 19,
+    DMA_REQ_SPI0_TX = 20,
+    DMA_REQ_SPI0_RX = 21,
+    DMA_REQ_SPI1_TX = 22,
+    DMA_REQ_SPI1_RX = 23,
+    DMA_REQ_SPI2_TX = 24,
+    DMA_REQ_SPI2_RX = 25,
+    DMA_REQ_SPI3_TX = 26,
+    DMA_REQ_SPI3_RX = 27,
+} DMA_REQ_Type;
+
+/* ================================================================================ */
+/* ================                       IRQ                      ================ */
+/* ================================================================================ */
+#ifdef HAL_MCU_CORE
+#define INTMUX_IRQ_START_NUM      32
+#define INTMUX_OUT_IRQ_START_NUM  0
+#define INTMUX_NUM_INT_PER_OUT    64
+#define INTMUX_NUM_GROUP_PER_CON  8
+#define INTMUX_NUM_GROUP_PER_OUT  8
+#define INTMUX_NUM_INT_PER_GROUP  8
+#define NUM_EXT_INTERRUPTS        320
+
+typedef enum
+{
+/******  Platform Exceptions Numbers ***************************************************/
+    NUM_INTERRUPTS         = 0,
+    DMAC0_ABORT_IRQn       = 45,       /*!< DMAC0 Abort Interrupt       */
+    DMAC0_IRQn             = 46,       /*!< DMAC0 Interrupt             */
+    DMAC1_ABORT_IRQn       = 47,       /*!< DMAC1 Abort Interrupt       */
+    DMAC1_IRQn             = 48,       /*!< DMAC1 Interrupt             */
+    GPIO0_IRQn             = 65,       /*!< GPIO0 Interrupt             */
+    GPIO1_IRQn             = 66,       /*!< GPIO1 Interrupt             */
+    GPIO2_IRQn             = 67,       /*!< GPIO2 Interrupt             */
+    GPIO3_IRQn             = 68,       /*!< GPIO3 Interrupt             */
+    GPIO4_IRQn             = 69,       /*!< GPIO4 Interrupt             */
+    I2C0_IRQn              = 78,       /*!< I2C0 Interrupt              */
+    I2C1_IRQn              = 79,       /*!< I2C1 Interrupt              */
+    I2C2_IRQn              = 80,       /*!< I2C2 Interrupt              */
+    I2C3_IRQn              = 81,       /*!< I2C3 Interrupt              */
+    I2C4_IRQn              = 82,       /*!< I2C4 Interrupt              */
+    I2C5_IRQn              = 83,       /*!< I2C5 Interrupt              */
+    PWM_PMU_IRQn           = 114,      /*!< PWM_PMU Interrupt           */
+    PWM1_IRQn              = 115,      /*!< PWM1 Interrupt              */
+    PWM2_IRQn              = 116,      /*!< PWM2 Interrupt              */
+    PWM3_IRQn              = 117,      /*!< PWM3 Interrupt              */
+    PWM_PMU_PWR_IRQn       = 118,      /*!< PWM_PMU PWR Interrupt       */
+    PWM1_PWR_IRQn          = 119,      /*!< PWM1 PWR Interrupt          */
+    PWM2_PWR_IRQn          = 120,      /*!< PWM2 PWR Interrupt          */
+    PWM3_PWR_IRQn          = 121,      /*!< PWM3 PWR Interrupt          */
+    SARADC_IRQn            = 125,       /*!< SARADC Interrupt            */
+    FSPI0_IRQn             = 133,      /*!< FSPI Interrupt              */
+    SPI0_IRQn              = 135,      /*!< SPI0 Interrupt              */
+    SPI1_IRQn              = 136,      /*!< SPI1 Interrupt              */
+    SPI2_IRQn              = 137,      /*!< SPI2 Interrupt              */
+    SPI3_IRQn              = 138,      /*!< SPI3 Interrupt              */
+    TIMER0_IRQn            = 141,      /*!< TIMER0 Interrupt            */
+    TIMER1_IRQn            = 142,      /*!< TIMER1 Interrupt            */
+    TIMER2_IRQn            = 143,      /*!< TIMER2 Interrupt            */
+    TIMER3_IRQn            = 144,      /*!< TIMER3 Interrupt            */
+    TIMER4_IRQn            = 145,      /*!< TIMER4 Interrupt            */
+    TIMER5_IRQn            = 146,      /*!< TIMER5 Interrupt            */
+    UART0_IRQn             = 148,      /*!< UART0  Interrupt            */
+    UART1_IRQn             = 149,      /*!< UART1  Interrupt            */
+    UART2_IRQn             = 150,      /*!< UART2  Interrupt            */
+    UART3_IRQn             = 151,      /*!< UART3  Interrupt            */
+    UART4_IRQn             = 152,      /*!< UART4  Interrupt            */
+    UART5_IRQn             = 153,      /*!< UART5  Interrupt            */
+    UART6_IRQn             = 154,      /*!< UART6  Interrupt            */
+    UART7_IRQn             = 155,      /*!< UART7  Interrupt            */
+    UART8_IRQn             = 156,      /*!< UART8  Interrupt            */
+    UART9_IRQn             = 157,      /*!< UART9  Interrupt            */
+    WDT0_IRQn              = 181,      /*!< WDT0  Interrupt             */
+    MBOX0_CH0_B2A_IRQn     = 215,      /*!< MBOX0 CH0 B2A Interrupt     */
+    MBOX0_CH1_B2A_IRQn     = 216,      /*!< MBOX0 CH1 B2A Interrupt     */
+    MBOX0_CH2_B2A_IRQn     = 217,      /*!< MBOX0 CH2 B2A Interrupt     */
+    MBOX0_CH3_B2A_IRQn     = 218,      /*!< MBOX0 CH3 B2A Interrupt     */
+    MBOX0_CH0_A2B_IRQn     = 219,      /*!< MBOX0 CH0 A2B Interrupt     */
+    MBOX0_CH1_A2B_IRQn     = 220,      /*!< MBOX0 CH1 A2B Interrupt     */
+    MBOX0_CH2_A2B_IRQn     = 221,      /*!< MBOX0 CH2 A2B Interrupt     */
+    MBOX0_CH3_A2B_IRQn     = 222,      /*!< MBOX0 CH3 A2B Interrupt     */
+    TOTAL_INTERRUPTS       = (INTMUX_IRQ_START_NUM + NUM_INTERRUPTS + NUM_EXT_INTERRUPTS),
+} IRQn_Type;
+#else
+typedef enum
+{
+/* When IPI_SGIs are used in AMP mode, you need to pay attention to whether it conflicts
+ * with SMP mode. Especially in the case of Linux OS as The Master Core.
+ * IPI_SGI 0~7 for non-secure and IPI_SGI 8~15 for secure.
+ */
+    IPI_SGI0               = 0,
+    IPI_SGI1               = 1,
+    IPI_SGI2               = 2,
+    IPI_SGI3               = 3,
+    IPI_SGI4               = 4,
+    IPI_SGI5               = 5,
+    IPI_SGI6               = 6,
+    IPI_SGI7               = 7,
+    IPI_SGI8               = 8,
+    IPI_SGI9               = 9,
+    IPI_SGI10              = 10,
+    IPI_SGI11              = 11,
+    IPI_SGI12              = 12,
+    IPI_SGI13              = 13,
+    IPI_SGI14              = 14,
+    IPI_SGI15              = 15,
+
+    CNTHP_IRQn             = 26,
+    CNTV_IRQn              = 27,
+    CNTPS_IRQn             = 29,
+    CNTPNS_IRQn            = 30,
+
+/******  Platform Exceptions Numbers ***************************************************/
+    CAN0_IRQn              = 33,       /*!< CAN0 Interrupt              */
+    CAN1_IRQn              = 34,       /*!< CAN1 Interrupt              */
+    CAN2_IRQn              = 35,       /*!< CAN2 Interrupt              */
+    DMAC0_ABORT_IRQn       = 45,       /*!< DMAC0 Abort Interrupt       */
+    DMAC0_IRQn             = 46,       /*!< DMAC0 Interrupt             */
+    DMAC1_ABORT_IRQn       = 47,       /*!< DMAC1 Abort Interrupt       */
+    DMAC1_IRQn             = 48,       /*!< DMAC1 Interrupt             */
+    GMAC0_IRQn             = 59,       /*!< GMAC0 Interrupt             */
+    GMAC1_IRQn             = 64,       /*!< GMAC1 Interrupt             */
+    GPIO0_IRQn             = 65,       /*!< GPIO0 Interrupt             */
+    GPIO1_IRQn             = 66,       /*!< GPIO1 Interrupt             */
+    GPIO2_IRQn             = 67,       /*!< GPIO2 Interrupt             */
+    GPIO3_IRQn             = 68,       /*!< GPIO3 Interrupt             */
+    GPIO4_IRQn             = 69,       /*!< GPIO4 Interrupt             */
+    I2C0_IRQn              = 78,       /*!< I2C0 Interrupt              */
+    I2C1_IRQn              = 79,       /*!< I2C1 Interrupt              */
+    I2C2_IRQn              = 80,       /*!< I2C2 Interrupt              */
+    I2C3_IRQn              = 81,       /*!< I2C3 Interrupt              */
+    I2C4_IRQn              = 82,       /*!< I2C4 Interrupt              */
+    I2C5_IRQn              = 83,       /*!< I2C5 Interrupt              */
+    PWM_PMU_IRQn           = 114,      /*!< PWM_PMU Interrupt           */
+    PWM1_IRQn              = 115,      /*!< PWM1 Interrupt              */
+    PWM2_IRQn              = 116,      /*!< PWM2 Interrupt              */
+    PWM3_IRQn              = 117,      /*!< PWM3 Interrupt              */
+    PWM_PMU_PWR_IRQn       = 118,      /*!< PWM_PMU PWR Interrupt       */
+    PWM1_PWR_IRQn          = 119,      /*!< PWM1 PWR Interrupt          */
+    PWM2_PWR_IRQn          = 120,      /*!< PWM2 PWR Interrupt          */
+    PWM3_PWR_IRQn          = 121,      /*!< PWM3 PWR Interrupt          */
+    SARADC_IRQn            = 125,      /*!< SARADC Interrupt            */
+    FSPI0_IRQn             = 133,      /*!< FSPI Interrupt              */
+    SPI0_IRQn              = 135,      /*!< SPI0 Interrupt              */
+    SPI1_IRQn              = 136,      /*!< SPI1 Interrupt              */
+    SPI2_IRQn              = 137,      /*!< SPI2 Interrupt              */
+    SPI3_IRQn              = 138,      /*!< SPI3 Interrupt              */
+    TIMER0_IRQn            = 141,      /*!< TIMER0 Interrupt            */
+    TIMER1_IRQn            = 142,      /*!< TIMER1 Interrupt            */
+    TIMER2_IRQn            = 143,      /*!< TIMER2 Interrupt            */
+    TIMER3_IRQn            = 144,      /*!< TIMER3 Interrupt            */
+    TIMER4_IRQn            = 145,      /*!< TIMER4 Interrupt            */
+    TIMER5_IRQn            = 146,      /*!< TIMER5 Interrupt            */
+    UART0_IRQn             = 148,      /*!< UART0  Interrupt            */
+    UART1_IRQn             = 149,      /*!< UART1  Interrupt            */
+    UART2_IRQn             = 150,      /*!< UART2  Interrupt            */
+    UART3_IRQn             = 151,      /*!< UART3  Interrupt            */
+    UART4_IRQn             = 152,      /*!< UART4  Interrupt            */
+    UART5_IRQn             = 153,      /*!< UART5  Interrupt            */
+    UART6_IRQn             = 154,      /*!< UART6  Interrupt            */
+    UART7_IRQn             = 155,      /*!< UART7  Interrupt            */
+    UART8_IRQn             = 156,      /*!< UART8  Interrupt            */
+    UART9_IRQn             = 157,      /*!< UART9  Interrupt            */
+    WDT0_IRQn              = 181,      /*!< WDT0  Interrupt             */
+    PCIE30x2_LEGACY_IRQn   = 194,      /*!< PCIe3x2_legacy Interrupt    */
+    DDR_ECC_CE_IRQn        = 205,      /*!< DDR ECC correctable fault Interrupt */
+    DDR_ECC_UE_IRQn        = 207,      /*!< DDR ECC uncorrectable fault Interrupt */
+    MBOX0_CH0_B2A_IRQn     = 215,      /*!< MBOX0 CH0 B2A Interrupt     */
+    MBOX0_CH1_B2A_IRQn     = 216,      /*!< MBOX0 CH1 B2A Interrupt     */
+    MBOX0_CH2_B2A_IRQn     = 217,      /*!< MBOX0 CH2 B2A Interrupt     */
+    MBOX0_CH3_B2A_IRQn     = 218,      /*!< MBOX0 CH3 B2A Interrupt     */
+    MBOX0_CH0_A2B_IRQn     = 219,      /*!< MBOX0 CH0 A2B Interrupt     */
+    MBOX0_CH1_A2B_IRQn     = 220,      /*!< MBOX0 CH1 A2B Interrupt     */
+    MBOX0_CH2_A2B_IRQn     = 221,      /*!< MBOX0 CH2 A2B Interrupt     */
+    MBOX0_CH3_A2B_IRQn     = 222,      /*!< MBOX0 CH3 A2B Interrupt     */
+    NFAULT0_IRQn           = 272,      /*!< DSU L3 CACHE ECC FAULT Interrupt */
+    NFAULT1_IRQn           = 273,      /*!< CPU0 L1-L2 CACHE ECC FAULT Interrupt */
+    NFAULT2_IRQn           = 274,      /*!< CPU1 L1-L2 CACHE ECC FAULT Interrupt */
+    NFAULT3_IRQn           = 275,      /*!< CPU2 L1-L2 CACHE ECC FAULT Interrupt */
+    NFAULT4_IRQn           = 276,      /*!< CPU3 L1-L2 CACHE ECC FAULT Interrupt */
+    NERR0_IRQn             = 277,      /*!< DSU L3 CACHE ECC ERROR Interrupt */
+    NERR1_IRQn             = 278,      /*!< CPU0 L1-L2 CACHE ECC ERROR Interrupt */
+    NERR2_IRQn             = 279,      /*!< CPU1 L1-L2 CACHE ECC ERROR Interrupt */
+    NERR3_IRQn             = 280,      /*!< CPU2 L1-L2 CACHE ECC ERROR Interrupt */
+    NERR4_IRQn             = 281,      /*!< CPU3 L1-L2 CACHE ECC ERROR Interrupt */
+    RSVD0_IRQn             = 283,      /*!< RSVD0  Interrupt            */
+    RPMSG_01_IRQn          = 285,      /*!< RPMSG 0->1 Interrupt        */
+    RPMSG_02_IRQn          = 286,      /*!< RPMSG 0->2 Interrupt        */
+    RPMSG_03_IRQn          = 287,      /*!< RPMSG 0->3 Interrupt        */
+    RPMSG_10_IRQn          = 288,      /*!< RPMSG 1->0 Interrupt        */
+    RPMSG_12_IRQn          = 289,      /*!< RPMSG 1->2 Interrupt        */
+    RPMSG_13_IRQn          = 290,      /*!< RPMSG 1->3 Interrupt        */
+    RPMSG_20_IRQn          = 291,      /*!< RPMSG 2->0 Interrupt        */
+    RPMSG_21_IRQn          = 292,      /*!< RPMSG 2->1 Interrupt        */
+    RPMSG_23_IRQn          = 293,      /*!< RPMSG 2->3 Interrupt        */
+    RPMSG_30_IRQn          = 294,      /*!< RPMSG 3->0 Interrupt        */
+    RPMSG_31_IRQn          = 295,      /*!< RPMSG 3->1 Interrupt        */
+    RPMSG_32_IRQn          = 296,      /*!< RPMSG 3->2 Interrupt        */
+    NUM_INTERRUPTS         = 352,
+} IRQn_Type;
+#endif
+
+#define RSVD_IRQn(_N)               (RSVD0_IRQn + (_N))
+
+#define AMP_CPUOFF_REQ_IRQ(cpu)     RSVD_IRQn(11 + (cpu)) /* gic irq: 294 */
+#define GIC_TOUCH_REQ_IRQ(cpu)      (AMP_CPUOFF_REQ_IRQ(4) + cpu) /* gic irq: 298 */
+
+#define GPIO_IRQ_GROUP_DIRQ_BASE    RSVD_IRQn(37) /* gic irq: 320 */
+#define GPIO_IRQ_GROUP_DIRQ_NUM     (NUM_INTERRUPTS - GPIO_IRQ_GROUP_DIRQ_BASE)
+
+#define GPIO_IRQ_GROUP_GPIO0_HWIRQ  GPIO0_IRQn
+#define GPIO_IRQ_GROUP_GPION_HWIRQ  GPIO4_IRQn
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+#if defined(HAL_AP_CORE) && defined(HAL_MCU_CORE)
+#error "HAL_AP_CORE and HAL_MCU_CORE only one of them can be enabled"
+#endif
+
+// #if !defined(HAL_AP_CORE) && !defined(HAL_MCU_CORE)
+// #error "Please define HAL_AP_CORE or HAL_MCU_CORE on hal_conf.h"
+// #endif
+
+#ifdef HAL_AP_CORE
+#define __CORTEX_A           55U          /* Cortex-A55 Core                          */
+#define __FPU_PRESENT         1U          /* FPU present                              */
+#define __TIM_PRESENT         1U          /* Generic Timer                            */
+
+#define CACHE_LINE_SHIFT    (6U)
+#define CACHE_LINE_SIZE     (0x1U << CACHE_LINE_SHIFT)
+
+#else
+#define __RISC_V
+#endif
+
+// #ifndef __ASSEMBLY__
+// #include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+// #ifdef __CORTEX_A
+// #include "core_ca.h"
+// #endif
+// #include "system_rk3568.h"
+// #endif /* __ASSEMBLY__ */
+#include "rk3568.h"
+
+/****************************************************************************************/
+/*                                                                                      */
+/*                                Module Address Section                                */
+/*                                                                                      */
+/****************************************************************************************/
+/* Memory Base */
+#define PCIE3X2_DBI_BASE        0xF6000000 /* PCIe dbi base address */
+#define GIC_DISTRIBUTOR_BASE    0xFD400000 /* GICD base address */
+#define GIC_REDISTRIBUTOR_BASE  0xFD460000 /* GICR base address */
+#define PCIE3PHY_GRF_BASE       0xFDCB8000 /* S-PHY_GRF base address */
+#define PCIE3X2_APB_BASE        0xFE280000 /* PCIe apb base address */
+
+/****************************************************************************************/
+/*                                                                                      */
+/*                               Register Bitmap Section                                */
+/*                                                                                      */
+/****************************************************************************************/
+/********************************** CPU Topology ****************************************/
+#define MPIDR_MT_MASK       ((1U) << 24)
+#define MPIDR_AFFLVL_MASK   (0xFFU)
+#define MPIDR_AFF0_SHIFT    (0U)
+#define MPIDR_AFF1_SHIFT    (8U)
+#define MPIDR_AFF2_SHIFT    (16U)
+#define MPIDR_AFF3_SHIFT    (32U)
+#define MPIDR_AFFINITY_MASK (0xFFFFFFU)
+#define PLATFORM_CLUSTER0_CORE_COUNT (4)
+#define PLATFORM_CLUSTER1_CORE_COUNT (0)
+#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
+#define CPU_GET_AFFINITY(cpuId, clusterId) ((cpuId) << MPIDR_AFF1_SHIFT)
+
+/********************************** CACHE ECC ****************************************/
+#ifndef __ASSEMBLY__
+/** @addtogroup CACHE_ECC_Exported_Definition_Group1
+ *  @{
+ */
+/** the fault value will be injected */
+typedef enum {
+    CACHE_ECC_INJECT_UC     = 0x80000002, /**< Uncontainable Error generation */
+    CACHE_ECC_INJECT_DE_UER = 0x8000000a, /**< for l1~l2, generate a exception */
+} eCACHE_ECC_InjectFault;
+/** @} */
+#endif
+/******************************************CRU*******************************************/
+#define PLL_INPUT_OSC_RATE (24 * 1000 * 1000)
+
+#define CRU_SRST_CON_CNT    29
+#define CRU_GATE_CON_CNT    35
+#define CRU_CLK_DIV_CON_CNT 84
+#define CRU_CLK_SEL_CON_CNT 84
+
+#define CLK(mux, div) \
+    (((mux) & 0x0F0F00FFU) | (((div) & 0xFFU) << 8) | (((div) & 0x0F0F0000U) << 4))
+
+#ifndef __ASSEMBLY__
+typedef enum CLOCK_Name {
+    CLK_INVALID = 0U,
+    PLL_APLL,
+    PLL_CPLL,
+    PLL_GPLL,
+    PLL_NPLL,
+    PLL_VPLL,
+    PLL_PPLL,
+    PLL_HPLL,
+    CLK_WDT,
+    CLK_UART0,
+    CLK_I2C        = CLK(CLK_I2C_SEL, 0U),
+    CLK_PWM1       = CLK(CLK_PWM1_SEL, 0U),
+    CLK_PWM2       = CLK(CLK_PWM2_SEL, 0U),
+    CLK_PWM3       = CLK(CLK_PWM3_SEL, 0U),
+    CLK_SPI0       = CLK(CLK_SPI0_SEL, 0U),
+    CLK_SPI1       = CLK(CLK_SPI1_SEL, 0U),
+    CLK_SPI2       = CLK(CLK_SPI2_SEL, 0U),
+    CLK_SPI3       = CLK(CLK_SPI3_SEL, 0U),
+    CLK_UART1_SRC  = CLK(CLK_UART1_SRC_SEL, CLK_UART1_SRC_DIV),
+    CLK_UART1_FRAC = CLK(0U, CLK_UART1_FRAC_DIV),
+    CLK_UART1      = CLK(SCLK_UART1_SEL, 0U),
+    CLK_UART2_SRC  = CLK(CLK_UART2_SRC_SEL, CLK_UART2_SRC_DIV),
+    CLK_UART2_FRAC = CLK(0U, CLK_UART2_FRAC_DIV),
+    CLK_UART2      = CLK(SCLK_UART2_SEL, 0U),
+    CLK_UART3_SRC  = CLK(CLK_UART3_SRC_SEL, CLK_UART3_SRC_DIV),
+    CLK_UART3_FRAC = CLK(0U, CLK_UART3_FRAC_DIV),
+    CLK_UART3      = CLK(SCLK_UART3_SEL, 0U),
+    CLK_UART4_SRC  = CLK(CLK_UART4_SRC_SEL, CLK_UART4_SRC_DIV),
+    CLK_UART4_FRAC = CLK(0U, CLK_UART4_FRAC_DIV),
+    CLK_UART4      = CLK(SCLK_UART4_SEL, 0U),
+    CLK_UART5_SRC  = CLK(CLK_UART5_SRC_SEL, CLK_UART5_SRC_DIV),
+    CLK_UART5_FRAC = CLK(0U, CLK_UART5_FRAC_DIV),
+    CLK_UART5      = CLK(SCLK_UART5_SEL, 0U),
+    CLK_UART6_SRC  = CLK(CLK_UART6_SRC_SEL, CLK_UART6_SRC_DIV),
+    CLK_UART6_FRAC = CLK(0U, CLK_UART6_FRAC_DIV),
+    CLK_UART6      = CLK(SCLK_UART6_SEL, 0U),
+    CLK_UART7_SRC  = CLK(CLK_UART7_SRC_SEL, CLK_UART7_SRC_DIV),
+    CLK_UART7_FRAC = CLK(0U, CLK_UART7_FRAC_DIV),
+    CLK_UART7      = CLK(SCLK_UART7_SEL, 0U),
+    CLK_UART8_SRC  = CLK(CLK_UART8_SRC_SEL, CLK_UART8_SRC_DIV),
+    CLK_UART8_FRAC = CLK(0U, CLK_UART8_FRAC_DIV),
+    CLK_UART8      = CLK(SCLK_UART8_SEL, 0U),
+    CLK_UART9_SRC  = CLK(CLK_UART9_SRC_SEL, CLK_UART9_SRC_DIV),
+    CLK_UART9_FRAC = CLK(0U, CLK_UART9_FRAC_DIV),
+    CLK_UART9      = CLK(SCLK_UART9_SEL, 0U),
+    CLK_CAN0       = CLK(CLK_CAN0_SEL, CLK_CAN0_DIV),
+    CLK_CAN1       = CLK(CLK_CAN1_SEL, CLK_CAN1_DIV),
+    CLK_CAN2       = CLK(CLK_CAN2_SEL, CLK_CAN2_DIV),
+    CLK_TSADC_TSEN = CLK(CLK_TSADC_TSEN_SEL, CLK_TSADC_TSEN_DIV),
+    CLK_TSADC      = CLK(0, CLK_TSADC_DIV),
+    SCLK_SFC       = CLK(SCLK_SFC_SEL, 0U),
+    CLK_MAC0_2TOP          = CLK(CLK_MAC0_2TOP_SEL, 0U),
+    CLK_MAC1_2TOP          = CLK(CLK_MAC1_2TOP_SEL, 0U),
+    CLK_MAC0_OUT           = CLK(CLK_MAC0_OUT_SEL, 0U),
+    CLK_MAC1_OUT           = CLK(CLK_MAC1_OUT_SEL, 0U),
+    CLK_GMAC0_PTP_REF      = CLK(CLK_GMAC0_PTP_REF_SEL, 0U),
+    CLK_GMAC1_PTP_REF      = CLK(CLK_GMAC1_PTP_REF_SEL, 0U),
+    SCLK_GMAC0             = CLK(RMII0_EXTCLK_SEL, 0U),
+    SCLK_GMAC1             = CLK(RMII1_EXTCLK_SEL, 0U),
+    SCLK_GMAC0_RGMII_SPEED = CLK(RGMII0_CLK_SEL, 0U),
+    SCLK_GMAC1_RGMII_SPEED = CLK(RGMII1_CLK_SEL, 0U),
+    SCLK_GMAC0_RMII_SPEED  = CLK(RMII0_CLK_SEL, 0U),
+    SCLK_GMAC1_RMII_SPEED  = CLK(RMII1_CLK_SEL, 0U),
+    SCLK_GMAC0_RX_TX       = CLK(CLK_GMAC0_RX_TX_SEL, 0U),
+    SCLK_GMAC1_RX_TX       = CLK(CLK_GMAC1_RX_TX_SEL, 0U),
+    ACLK_PHP               = CLK(ACLK_PHP_SEL, 0U),
+    HCLK_PHP               = CLK(HCLK_PHP_SEL, 0U),
+    PCLK_PHP               = CLK(0U, PCLK_PHP_DIV),
+    ACLK_USB               = CLK(ACLK_USB_SEL, 0U),
+    HCLK_USB               = CLK(HCLK_USB_SEL, 0U),
+    PCLK_USB               = CLK(0U, PCLK_USB_DIV),
+} eCLOCK_Name;
+#endif
+/****************************************MBOX********************************************/
+#define MBOX_CNT             2
+#define MBOX_CHAN_CNT        4
+/****************************************GRF*********************************************/
+#define GRF_IOMUX_BIT_PER_PIN	(4)
+#define GRF_DS_BIT_PER_PIN	(8)
+#define GRF_PULL_BIT_PER_PIN	(2)
+/****************************************GPIO********************************************/
+#ifdef GPIO_VER_ID
+#undef GPIO_VER_ID
+#define GPIO_VER_ID             (0x01000C2BU)
+#endif
+/****************************************PMU*********************************************/
+#ifndef __ASSEMBLY__
+typedef enum PD_Id {
+    PD_INVALID = 0U,
+} ePD_Id;
+#endif
+/****************************************FSPI********************************************/
+#define FSPI_CHIP_CNT                            (2)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __SOC_H */