forked from xuos/xiuos
88 lines
2.7 KiB
C
88 lines
2.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Copyright (c) 2020-2021 Rockchip Electronics Co., Ltd.
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*/
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/** @addtogroup RK_HAL_Driver
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* @{
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*/
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/** @addtogroup CACHE
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* @{
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*/
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#ifndef _HAL_CACHE_H_
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#define _HAL_CACHE_H_
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#include "hal_def.h"
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#include "hal_debug.h"
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/***************************** MACRO Definition ******************************/
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/** @defgroup CACHE_Exported_Definition_Group1 Basic Definition
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* @{
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*/
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/***************************** Structure Definition **************************/
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/**
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* performance measurement count for icache & dcache
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*
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*/
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struct CACHE_PMU_CNT {
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uint32_t rdNum; /**< PMU read number counter */
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uint32_t wrNum; /**< PMU write number counter */
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uint32_t sramRdHit; /**< PMU SRAM hit counter */
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uint32_t hbRdHit; /**< PMU hot buffer hit */
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uint32_t stbRdHit; /**< PMU store buffer hit */
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uint32_t rdHit; /**< PMU read hit counter */
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uint32_t wrHit; /**< PMU write hit counter */
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uint32_t rdMissPenalty; /**< PMU read miss penalty counter */
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uint32_t wrMissPenalty; /**< PMU write miss penalty counter */
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uint32_t rdLat; /**< PMU read latency */
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uint32_t wrLat; /**< PMU write latency */
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};
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/** @} */
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/********************* Public Function Definition ****************************/
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/** @defgroup CACHE_Exported_Functions_Group5 Other Functions
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* @attention these APIs allow direct use in the HAL layer
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* @{
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*/
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uint32_t HAL_CpuAddrToDmaAddr(uint32_t cpuAddr);
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HAL_Status HAL_ICACHE_Enable(void);
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HAL_Status HAL_ICACHE_Disable(void);
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HAL_Status HAL_ICACHE_Invalidate(void);
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HAL_Status HAL_ICACHE_InvalidateByRange(uint32_t address, uint32_t sizeByte);
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HAL_Status HAL_ICACHE_EnablePMU(void);
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HAL_Status HAL_ICACHE_DisablePMU(void);
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HAL_Status HAL_ICACHE_GetPMU(struct CACHE_PMU_CNT *stat);
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HAL_Status HAL_ICACHE_EnableInt(void);
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HAL_Status HAL_ICACHE_DisableInt(void);
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HAL_Check HAL_ICACHE_GetInt(void);
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uint32_t HAL_ICACHE_GetErrAddr(void);
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HAL_Status HAL_ICACHE_ClearInt(void);
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HAL_Status HAL_DCACHE_Enable(void);
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HAL_Status HAL_DCACHE_Disable(void);
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HAL_Status HAL_DCACHE_Invalidate(void);
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HAL_Status HAL_DCACHE_InvalidateByRange(uint32_t address, uint32_t sizeByte);
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HAL_Status HAL_DCACHE_CleanByRange(uint32_t address, uint32_t sizeByte);
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HAL_Status HAL_DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t sizeByte);
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HAL_Status HAL_DCACHE_CleanInvalidate(void);
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HAL_Status HAL_DCACHE_EnablePMU(void);
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HAL_Status HAL_DCACHE_DisablePMU(void);
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HAL_Status HAL_DCACHE_GetPMU(struct CACHE_PMU_CNT *stat);
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HAL_Status HAL_DCACHE_EnableInt(void);
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HAL_Status HAL_DCACHE_DisableInt(void);
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HAL_Check HAL_DCACHE_GetInt(void);
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HAL_Status HAL_DCACHE_ClearInt(void);
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uint32_t HAL_DCACHE_GetErrAddr(void);
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/** @} */
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#endif
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/** @} */
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/** @} */
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