forked from xuos/xiuos
chunyexixiaoyu
commit
041435971b
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@ -0,0 +1,354 @@
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|||
#
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# Automatically generated file; DO NOT EDIT.
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# RT-Thread Configuration
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#
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CONFIG_ROOT_DIR="../../../.."
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CONFIG_BSP_DIR="."
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CONFIG_RT_Thread_DIR="../.."
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CONFIG_RTT_DIR="../../rt-thread"
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#
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# RT-Thread Kernel
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#
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||||
CONFIG_RT_NAME_MAX=8
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||||
# CONFIG_RT_USING_BIG_ENDIAN is not set
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||||
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
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# CONFIG_RT_USING_SMP is not set
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||||
CONFIG_RT_ALIGN_SIZE=4
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# CONFIG_RT_THREAD_PRIORITY_8 is not set
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CONFIG_RT_THREAD_PRIORITY_32=y
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||||
# CONFIG_RT_THREAD_PRIORITY_256 is not set
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||||
CONFIG_RT_THREAD_PRIORITY_MAX=32
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CONFIG_RT_TICK_PER_SECOND=1000
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CONFIG_RT_USING_OVERFLOW_CHECK=y
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CONFIG_RT_USING_HOOK=y
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CONFIG_RT_USING_IDLE_HOOK=y
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||||
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
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||||
CONFIG_IDLE_THREAD_STACK_SIZE=256
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# CONFIG_RT_USING_TIMER_SOFT is not set
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#
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||||
# kservice optimization
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#
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# CONFIG_RT_KSERVICE_USING_STDLIB is not set
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# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
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||||
# CONFIG_RT_USING_ASM_MEMCPY is not set
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CONFIG_RT_DEBUG=y
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CONFIG_RT_DEBUG_COLOR=y
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||||
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
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||||
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
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||||
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
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||||
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
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# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
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||||
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
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# CONFIG_RT_DEBUG_MEM_CONFIG is not set
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# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
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# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
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# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
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#
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# Inter-Thread communication
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#
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CONFIG_RT_USING_SEMAPHORE=y
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CONFIG_RT_USING_MUTEX=y
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CONFIG_RT_USING_EVENT=y
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CONFIG_RT_USING_MAILBOX=y
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CONFIG_RT_USING_MESSAGEQUEUE=y
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# CONFIG_RT_USING_SIGNALS is not set
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#
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# Memory Management
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#
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CONFIG_RT_USING_MEMPOOL=y
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CONFIG_RT_USING_MEMHEAP=y
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CONFIG_RT_USING_MEMHEAP_AUTO_BINDING=y
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# CONFIG_RT_USING_NOHEAP is not set
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# CONFIG_RT_USING_SMALL_MEM is not set
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# CONFIG_RT_USING_SLAB is not set
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CONFIG_RT_USING_MEMHEAP_AS_HEAP=y
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# CONFIG_RT_USING_USERHEAP is not set
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# CONFIG_RT_USING_MEMTRACE is not set
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CONFIG_RT_USING_HEAP=y
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#
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# Kernel Device Object
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#
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CONFIG_RT_USING_DEVICE=y
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# CONFIG_RT_USING_DEVICE_OPS is not set
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# CONFIG_RT_USING_INTERRUPT_INFO is not set
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CONFIG_RT_USING_CONSOLE=y
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CONFIG_RT_CONSOLEBUF_SIZE=256
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CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
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# CONFIG_RT_PRINTF_LONGLONG is not set
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CONFIG_RT_VER_NUM=0x40004
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CONFIG_ARCH_ARM=y
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CONFIG_RT_USING_CPU_FFS=y
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CONFIG_ARCH_ARM_CORTEX_M=y
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CONFIG_ARCH_ARM_CORTEX_M7=y
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# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
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#
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# RT-Thread Components
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#
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CONFIG_RT_USING_COMPONENTS_INIT=y
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CONFIG_RT_USING_USER_MAIN=y
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CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
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CONFIG_RT_MAIN_THREAD_PRIORITY=10
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#
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# C++ features
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#
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CONFIG_RT_USING_CPLUSPLUS=y
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# CONFIG_RT_USING_CPLUSPLUS11 is not set
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#
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# Command shell
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#
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CONFIG_RT_USING_FINSH=y
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CONFIG_RT_USING_MSH=y
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CONFIG_FINSH_USING_MSH=y
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CONFIG_FINSH_THREAD_NAME="tshell"
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CONFIG_FINSH_THREAD_PRIORITY=20
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CONFIG_FINSH_THREAD_STACK_SIZE=4096
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CONFIG_FINSH_USING_HISTORY=y
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CONFIG_FINSH_HISTORY_LINES=5
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CONFIG_FINSH_USING_SYMTAB=y
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CONFIG_FINSH_CMD_SIZE=80
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CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
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CONFIG_FINSH_USING_DESCRIPTION=y
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# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
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# CONFIG_FINSH_USING_AUTH is not set
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CONFIG_FINSH_ARG_MAX=10
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#
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# Device virtual file system
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#
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CONFIG_RT_USING_DFS=y
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CONFIG_DFS_USING_WORKDIR=y
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CONFIG_DFS_FILESYSTEMS_MAX=4
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CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
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CONFIG_DFS_FD_MAX=16
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# CONFIG_RT_USING_DFS_MNTTABLE is not set
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CONFIG_RT_USING_DFS_ELMFAT=y
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#
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# elm-chan's FatFs, Generic FAT Filesystem Module
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#
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CONFIG_RT_DFS_ELM_CODE_PAGE=437
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CONFIG_RT_DFS_ELM_WORD_ACCESS=y
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# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
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# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
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# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
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CONFIG_RT_DFS_ELM_USE_LFN_3=y
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CONFIG_RT_DFS_ELM_USE_LFN=3
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CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y
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||||
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
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# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
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# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
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||||
CONFIG_RT_DFS_ELM_LFN_UNICODE=0
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CONFIG_RT_DFS_ELM_MAX_LFN=255
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CONFIG_RT_DFS_ELM_DRIVES=2
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CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
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# CONFIG_RT_DFS_ELM_USE_ERASE is not set
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||||
CONFIG_RT_DFS_ELM_REENTRANT=y
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||||
CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000
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||||
CONFIG_RT_USING_DFS_DEVFS=y
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||||
CONFIG_RT_USING_DFS_ROMFS=y
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||||
# CONFIG_RT_USING_DFS_RAMFS is not set
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||||
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||||
#
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||||
# Device Drivers
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||||
#
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||||
CONFIG_RT_USING_DEVICE_IPC=y
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||||
CONFIG_RT_PIPE_BUFSZ=512
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# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
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CONFIG_RT_USING_SERIAL=y
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CONFIG_RT_USING_SERIAL_V1=y
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# CONFIG_RT_USING_SERIAL_V2 is not set
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||||
CONFIG_RT_SERIAL_USING_DMA=y
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||||
CONFIG_RT_SERIAL_RB_BUFSZ=64
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# CONFIG_RT_USING_CAN is not set
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||||
# CONFIG_RT_USING_HWTIMER is not set
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||||
# CONFIG_RT_USING_CPUTIME is not set
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||||
# CONFIG_RT_USING_I2C is not set
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||||
# CONFIG_RT_USING_PHY is not set
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||||
CONFIG_RT_USING_PIN=y
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||||
# CONFIG_RT_USING_ADC is not set
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||||
# CONFIG_RT_USING_DAC is not set
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||||
# CONFIG_RT_USING_PWM is not set
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||||
# CONFIG_RT_USING_MTD_NOR is not set
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||||
# CONFIG_RT_USING_MTD_NAND is not set
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||||
# CONFIG_RT_USING_PM is not set
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||||
# CONFIG_RT_USING_RTC is not set
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||||
# CONFIG_RT_USING_SDIO is not set
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||||
# CONFIG_RT_USING_SPI is not set
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||||
# CONFIG_RT_USING_WDT is not set
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||||
# CONFIG_RT_USING_AUDIO is not set
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||||
# CONFIG_RT_USING_SENSOR is not set
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||||
# CONFIG_RT_USING_TOUCH is not set
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||||
# CONFIG_RT_USING_HWCRYPTO is not set
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||||
# CONFIG_RT_USING_PULSE_ENCODER is not set
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||||
# CONFIG_RT_USING_INPUT_CAPTURE is not set
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||||
# CONFIG_RT_USING_WIFI is not set
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||||
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||||
#
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||||
# Using USB
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||||
#
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||||
# CONFIG_RT_USING_USB_HOST is not set
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||||
# CONFIG_RT_USING_USB_DEVICE is not set
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||||
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||||
#
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||||
# POSIX layer and C standard library
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||||
#
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||||
CONFIG_RT_USING_LIBC=y
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||||
CONFIG_RT_USING_PTHREADS=y
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||||
CONFIG_PTHREAD_NUM_MAX=8
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||||
CONFIG_RT_USING_POSIX=y
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||||
# CONFIG_RT_USING_POSIX_MMAP is not set
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||||
# CONFIG_RT_USING_POSIX_TERMIOS is not set
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||||
# CONFIG_RT_USING_POSIX_GETLINE is not set
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||||
# CONFIG_RT_USING_POSIX_AIO is not set
|
||||
CONFIG_RT_LIBC_USING_TIME=y
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||||
# CONFIG_RT_USING_MODULE is not set
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||||
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
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||||
|
||||
#
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||||
# Network
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||||
#
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||||
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||||
#
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||||
# Socket abstraction layer
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||||
#
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||||
# CONFIG_RT_USING_SAL is not set
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||||
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||||
#
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||||
# Network interface device
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||||
#
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||||
# CONFIG_RT_USING_NETDEV is not set
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||||
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||||
#
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||||
# light weight TCP/IP stack
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||||
#
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||||
# CONFIG_RT_USING_LWIP is not set
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||||
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||||
#
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||||
# AT commands
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||||
#
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||||
# CONFIG_RT_USING_AT is not set
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||||
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||||
#
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||||
# VBUS(Virtual Software BUS)
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||||
#
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||||
# CONFIG_RT_USING_VBUS is not set
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||||
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||||
#
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||||
# Utilities
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||||
#
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||||
# CONFIG_RT_USING_RYM is not set
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||||
# CONFIG_RT_USING_ULOG is not set
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||||
# CONFIG_RT_USING_UTEST is not set
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||||
# CONFIG_RT_USING_VAR_EXPORT is not set
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||||
# CONFIG_RT_USING_RT_LINK is not set
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||||
# CONFIG_RT_USING_LWP is not set
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||||
|
||||
#
|
||||
# RT-Thread Utestcases
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||||
#
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||||
# CONFIG_RT_USING_UTESTCASES is not set
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||||
CONFIG_SOC_FAMILY_STM32=y
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||||
CONFIG_SOC_SERIES_STM32H7=y
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||||
|
||||
#
|
||||
# Hardware Drivers Config
|
||||
#
|
||||
CONFIG_SOC_STM32H743II=y
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||||
|
||||
#
|
||||
# On-chip Peripheral Drivers
|
||||
#
|
||||
CONFIG_BSP_USING_GPIO=y
|
||||
CONFIG_BSP_USING_UART=y
|
||||
CONFIG_BSP_USING_UART1=y
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||||
# CONFIG_BSP_UART1_RX_USING_DMA is not set
|
||||
# CONFIG_BSP_USING_UART2 is not set
|
||||
# CONFIG_BSP_USING_LPUART1 is not set
|
||||
CONFIG_BSP_USING_SDRAM=y
|
||||
# CONFIG_BSP_USING_CRC is not set
|
||||
# CONFIG_BSP_USING_RNG is not set
|
||||
# CONFIG_BSP_USING_UDID is not set
|
||||
|
||||
#
|
||||
# More Drivers
|
||||
#
|
||||
# CONFIG_PKG_USING_RW007 is not set
|
||||
# CONFIG_DRV_USING_OV2640 is not set
|
||||
|
||||
#
|
||||
# APP_Framework
|
||||
#
|
||||
|
||||
#
|
||||
# Framework
|
||||
#
|
||||
CONFIG_TRANSFORM_LAYER_ATTRIUBUTE=y
|
||||
CONFIG_ADD_XIZI_FETURES=y
|
||||
# CONFIG_ADD_NUTTX_FETURES is not set
|
||||
# CONFIG_ADD_RTTHREAD_FETURES is not set
|
||||
# CONFIG_SUPPORT_SENSOR_FRAMEWORK is not set
|
||||
# CONFIG_SUPPORT_CONNECTION_FRAMEWORK is not set
|
||||
# CONFIG_SUPPORT_KNOWING_FRAMEWORK is not set
|
||||
# CONFIG_SUPPORT_CONTROL_FRAMEWORK is not set
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
# CONFIG_CRYPTO is not set
|
||||
|
||||
#
|
||||
# Applications
|
||||
#
|
||||
|
||||
#
|
||||
# config stack size and priority of main task
|
||||
#
|
||||
CONFIG_MAIN_KTASK_STACK_SIZE=1024
|
||||
|
||||
#
|
||||
# ota app
|
||||
#
|
||||
# CONFIG_APPLICATION_OTA is not set
|
||||
|
||||
#
|
||||
# test app
|
||||
#
|
||||
# CONFIG_USER_TEST is not set
|
||||
|
||||
#
|
||||
# connection app
|
||||
#
|
||||
# CONFIG_APPLICATION_CONNECTION is not set
|
||||
|
||||
#
|
||||
# control app
|
||||
#
|
||||
|
||||
#
|
||||
# knowing app
|
||||
#
|
||||
# CONFIG_APPLICATION_KNOWING is not set
|
||||
|
||||
#
|
||||
# sensor app
|
||||
#
|
||||
# CONFIG_APPLICATION_SENSOR is not set
|
||||
# CONFIG_USING_EMBEDDED_DATABASE_APP is not set
|
||||
|
||||
#
|
||||
# lib
|
||||
#
|
||||
CONFIG_APP_SELECT_NEWLIB=y
|
||||
# CONFIG_APP_SELECT_OTHER_LIB is not set
|
||||
# CONFIG_LIB_USING_CJSON is not set
|
||||
# CONFIG_LIB_USING_QUEUE is not set
|
||||
# CONFIG_LIB_LV is not set
|
||||
# CONFIG_USING_EMBEDDED_DATABASE is not set
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
*.pyc
|
||||
*.map
|
||||
*.dblite
|
||||
*.elf
|
||||
*.bin
|
||||
*.hex
|
||||
*.axf
|
||||
*.exe
|
||||
*.pdb
|
||||
*.idb
|
||||
*.ilk
|
||||
*.old
|
||||
build
|
||||
Debug
|
||||
documentation/html
|
||||
packages/
|
||||
*~
|
||||
*.o
|
||||
*.obj
|
||||
*.out
|
||||
*.bak
|
||||
*.dep
|
||||
*.lib
|
||||
*.i
|
||||
*.d
|
||||
.DS_Stor*
|
||||
.config 3
|
||||
.config 4
|
||||
.config 5
|
||||
Midea-X1
|
||||
*.uimg
|
||||
GPATH
|
||||
GRTAGS
|
||||
GTAGS
|
||||
.vscode
|
||||
JLinkLog.txt
|
||||
JLinkSettings.ini
|
||||
DebugConfig/
|
||||
RTE/
|
||||
settings/
|
||||
*.uvguix*
|
||||
cconfig.h
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
mainmenu "RT-Thread Configuration"
|
||||
|
||||
config ROOT_DIR
|
||||
string
|
||||
default "../../../.."
|
||||
|
||||
config BSP_DIR
|
||||
string
|
||||
default "."
|
||||
|
||||
config RT_Thread_DIR
|
||||
string
|
||||
default "../.."
|
||||
|
||||
config RTT_DIR
|
||||
string
|
||||
default "../../rt-thread"
|
||||
|
||||
|
||||
config APP_DIR
|
||||
string
|
||||
default "../../../../APP_Framework"
|
||||
|
||||
source "$RTT_DIR/Kconfig"
|
||||
source "$RTT_DIR/bsp/stm32/libraries/Kconfig"
|
||||
source "board/Kconfig"
|
||||
source "$RT_Thread_DIR/app_match_rt-thread/Kconfig"
|
||||
source "$ROOT_DIR/APP_Framework/Kconfig"
|
||||
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
# OPENMV4 H7 PLUS说明
|
||||
|
||||
## 使用说明
|
||||
|
||||
- 使用ST-LINK无法连接OPENMV时，可以尝试连接RST引脚和GND引脚进入RESET后连接。
|
||||
- 当前串口通信需要使用USB转TTL连接USART1(P1 TX)(P0 RX)。
|
||||
- 用户RAM空间为512Kb AXI-SRAM，起始地址 0x24000000。
|
||||
|
||||
## 以下为引脚硬件的连接表
|
||||
|
||||
### GPIO
|
||||
|
||||
| 引脚 | 作用 |
|
||||
| ---- | ----- |
|
||||
| PC0 | LED_R |
|
||||
| PC1 | LED_G |
|
||||
| PC2 | LED_B |
|
||||
|
||||
### USART1 串口
|
||||
|
||||
| 引脚 | 作用 |
|
||||
| ---- | --------- |
|
||||
| PB14 | USART1 TX |
|
||||
| PB15 | USART1 RX |
|
||||
|
||||
### SDRAM (FMC接口) IS42S32800 BANK1
|
||||
|
||||
| 引脚 | 作用 |
|
||||
| ---- | ---------- |
|
||||
| PF0 | FMC_A0 |
|
||||
| PF1 | FMC_A1 |
|
||||
| PF2 | FMC_A2 |
|
||||
| PF3 | FMC_A3 |
|
||||
| PF4 | FMC_A4 |
|
||||
| PF5 | FMC_A5 |
|
||||
| PF12 | FMC_A6 |
|
||||
| PF13 | FMC_A7 |
|
||||
| PF14 | FMC_A8 |
|
||||
| PF15 | FMC_A9 |
|
||||
| PG0 | FMC_A10 |
|
||||
| PG1 | FMC_A11 |
|
||||
| PG4 | FMC_BA0 |
|
||||
| PG5 | FMC_BA1 |
|
||||
| PD14 | FMC_D0 |
|
||||
| PD15 | FMC_D1 |
|
||||
| PD0 | FMC_D2 |
|
||||
| PD1 | FMC_D3 |
|
||||
| PE7 | FMC_D4 |
|
||||
| PE8 | FMC_D5 |
|
||||
| PE9 | FMC_D6 |
|
||||
| PE10 | FMC_D7 |
|
||||
| PE11 | FMC_D8 |
|
||||
| PE12 | FMC_D9 |
|
||||
| PE13 | FMC_D10 |
|
||||
| PE14 | FMC_D11 |
|
||||
| PE15 | FMC_D12 |
|
||||
| PD8 | FMC_D13 |
|
||||
| PD9 | FMC_D14 |
|
||||
| PD10 | FMC_D15 |
|
||||
| PH8 | FMC_D16 |
|
||||
| PH9 | FMC_D17 |
|
||||
| PH10 | FMC_D18 |
|
||||
| PH11 | FMC_D19 |
|
||||
| PH12 | FMC_D20 |
|
||||
| PH13 | FMC_D21 |
|
||||
| PH14 | FMC_D22 |
|
||||
| PH15 | FMC_D23 |
|
||||
| PI0 | FMC_D24 |
|
||||
| PI1 | FMC_D25 |
|
||||
| PI2 | FMC_D26 |
|
||||
| PI3 | FMC_D27 |
|
||||
| PI6 | FMC_D28 |
|
||||
| PI7 | FMC_D29 |
|
||||
| PI9 | FMC_D30 |
|
||||
| PI10 | FMC_D31 |
|
||||
| PE0 | FMC_NBL0 |
|
||||
| PE1 | FMC_NBL1 |
|
||||
| PI4 | FMC_NBL2 |
|
||||
| PI5 | FMC_NBL3 |
|
||||
| PA7 | FMC_SDNWE |
|
||||
| PC4 | FMC_SDNE0 |
|
||||
| PC5 | FMC_SDCKE0 |
|
||||
| PG8 | FMC_SDCLK |
|
||||
| PG15 | FMC_SDNCAS |
|
||||
| PF11 | FMC_SDNRAS |
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
# for module compiling
|
||||
import os
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
import SCons
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../rt-thread')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
TARGET = 'rt-thread.' + rtconfig.TARGET_EXT
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
AddOption('--compiledb',
|
||||
dest = 'compiledb',
|
||||
action = 'store_true',
|
||||
default = False,
|
||||
help = 'generate compile_commands.json')
|
||||
|
||||
if GetOption('compiledb'):
|
||||
if int(SCons.__version__.split('.')[0]) >= 4:
|
||||
env['COMPILATIONDB_USE_ABSPATH'] = True
|
||||
env.Tool('compilation_db')
|
||||
env.CompilationDatabase('compile_commands.json')
|
||||
else:
|
||||
print('Warning: --compiledb only support on SCons 4.0+')
|
||||
|
||||
if rtconfig.PLATFORM == 'iar':
|
||||
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map')
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
|
||||
#if os.path.exists(SDK_ROOT + '/libraries'):
|
||||
# libraries_path_prefix = SDK_ROOT + '/libraries'
|
||||
#else:
|
||||
# libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
|
||||
|
||||
libraries_path_prefix = RTT_ROOT + '/bsp/stm32/libraries'
|
||||
|
||||
SDK_LIB = libraries_path_prefix
|
||||
Export('SDK_LIB')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
stm32_library = 'STM32H7xx_HAL'
|
||||
rtconfig.BSP_LIBRARY_TYPE = stm32_library
|
||||
|
||||
# include libraries
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, stm32_library, 'SConscript')))
|
||||
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'HAL_Drivers', 'SConscript')))
|
||||
|
||||
# include more drivers
|
||||
objs.extend(SConscript(os.getcwd() + '/../../app_match_rt-thread/SConscript'))
|
||||
|
||||
# include APP_Framework/Framework
|
||||
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Framework/SConscript'))
|
||||
|
||||
# include APP_Framework/Applications
|
||||
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/Applications/SConscript'))
|
||||
|
||||
# include APP_Framework/lib
|
||||
objs.extend(SConscript(os.getcwd() + '/../../../../APP_Framework/lib/SConscript'))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
import rtconfig
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
CPPPATH = [str(Dir('#')), cwd]
|
||||
src = Split('''
|
||||
main.c
|
||||
''')
|
||||
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-12-14 supperthomas first version
|
||||
* 2022-03-14 wwt add xiuos framework
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
#ifdef RT_USING_POSIX
|
||||
#include <pthread.h>
|
||||
#include <unistd.h>
|
||||
#include <stdio.h>
|
||||
#include <dfs_poll.h>
|
||||
#include <dfs_posix.h>
|
||||
#include <dfs.h>
|
||||
#ifdef RT_USING_POSIX_TERMIOS
|
||||
#include <posix_termios.h>
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define LEDR_PIN GET_PIN(C, 0)
|
||||
extern int FrameworkInit();
|
||||
|
||||
int main(void)
|
||||
{
|
||||
rt_pin_mode(LEDR_PIN, PIN_MODE_OUTPUT);
|
||||
rt_thread_mdelay(100);
|
||||
FrameworkInit();
|
||||
printf("XIUOS stm32h7 build %s %s\n",__DATE__,__TIME__);
|
||||
while (1)
|
||||
{
|
||||
rt_pin_write(LEDR_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(500);
|
||||
rt_pin_write(LEDR_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
}
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,74 @@
|
|||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file : main.h
|
||||
* @brief : Header for main.c file.
|
||||
* This file contains the common defines of the application.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __MAIN_H
|
||||
#define __MAIN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32h7xx_hal.h"
|
||||
|
||||
/* Private includes ----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Includes */
|
||||
|
||||
/* USER CODE END Includes */
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN ET */
|
||||
|
||||
/* USER CODE END ET */
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* USER CODE BEGIN EC */
|
||||
|
||||
/* USER CODE END EC */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN EM */
|
||||
|
||||
/* USER CODE END EM */
|
||||
|
||||
/* Exported functions prototypes ---------------------------------------------*/
|
||||
void Error_Handler(void);
|
||||
|
||||
/* USER CODE BEGIN EFP */
|
||||
|
||||
/* USER CODE END EFP */
|
||||
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
#define LED_RED_Pin GPIO_PIN_0
|
||||
#define LED_RED_GPIO_Port GPIOC
|
||||
#define LED_GREEN_Pin GPIO_PIN_1
|
||||
#define LED_GREEN_GPIO_Port GPIOC
|
||||
#define LED_BLUE_Pin GPIO_PIN_2
|
||||
#define LED_BLUE_GPIO_Port GPIOC
|
||||
/* USER CODE BEGIN Private defines */
|
||||
|
||||
/* USER CODE END Private defines */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MAIN_H */
|
||||
|
|
@ -0,0 +1,510 @@
|
|||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_conf.h
|
||||
* @author MCD Application Team
|
||||
* @brief HAL configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef STM32H7xx_HAL_CONF_H
|
||||
#define STM32H7xx_HAL_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/* ########################## Module Selection ############################## */
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the HAL driver
|
||||
*/
|
||||
#define HAL_MODULE_ENABLED
|
||||
|
||||
/* #define HAL_ADC_MODULE_ENABLED */
|
||||
/* #define HAL_FDCAN_MODULE_ENABLED */
|
||||
/* #define HAL_FMAC_MODULE_ENABLED */
|
||||
/* #define HAL_CEC_MODULE_ENABLED */
|
||||
/* #define HAL_COMP_MODULE_ENABLED */
|
||||
/* #define HAL_CORDIC_MODULE_ENABLED */
|
||||
/* #define HAL_CRC_MODULE_ENABLED */
|
||||
/* #define HAL_CRYP_MODULE_ENABLED */
|
||||
/* #define HAL_DAC_MODULE_ENABLED */
|
||||
/* #define HAL_DCMI_MODULE_ENABLED */
|
||||
/* #define HAL_DMA2D_MODULE_ENABLED */
|
||||
/* #define HAL_ETH_MODULE_ENABLED */
|
||||
/* #define HAL_NAND_MODULE_ENABLED */
|
||||
/* #define HAL_NOR_MODULE_ENABLED */
|
||||
/* #define HAL_OTFDEC_MODULE_ENABLED */
|
||||
/* #define HAL_SRAM_MODULE_ENABLED */
|
||||
#define HAL_SDRAM_MODULE_ENABLED
|
||||
/* #define HAL_HASH_MODULE_ENABLED */
|
||||
/* #define HAL_HRTIM_MODULE_ENABLED */
|
||||
/* #define HAL_HSEM_MODULE_ENABLED */
|
||||
/* #define HAL_GFXMMU_MODULE_ENABLED */
|
||||
/* #define HAL_JPEG_MODULE_ENABLED */
|
||||
/* #define HAL_OPAMP_MODULE_ENABLED */
|
||||
/* #define HAL_OSPI_MODULE_ENABLED */
|
||||
/* #define HAL_OSPI_MODULE_ENABLED */
|
||||
/* #define HAL_I2S_MODULE_ENABLED */
|
||||
/* #define HAL_SMBUS_MODULE_ENABLED */
|
||||
/* #define HAL_IWDG_MODULE_ENABLED */
|
||||
/* #define HAL_LPTIM_MODULE_ENABLED */
|
||||
/* #define HAL_LTDC_MODULE_ENABLED */
|
||||
/* #define HAL_QSPI_MODULE_ENABLED */
|
||||
/* #define HAL_RAMECC_MODULE_ENABLED */
|
||||
/* #define HAL_RNG_MODULE_ENABLED */
|
||||
/* #define HAL_RTC_MODULE_ENABLED */
|
||||
/* #define HAL_SAI_MODULE_ENABLED */
|
||||
/* #define HAL_SD_MODULE_ENABLED */
|
||||
/* #define HAL_MMC_MODULE_ENABLED */
|
||||
/* #define HAL_SPDIFRX_MODULE_ENABLED */
|
||||
/* #define HAL_SPI_MODULE_ENABLED */
|
||||
/* #define HAL_SWPMI_MODULE_ENABLED */
|
||||
/* #define HAL_TIM_MODULE_ENABLED */
|
||||
#define HAL_UART_MODULE_ENABLED
|
||||
/* #define HAL_USART_MODULE_ENABLED */
|
||||
/* #define HAL_IRDA_MODULE_ENABLED */
|
||||
/* #define HAL_SMARTCARD_MODULE_ENABLED */
|
||||
/* #define HAL_WWDG_MODULE_ENABLED */
|
||||
/* #define HAL_PCD_MODULE_ENABLED */
|
||||
/* #define HAL_HCD_MODULE_ENABLED */
|
||||
/* #define HAL_DFSDM_MODULE_ENABLED */
|
||||
/* #define HAL_DSI_MODULE_ENABLED */
|
||||
/* #define HAL_JPEG_MODULE_ENABLED */
|
||||
/* #define HAL_MDIOS_MODULE_ENABLED */
|
||||
/* #define HAL_PSSI_MODULE_ENABLED */
|
||||
/* #define HAL_DTS_MODULE_ENABLED */
|
||||
#define HAL_GPIO_MODULE_ENABLED
|
||||
#define HAL_DMA_MODULE_ENABLED
|
||||
#define HAL_MDMA_MODULE_ENABLED
|
||||
#define HAL_RCC_MODULE_ENABLED
|
||||
#define HAL_FLASH_MODULE_ENABLED
|
||||
#define HAL_EXTI_MODULE_ENABLED
|
||||
#define HAL_PWR_MODULE_ENABLED
|
||||
#define HAL_I2C_MODULE_ENABLED
|
||||
#define HAL_CORTEX_MODULE_ENABLED
|
||||
#define HAL_HSEM_MODULE_ENABLED
|
||||
|
||||
/* ########################## Oscillator Values adaptation ####################*/
|
||||
/**
|
||||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSE is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSE_VALUE)
|
||||
#define HSE_VALUE (12000000UL) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
|
||||
#endif /* HSE_VALUE */
|
||||
|
||||
#if !defined (HSE_STARTUP_TIMEOUT)
|
||||
#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */
|
||||
#endif /* HSE_STARTUP_TIMEOUT */
|
||||
|
||||
/**
|
||||
* @brief Internal oscillator (CSI) default value.
|
||||
* This value is the default CSI value after Reset.
|
||||
*/
|
||||
#if !defined (CSI_VALUE)
|
||||
#define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* CSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief Internal High Speed oscillator (HSI) value.
|
||||
* This value is used by the RCC HAL module to compute the system frequency
|
||||
* (when HSI is used as system clock source, directly or through the PLL).
|
||||
*/
|
||||
#if !defined (HSI_VALUE)
|
||||
#define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz*/
|
||||
#endif /* HSI_VALUE */
|
||||
|
||||
/**
|
||||
* @brief External Low Speed oscillator (LSE) value.
|
||||
* This value is used by the UART, RTC HAL module to compute the system frequency
|
||||
*/
|
||||
#if !defined (LSE_VALUE)
|
||||
#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/
|
||||
#endif /* LSE_VALUE */
|
||||
|
||||
#if !defined (LSE_STARTUP_TIMEOUT)
|
||||
#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */
|
||||
#endif /* LSE_STARTUP_TIMEOUT */
|
||||
|
||||
#if !defined (LSI_VALUE)
|
||||
#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/
|
||||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
|
||||
The real value may vary depending on the variations
|
||||
in voltage and temperature.*/
|
||||
|
||||
/**
|
||||
* @brief External clock source for I2S peripheral
|
||||
* This value is used by the I2S HAL module to compute the I2S clock source
|
||||
* frequency, this source is inserted directly through I2S_CKIN pad.
|
||||
*/
|
||||
#if !defined (EXTERNAL_CLOCK_VALUE)
|
||||
#define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the External clock in Hz*/
|
||||
#endif /* EXTERNAL_CLOCK_VALUE */
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to use different HSE,
|
||||
=== you can define the HSE value in your toolchain compiler preprocessor. */
|
||||
|
||||
/* ########################### System Configuration ######################### */
|
||||
/**
|
||||
* @brief This is the HAL system configuration section
|
||||
*/
|
||||
#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
|
||||
#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority */
|
||||
#define USE_RTOS 0
|
||||
#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
|
||||
#define USE_SPI_CRC 0U /*!< use CRC in SPI */
|
||||
|
||||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
|
||||
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
|
||||
#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
|
||||
#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */
|
||||
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */
|
||||
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
|
||||
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */
|
||||
#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */
|
||||
#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */
|
||||
#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */
|
||||
#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */
|
||||
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */
|
||||
#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */
|
||||
#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */
|
||||
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
|
||||
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
|
||||
#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */
|
||||
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
|
||||
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */
|
||||
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */
|
||||
#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */
|
||||
#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */
|
||||
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
|
||||
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
|
||||
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
|
||||
#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */
|
||||
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */
|
||||
#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */
|
||||
#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */
|
||||
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */
|
||||
#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */
|
||||
#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OSPI register callback disabled */
|
||||
#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */
|
||||
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
|
||||
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */
|
||||
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */
|
||||
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
|
||||
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */
|
||||
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */
|
||||
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
|
||||
#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
|
||||
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
|
||||
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
|
||||
#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0U /* SWPMI register callback disabled */
|
||||
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
|
||||
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
|
||||
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
|
||||
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
|
||||
|
||||
/* ########################### Ethernet Configuration ######################### */
|
||||
#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */
|
||||
#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */
|
||||
|
||||
#define ETH_MAC_ADDR0 (0x02UL)
|
||||
#define ETH_MAC_ADDR1 (0x00UL)
|
||||
#define ETH_MAC_ADDR2 (0x00UL)
|
||||
#define ETH_MAC_ADDR3 (0x00UL)
|
||||
#define ETH_MAC_ADDR4 (0x00UL)
|
||||
#define ETH_MAC_ADDR5 (0x00UL)
|
||||
|
||||
/* ########################## Assert Selection ############################## */
|
||||
/**
|
||||
* @brief Uncomment the line below to expanse the "assert_param" macro in the
|
||||
* HAL drivers code
|
||||
*/
|
||||
/* #define USE_FULL_ASSERT 1U */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief Include module's header file
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_rcc.h"
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_gpio.h"
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_dma.h"
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MDMA_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_mdma.h"
|
||||
#endif /* HAL_MDMA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HASH_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_hash.h"
|
||||
#endif /* HAL_HASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DCMI_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_dcmi.h"
|
||||
#endif /* HAL_DCMI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DMA2D_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_dma2d.h"
|
||||
#endif /* HAL_DMA2D_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DSI_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_dsi.h"
|
||||
#endif /* HAL_DSI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DFSDM_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_dfsdm.h"
|
||||
#endif /* HAL_DFSDM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DTS_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_dts.h"
|
||||
#endif /* HAL_DTS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ETH_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_eth.h"
|
||||
#endif /* HAL_ETH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_exti.h"
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_cortex.h"
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_ADC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_adc.h"
|
||||
#endif /* HAL_ADC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FDCAN_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_fdcan.h"
|
||||
#endif /* HAL_FDCAN_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CEC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_cec.h"
|
||||
#endif /* HAL_CEC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_COMP_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_comp.h"
|
||||
#endif /* HAL_COMP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CORDIC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_cordic.h"
|
||||
#endif /* HAL_CORDIC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_crc.h"
|
||||
#endif /* HAL_CRC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_CRYP_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_cryp.h"
|
||||
#endif /* HAL_CRYP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_DAC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_dac.h"
|
||||
#endif /* HAL_DAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_flash.h"
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_GFXMMU_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_gfxmmu.h"
|
||||
#endif /* HAL_GFXMMU_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_FMAC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_fmac.h"
|
||||
#endif /* HAL_FMAC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HRTIM_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_hrtim.h"
|
||||
#endif /* HAL_HRTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HSEM_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_hsem.h"
|
||||
#endif /* HAL_HSEM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SRAM_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_sram.h"
|
||||
#endif /* HAL_SRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NOR_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_nor.h"
|
||||
#endif /* HAL_NOR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_NAND_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_nand.h"
|
||||
#endif /* HAL_NAND_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2C_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_i2c.h"
|
||||
#endif /* HAL_I2C_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_I2S_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_i2s.h"
|
||||
#endif /* HAL_I2S_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IWDG_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_iwdg.h"
|
||||
#endif /* HAL_IWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_JPEG_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_jpeg.h"
|
||||
#endif /* HAL_JPEG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MDIOS_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_mdios.h"
|
||||
#endif /* HAL_MDIOS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_MMC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_mmc.h"
|
||||
#endif /* HAL_MMC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LPTIM_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_lptim.h"
|
||||
#endif /* HAL_LPTIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_LTDC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_ltdc.h"
|
||||
#endif /* HAL_LTDC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_OPAMP_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_opamp.h"
|
||||
#endif /* HAL_OPAMP_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_OSPI_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_ospi.h"
|
||||
#endif /* HAL_OSPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_OTFDEC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_otfdec.h"
|
||||
#endif /* HAL_OTFDEC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PSSI_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_pssi.h"
|
||||
#endif /* HAL_PSSI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_pwr.h"
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_QSPI_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_qspi.h"
|
||||
#endif /* HAL_QSPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RAMECC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_ramecc.h"
|
||||
#endif /* HAL_RAMECC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RNG_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_rng.h"
|
||||
#endif /* HAL_RNG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_RTC_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_rtc.h"
|
||||
#endif /* HAL_RTC_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SAI_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_sai.h"
|
||||
#endif /* HAL_SAI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SD_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_sd.h"
|
||||
#endif /* HAL_SD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SDRAM_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_sdram.h"
|
||||
#endif /* HAL_SDRAM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPI_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_spi.h"
|
||||
#endif /* HAL_SPI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SPDIFRX_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_spdifrx.h"
|
||||
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SWPMI_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_swpmi.h"
|
||||
#endif /* HAL_SWPMI_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_tim.h"
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_UART_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_uart.h"
|
||||
#endif /* HAL_UART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_USART_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_usart.h"
|
||||
#endif /* HAL_USART_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_IRDA_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_irda.h"
|
||||
#endif /* HAL_IRDA_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMARTCARD_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_smartcard.h"
|
||||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_SMBUS_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_smbus.h"
|
||||
#endif /* HAL_SMBUS_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_WWDG_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_wwdg.h"
|
||||
#endif /* HAL_WWDG_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_PCD_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_pcd.h"
|
||||
#endif /* HAL_PCD_MODULE_ENABLED */
|
||||
|
||||
#ifdef HAL_HCD_MODULE_ENABLED
|
||||
#include "stm32h7xx_hal_hcd.h"
|
||||
#endif /* HAL_HCD_MODULE_ENABLED */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief The assert_param macro is used for function's parameters check.
|
||||
* @param expr: If expr is false, it calls assert_failed function
|
||||
* which reports the name of the source file and the source
|
||||
* line number of the call that failed.
|
||||
* If expr is true, it returns no value.
|
||||
* @retval None
|
||||
*/
|
||||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
void assert_failed(uint8_t *file, uint32_t line);
|
||||
#else
|
||||
#define assert_param(expr) ((void)0U)
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* STM32H7xx_HAL_CONF_H */
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_it.h
|
||||
* @brief This file contains the headers of the interrupt handlers.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32H7xx_IT_H
|
||||
#define __STM32H7xx_IT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Private includes ----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Includes */
|
||||
|
||||
/* USER CODE END Includes */
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN ET */
|
||||
|
||||
/* USER CODE END ET */
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
/* USER CODE BEGIN EC */
|
||||
|
||||
/* USER CODE END EC */
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN EM */
|
||||
|
||||
/* USER CODE END EM */
|
||||
|
||||
/* Exported functions prototypes ---------------------------------------------*/
|
||||
void NMI_Handler(void);
|
||||
void HardFault_Handler(void);
|
||||
void MemManage_Handler(void);
|
||||
void BusFault_Handler(void);
|
||||
void UsageFault_Handler(void);
|
||||
void SVC_Handler(void);
|
||||
void DebugMon_Handler(void);
|
||||
void PendSV_Handler(void);
|
||||
void SysTick_Handler(void);
|
||||
/* USER CODE BEGIN EFP */
|
||||
|
||||
/* USER CODE END EFP */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32H7xx_IT_H */
|
||||
|
|
@ -0,0 +1,329 @@
|
|||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file : main.c
|
||||
* @brief : Main program body
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "main.h"
|
||||
|
||||
/* Private includes ----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Includes */
|
||||
|
||||
/* USER CODE END Includes */
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PTD */
|
||||
|
||||
/* USER CODE END PTD */
|
||||
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PD */
|
||||
/* USER CODE END PD */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PM */
|
||||
|
||||
/* USER CODE END PM */
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
UART_HandleTypeDef huart1;
|
||||
|
||||
SDRAM_HandleTypeDef hsdram1;
|
||||
|
||||
/* USER CODE BEGIN PV */
|
||||
|
||||
/* USER CODE END PV */
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
void SystemClock_Config(void);
|
||||
static void MX_GPIO_Init(void);
|
||||
static void MX_USART1_UART_Init(void);
|
||||
static void MX_FMC_Init(void);
|
||||
/* USER CODE BEGIN PFP */
|
||||
|
||||
/* USER CODE END PFP */
|
||||
|
||||
/* Private user code ---------------------------------------------------------*/
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
|
||||
/**
|
||||
* @brief The application entry point.
|
||||
* @retval int
|
||||
*/
|
||||
int main(void)
|
||||
{
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
||||
/* MCU Configuration--------------------------------------------------------*/
|
||||
|
||||
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
||||
HAL_Init();
|
||||
|
||||
/* USER CODE BEGIN Init */
|
||||
|
||||
/* USER CODE END Init */
|
||||
|
||||
/* Configure the system clock */
|
||||
SystemClock_Config();
|
||||
|
||||
/* USER CODE BEGIN SysInit */
|
||||
|
||||
/* USER CODE END SysInit */
|
||||
|
||||
/* Initialize all configured peripherals */
|
||||
MX_GPIO_Init();
|
||||
MX_USART1_UART_Init();
|
||||
MX_FMC_Init();
|
||||
/* USER CODE BEGIN 2 */
|
||||
|
||||
/* USER CODE END 2 */
|
||||
|
||||
/* Infinite loop */
|
||||
/* USER CODE BEGIN WHILE */
|
||||
while (1)
|
||||
{
|
||||
/* USER CODE END WHILE */
|
||||
|
||||
/* USER CODE BEGIN 3 */
|
||||
}
|
||||
/* USER CODE END 3 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief System Clock Configuration
|
||||
* @retval None
|
||||
*/
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
|
||||
/** Supply configuration update enable
|
||||
*/
|
||||
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
|
||||
|
||||
/** Configure the main internal regulator output voltage
|
||||
*/
|
||||
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
|
||||
|
||||
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
|
||||
|
||||
/** Initializes the RCC Oscillators according to the specified parameters
|
||||
* in the RCC_OscInitTypeDef structure.
|
||||
*/
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
RCC_OscInitStruct.PLL.PLLM = 3;
|
||||
RCC_OscInitStruct.PLL.PLLN = 200;
|
||||
RCC_OscInitStruct.PLL.PLLP = 2;
|
||||
RCC_OscInitStruct.PLL.PLLQ = 2;
|
||||
RCC_OscInitStruct.PLL.PLLR = 2;
|
||||
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
|
||||
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
|
||||
RCC_OscInitStruct.PLL.PLLFRACN = 0;
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/** Initializes the CPU, AHB and APB buses clocks
|
||||
*/
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
||||
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
|
||||
|RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||||
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
|
||||
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
|
||||
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
|
||||
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief USART1 Initialization Function
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void MX_USART1_UART_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN USART1_Init 0 */
|
||||
|
||||
/* USER CODE END USART1_Init 0 */
|
||||
|
||||
/* USER CODE BEGIN USART1_Init 1 */
|
||||
|
||||
/* USER CODE END USART1_Init 1 */
|
||||
huart1.Instance = USART1;
|
||||
huart1.Init.BaudRate = 115200;
|
||||
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
||||
huart1.Init.StopBits = UART_STOPBITS_1;
|
||||
huart1.Init.Parity = UART_PARITY_NONE;
|
||||
huart1.Init.Mode = UART_MODE_TX_RX;
|
||||
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
||||
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
||||
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
||||
huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
|
||||
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
||||
if (HAL_UART_Init(&huart1) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN USART1_Init 2 */
|
||||
|
||||
/* USER CODE END USART1_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
/* FMC initialization function */
|
||||
static void MX_FMC_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN FMC_Init 0 */
|
||||
|
||||
/* USER CODE END FMC_Init 0 */
|
||||
|
||||
FMC_SDRAM_TimingTypeDef SdramTiming = {0};
|
||||
|
||||
/* USER CODE BEGIN FMC_Init 1 */
|
||||
|
||||
/* USER CODE END FMC_Init 1 */
|
||||
|
||||
/** Perform the SDRAM1 memory initialization sequence
|
||||
*/
|
||||
hsdram1.Instance = FMC_SDRAM_DEVICE;
|
||||
/* hsdram1.Init */
|
||||
hsdram1.Init.SDBank = FMC_SDRAM_BANK1;
|
||||
hsdram1.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9;
|
||||
hsdram1.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
|
||||
hsdram1.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32;
|
||||
hsdram1.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
|
||||
hsdram1.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
|
||||
hsdram1.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
|
||||
hsdram1.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2;
|
||||
hsdram1.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
|
||||
hsdram1.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
|
||||
/* SdramTiming */
|
||||
SdramTiming.LoadToActiveDelay = 2;
|
||||
SdramTiming.ExitSelfRefreshDelay = 7;
|
||||
SdramTiming.SelfRefreshTime = 5;
|
||||
SdramTiming.RowCycleDelay = 6;
|
||||
SdramTiming.WriteRecoveryTime = 3;
|
||||
SdramTiming.RPDelay = 2;
|
||||
SdramTiming.RCDDelay = 2;
|
||||
|
||||
if (HAL_SDRAM_Init(&hsdram1, &SdramTiming) != HAL_OK)
|
||||
{
|
||||
Error_Handler( );
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN FMC_Init 2 */
|
||||
|
||||
/* USER CODE END FMC_Init 2 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief GPIO Initialization Function
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void MX_GPIO_Init(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
|
||||
/* GPIO Ports Clock Enable */
|
||||
__HAL_RCC_GPIOE_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOG_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOD_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOI_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOH_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOF_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOC_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOA_CLK_ENABLE();
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
|
||||
/*Configure GPIO pin Output Level */
|
||||
HAL_GPIO_WritePin(GPIOC, LED_RED_Pin|LED_GREEN_Pin|LED_BLUE_Pin, GPIO_PIN_RESET);
|
||||
|
||||
/*Configure GPIO pins : LED_RED_Pin LED_GREEN_Pin LED_BLUE_Pin */
|
||||
GPIO_InitStruct.Pin = LED_RED_Pin|LED_GREEN_Pin|LED_BLUE_Pin;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
||||
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 4 */
|
||||
|
||||
/* USER CODE END 4 */
|
||||
|
||||
/**
|
||||
* @brief This function is executed in case of error occurrence.
|
||||
* @retval None
|
||||
*/
|
||||
void Error_Handler(void)
|
||||
{
|
||||
/* USER CODE BEGIN Error_Handler_Debug */
|
||||
/* User can add his own implementation to report the HAL error return state */
|
||||
__disable_irq();
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
/* USER CODE END Error_Handler_Debug */
|
||||
}
|
||||
|
||||
#ifdef USE_FULL_ASSERT
|
||||
/**
|
||||
* @brief Reports the name of the source file and the source line number
|
||||
* where the assert_param error has occurred.
|
||||
* @param file: pointer to the source file name
|
||||
* @param line: assert_param error line source number
|
||||
* @retval None
|
||||
*/
|
||||
void assert_failed(uint8_t *file, uint32_t line)
|
||||
{
|
||||
/* USER CODE BEGIN 6 */
|
||||
/* User can add his own implementation to report the file name and line number,
|
||||
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
|
||||
/* USER CODE END 6 */
|
||||
}
|
||||
#endif /* USE_FULL_ASSERT */
|
||||
|
|
@ -0,0 +1,432 @@
|
|||
/* USER CODE BEGIN Header */
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32h7xx_hal_msp.c
|
||||
* @brief This file provides code for the MSP Initialization
|
||||
* and de-Initialization codes.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2021 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
/* USER CODE END Header */
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "main.h"
|
||||
/* USER CODE BEGIN Includes */
|
||||
#ifdef __RTTHREAD__
|
||||
#include "drv_common.h"
|
||||
#endif
|
||||
/* USER CODE END Includes */
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* USER CODE BEGIN TD */
|
||||
|
||||
/* USER CODE END TD */
|
||||
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Define */
|
||||
|
||||
/* USER CODE END Define */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* USER CODE BEGIN Macro */
|
||||
|
||||
/* USER CODE END Macro */
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* USER CODE BEGIN PV */
|
||||
|
||||
/* USER CODE END PV */
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* USER CODE BEGIN PFP */
|
||||
|
||||
/* USER CODE END PFP */
|
||||
|
||||
/* External functions --------------------------------------------------------*/
|
||||
/* USER CODE BEGIN ExternalFunctions */
|
||||
|
||||
/* USER CODE END ExternalFunctions */
|
||||
|
||||
/* USER CODE BEGIN 0 */
|
||||
|
||||
/* USER CODE END 0 */
|
||||
/**
|
||||
* Initializes the Global MSP.
|
||||
*/
|
||||
void HAL_MspInit(void)
|
||||
{
|
||||
/* USER CODE BEGIN MspInit 0 */
|
||||
|
||||
/* USER CODE END MspInit 0 */
|
||||
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
/* System interrupt init*/
|
||||
|
||||
/* USER CODE BEGIN MspInit 1 */
|
||||
|
||||
/* USER CODE END MspInit 1 */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief UART MSP Initialization
|
||||
* This function configures the hardware resources used in this example
|
||||
* @param huart: UART handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
if(huart->Instance==USART1)
|
||||
{
|
||||
/* USER CODE BEGIN USART1_MspInit 0 */
|
||||
|
||||
/* USER CODE END USART1_MspInit 0 */
|
||||
|
||||
/** Initializes the peripherals clock
|
||||
*/
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1;
|
||||
PeriphClkInitStruct.Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_USART1_CLK_ENABLE();
|
||||
|
||||
__HAL_RCC_GPIOB_CLK_ENABLE();
|
||||
/**USART1 GPIO Configuration
|
||||
PB14 ------> USART1_TX
|
||||
PB15 ------> USART1_RX
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF4_USART1;
|
||||
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
||||
|
||||
/* USER CODE BEGIN USART1_MspInit 1 */
|
||||
|
||||
/* USER CODE END USART1_MspInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief UART MSP De-Initialization
|
||||
* This function freeze the hardware resources used in this example
|
||||
* @param huart: UART handle pointer
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
|
||||
{
|
||||
if(huart->Instance==USART1)
|
||||
{
|
||||
/* USER CODE BEGIN USART1_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END USART1_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_USART1_CLK_DISABLE();
|
||||
|
||||
/**USART1 GPIO Configuration
|
||||
PB14 ------> USART1_TX
|
||||
PB15 ------> USART1_RX
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_14|GPIO_PIN_15);
|
||||
|
||||
/* USER CODE BEGIN USART1_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END USART1_MspDeInit 1 */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static uint32_t FMC_Initialized = 0;
|
||||
|
||||
static void HAL_FMC_MspInit(void){
|
||||
/* USER CODE BEGIN FMC_MspInit 0 */
|
||||
|
||||
/* USER CODE END FMC_MspInit 0 */
|
||||
GPIO_InitTypeDef GPIO_InitStruct ={0};
|
||||
if (FMC_Initialized) {
|
||||
return;
|
||||
}
|
||||
FMC_Initialized = 1;
|
||||
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
|
||||
|
||||
/** Initializes the peripherals clock
|
||||
*/
|
||||
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_FMC;
|
||||
PeriphClkInitStruct.FmcClockSelection = RCC_FMCCLKSOURCE_D1HCLK;
|
||||
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_FMC_CLK_ENABLE();
|
||||
|
||||
/** FMC GPIO Configuration
|
||||
PE1 ------> FMC_NBL1
|
||||
PE0 ------> FMC_NBL0
|
||||
PG15 ------> FMC_SDNCAS
|
||||
PD0 ------> FMC_D2
|
||||
PI7 ------> FMC_D29
|
||||
PI6 ------> FMC_D28
|
||||
PI5 ------> FMC_NBL3
|
||||
PD1 ------> FMC_D3
|
||||
PI3 ------> FMC_D27
|
||||
PI2 ------> FMC_D26
|
||||
PI9 ------> FMC_D30
|
||||
PI4 ------> FMC_NBL2
|
||||
PH15 ------> FMC_D23
|
||||
PI1 ------> FMC_D25
|
||||
PF0 ------> FMC_A0
|
||||
PI10 ------> FMC_D31
|
||||
PH13 ------> FMC_D21
|
||||
PH14 ------> FMC_D22
|
||||
PI0 ------> FMC_D24
|
||||
PF2 ------> FMC_A2
|
||||
PF1 ------> FMC_A1
|
||||
PG8 ------> FMC_SDCLK
|
||||
PF3 ------> FMC_A3
|
||||
PF4 ------> FMC_A4
|
||||
PF5 ------> FMC_A5
|
||||
PH12 ------> FMC_D20
|
||||
PG5 ------> FMC_BA1
|
||||
PG4 ------> FMC_BA0
|
||||
PH11 ------> FMC_D19
|
||||
PH10 ------> FMC_D18
|
||||
PD15 ------> FMC_D1
|
||||
PG1 ------> FMC_A11
|
||||
PH8 ------> FMC_D16
|
||||
PH9 ------> FMC_D17
|
||||
PD14 ------> FMC_D0
|
||||
PC4 ------> FMC_SDNE0
|
||||
PF13 ------> FMC_A7
|
||||
PG0 ------> FMC_A10
|
||||
PE13 ------> FMC_D10
|
||||
PD10 ------> FMC_D15
|
||||
PC5 ------> FMC_SDCKE0
|
||||
PF12 ------> FMC_A6
|
||||
PF15 ------> FMC_A9
|
||||
PE8 ------> FMC_D5
|
||||
PE9 ------> FMC_D6
|
||||
PE11 ------> FMC_D8
|
||||
PE14 ------> FMC_D11
|
||||
PD9 ------> FMC_D14
|
||||
PD8 ------> FMC_D13
|
||||
PA7 ------> FMC_SDNWE
|
||||
PF11 ------> FMC_SDNRAS
|
||||
PF14 ------> FMC_A8
|
||||
PE7 ------> FMC_D4
|
||||
PE10 ------> FMC_D7
|
||||
PE12 ------> FMC_D9
|
||||
PE15 ------> FMC_D12
|
||||
*/
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_13|GPIO_PIN_8
|
||||
|GPIO_PIN_9|GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7
|
||||
|GPIO_PIN_10|GPIO_PIN_12|GPIO_PIN_15;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
||||
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_5|GPIO_PIN_4
|
||||
|GPIO_PIN_1|GPIO_PIN_0;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
||||
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_14
|
||||
|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_8;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
||||
HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_3
|
||||
|GPIO_PIN_2|GPIO_PIN_9|GPIO_PIN_4|GPIO_PIN_1
|
||||
|GPIO_PIN_10|GPIO_PIN_0;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
||||
HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_15|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_12
|
||||
|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_8|GPIO_PIN_9;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
||||
HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_3
|
||||
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_13|GPIO_PIN_12
|
||||
|GPIO_PIN_15|GPIO_PIN_11|GPIO_PIN_14;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
||||
HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
||||
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
||||
|
||||
GPIO_InitStruct.Pin = GPIO_PIN_7;
|
||||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
||||
GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
||||
GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
|
||||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
||||
|
||||
/* USER CODE BEGIN FMC_MspInit 1 */
|
||||
|
||||
/* USER CODE END FMC_MspInit 1 */
|
||||
}
|
||||
|
||||
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){
|
||||
/* USER CODE BEGIN SDRAM_MspInit 0 */
|
||||
|
||||
/* USER CODE END SDRAM_MspInit 0 */
|
||||
HAL_FMC_MspInit();
|
||||
/* USER CODE BEGIN SDRAM_MspInit 1 */
|
||||
|
||||
/* USER CODE END SDRAM_MspInit 1 */
|
||||
}
|
||||
|
||||
static uint32_t FMC_DeInitialized = 0;
|
||||
|
||||
static void HAL_FMC_MspDeInit(void){
|
||||
/* USER CODE BEGIN FMC_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END FMC_MspDeInit 0 */
|
||||
if (FMC_DeInitialized) {
|
||||
return;
|
||||
}
|
||||
FMC_DeInitialized = 1;
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_FMC_CLK_DISABLE();
|
||||
|
||||
/** FMC GPIO Configuration
|
||||
PE1 ------> FMC_NBL1
|
||||
PE0 ------> FMC_NBL0
|
||||
PG15 ------> FMC_SDNCAS
|
||||
PD0 ------> FMC_D2
|
||||
PI7 ------> FMC_D29
|
||||
PI6 ------> FMC_D28
|
||||
PI5 ------> FMC_NBL3
|
||||
PD1 ------> FMC_D3
|
||||
PI3 ------> FMC_D27
|
||||
PI2 ------> FMC_D26
|
||||
PI9 ------> FMC_D30
|
||||
PI4 ------> FMC_NBL2
|
||||
PH15 ------> FMC_D23
|
||||
PI1 ------> FMC_D25
|
||||
PF0 ------> FMC_A0
|
||||
PI10 ------> FMC_D31
|
||||
PH13 ------> FMC_D21
|
||||
PH14 ------> FMC_D22
|
||||
PI0 ------> FMC_D24
|
||||
PF2 ------> FMC_A2
|
||||
PF1 ------> FMC_A1
|
||||
PG8 ------> FMC_SDCLK
|
||||
PF3 ------> FMC_A3
|
||||
PF4 ------> FMC_A4
|
||||
PF5 ------> FMC_A5
|
||||
PH12 ------> FMC_D20
|
||||
PG5 ------> FMC_BA1
|
||||
PG4 ------> FMC_BA0
|
||||
PH11 ------> FMC_D19
|
||||
PH10 ------> FMC_D18
|
||||
PD15 ------> FMC_D1
|
||||
PG1 ------> FMC_A11
|
||||
PH8 ------> FMC_D16
|
||||
PH9 ------> FMC_D17
|
||||
PD14 ------> FMC_D0
|
||||
PC4 ------> FMC_SDNE0
|
||||
PF13 ------> FMC_A7
|
||||
PG0 ------> FMC_A10
|
||||
PE13 ------> FMC_D10
|
||||
PD10 ------> FMC_D15
|
||||
PC5 ------> FMC_SDCKE0
|
||||
PF12 ------> FMC_A6
|
||||
PF15 ------> FMC_A9
|
||||
PE8 ------> FMC_D5
|
||||
PE9 ------> FMC_D6
|
||||
PE11 ------> FMC_D8
|
||||
PE14 ------> FMC_D11
|
||||
PD9 ------> FMC_D14
|
||||
PD8 ------> FMC_D13
|
||||
PA7 ------> FMC_SDNWE
|
||||
PF11 ------> FMC_SDNRAS
|
||||
PF14 ------> FMC_A8
|
||||
PE7 ------> FMC_D4
|
||||
PE10 ------> FMC_D7
|
||||
PE12 ------> FMC_D9
|
||||
PE15 ------> FMC_D12
|
||||
*/
|
||||
HAL_GPIO_DeInit(GPIOE, GPIO_PIN_1|GPIO_PIN_0|GPIO_PIN_13|GPIO_PIN_8
|
||||
|GPIO_PIN_9|GPIO_PIN_11|GPIO_PIN_14|GPIO_PIN_7
|
||||
|GPIO_PIN_10|GPIO_PIN_12|GPIO_PIN_15);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOG, GPIO_PIN_15|GPIO_PIN_8|GPIO_PIN_5|GPIO_PIN_4
|
||||
|GPIO_PIN_1|GPIO_PIN_0);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_15|GPIO_PIN_14
|
||||
|GPIO_PIN_10|GPIO_PIN_9|GPIO_PIN_8);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOI, GPIO_PIN_7|GPIO_PIN_6|GPIO_PIN_5|GPIO_PIN_3
|
||||
|GPIO_PIN_2|GPIO_PIN_9|GPIO_PIN_4|GPIO_PIN_1
|
||||
|GPIO_PIN_10|GPIO_PIN_0);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOH, GPIO_PIN_15|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_12
|
||||
|GPIO_PIN_11|GPIO_PIN_10|GPIO_PIN_8|GPIO_PIN_9);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_2|GPIO_PIN_1|GPIO_PIN_3
|
||||
|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_13|GPIO_PIN_12
|
||||
|GPIO_PIN_15|GPIO_PIN_11|GPIO_PIN_14);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOC, GPIO_PIN_4|GPIO_PIN_5);
|
||||
|
||||
HAL_GPIO_DeInit(GPIOA, GPIO_PIN_7);
|
||||
|
||||
/* USER CODE BEGIN FMC_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END FMC_MspDeInit 1 */
|
||||
}
|
||||
|
||||
void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* hsdram){
|
||||
/* USER CODE BEGIN SDRAM_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END SDRAM_MspDeInit 0 */
|
||||
HAL_FMC_MspDeInit();
|
||||
/* USER CODE BEGIN SDRAM_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END SDRAM_MspDeInit 1 */
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
/* USER CODE END 1 */
|
||||
|
|
@ -0,0 +1,526 @@
|
|||
#MicroXplorer Configuration settings - do not modify
|
||||
FMC.BankMapConfig=FMC_SWAPBMAP_DISABLE
|
||||
FMC.CASLatency1=FMC_SDRAM_CAS_LATENCY_2
|
||||
FMC.ColumnBitsNumber1=FMC_SDRAM_COLUMN_BITS_NUM_9
|
||||
FMC.ExitSelfRefreshDelay1=7
|
||||
FMC.IPParameters=ColumnBitsNumber1,CASLatency1,SDClockPeriod1,LoadToActiveDelay1,RCDDelay1,ExitSelfRefreshDelay1,SelfRefreshTime1,RowCycleDelay1,RPDelay1,BankMapConfig,WriteRecoveryTime1,ReadBurst1
|
||||
FMC.LoadToActiveDelay1=2
|
||||
FMC.RCDDelay1=2
|
||||
FMC.RPDelay1=2
|
||||
FMC.ReadBurst1=FMC_SDRAM_RBURST_ENABLE
|
||||
FMC.RowCycleDelay1=6
|
||||
FMC.SDClockPeriod1=FMC_SDRAM_CLOCK_PERIOD_2
|
||||
FMC.SelfRefreshTime1=5
|
||||
FMC.WriteRecoveryTime1=3
|
||||
File.Version=6
|
||||
GPIO.groupedBy=Group By Peripherals
|
||||
KeepUserPlacement=false
|
||||
Mcu.CPN=STM32H743IIK6
|
||||
Mcu.Family=STM32H7
|
||||
Mcu.IP0=CORTEX_M7
|
||||
Mcu.IP1=FMC
|
||||
Mcu.IP2=NVIC
|
||||
Mcu.IP3=RCC
|
||||
Mcu.IP4=SYS
|
||||
Mcu.IP5=USART1
|
||||
Mcu.IPNb=6
|
||||
Mcu.Name=STM32H743IIKx
|
||||
Mcu.Package=UFBGA176
|
||||
Mcu.Pin0=PE1
|
||||
Mcu.Pin1=PE0
|
||||
Mcu.Pin10=PI9
|
||||
Mcu.Pin11=PI4
|
||||
Mcu.Pin12=PH15
|
||||
Mcu.Pin13=PI1
|
||||
Mcu.Pin14=PF0
|
||||
Mcu.Pin15=PI10
|
||||
Mcu.Pin16=PH13
|
||||
Mcu.Pin17=PH14
|
||||
Mcu.Pin18=PI0
|
||||
Mcu.Pin19=PH0-OSC_IN (PH0)
|
||||
Mcu.Pin2=PG15
|
||||
Mcu.Pin20=PH1-OSC_OUT (PH1)
|
||||
Mcu.Pin21=PF2
|
||||
Mcu.Pin22=PF1
|
||||
Mcu.Pin23=PG8
|
||||
Mcu.Pin24=PF3
|
||||
Mcu.Pin25=PF4
|
||||
Mcu.Pin26=PF5
|
||||
Mcu.Pin27=PH12
|
||||
Mcu.Pin28=PG5
|
||||
Mcu.Pin29=PG4
|
||||
Mcu.Pin3=PD0
|
||||
Mcu.Pin30=PH11
|
||||
Mcu.Pin31=PH10
|
||||
Mcu.Pin32=PD15
|
||||
Mcu.Pin33=PC0
|
||||
Mcu.Pin34=PC1
|
||||
Mcu.Pin35=PC2_C
|
||||
Mcu.Pin36=PG1
|
||||
Mcu.Pin37=PH8
|
||||
Mcu.Pin38=PH9
|
||||
Mcu.Pin39=PD14
|
||||
Mcu.Pin4=PI7
|
||||
Mcu.Pin40=PC4
|
||||
Mcu.Pin41=PF13
|
||||
Mcu.Pin42=PG0
|
||||
Mcu.Pin43=PE13
|
||||
Mcu.Pin44=PD10
|
||||
Mcu.Pin45=PC5
|
||||
Mcu.Pin46=PF12
|
||||
Mcu.Pin47=PF15
|
||||
Mcu.Pin48=PE8
|
||||
Mcu.Pin49=PE9
|
||||
Mcu.Pin5=PI6
|
||||
Mcu.Pin50=PE11
|
||||
Mcu.Pin51=PE14
|
||||
Mcu.Pin52=PD9
|
||||
Mcu.Pin53=PD8
|
||||
Mcu.Pin54=PA7
|
||||
Mcu.Pin55=PF11
|
||||
Mcu.Pin56=PF14
|
||||
Mcu.Pin57=PE7
|
||||
Mcu.Pin58=PE10
|
||||
Mcu.Pin59=PE12
|
||||
Mcu.Pin6=PI5
|
||||
Mcu.Pin60=PE15
|
||||
Mcu.Pin61=PB14
|
||||
Mcu.Pin62=PB15
|
||||
Mcu.Pin63=VP_SYS_VS_Systick
|
||||
Mcu.Pin7=PD1
|
||||
Mcu.Pin8=PI3
|
||||
Mcu.Pin9=PI2
|
||||
Mcu.PinsNb=64
|
||||
Mcu.ThirdPartyNb=0
|
||||
Mcu.UserConstants=
|
||||
Mcu.UserName=STM32H743IIKx
|
||||
MxCube.Version=6.5.0
|
||||
MxDb.Version=DB.6.0.50
|
||||
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
|
||||
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
|
||||
NVIC.ForceEnableDMAVector=true
|
||||
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
|
||||
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
|
||||
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
|
||||
NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
|
||||
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
|
||||
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
|
||||
NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:true
|
||||
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
|
||||
PA7.GPIOParameters=GPIO_PuPd
|
||||
PA7.GPIO_PuPd=GPIO_PULLUP
|
||||
PA7.Locked=true
|
||||
PA7.Signal=FMC_SDNWE
|
||||
PB14.Locked=true
|
||||
PB14.Mode=Asynchronous
|
||||
PB14.Signal=USART1_TX
|
||||
PB15.Locked=true
|
||||
PB15.Mode=Asynchronous
|
||||
PB15.Signal=USART1_RX
|
||||
PC0.GPIOParameters=GPIO_Label
|
||||
PC0.GPIO_Label=LED_RED
|
||||
PC0.Locked=true
|
||||
PC0.Signal=GPIO_Output
|
||||
PC1.GPIOParameters=GPIO_Label
|
||||
PC1.GPIO_Label=LED_GREEN
|
||||
PC1.Locked=true
|
||||
PC1.Signal=GPIO_Output
|
||||
PC2_C.GPIOParameters=GPIO_Label
|
||||
PC2_C.GPIO_Label=LED_BLUE
|
||||
PC2_C.Locked=true
|
||||
PC2_C.Signal=GPIO_Output
|
||||
PC4.GPIOParameters=GPIO_PuPd
|
||||
PC4.GPIO_PuPd=GPIO_PULLUP
|
||||
PC4.Locked=true
|
||||
PC4.Mode=SdramChipSelect1_1
|
||||
PC4.Signal=FMC_SDNE0
|
||||
PC5.GPIOParameters=GPIO_PuPd
|
||||
PC5.GPIO_PuPd=GPIO_PULLUP
|
||||
PC5.Locked=true
|
||||
PC5.Mode=SdramChipSelect1_1
|
||||
PC5.Signal=FMC_SDCKE0
|
||||
PD0.GPIOParameters=GPIO_PuPd
|
||||
PD0.GPIO_PuPd=GPIO_PULLUP
|
||||
PD0.Signal=FMC_D2_DA2
|
||||
PD1.GPIOParameters=GPIO_PuPd
|
||||
PD1.GPIO_PuPd=GPIO_PULLUP
|
||||
PD1.Signal=FMC_D3_DA3
|
||||
PD10.GPIOParameters=GPIO_PuPd
|
||||
PD10.GPIO_PuPd=GPIO_PULLUP
|
||||
PD10.Signal=FMC_D15_DA15
|
||||
PD14.GPIOParameters=GPIO_PuPd
|
||||
PD14.GPIO_PuPd=GPIO_PULLUP
|
||||
PD14.Signal=FMC_D0_DA0
|
||||
PD15.GPIOParameters=GPIO_PuPd
|
||||
PD15.GPIO_PuPd=GPIO_PULLUP
|
||||
PD15.Signal=FMC_D1_DA1
|
||||
PD8.GPIOParameters=GPIO_PuPd
|
||||
PD8.GPIO_PuPd=GPIO_PULLUP
|
||||
PD8.Signal=FMC_D13_DA13
|
||||
PD9.GPIOParameters=GPIO_PuPd
|
||||
PD9.GPIO_PuPd=GPIO_PULLUP
|
||||
PD9.Signal=FMC_D14_DA14
|
||||
PE0.GPIOParameters=GPIO_PuPd
|
||||
PE0.GPIO_PuPd=GPIO_PULLUP
|
||||
PE0.Signal=FMC_NBL0
|
||||
PE1.GPIOParameters=GPIO_PuPd
|
||||
PE1.GPIO_PuPd=GPIO_PULLUP
|
||||
PE1.Signal=FMC_NBL1
|
||||
PE10.GPIOParameters=GPIO_PuPd
|
||||
PE10.GPIO_PuPd=GPIO_PULLUP
|
||||
PE10.Signal=FMC_D7_DA7
|
||||
PE11.GPIOParameters=GPIO_PuPd
|
||||
PE11.GPIO_PuPd=GPIO_PULLUP
|
||||
PE11.Signal=FMC_D8_DA8
|
||||
PE12.GPIOParameters=GPIO_PuPd
|
||||
PE12.GPIO_PuPd=GPIO_PULLUP
|
||||
PE12.Signal=FMC_D9_DA9
|
||||
PE13.GPIOParameters=GPIO_PuPd
|
||||
PE13.GPIO_PuPd=GPIO_PULLUP
|
||||
PE13.Signal=FMC_D10_DA10
|
||||
PE14.GPIOParameters=GPIO_PuPd
|
||||
PE14.GPIO_PuPd=GPIO_PULLUP
|
||||
PE14.Signal=FMC_D11_DA11
|
||||
PE15.GPIOParameters=GPIO_PuPd
|
||||
PE15.GPIO_PuPd=GPIO_PULLUP
|
||||
PE15.Signal=FMC_D12_DA12
|
||||
PE7.GPIOParameters=GPIO_PuPd
|
||||
PE7.GPIO_PuPd=GPIO_PULLUP
|
||||
PE7.Signal=FMC_D4_DA4
|
||||
PE8.GPIOParameters=GPIO_PuPd
|
||||
PE8.GPIO_PuPd=GPIO_PULLUP
|
||||
PE8.Signal=FMC_D5_DA5
|
||||
PE9.GPIOParameters=GPIO_PuPd
|
||||
PE9.GPIO_PuPd=GPIO_PULLUP
|
||||
PE9.Signal=FMC_D6_DA6
|
||||
PF0.GPIOParameters=GPIO_PuPd
|
||||
PF0.GPIO_PuPd=GPIO_PULLUP
|
||||
PF0.Signal=FMC_A0
|
||||
PF1.GPIOParameters=GPIO_PuPd
|
||||
PF1.GPIO_PuPd=GPIO_PULLUP
|
||||
PF1.Signal=FMC_A1
|
||||
PF11.GPIOParameters=GPIO_PuPd
|
||||
PF11.GPIO_PuPd=GPIO_PULLUP
|
||||
PF11.Signal=FMC_SDNRAS
|
||||
PF12.GPIOParameters=GPIO_PuPd
|
||||
PF12.GPIO_PuPd=GPIO_PULLUP
|
||||
PF12.Signal=FMC_A6
|
||||
PF13.GPIOParameters=GPIO_PuPd
|
||||
PF13.GPIO_PuPd=GPIO_PULLUP
|
||||
PF13.Signal=FMC_A7
|
||||
PF14.GPIOParameters=GPIO_PuPd
|
||||
PF14.GPIO_PuPd=GPIO_PULLUP
|
||||
PF14.Signal=FMC_A8
|
||||
PF15.GPIOParameters=GPIO_PuPd
|
||||
PF15.GPIO_PuPd=GPIO_PULLUP
|
||||
PF15.Signal=FMC_A9
|
||||
PF2.GPIOParameters=GPIO_PuPd
|
||||
PF2.GPIO_PuPd=GPIO_PULLUP
|
||||
PF2.Signal=FMC_A2
|
||||
PF3.GPIOParameters=GPIO_PuPd
|
||||
PF3.GPIO_PuPd=GPIO_PULLUP
|
||||
PF3.Signal=FMC_A3
|
||||
PF4.GPIOParameters=GPIO_PuPd
|
||||
PF4.GPIO_PuPd=GPIO_PULLUP
|
||||
PF4.Signal=FMC_A4
|
||||
PF5.GPIOParameters=GPIO_PuPd
|
||||
PF5.GPIO_PuPd=GPIO_PULLUP
|
||||
PF5.Signal=FMC_A5
|
||||
PG0.GPIOParameters=GPIO_PuPd
|
||||
PG0.GPIO_PuPd=GPIO_PULLUP
|
||||
PG0.Signal=FMC_A10
|
||||
PG1.GPIOParameters=GPIO_PuPd
|
||||
PG1.GPIO_PuPd=GPIO_PULLUP
|
||||
PG1.Signal=FMC_A11
|
||||
PG15.GPIOParameters=GPIO_PuPd
|
||||
PG15.GPIO_PuPd=GPIO_PULLUP
|
||||
PG15.Signal=FMC_SDNCAS
|
||||
PG4.GPIOParameters=GPIO_PuPd
|
||||
PG4.GPIO_PuPd=GPIO_PULLUP
|
||||
PG4.Signal=FMC_A14_BA0
|
||||
PG5.GPIOParameters=GPIO_PuPd
|
||||
PG5.GPIO_PuPd=GPIO_PULLUP
|
||||
PG5.Signal=FMC_A15_BA1
|
||||
PG8.GPIOParameters=GPIO_PuPd
|
||||
PG8.GPIO_PuPd=GPIO_PULLUP
|
||||
PG8.Signal=FMC_SDCLK
|
||||
PH0-OSC_IN\ (PH0).Mode=HSE-External-Oscillator
|
||||
PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
|
||||
PH1-OSC_OUT\ (PH1).Mode=HSE-External-Oscillator
|
||||
PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
|
||||
PH10.GPIOParameters=GPIO_PuPd
|
||||
PH10.GPIO_PuPd=GPIO_PULLUP
|
||||
PH10.Signal=FMC_D18
|
||||
PH11.GPIOParameters=GPIO_PuPd
|
||||
PH11.GPIO_PuPd=GPIO_PULLUP
|
||||
PH11.Signal=FMC_D19
|
||||
PH12.GPIOParameters=GPIO_PuPd
|
||||
PH12.GPIO_PuPd=GPIO_PULLUP
|
||||
PH12.Signal=FMC_D20
|
||||
PH13.GPIOParameters=GPIO_PuPd
|
||||
PH13.GPIO_PuPd=GPIO_PULLUP
|
||||
PH13.Signal=FMC_D21
|
||||
PH14.GPIOParameters=GPIO_PuPd
|
||||
PH14.GPIO_PuPd=GPIO_PULLUP
|
||||
PH14.Signal=FMC_D22
|
||||
PH15.GPIOParameters=GPIO_PuPd
|
||||
PH15.GPIO_PuPd=GPIO_PULLUP
|
||||
PH15.Signal=FMC_D23
|
||||
PH8.GPIOParameters=GPIO_PuPd
|
||||
PH8.GPIO_PuPd=GPIO_PULLUP
|
||||
PH8.Signal=FMC_D16
|
||||
PH9.GPIOParameters=GPIO_PuPd
|
||||
PH9.GPIO_PuPd=GPIO_PULLUP
|
||||
PH9.Signal=FMC_D17
|
||||
PI0.GPIOParameters=GPIO_PuPd
|
||||
PI0.GPIO_PuPd=GPIO_PULLUP
|
||||
PI0.Signal=FMC_D24
|
||||
PI1.GPIOParameters=GPIO_PuPd
|
||||
PI1.GPIO_PuPd=GPIO_PULLUP
|
||||
PI1.Signal=FMC_D25
|
||||
PI10.GPIOParameters=GPIO_PuPd
|
||||
PI10.GPIO_PuPd=GPIO_PULLUP
|
||||
PI10.Signal=FMC_D31
|
||||
PI2.GPIOParameters=GPIO_PuPd
|
||||
PI2.GPIO_PuPd=GPIO_PULLUP
|
||||
PI2.Signal=FMC_D26
|
||||
PI3.GPIOParameters=GPIO_PuPd
|
||||
PI3.GPIO_PuPd=GPIO_PULLUP
|
||||
PI3.Signal=FMC_D27
|
||||
PI4.GPIOParameters=GPIO_PuPd
|
||||
PI4.GPIO_PuPd=GPIO_PULLUP
|
||||
PI4.Signal=FMC_NBL2
|
||||
PI5.GPIOParameters=GPIO_PuPd
|
||||
PI5.GPIO_PuPd=GPIO_PULLUP
|
||||
PI5.Signal=FMC_NBL3
|
||||
PI6.GPIOParameters=GPIO_PuPd
|
||||
PI6.GPIO_PuPd=GPIO_PULLUP
|
||||
PI6.Signal=FMC_D28
|
||||
PI7.GPIOParameters=GPIO_PuPd
|
||||
PI7.GPIO_PuPd=GPIO_PULLUP
|
||||
PI7.Signal=FMC_D29
|
||||
PI9.GPIOParameters=GPIO_PuPd
|
||||
PI9.GPIO_PuPd=GPIO_PULLUP
|
||||
PI9.Signal=FMC_D30
|
||||
PinOutPanel.CurrentBGAView=Top
|
||||
PinOutPanel.RotationAngle=0
|
||||
ProjectManager.AskForMigrate=true
|
||||
ProjectManager.BackupPrevious=false
|
||||
ProjectManager.CompilerOptimize=6
|
||||
ProjectManager.ComputerToolchain=false
|
||||
ProjectManager.CoupleFile=false
|
||||
ProjectManager.CustomerFirmwarePackage=
|
||||
ProjectManager.DefaultFWLocation=true
|
||||
ProjectManager.DeletePrevious=true
|
||||
ProjectManager.DeviceId=STM32H743IIKx
|
||||
ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.10.0
|
||||
ProjectManager.FreePins=false
|
||||
ProjectManager.HalAssertFull=false
|
||||
ProjectManager.HeapSize=0x200
|
||||
ProjectManager.KeepUserCode=true
|
||||
ProjectManager.LastFirmware=true
|
||||
ProjectManager.LibraryCopy=1
|
||||
ProjectManager.MainLocation=Core/Src
|
||||
ProjectManager.NoMain=false
|
||||
ProjectManager.PreviousToolchain=
|
||||
ProjectManager.ProjectBuild=false
|
||||
ProjectManager.ProjectFileName=CubeMX_Config.ioc
|
||||
ProjectManager.ProjectName=CubeMX_Config
|
||||
ProjectManager.RegisterCallBack=
|
||||
ProjectManager.StackSize=0x400
|
||||
ProjectManager.TargetToolchain=MDK-ARM V5.32
|
||||
ProjectManager.ToolChainLocation=
|
||||
ProjectManager.UnderRoot=false
|
||||
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_FMC_Init-FMC-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
|
||||
RCC.ADCFreq_Value=24187500
|
||||
RCC.AHB12Freq_Value=200000000
|
||||
RCC.AHB4Freq_Value=200000000
|
||||
RCC.APB1Freq_Value=100000000
|
||||
RCC.APB2Freq_Value=100000000
|
||||
RCC.APB3Freq_Value=100000000
|
||||
RCC.APB4Freq_Value=100000000
|
||||
RCC.AXIClockFreq_Value=200000000
|
||||
RCC.CECFreq_Value=32000
|
||||
RCC.CKPERFreq_Value=64000000
|
||||
RCC.CortexFreq_Value=400000000
|
||||
RCC.CpuClockFreq_Value=400000000
|
||||
RCC.D1CPREFreq_Value=400000000
|
||||
RCC.D1PPRE=RCC_APB3_DIV2
|
||||
RCC.D2PPRE1=RCC_APB1_DIV2
|
||||
RCC.D2PPRE2=RCC_APB2_DIV2
|
||||
RCC.D3PPRE=RCC_APB4_DIV2
|
||||
RCC.DFSDMACLkFreq_Value=400000000
|
||||
RCC.DFSDMFreq_Value=100000000
|
||||
RCC.DIVM1=3
|
||||
RCC.DIVN1=200
|
||||
RCC.DIVP1Freq_Value=400000000
|
||||
RCC.DIVP2Freq_Value=24187500
|
||||
RCC.DIVP3Freq_Value=24187500
|
||||
RCC.DIVQ1Freq_Value=400000000
|
||||
RCC.DIVQ2Freq_Value=24187500
|
||||
RCC.DIVQ3Freq_Value=24187500
|
||||
RCC.DIVR1Freq_Value=400000000
|
||||
RCC.DIVR2Freq_Value=24187500
|
||||
RCC.DIVR3Freq_Value=24187500
|
||||
RCC.FDCANFreq_Value=400000000
|
||||
RCC.FMCFreq_Value=200000000
|
||||
RCC.FamilyName=M
|
||||
RCC.HCLK3ClockFreq_Value=200000000
|
||||
RCC.HCLKFreq_Value=200000000
|
||||
RCC.HPRE=RCC_HCLK_DIV2
|
||||
RCC.HRTIMFreq_Value=200000000
|
||||
RCC.HSE_VALUE=12000000
|
||||
RCC.I2C123Freq_Value=100000000
|
||||
RCC.I2C4Freq_Value=100000000
|
||||
RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVN1,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,HSE_VALUE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,PLLSourceVirtual,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
|
||||
RCC.LPTIM1Freq_Value=100000000
|
||||
RCC.LPTIM2Freq_Value=100000000
|
||||
RCC.LPTIM345Freq_Value=100000000
|
||||
RCC.LPUART1Freq_Value=100000000
|
||||
RCC.LTDCFreq_Value=24187500
|
||||
RCC.MCO1PinFreq_Value=64000000
|
||||
RCC.MCO2PinFreq_Value=400000000
|
||||
RCC.PLL2FRACN=0
|
||||
RCC.PLL3FRACN=0
|
||||
RCC.PLLFRACN=0
|
||||
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
|
||||
RCC.QSPIFreq_Value=200000000
|
||||
RCC.RNGFreq_Value=48000000
|
||||
RCC.RTCFreq_Value=32000
|
||||
RCC.SAI1Freq_Value=400000000
|
||||
RCC.SAI23Freq_Value=400000000
|
||||
RCC.SAI4AFreq_Value=400000000
|
||||
RCC.SAI4BFreq_Value=400000000
|
||||
RCC.SDMMCFreq_Value=400000000
|
||||
RCC.SPDIFRXFreq_Value=400000000
|
||||
RCC.SPI123Freq_Value=400000000
|
||||
RCC.SPI45Freq_Value=100000000
|
||||
RCC.SPI6Freq_Value=100000000
|
||||
RCC.SWPMI1Freq_Value=100000000
|
||||
RCC.SYSCLKFreq_VALUE=400000000
|
||||
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
|
||||
RCC.Tim1OutputFreq_Value=200000000
|
||||
RCC.Tim2OutputFreq_Value=200000000
|
||||
RCC.TraceFreq_Value=64000000
|
||||
RCC.USART16Freq_Value=100000000
|
||||
RCC.USART234578Freq_Value=100000000
|
||||
RCC.USBFreq_Value=400000000
|
||||
RCC.VCO1OutputFreq_Value=800000000
|
||||
RCC.VCO2OutputFreq_Value=48375000
|
||||
RCC.VCO3OutputFreq_Value=48375000
|
||||
RCC.VCOInput1Freq_Value=4000000
|
||||
RCC.VCOInput2Freq_Value=375000
|
||||
RCC.VCOInput3Freq_Value=375000
|
||||
SH.FMC_A0.0=FMC_A0,12b-sda1
|
||||
SH.FMC_A0.ConfNb=1
|
||||
SH.FMC_A1.0=FMC_A1,12b-sda1
|
||||
SH.FMC_A1.ConfNb=1
|
||||
SH.FMC_A10.0=FMC_A10,12b-sda1
|
||||
SH.FMC_A10.ConfNb=1
|
||||
SH.FMC_A11.0=FMC_A11,12b-sda1
|
||||
SH.FMC_A11.ConfNb=1
|
||||
SH.FMC_A14_BA0.0=FMC_BA0,FourSdramBanks1
|
||||
SH.FMC_A14_BA0.ConfNb=1
|
||||
SH.FMC_A15_BA1.0=FMC_BA1,FourSdramBanks1
|
||||
SH.FMC_A15_BA1.ConfNb=1
|
||||
SH.FMC_A2.0=FMC_A2,12b-sda1
|
||||
SH.FMC_A2.ConfNb=1
|
||||
SH.FMC_A3.0=FMC_A3,12b-sda1
|
||||
SH.FMC_A3.ConfNb=1
|
||||
SH.FMC_A4.0=FMC_A4,12b-sda1
|
||||
SH.FMC_A4.ConfNb=1
|
||||
SH.FMC_A5.0=FMC_A5,12b-sda1
|
||||
SH.FMC_A5.ConfNb=1
|
||||
SH.FMC_A6.0=FMC_A6,12b-sda1
|
||||
SH.FMC_A6.ConfNb=1
|
||||
SH.FMC_A7.0=FMC_A7,12b-sda1
|
||||
SH.FMC_A7.ConfNb=1
|
||||
SH.FMC_A8.0=FMC_A8,12b-sda1
|
||||
SH.FMC_A8.ConfNb=1
|
||||
SH.FMC_A9.0=FMC_A9,12b-sda1
|
||||
SH.FMC_A9.ConfNb=1
|
||||
SH.FMC_D0_DA0.0=FMC_D0,sd-32b-d1
|
||||
SH.FMC_D0_DA0.ConfNb=1
|
||||
SH.FMC_D10_DA10.0=FMC_D10,sd-32b-d1
|
||||
SH.FMC_D10_DA10.ConfNb=1
|
||||
SH.FMC_D11_DA11.0=FMC_D11,sd-32b-d1
|
||||
SH.FMC_D11_DA11.ConfNb=1
|
||||
SH.FMC_D12_DA12.0=FMC_D12,sd-32b-d1
|
||||
SH.FMC_D12_DA12.ConfNb=1
|
||||
SH.FMC_D13_DA13.0=FMC_D13,sd-32b-d1
|
||||
SH.FMC_D13_DA13.ConfNb=1
|
||||
SH.FMC_D14_DA14.0=FMC_D14,sd-32b-d1
|
||||
SH.FMC_D14_DA14.ConfNb=1
|
||||
SH.FMC_D15_DA15.0=FMC_D15,sd-32b-d1
|
||||
SH.FMC_D15_DA15.ConfNb=1
|
||||
SH.FMC_D16.0=FMC_D16,sd-32b-d1
|
||||
SH.FMC_D16.ConfNb=1
|
||||
SH.FMC_D17.0=FMC_D17,sd-32b-d1
|
||||
SH.FMC_D17.ConfNb=1
|
||||
SH.FMC_D18.0=FMC_D18,sd-32b-d1
|
||||
SH.FMC_D18.ConfNb=1
|
||||
SH.FMC_D19.0=FMC_D19,sd-32b-d1
|
||||
SH.FMC_D19.ConfNb=1
|
||||
SH.FMC_D1_DA1.0=FMC_D1,sd-32b-d1
|
||||
SH.FMC_D1_DA1.ConfNb=1
|
||||
SH.FMC_D20.0=FMC_D20,sd-32b-d1
|
||||
SH.FMC_D20.ConfNb=1
|
||||
SH.FMC_D21.0=FMC_D21,sd-32b-d1
|
||||
SH.FMC_D21.ConfNb=1
|
||||
SH.FMC_D22.0=FMC_D22,sd-32b-d1
|
||||
SH.FMC_D22.ConfNb=1
|
||||
SH.FMC_D23.0=FMC_D23,sd-32b-d1
|
||||
SH.FMC_D23.ConfNb=1
|
||||
SH.FMC_D24.0=FMC_D24,sd-32b-d1
|
||||
SH.FMC_D24.ConfNb=1
|
||||
SH.FMC_D25.0=FMC_D25,sd-32b-d1
|
||||
SH.FMC_D25.ConfNb=1
|
||||
SH.FMC_D26.0=FMC_D26,sd-32b-d1
|
||||
SH.FMC_D26.ConfNb=1
|
||||
SH.FMC_D27.0=FMC_D27,sd-32b-d1
|
||||
SH.FMC_D27.ConfNb=1
|
||||
SH.FMC_D28.0=FMC_D28,sd-32b-d1
|
||||
SH.FMC_D28.ConfNb=1
|
||||
SH.FMC_D29.0=FMC_D29,sd-32b-d1
|
||||
SH.FMC_D29.ConfNb=1
|
||||
SH.FMC_D2_DA2.0=FMC_D2,sd-32b-d1
|
||||
SH.FMC_D2_DA2.ConfNb=1
|
||||
SH.FMC_D30.0=FMC_D30,sd-32b-d1
|
||||
SH.FMC_D30.ConfNb=1
|
||||
SH.FMC_D31.0=FMC_D31,sd-32b-d1
|
||||
SH.FMC_D31.ConfNb=1
|
||||
SH.FMC_D3_DA3.0=FMC_D3,sd-32b-d1
|
||||
SH.FMC_D3_DA3.ConfNb=1
|
||||
SH.FMC_D4_DA4.0=FMC_D4,sd-32b-d1
|
||||
SH.FMC_D4_DA4.ConfNb=1
|
||||
SH.FMC_D5_DA5.0=FMC_D5,sd-32b-d1
|
||||
SH.FMC_D5_DA5.ConfNb=1
|
||||
SH.FMC_D6_DA6.0=FMC_D6,sd-32b-d1
|
||||
SH.FMC_D6_DA6.ConfNb=1
|
||||
SH.FMC_D7_DA7.0=FMC_D7,sd-32b-d1
|
||||
SH.FMC_D7_DA7.ConfNb=1
|
||||
SH.FMC_D8_DA8.0=FMC_D8,sd-32b-d1
|
||||
SH.FMC_D8_DA8.ConfNb=1
|
||||
SH.FMC_D9_DA9.0=FMC_D9,sd-32b-d1
|
||||
SH.FMC_D9_DA9.ConfNb=1
|
||||
SH.FMC_NBL0.0=FMC_NBL0,Sd4ByteEnable1
|
||||
SH.FMC_NBL0.ConfNb=1
|
||||
SH.FMC_NBL1.0=FMC_NBL1,Sd4ByteEnable1
|
||||
SH.FMC_NBL1.ConfNb=1
|
||||
SH.FMC_NBL2.0=FMC_NBL2,Sd4ByteEnable1
|
||||
SH.FMC_NBL2.ConfNb=1
|
||||
SH.FMC_NBL3.0=FMC_NBL3,Sd4ByteEnable1
|
||||
SH.FMC_NBL3.ConfNb=1
|
||||
SH.FMC_SDCLK.0=FMC_SDCLK,12b-sda1
|
||||
SH.FMC_SDCLK.ConfNb=1
|
||||
SH.FMC_SDNCAS.0=FMC_SDNCAS,12b-sda1
|
||||
SH.FMC_SDNCAS.ConfNb=1
|
||||
SH.FMC_SDNRAS.0=FMC_SDNRAS,12b-sda1
|
||||
SH.FMC_SDNRAS.ConfNb=1
|
||||
SH.FMC_SDNWE.0=FMC_SDNWE,12b-sda1
|
||||
SH.FMC_SDNWE.ConfNb=1
|
||||
USART1.IPParameters=VirtualMode-Asynchronous
|
||||
USART1.VirtualMode-Asynchronous=VM_ASYNC
|
||||
VP_SYS_VS_Systick.Mode=SysTick
|
||||
VP_SYS_VS_Systick.Signal=SYS_VS_Systick
|
||||
board=custom
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
menu "Hardware Drivers Config"
|
||||
|
||||
config SOC_STM32H743II
|
||||
bool
|
||||
select SOC_SERIES_STM32H7
|
||||
select RT_USING_COMPONENTS_INIT
|
||||
select RT_USING_USER_MAIN
|
||||
default y
|
||||
|
||||
menu "On-chip Peripheral Drivers"
|
||||
|
||||
config BSP_USING_GPIO
|
||||
bool "Enable GPIO"
|
||||
select RT_USING_PIN
|
||||
default y
|
||||
|
||||
menuconfig BSP_USING_UART
|
||||
bool "Enable UART"
|
||||
default y
|
||||
select RT_USING_SERIAL
|
||||
|
||||
if BSP_USING_UART
|
||||
config BSP_USING_UART1
|
||||
bool "Enable UART1"
|
||||
default y
|
||||
|
||||
config BSP_UART1_RX_USING_DMA
|
||||
bool "Enable UART1 RX DMA"
|
||||
depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_UART2
|
||||
bool "Enable UART2"
|
||||
default n
|
||||
|
||||
config BSP_UART2_RX_USING_DMA
|
||||
bool "Enable UART2 RX DMA"
|
||||
depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
|
||||
config BSP_USING_LPUART1
|
||||
bool "Enable LPUART1"
|
||||
default n
|
||||
|
||||
config BSP_LPUART1_RX_USING_DMA
|
||||
bool "Enable LPUART1 RX DMA"
|
||||
depends on BSP_USING_LPUART1 && RT_SERIAL_USING_DMA
|
||||
default n
|
||||
endif
|
||||
|
||||
config BSP_USING_SDRAM
|
||||
bool "Enable SDRAM"
|
||||
default n
|
||||
|
||||
source "$RTT_DIR/bsp/stm32/libraries/HAL_Drivers/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
||||
endmenu
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
import os
|
||||
import rtconfig
|
||||
from building import *
|
||||
|
||||
Import('SDK_LIB')
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add general drivers
|
||||
src = Split('''
|
||||
board.c
|
||||
CubeMX_Config/Core/Src/stm32h7xx_hal_msp.c
|
||||
''')
|
||||
|
||||
if GetDepend(['BSP_USING_SDRAM']):
|
||||
src += Glob('ports/sdram_test.c')
|
||||
|
||||
path = [cwd]
|
||||
path += [cwd + '/CubeMX_Config/Core/Inc']
|
||||
path += [cwd + '/ports']
|
||||
|
||||
startup_path_prefix = SDK_LIB
|
||||
|
||||
if rtconfig.CROSS_TOOL == 'gcc':
|
||||
src += [startup_path_prefix + '/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/gcc/startup_stm32h743xx.s']
|
||||
elif rtconfig.CROSS_TOOL == 'keil':
|
||||
src += [startup_path_prefix + '/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/arm/startup_stm32h743xx.s']
|
||||
elif rtconfig.CROSS_TOOL == 'iar':
|
||||
src += [startup_path_prefix + '/STM32H7xx_HAL/CMSIS/Device/ST/STM32H7xx/Source/Templates/iar/startup_stm32h743xx.s']
|
||||
|
||||
CPPDEFINES = ['STM32H743xx']
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-12-14 supperthomas first version
|
||||
*/
|
||||
|
||||
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
||||
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
||||
|
||||
/** Supply configuration update enable
|
||||
*/
|
||||
HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
|
||||
/** Configure the main internal regulator output voltage
|
||||
*/
|
||||
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
|
||||
|
||||
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
|
||||
/** Initializes the RCC Oscillators according to the specified parameters
|
||||
* in the RCC_OscInitTypeDef structure.
|
||||
*/
|
||||
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
|
||||
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
|
||||
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
||||
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
|
||||
RCC_OscInitStruct.PLL.PLLM = 3;
|
||||
RCC_OscInitStruct.PLL.PLLN = 200;
|
||||
RCC_OscInitStruct.PLL.PLLP = 2;
|
||||
RCC_OscInitStruct.PLL.PLLQ = 2;
|
||||
RCC_OscInitStruct.PLL.PLLR = 2;
|
||||
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
|
||||
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
|
||||
RCC_OscInitStruct.PLL.PLLFRACN = 0;
|
||||
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/** Initializes the CPU, AHB and APB buses clocks
|
||||
*/
|
||||
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
||||
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
|
||||
|RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1;
|
||||
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
||||
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
|
||||
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
|
||||
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
|
||||
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
|
||||
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
|
||||
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
|
||||
|
||||
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-12-14 supperthomas first version
|
||||
* 2022-03-14 wwt add sram2
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <stm32h7xx.h>
|
||||
#include "drv_common.h"
|
||||
#include "drv_gpio.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define STM32_FLASH_START_ADRESS ((uint32_t)0x08000000)
|
||||
#define STM32_FLASH_SIZE (2048 * 1024)
|
||||
#define STM32_FLASH_END_ADDRESS ((uint32_t)(STM32_FLASH_START_ADRESS + STM32_FLASH_SIZE))
|
||||
|
||||
#define STM32_SRAM1_SIZE (128)
|
||||
#define STM32_SRAM1_START (0x20000000)
|
||||
#define STM32_SRAM1_END (STM32_SRAM1_START + STM32_SRAM1_SIZE * 1024)
|
||||
|
||||
#define STM32_SRAM2_SIZE (512)
|
||||
#define STM32_SRAM2_START (0x24000000)
|
||||
#define STM32_SRAM2_END (STM32_SRAM2_START + STM32_SRAM2_SIZE * 1024)
|
||||
|
||||
#if defined(__ARMCC_VERSION)
|
||||
extern int Image$$RW_IRAM1$$ZI$$Limit;
|
||||
#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="CSTACK"
|
||||
#define HEAP_BEGIN (__segment_end("CSTACK"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN ((void *)&__bss_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_END STM32_SRAM2_END
|
||||
|
||||
void SystemClock_Config(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x081FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM1_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM1_end__ = 0x2001FFFF;
|
||||
define symbol __ICFEDIT_region_RAM2_start__ = 0x24000000;
|
||||
define symbol __ICFEDIT_region_RAM2_end__ = 0x2407FFFF;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x0400;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM1_region = mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__];
|
||||
define region RAM2_region = mem:[from __ICFEDIT_region_RAM2_start__ to __ICFEDIT_region_RAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM1_region { section .sram , readwrite, last block CSTACK};
|
||||
|
|
@ -0,0 +1,157 @@
|
|||
/*
|
||||
* linker script for STM32H7XX with GNU ld
|
||||
*/
|
||||
|
||||
/* Program Entry, set to mark it as "used" and avoid gc */
|
||||
MEMORY
|
||||
{
|
||||
ROM (rx) : ORIGIN = 0x08000000, LENGTH = 2048k /* 2048KB flash */
|
||||
RAM1 (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128K sram */
|
||||
RAM2 (rw) : ORIGIN = 0x24000000, LENGTH = 512k /* 512K sram */
|
||||
}
|
||||
ENTRY(Reset_Handler)
|
||||
_system_stack_size = 0x400;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_stext = .;
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
|
||||
. = ALIGN(4);
|
||||
*(.text) /* remaining code */
|
||||
*(.text.*) /* remaining code */
|
||||
*(.rodata) /* read-only data (constants) */
|
||||
*(.rodata*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.gnu.linkonce.t*)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
PROVIDE(__ctors_start__ = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
PROVIDE(__ctors_end__ = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
|
||||
_etext = .;
|
||||
} > ROM = 0
|
||||
|
||||
/* .ARM.exidx is sorted, so has to go in its own output section. */
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sidata = .;
|
||||
} > ROM
|
||||
__exidx_end = .;
|
||||
|
||||
/* .data section which is used for initialized data */
|
||||
|
||||
.data : AT (_sidata)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_sdata = . ;
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.gnu.linkonce.d*)
|
||||
|
||||
PROVIDE(__dtors_start__ = .);
|
||||
KEEP(*(SORT(.dtors.*)))
|
||||
KEEP(*(.dtors))
|
||||
PROVIDE(__dtors_end__ = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .data secion */
|
||||
_edata = . ;
|
||||
} >RAM2
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sstack = .;
|
||||
. = . + _system_stack_size;
|
||||
. = ALIGN(4);
|
||||
_estack = .;
|
||||
} >RAM2
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .;
|
||||
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_ebss = . ;
|
||||
|
||||
*(.bss.init)
|
||||
} > RAM2
|
||||
__bss_end = .;
|
||||
|
||||
_end = .;
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
* Symbols in the DWARF debugging sections are relative to the beginning
|
||||
* of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x08000000 0x00200000 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x00200000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
RW_IRAM1 0x20000000 0x00020000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
RW_IRAM2 0x24000000 0x0080000 {
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* Copyright (c) 2006-2021, RT-Thread Development Team
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-12-14 supperthomas The first version for STM32H7xx
|
||||
*/
|
||||
|
||||
#ifndef __SDRAM_PORT_H__
|
||||
#define __SDRAM_PORT_H__
|
||||
|
||||
/* parameters for sdram peripheral */
|
||||
/* Bank1 or Bank2 */
|
||||
#define SDRAM_TARGET_BANK 1
|
||||
/* stm32h7 Bank1:0XC0000000 Bank2:0XD0000000 */
|
||||
#define SDRAM_BANK_ADDR ((uint32_t)0XC0000000)
|
||||
/* data width: 8, 16, 32 */
|
||||
#define SDRAM_DATA_WIDTH 32
|
||||
/* column bit numbers: 8, 9, 10, 11 */
|
||||
#define SDRAM_COLUMN_BITS 9
|
||||
/* row bit numbers: 11, 12, 13 */
|
||||
#define SDRAM_ROW_BITS 12
|
||||
/* cas latency clock number: 1, 2, 3 */
|
||||
#define SDRAM_CAS_LATENCY 2
|
||||
/* read pipe delay: 0, 1, 2 */
|
||||
#define SDRAM_RPIPE_DELAY 0
|
||||
/* clock divid: 2, 3 */
|
||||
#define SDCLOCK_PERIOD 2
|
||||
/* refresh rate counter */
|
||||
#define SDRAM_REFRESH_RATE (64) // ms
|
||||
#define SDRAM_FREQUENCY (100000) // 100 MHz
|
||||
#define SDRAM_REFRESH_CYCLES 4096
|
||||
#define SDRAM_REFRESH_COUNT (SDRAM_REFRESH_RATE * SDRAM_FREQUENCY / SDRAM_REFRESH_CYCLES - 20) //((uint32_t)0x02A5)
|
||||
#define SDRAM_SIZE (32 * 1024 * 1024)
|
||||
|
||||
/* Timing configuration for W9825G6KH-6 */
|
||||
/* 100 MHz of HCKL3 clock frequency (200MHz/2) */
|
||||
/* TMRD: 2 Clock cycles */
|
||||
#define LOADTOACTIVEDELAY 2
|
||||
/* TXSR: 8x10ns */
|
||||
#define EXITSELFREFRESHDELAY 7
|
||||
/* TRAS: 5x10ns */
|
||||
#define SELFREFRESHTIME 5
|
||||
/* TRC: 7x10ns */
|
||||
#define ROWCYCLEDELAY 6
|
||||
/* TWR: 2 Clock cycles */
|
||||
#define WRITERECOVERYTIME 3
|
||||
/* TRP: 2x10ns */
|
||||
#define RPDELAY 2
|
||||
/* TRCD: 2x10ns */
|
||||
#define RCDDELAY 2
|
||||
|
||||
/* memory mode register */
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
|
||||
#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
|
||||
#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
|
||||
#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
|
||||
#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
|
||||
#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
|
||||
#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
#ifdef BSP_USING_SDRAM
|
||||
#include <sdram_port.h>
|
||||
|
||||
#define DRV_DEBUG
|
||||
#define LOG_TAG "drv.sram"
|
||||
#include <drv_log.h>
|
||||
|
||||
static void sdram_test2(void)
|
||||
{
|
||||
char *p =NULL;
|
||||
p = rt_malloc(1024 * 1024 * 1);
|
||||
if(p == NULL)
|
||||
{
|
||||
LOG_E("apply for 1MB memory fail ~!!!");
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_D("appyle for 1MB memory success!!!");
|
||||
}
|
||||
rt_free(p);
|
||||
}
|
||||
MSH_CMD_EXPORT(sdram_test2, sdram test2);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,208 @@
|
|||
#ifndef RT_CONFIG_H__
|
||||
#define RT_CONFIG_H__
|
||||
|
||||
/* Automatically generated file; DO NOT EDIT. */
|
||||
/* RT-Thread Configuration */
|
||||
|
||||
#define ROOT_DIR "../../../.."
|
||||
#define BSP_DIR "."
|
||||
#define RT_Thread_DIR "../.."
|
||||
#define RTT_DIR "../../rt-thread"
|
||||
|
||||
/* RT-Thread Kernel */
|
||||
|
||||
#define RT_NAME_MAX 8
|
||||
#define RT_ALIGN_SIZE 4
|
||||
#define RT_THREAD_PRIORITY_32
|
||||
#define RT_THREAD_PRIORITY_MAX 32
|
||||
#define RT_TICK_PER_SECOND 1000
|
||||
#define RT_USING_OVERFLOW_CHECK
|
||||
#define RT_USING_HOOK
|
||||
#define RT_USING_IDLE_HOOK
|
||||
#define RT_IDLE_HOOK_LIST_SIZE 4
|
||||
#define IDLE_THREAD_STACK_SIZE 256
|
||||
|
||||
/* kservice optimization */
|
||||
|
||||
#define RT_DEBUG
|
||||
#define RT_DEBUG_COLOR
|
||||
|
||||
/* Inter-Thread communication */
|
||||
|
||||
#define RT_USING_SEMAPHORE
|
||||
#define RT_USING_MUTEX
|
||||
#define RT_USING_EVENT
|
||||
#define RT_USING_MAILBOX
|
||||
#define RT_USING_MESSAGEQUEUE
|
||||
|
||||
/* Memory Management */
|
||||
|
||||
#define RT_USING_MEMPOOL
|
||||
#define RT_USING_MEMHEAP
|
||||
#define RT_USING_MEMHEAP_AUTO_BINDING
|
||||
#define RT_USING_MEMHEAP_AS_HEAP
|
||||
#define RT_USING_HEAP
|
||||
|
||||
/* Kernel Device Object */
|
||||
|
||||
#define RT_USING_DEVICE
|
||||
#define RT_USING_CONSOLE
|
||||
#define RT_CONSOLEBUF_SIZE 256
|
||||
#define RT_CONSOLE_DEVICE_NAME "uart1"
|
||||
#define RT_VER_NUM 0x40004
|
||||
#define ARCH_ARM
|
||||
#define RT_USING_CPU_FFS
|
||||
#define ARCH_ARM_CORTEX_M
|
||||
#define ARCH_ARM_CORTEX_M7
|
||||
|
||||
/* RT-Thread Components */
|
||||
|
||||
#define RT_USING_COMPONENTS_INIT
|
||||
#define RT_USING_USER_MAIN
|
||||
#define RT_MAIN_THREAD_STACK_SIZE 2048
|
||||
#define RT_MAIN_THREAD_PRIORITY 10
|
||||
|
||||
/* C++ features */
|
||||
|
||||
#define RT_USING_CPLUSPLUS
|
||||
|
||||
/* Command shell */
|
||||
|
||||
#define RT_USING_FINSH
|
||||
#define RT_USING_MSH
|
||||
#define FINSH_USING_MSH
|
||||
#define FINSH_THREAD_NAME "tshell"
|
||||
#define FINSH_THREAD_PRIORITY 20
|
||||
#define FINSH_THREAD_STACK_SIZE 4096
|
||||
#define FINSH_USING_HISTORY
|
||||
#define FINSH_HISTORY_LINES 5
|
||||
#define FINSH_USING_SYMTAB
|
||||
#define FINSH_CMD_SIZE 80
|
||||
#define MSH_USING_BUILT_IN_COMMANDS
|
||||
#define FINSH_USING_DESCRIPTION
|
||||
#define FINSH_ARG_MAX 10
|
||||
|
||||
/* Device virtual file system */
|
||||
|
||||
#define RT_USING_DFS
|
||||
#define DFS_USING_WORKDIR
|
||||
#define DFS_FILESYSTEMS_MAX 4
|
||||
#define DFS_FILESYSTEM_TYPES_MAX 4
|
||||
#define DFS_FD_MAX 16
|
||||
#define RT_USING_DFS_ELMFAT
|
||||
|
||||
/* elm-chan's FatFs, Generic FAT Filesystem Module */
|
||||
|
||||
#define RT_DFS_ELM_CODE_PAGE 437
|
||||
#define RT_DFS_ELM_WORD_ACCESS
|
||||
#define RT_DFS_ELM_USE_LFN_3
|
||||
#define RT_DFS_ELM_USE_LFN 3
|
||||
#define RT_DFS_ELM_LFN_UNICODE_0
|
||||
#define RT_DFS_ELM_LFN_UNICODE 0
|
||||
#define RT_DFS_ELM_MAX_LFN 255
|
||||
#define RT_DFS_ELM_DRIVES 2
|
||||
#define RT_DFS_ELM_MAX_SECTOR_SIZE 4096
|
||||
#define RT_DFS_ELM_REENTRANT
|
||||
#define RT_DFS_ELM_MUTEX_TIMEOUT 3000
|
||||
#define RT_USING_DFS_DEVFS
|
||||
#define RT_USING_DFS_ROMFS
|
||||
|
||||
/* Device Drivers */
|
||||
|
||||
#define RT_USING_DEVICE_IPC
|
||||
#define RT_PIPE_BUFSZ 512
|
||||
#define RT_USING_SERIAL
|
||||
#define RT_USING_SERIAL_V1
|
||||
#define RT_SERIAL_USING_DMA
|
||||
#define RT_SERIAL_RB_BUFSZ 64
|
||||
#define RT_USING_PIN
|
||||
|
||||
/* Using USB */
|
||||
|
||||
|
||||
/* POSIX layer and C standard library */
|
||||
|
||||
#define RT_USING_LIBC
|
||||
#define RT_USING_PTHREADS
|
||||
#define PTHREAD_NUM_MAX 8
|
||||
#define RT_USING_POSIX
|
||||
#define RT_LIBC_USING_TIME
|
||||
#define RT_LIBC_DEFAULT_TIMEZONE 8
|
||||
|
||||
/* Network */
|
||||
|
||||
/* Socket abstraction layer */
|
||||
|
||||
|
||||
/* Network interface device */
|
||||
|
||||
|
||||
/* light weight TCP/IP stack */
|
||||
|
||||
|
||||
/* AT commands */
|
||||
|
||||
|
||||
/* VBUS(Virtual Software BUS) */
|
||||
|
||||
|
||||
/* Utilities */
|
||||
|
||||
|
||||
/* RT-Thread Utestcases */
|
||||
|
||||
#define SOC_FAMILY_STM32
|
||||
#define SOC_SERIES_STM32H7
|
||||
|
||||
/* Hardware Drivers Config */
|
||||
|
||||
#define SOC_STM32H743II
|
||||
|
||||
/* On-chip Peripheral Drivers */
|
||||
|
||||
#define BSP_USING_GPIO
|
||||
#define BSP_USING_UART
|
||||
#define BSP_USING_UART1
|
||||
#define BSP_USING_SDRAM
|
||||
|
||||
/* More Drivers */
|
||||
|
||||
|
||||
/* APP_Framework */
|
||||
|
||||
/* Framework */
|
||||
|
||||
#define TRANSFORM_LAYER_ATTRIUBUTE
|
||||
#define ADD_XIZI_FETURES
|
||||
|
||||
/* Security */
|
||||
|
||||
|
||||
/* Applications */
|
||||
|
||||
/* config stack size and priority of main task */
|
||||
|
||||
#define MAIN_KTASK_STACK_SIZE 1024
|
||||
|
||||
/* ota app */
|
||||
|
||||
|
||||
/* test app */
|
||||
|
||||
|
||||
/* connection app */
|
||||
|
||||
|
||||
/* control app */
|
||||
|
||||
/* knowing app */
|
||||
|
||||
|
||||
/* sensor app */
|
||||
|
||||
|
||||
/* lib */
|
||||
|
||||
#define APP_SELECT_NEWLIB
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,151 @@
|
|||
import os
|
||||
SRC_APP_DIR = '../../../../APP_Framework'
|
||||
# toolchains options
|
||||
ARCH='arm'
|
||||
CPU='cortex-m4'
|
||||
CROSS_TOOL='gcc'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
EXEC_PATH = r'/opt/gcc-arm-none-eabi-7-2018-q2-update/bin'
|
||||
elif CROSS_TOOL == 'keil':
|
||||
PLATFORM = 'armcc'
|
||||
EXEC_PATH = r'C:/Keil_v5'
|
||||
elif CROSS_TOOL == 'iar':
|
||||
PLATFORM = 'iar'
|
||||
EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.0'
|
||||
|
||||
if os.getenv('RTT_EXEC_PATH'):
|
||||
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
|
||||
BUILD = 'debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
# toolchains
|
||||
PREFIX = 'arm-none-eabi-'
|
||||
CC = PREFIX + 'gcc'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
CXX = PREFIX + 'g++'
|
||||
LINK = PREFIX + 'gcc'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
|
||||
DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
|
||||
CFLAGS = DEVICE + ' -Dgcc'
|
||||
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
|
||||
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -O0 -gdwarf-2 -g'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CXXFLAGS += ' -std=gnu++11'
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
elif PLATFORM == 'armcc':
|
||||
# toolchains
|
||||
CC = 'armcc'
|
||||
CXX = 'armcc'
|
||||
AS = 'armasm'
|
||||
AR = 'armar'
|
||||
LINK = 'armlink'
|
||||
TARGET_EXT = 'axf'
|
||||
|
||||
DEVICE = ' --cpu Cortex-M4.fp '
|
||||
CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99'
|
||||
AFLAGS = DEVICE + ' --apcs=interwork '
|
||||
LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict'
|
||||
CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include'
|
||||
LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib'
|
||||
|
||||
CFLAGS += ' -D__MICROLIB '
|
||||
AFLAGS += ' --pd "__MICROLIB SETA 1" '
|
||||
LFLAGS += ' --library_type=microlib '
|
||||
EXEC_PATH += '/ARM/ARMCC/bin/'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' -g -O0'
|
||||
AFLAGS += ' -g'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
CFLAGS += ' -std=c99'
|
||||
|
||||
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
|
||||
|
||||
elif PLATFORM == 'iar':
|
||||
# toolchains
|
||||
CC = 'iccarm'
|
||||
CXX = 'iccarm'
|
||||
AS = 'iasmarm'
|
||||
AR = 'iarchive'
|
||||
LINK = 'ilinkarm'
|
||||
TARGET_EXT = 'out'
|
||||
|
||||
DEVICE = '-Dewarm'
|
||||
|
||||
CFLAGS = DEVICE
|
||||
CFLAGS += ' --diag_suppress Pa050'
|
||||
CFLAGS += ' --no_cse'
|
||||
CFLAGS += ' --no_unroll'
|
||||
CFLAGS += ' --no_inline'
|
||||
CFLAGS += ' --no_code_motion'
|
||||
CFLAGS += ' --no_tbaa'
|
||||
CFLAGS += ' --no_clustering'
|
||||
CFLAGS += ' --no_scheduling'
|
||||
CFLAGS += ' --endian=little'
|
||||
CFLAGS += ' --cpu=Cortex-M4'
|
||||
CFLAGS += ' -e'
|
||||
CFLAGS += ' --fpu=VFPv4_sp'
|
||||
CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
|
||||
CFLAGS += ' --silent'
|
||||
|
||||
AFLAGS = DEVICE
|
||||
AFLAGS += ' -s+'
|
||||
AFLAGS += ' -w+'
|
||||
AFLAGS += ' -r'
|
||||
AFLAGS += ' --cpu Cortex-M4'
|
||||
AFLAGS += ' --fpu VFPv4_sp'
|
||||
AFLAGS += ' -S'
|
||||
|
||||
if BUILD == 'debug':
|
||||
CFLAGS += ' --debug'
|
||||
CFLAGS += ' -On'
|
||||
else:
|
||||
CFLAGS += ' -Oh'
|
||||
|
||||
LFLAGS = ' --config "board/linker_scripts/link.icf"'
|
||||
LFLAGS += ' --entry __iar_program_start'
|
||||
|
||||
CXXFLAGS = CFLAGS
|
||||
|
||||
EXEC_PATH = EXEC_PATH + '/arm/bin/'
|
||||
POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
|
||||
|
||||
def dist_handle(BSP_ROOT, dist_dir):
|
||||
import sys
|
||||
cwd_path = os.getcwd()
|
||||
sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
|
||||
from sdk_dist import dist_do_building
|
||||
dist_do_building(BSP_ROOT, dist_dir)
|
||||
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Reference in New Issue