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Add dwc3_core_soft_reset

This commit is contained in:
songyanguang 2024-09-13 10:23:25 +08:00
parent 7d575c4cea
commit ee3bcc6f66
1 changed files with 51 additions and 2 deletions
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53
Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c
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@ -239,12 +239,61 @@ void dwc3_core_exit(struct dwc3 *dwc){
int dwc3_core_soft_reset(struct dwc3 *dwc){
/**
* dwc3_core_soft_reset - Issues core soft reset and PHY reset
* @dwc: pointer to our context structure
*/
int dwc3_core_soft_reset(struct dwc3 *dwc)
{
uint32_t reg;
/* Before Resetting PHY, put Core in Reset */
reg = dwc3_readl(dwc->regs_vir, DWC3_GCTL);
reg |= DWC3_GCTL_CORESOFTRESET;
dwc3_writel(dwc->regs_vir, DWC3_GCTL, reg);
/* Assert USB3 PHY reset */
reg = dwc3_readl(dwc->regs_vir, DWC3_GUSB3PIPECTL(0));
reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
dwc3_writel(dwc->regs_vir, DWC3_GUSB3PIPECTL(0), reg);
/* Assert USB2 PHY reset */
reg = dwc3_readl(dwc->regs_vir, DWC3_GUSB2PHYCFG(0));
reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
dwc3_writel(dwc->regs_vir, DWC3_GUSB2PHYCFG(0), reg);
usb_osal_msleep(100);
/* Clear USB3 PHY reset */
reg = dwc3_readl(dwc->regs_vir, DWC3_GUSB3PIPECTL(0));
reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
dwc3_writel(dwc->regs_vir, DWC3_GUSB3PIPECTL(0), reg);
/* Clear USB2 PHY reset */
reg = dwc3_readl(dwc->regs_vir, DWC3_GUSB2PHYCFG(0));
reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
dwc3_writel(dwc->regs_vir, DWC3_GUSB2PHYCFG(0), reg);
usb_osal_msleep(100);
/* After PHYs are stable we can take Core out of reset state */
reg = dwc3_readl(dwc->regs_vir, DWC3_GCTL);
reg &= ~DWC3_GCTL_CORESOFTRESET;
dwc3_writel(dwc->regs_vir, DWC3_GCTL, reg);
return 0;
}
void dwc3_core_num_eps(struct dwc3 *dwc){
void dwc3_core_num_eps(struct dwc3 *dwc)
{
struct dwc3_hwparams *parms = &dwc->hwparams;
dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
USB_LOG_DBG("found %d IN and %d OUT endpoints\n",
dwc->num_in_eps, dwc->num_out_eps);
}