From ee3bcc6f664c9222d39318b1768c648a6582b89e Mon Sep 17 00:00:00 2001
From: songyanguang <345810377@qq.com>
Date: Fri, 13 Sep 2024 10:23:25 +0800
Subject: [PATCH] Add dwc3_core_soft_reset

---
 .../drivers/usb/components/port/dwc3/dwc3.c   | 53 ++++++++++++++++++-
 1 file changed, 51 insertions(+), 2 deletions(-)

diff --git a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c
index e11ebdf38..ebcc8c518 100644
--- a/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c
+++ b/Ubiquitous/XiZi_AIoT/services/drivers/usb/components/port/dwc3/dwc3.c
@@ -239,12 +239,61 @@ void dwc3_core_exit(struct dwc3 *dwc){
 
 
 
-int dwc3_core_soft_reset(struct dwc3 *dwc){
+/**
+ * dwc3_core_soft_reset - Issues core soft reset and PHY reset
+ * @dwc: pointer to our context structure
+ */
+int dwc3_core_soft_reset(struct dwc3 *dwc)
+{
+    uint32_t     reg;
+
+    /* Before Resetting PHY, put Core in Reset */
+    reg = dwc3_readl(dwc->regs_vir, DWC3_GCTL);
+    reg |= DWC3_GCTL_CORESOFTRESET;
+    dwc3_writel(dwc->regs_vir, DWC3_GCTL, reg);
+
+    /* Assert USB3 PHY reset */
+    reg = dwc3_readl(dwc->regs_vir, DWC3_GUSB3PIPECTL(0));
+    reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
+    dwc3_writel(dwc->regs_vir, DWC3_GUSB3PIPECTL(0), reg);
+
+    /* Assert USB2 PHY reset */
+    reg = dwc3_readl(dwc->regs_vir, DWC3_GUSB2PHYCFG(0));
+    reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
+    dwc3_writel(dwc->regs_vir, DWC3_GUSB2PHYCFG(0), reg);
+
+    usb_osal_msleep(100);
+
+    /* Clear USB3 PHY reset */
+    reg = dwc3_readl(dwc->regs_vir, DWC3_GUSB3PIPECTL(0));
+    reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
+    dwc3_writel(dwc->regs_vir, DWC3_GUSB3PIPECTL(0), reg);
+
+    /* Clear USB2 PHY reset */
+    reg = dwc3_readl(dwc->regs_vir, DWC3_GUSB2PHYCFG(0));
+    reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
+    dwc3_writel(dwc->regs_vir, DWC3_GUSB2PHYCFG(0), reg);
+
+    usb_osal_msleep(100);
+
+    /* After PHYs are stable we can take Core out of reset state */
+    reg = dwc3_readl(dwc->regs_vir, DWC3_GCTL);
+    reg &= ~DWC3_GCTL_CORESOFTRESET;
+    dwc3_writel(dwc->regs_vir, DWC3_GCTL, reg);
+
     return 0;
 }
 
 
-void dwc3_core_num_eps(struct dwc3 *dwc){
+void dwc3_core_num_eps(struct dwc3 *dwc)
+{
+    struct dwc3_hwparams    *parms = &dwc->hwparams;
+
+    dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
+    dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
+
+    USB_LOG_DBG("found %d IN and %d OUT endpoints\n",
+            dwc->num_in_eps, dwc->num_out_eps);
 }