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change support usb1 to usb2 on xidatong

This commit is contained in:
wgzAIIT 2022-04-01 10:15:39 +08:00
parent 0295b7ca38
commit a2921db3f6
11 changed files with 63 additions and 45 deletions
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1
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/include/board.h
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@ -128,6 +128,7 @@
#define IMXRT_SYS_PLL_SELECT CCM_ANALOG_PLL_SYS_DIV_SELECT_22 #define IMXRT_SYS_PLL_SELECT CCM_ANALOG_PLL_SYS_DIV_SELECT_22
#define IMXRT_USB1_PLL_DIV_SELECT CCM_ANALOG_PLL_USB1_DIV_SELECT_20 #define IMXRT_USB1_PLL_DIV_SELECT CCM_ANALOG_PLL_USB1_DIV_SELECT_20
#define IMXRT_USB2_PLL_DIV_SELECT CCM_ANALOG_PLL_USB2_DIV_SELECT_20
// #define BOARD_CPU_FREQUENCY \ // #define BOARD_CPU_FREQUENCY \
// (BOARD_XTAL_FREQUENCY * (IMXRT_ARM_PLL_DIV_SELECT / 2)) / IMXRT_ARM_PODF_DIVIDER // (BOARD_XTAL_FREQUENCY * (IMXRT_ARM_PLL_DIV_SELECT / 2)) / IMXRT_ARM_PODF_DIVIDER

2
Ubiquitous/Nuttx_Fusion_XiUOS/aiit_board/xidatong/src/imxrt_usbhost.c
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@ -138,7 +138,7 @@ int imxrt_usbhost_initialize(void)
/* Make sure we don't accidentally switch on USB bus power */ /* Make sure we don't accidentally switch on USB bus power */
*((uint32_t *)IMXRT_USBNC_USB_OTG1_CTRL) = USBNC_PWR_POL; *((uint32_t *)IMXRT_USBNC_USB_OTG2_CTRL) = USBNC_PWR_POL;
*((uint32_t *)0x400d9030) = (1 << 21); *((uint32_t *)0x400d9030) = (1 << 21);
*((uint32_t *)0x400d9000) = 0; *((uint32_t *)0x400d9000) = 0;

5
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/hardware/imxrt_usbotg.h
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@ -117,7 +117,9 @@
/* USB Non-core memory map & register definition */ /* USB Non-core memory map & register definition */
#define IMXRT_USBNC_USB_OTG1_CTRL_OFFSET 0x0800 /* OTG1 Control Register */ #define IMXRT_USBNC_USB_OTG1_CTRL_OFFSET 0x0800 /* OTG1 Control Register */
#define IMXRT_USBNC_USB_OTG2_CTRL_OFFSET 0x0800 /* OTG2 Control Register */
#define IMXRT_USBNC_USB_OTG1_PHY_CTRL_0_OFFSET 0x0818 /* OTG1 Phy Control Register */ #define IMXRT_USBNC_USB_OTG1_PHY_CTRL_0_OFFSET 0x0818 /* OTG1 Phy Control Register */
#define IMXRT_USBNC_USB_OTG2_PHY_CTRL_0_OFFSET 0x0818 /* OTG2 Phy Control Register */
/* USBOTG register (virtual) addresses **************************************/ /* USBOTG register (virtual) addresses **************************************/
@ -201,6 +203,9 @@
#define IMXRT_USBNC_USB_OTG1_CTRL (IMXRT_USB_BASE + IMXRT_USBNC_USB_OTG1_CTRL_OFFSET) #define IMXRT_USBNC_USB_OTG1_CTRL (IMXRT_USB_BASE + IMXRT_USBNC_USB_OTG1_CTRL_OFFSET)
#define IMXRT_USBNC_USB_OTG1_PHY_CTRL_0 (IMXRT_USB_BASE + IMXRT_USBNC_USB_OTG1_PHY_CTRL_0_OFFSET) #define IMXRT_USBNC_USB_OTG1_PHY_CTRL_0 (IMXRT_USB_BASE + IMXRT_USBNC_USB_OTG1_PHY_CTRL_0_OFFSET)
#define IMXRT_USBNC_USB_OTG2_CTRL (IMXRT_USB_BASE + IMXRT_USBNC_USB_OTG2_CTRL_OFFSET)
#define IMXRT_USBNC_USB_OTG2_PHY_CTRL_0 (IMXRT_USB_BASE + IMXRT_USBNC_USB_OTG2_PHY_CTRL_0_OFFSET)
/* USBOTG register bit definitions ******************************************/ /* USBOTG register bit definitions ******************************************/
/* Device/host capability registers */ /* Device/host capability registers */

32
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/hardware/imxrt_usbphy.h
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@ -32,23 +32,35 @@
* Pre-processor Definitions * Pre-processor Definitions
****************************************************************************/ ****************************************************************************/
#define IMXRT_USBPHY_BASE_OFFSET 0x1000 /* USB PHY Base */ #define IMXRT_USBPHY1_BASE_OFFSET 0x1000 /* USB PHY1 Base */
#define IMXRT_USBPHY2_BASE_OFFSET 0x2000 /* USB PHY2 Base */
#define IMXRT_USBPHY_BASE (IMXRT_ANATOP_BASE + IMXRT_USBPHY_BASE_OFFSET) /* USB PHY Base */ #define IMXRT_USBPHY1_BASE (IMXRT_ANATOP_BASE + IMXRT_USBPHY1_BASE_OFFSET) /* USB PHY1 Base */
#define IMXRT_USBPHY2_BASE (IMXRT_ANATOP_BASE + IMXRT_USBPHY2_BASE_OFFSET) /* USB PHY2 Base */
/* Register Offsets *********************************************************/ /* Register Offsets *********************************************************/
#define IMXRT_USBPHY1_PWD_OFFSET 0x0000 /* USBPHY1 USB PHY Power-Down Register */ #define IMXRT_USBPHY1_PWD_OFFSET 0x0000 /* USBPHY1 USB PHY1 Power-Down Register */
#define IMXRT_USBPHY1_PWD_CLR_OFFSET 0x0008 /* USBPHY1 USB PHY Power-Down Register Clear */ #define IMXRT_USBPHY1_PWD_CLR_OFFSET 0x0008 /* USBPHY1 USB PHY1 Power-Down Register Clear */
#define IMXRT_USBPHY1_CTRL_OFFSET 0x0030 /* USBPHY1 USB PHY General Control Register */ #define IMXRT_USBPHY1_CTRL_OFFSET 0x0030 /* USBPHY1 USB PHY1 General Control Register */
#define IMXRT_USBPHY1_CTRL_CLR_OFFSET 0x0038 /* USBPHY1 USB PHY General Control Register Clear */ #define IMXRT_USBPHY1_CTRL_CLR_OFFSET 0x0038 /* USBPHY1 USB PHY1 General Control Register Clear */
#define IMXRT_USBPHY2_PWD_OFFSET 0x0000 /* USBPHY2 USB PHY Power-Down Register */
#define IMXRT_USBPHY2_PWD_CLR_OFFSET 0x0008 /* USBPHY2 USB PHY Power-Down Register Clear */
#define IMXRT_USBPHY2_CTRL_OFFSET 0x0030 /* USBPHY2 USB PHY General Control Register */
#define IMXRT_USBPHY2_CTRL_CLR_OFFSET 0x0038 /* USBPHY2 USB PHY General Control Register Clear */
/* Register addresses *******************************************************/ /* Register addresses *******************************************************/
#define IMXRT_USBPHY1_PWD (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_PWD_OFFSET) /* USBPHY1 USB PHY Power-Down Register */ #define IMXRT_USBPHY1_PWD (IMXRT_USBPHY1_BASE + IMXRT_USBPHY1_PWD_OFFSET) /* USBPHY1 USB PHY1 Power-Down Register */
#define IMXRT_USBPHY1_PWD_CLR (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_PWD_CLR_OFFSET) /* USBPHY1 USB PHY Power-Down Register Clear */ #define IMXRT_USBPHY1_PWD_CLR (IMXRT_USBPHY1_BASE + IMXRT_USBPHY1_PWD_CLR_OFFSET) /* USBPHY1 USB PHY1 Power-Down Register Clear */
#define IMXRT_USBPHY1_CTRL (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_CTRL_OFFSET) /* USBPHY1 USB PHY General Control Register */ #define IMXRT_USBPHY1_CTRL (IMXRT_USBPHY1_BASE + IMXRT_USBPHY1_CTRL_OFFSET) /* USBPHY1 USB PHY1 General Control Register */
#define IMXRT_USBPHY1_CTRL_CLR (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_CTRL_CLR_OFFSET) /* USBPHY1 USB PHY General Control Register Clear */ #define IMXRT_USBPHY1_CTRL_CLR (IMXRT_USBPHY1_BASE + IMXRT_USBPHY1_CTRL_CLR_OFFSET) /* USBPHY1 USB PHY1 General Control Register Clear */
#define IMXRT_USBPHY2_PWD (IMXRT_USBPHY2_BASE + IMXRT_USBPHY2_PWD_OFFSET) /* USBPHY2 USB PHY2 Power-Down Register */
#define IMXRT_USBPHY2_PWD_CLR (IMXRT_USBPHY2_BASE + IMXRT_USBPHY2_PWD_CLR_OFFSET) /* USBPHY2 USB PHY2 Power-Down Register Clear */
#define IMXRT_USBPHY2_CTRL (IMXRT_USBPHY2_BASE + IMXRT_USBPHY2_CTRL_OFFSET) /* USBPHY2 USB PHY2 General Control Register */
#define IMXRT_USBPHY2_CTRL_CLR (IMXRT_USBPHY2_BASE + IMXRT_USBPHY2_CTRL_CLR_OFFSET) /* USBPHY2 USB PHY2 General Control Register Clear */
/* Register Bit Definitions *************************************************/ /* Register Bit Definitions *************************************************/

2
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/hardware/rt105x/imxrt105x_memorymap.h
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@ -232,7 +232,7 @@
/* 0x402d4000 16KB Reserved */ /* 0x402d4000 16KB Reserved */
#define IMXRT_ENET_BASE 0x402d8000 /* 16KB ENET */ #define IMXRT_ENET_BASE 0x402d8000 /* 16KB ENET */
#define IMXRT_USBPL301_BASE 0x402dc000 /* 16KB USB(PL301) */ #define IMXRT_USBPL301_BASE 0x402dc000 /* 16KB USB(PL301) */
#define IMXRT_USB_BASE 0x402e0000 /* 16KB USB(USB) */ #define IMXRT_USB_BASE 0x402e0200 /* 16KB USB(USB) */
/* 0x402e4000 16KB Reserved */ /* 0x402e4000 16KB Reserved */

26
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/imxrt_clockconfig.c
View File

@ -250,14 +250,14 @@ static void imxrt_pllsetup(void)
CCM_ANALOG_PFD_480_PFD3_CLKGATE, CCM_ANALOG_PFD_480_PFD3_CLKGATE,
IMXRT_CCM_ANALOG_PFD_480); IMXRT_CCM_ANALOG_PFD_480);
reg = IMXRT_USB1_PLL_DIV_SELECT | reg = IMXRT_USB2_PLL_DIV_SELECT |
CCM_ANALOG_PLL_USB1_ENABLE | CCM_ANALOG_PLL_USB2_ENABLE |
CCM_ANALOG_PLL_USB1_EN_USB_CLKS | CCM_ANALOG_PLL_USB2_EN_USB_CLKS |
CCM_ANALOG_PLL_USB1_POWER; CCM_ANALOG_PLL_USB2_POWER;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_USB1); putreg32(reg, IMXRT_CCM_ANALOG_PLL_USB2);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_USB1) & while ((getreg32(IMXRT_CCM_ANALOG_PLL_USB2) &
CCM_ANALOG_PLL_USB1_LOCK) == 0) CCM_ANALOG_PLL_USB2_LOCK) == 0)
{ {
} }
@ -320,13 +320,13 @@ static void imxrt_pllsetup(void)
CCM_ANALOG_PFD_480_PFD3_CLKGATE, CCM_ANALOG_PFD_480_PFD3_CLKGATE,
IMXRT_CCM_ANALOG_PFD_480); IMXRT_CCM_ANALOG_PFD_480);
reg = CCM_ANALOG_PLL_USB1_DIV_SELECT(IMXRT_USB1_PLL_DIV_SELECT) | reg = CCM_ANALOG_PLL_USB2_DIV_SELECT(IMXRT_USB2_PLL_DIV_SELECT) |
CCM_ANALOG_PLL_USB1_ENABLE | CCM_ANALOG_PLL_USB1_EN_USB_CLKS | CCM_ANALOG_PLL_USB2_ENABLE | CCM_ANALOG_PLL_USB2_EN_USB_CLKS |
CCM_ANALOG_PLL_USB1_POWER; CCM_ANALOG_PLL_USB2_POWER;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_USB1); putreg32(reg, IMXRT_CCM_ANALOG_PLL_USB2);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_USB1) & while ((getreg32(IMXRT_CCM_ANALOG_PLL_USB2) &
CCM_ANALOG_PLL_USB1_LOCK) == 0) CCM_ANALOG_PLL_USB2_LOCK) == 0)
{ {
} }

6
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/imxrt_ehci.c
View File

@ -5363,10 +5363,10 @@ FAR struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
/* Interrupt Configuration ************************************************/ /* Interrupt Configuration ************************************************/
ret = irq_attach(IMXRT_IRQ_USBOTG1, imxrt_ehci_interrupt, NULL); ret = irq_attach(IMXRT_IRQ_USBOTG2, imxrt_ehci_interrupt, NULL);
if (ret != 0) if (ret != 0)
{ {
usbhost_trace1(EHCI_TRACE1_IRQATTACH_FAILED, IMXRT_IRQ_USBOTG1); usbhost_trace1(EHCI_TRACE1_IRQATTACH_FAILED, IMXRT_IRQ_USBOTG2);
return NULL; return NULL;
} }
@ -5378,7 +5378,7 @@ FAR struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
/* Enable interrupts at the interrupt controller */ /* Enable interrupts at the interrupt controller */
up_enable_irq(IMXRT_IRQ_USBOTG1); up_enable_irq(IMXRT_IRQ_USBOTG2);
/* Drive Vbus +5V (the smoke test) */ /* Drive Vbus +5V (the smoke test) */

4
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/imxrt_lowputc.c
View File

@ -386,8 +386,8 @@ int imxrt_lpuart_configure(uint32_t base,
} }
else else
{ {
if ((getreg32(IMXRT_CCM_ANALOG_PLL_USB1) & if ((getreg32(IMXRT_CCM_ANALOG_PLL_USB2) &
CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0) CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) != 0)
{ {
pll3_div = 22; pll3_div = 22;
} }

4
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/imxrt_lpi2c.c
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@ -1054,8 +1054,8 @@ static void imxrt_lpi2c_setclock(FAR struct imxrt_lpi2c_priv_s *priv,
} }
else else
{ {
if ((getreg32(IMXRT_CCM_ANALOG_PLL_USB1) & if ((getreg32(IMXRT_CCM_ANALOG_PLL_USB2) &
CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0) CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) != 0)
{ {
pll3_div = 22; pll3_div = 22;
} }

8
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/imxrt_lpspi.c
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@ -702,8 +702,8 @@ static inline void imxrt_lpspi_master_set_delays(
uint32_t clock_div_prescaler; uint32_t clock_div_prescaler;
uint32_t additional_scaler; uint32_t additional_scaler;
if ((getreg32(IMXRT_CCM_ANALOG_PLL_USB1) & if ((getreg32(IMXRT_CCM_ANALOG_PLL_USB2) &
CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0) CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) != 0)
{ {
pll3_div = 22; pll3_div = 22;
} }
@ -915,8 +915,8 @@ static uint32_t imxrt_lpspi_setfrequency(FAR struct spi_dev_s *dev,
LPSPI_CR_MEN, 0); LPSPI_CR_MEN, 0);
} }
if ((getreg32(IMXRT_CCM_ANALOG_PLL_USB1) & if ((getreg32(IMXRT_CCM_ANALOG_PLL_USB2) &
CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0) CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) != 0)
{ {
pll3_div = 22; pll3_div = 22;
} }

18
Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/imxrt_usbdev.c
View File

@ -2879,7 +2879,7 @@ void arm_usbinitialize(void)
/* Soft reset PHY and enable clock */ /* Soft reset PHY and enable clock */
putreg32(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE, IMXRT_USBPHY1_CTRL_CLR); putreg32(USBPHY_CTRL_SFTRST | USBPHY_CTRL_CLKGATE, IMXRT_USBPHY2_CTRL_CLR);
/* Disconnect device */ /* Disconnect device */
@ -2898,7 +2898,7 @@ void arm_usbinitialize(void)
* CCM_ANALOG_USBPHYx_PLL_480_CTRLn. * CCM_ANALOG_USBPHYx_PLL_480_CTRLn.
*/ */
imxrt_putreg(0, IMXRT_USBPHY1_PWD); imxrt_putreg(0, IMXRT_USBPHY2_PWD);
/* Program the controller to be the USB device controller */ /* Program the controller to be the USB device controller */
@ -2907,8 +2907,8 @@ void arm_usbinitialize(void)
/* Attach USB controller interrupt handler */ /* Attach USB controller interrupt handler */
irq_attach(IMXRT_IRQ_USBOTG1, imxrt_usbinterrupt, NULL); irq_attach(IMXRT_IRQ_USBOTG2, imxrt_usbinterrupt, NULL);
up_enable_irq(IMXRT_IRQ_USBOTG1); up_enable_irq(IMXRT_IRQ_USBOTG2);
leave_critical_section(flags); leave_critical_section(flags);
@ -2945,8 +2945,8 @@ void arm_usbuninitialize(void)
/* Disable and detach IRQs */ /* Disable and detach IRQs */
up_disable_irq(IMXRT_IRQ_USBOTG1); up_disable_irq(IMXRT_IRQ_USBOTG2);
irq_detach(IMXRT_IRQ_USBOTG1); irq_detach(IMXRT_IRQ_USBOTG2);
/* Reset the controller */ /* Reset the controller */
@ -2958,7 +2958,7 @@ void arm_usbuninitialize(void)
/* Power down the PHY */ /* Power down the PHY */
imxrt_putreg(0xffffffff, IMXRT_USBPHY1_PWD); imxrt_putreg(0xffffffff, IMXRT_USBPHY2_PWD);
/* Stop clock /* Stop clock
* NOTE: This will interfere with USB OTG 2 and should probably be removed * NOTE: This will interfere with USB OTG 2 and should probably be removed
@ -3016,7 +3016,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
{ {
/* Enable USB controller interrupts */ /* Enable USB controller interrupts */
up_enable_irq(IMXRT_IRQ_USBOTG1); up_enable_irq(IMXRT_IRQ_USBOTG2);
} }
return ret; return ret;
@ -3051,7 +3051,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
/* Disable USB controller interrupts */ /* Disable USB controller interrupts */
up_disable_irq(IMXRT_IRQ_USBOTG1); up_disable_irq(IMXRT_IRQ_USBOTG2);
/* Unhook the driver */ /* Unhook the driver */