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backup 9 files from nuttx/arch/arm/src/imxrt/hardware for usb host

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wgzAIIT 2022-04-01 10:10:49 +08:00
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commit 0295b7ca38
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Ubiquitous/Nuttx_Fusion_XiUOS/app_match_nuttx/nuttx/arch/arm/src/imxrt/hardware/imxrt_usbotg.h Normal file
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/****************************************************************************
* arch/arm/src/imxrt/hardware/imxrt_usbotg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USBOTG_H
#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USBOTG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define IMXRT_EHCI_NRHPORT 1 /* There is only a single root hub port */
/* USBOTG register offsets (with respect to IMXRT_USB_BASE) *****************/
/* 0x000 - 0x0ff: Reserved */
/* Device/host capability registers */
#define IMXRT_USBOTG_HCCR_OFFSET 0x100 /* Offset to EHCI Host Controller Capabiliy registers */
#define IMXRT_USBOTG_CAPLENGTH_OFFSET 0x100 /* Capability register length (8-bit) */
#define IMXRT_USBHOST_HCIVERSION_OFFSET 0x102 /* Host interface version number (16-bit) */
#define IMXRT_USBHOST_HCSPARAMS_OFFSET 0x104 /* Host controller structural parameters */
#define IMXRT_USBHOST_HCCPARAMS_OFFSET 0x108 /* Host controller capability parameters */
#define IMXRT_USBDEV_DCIVERSION_OFFSET 0x120 /* Device interface version number */
#define IMXRT_USBDEV_DCCPARAMS_OFFSET 0x124 /* Device controller capability parameters */
/* Device/host/OTG operational registers */
#define IMXRT_USBOTG_HCOR_OFFSET 0x140 /* Offset to EHCI Host Controller Operational Registers */
#define IMXRT_USBOTG_USBCMD_OFFSET 0x140 /* USB command (both) */
#define IMXRT_USBOTG_USBSTS_OFFSET 0x144 /* USB status (both) */
#define IMXRT_USBOTG_USBINTR_OFFSET 0x148 /* USB interrupt enable (both) */
#define IMXRT_USBOTG_FRINDEX_OFFSET 0x14c /* USB frame index (both) */
/* EHCI 4G Segment Selector (not supported) */
#define IMXRT_USBOTG_PERIODICLIST_OFFSET 0x154 /* Frame list base address (host) */
#define IMXRT_USBOTG_DEVICEADDR_OFFSET 0x154 /* USB device address (device) */
#define IMXRT_USBOTG_ASYNCLISTADDR_OFFSET 0x158 /* Next asynchronous list address (host) */
#define IMXRT_USBOTG_ENDPOINTLIST_OFFSET 0x158 /* Address of endpoint list in memory (device) */
#define IMXRT_USBOTG_TTCTRL_OFFSET 0x15c /* Asynchronous buffer status for embedded TT (host) */
#define IMXRT_USBOTG_BURSTSIZE_OFFSET 0x160 /* Programmable burst size (both) */
#define IMXRT_USBOTG_TXFILLTUNING_OFFSET 0x164 /* Host transmit pre-buffer packet tuning (host) */
#define IMXRT_USBOTG_BINTERVAL_OFFSET 0x174 /* Length of virtual frame (both) */
#define IMXRT_USBOTG_ENDPTNAK_OFFSET 0x178 /* Endpoint NAK (device) */
#define IMXRT_USBOTG_ENDPTNAKEN_OFFSET 0x17c /* Endpoint NAK Enable (device) */
#define IMXRT_USBOTG_CONFIGFLAG_OFFSET 0x180 /* Configured flag register (not used in lpc313x) */
#define IMXRT_USBOTG_PORTSC1_OFFSET 0x184 /* Port status/control 1 (both) */
#define IMXRT_USBOTG_OTGSC_OFFSET 0x1a4 /* OTG status and control (otg) */
#define IMXRT_USBOTG_USBMODE_OFFSET 0x1a8 /* USB device mode (both) */
#define IMXRT_USBDEV_USBCMD_OFFSET 0x140 /* USB command (both) */
#define IMXRT_USBDEV_USBSTS_OFFSET 0x144 /* USB status (both) */
#define IMXRT_USBDEV_USBINTR_OFFSET 0x148 /* USB interrupt enable (both) */
#define IMXRT_USBDEV_FRINDEX_OFFSET 0x14c /* USB frame index (both) */
#define IMXRT_USBDEV_DEVICEADDR_OFFSET 0x154 /* USB device address (device) */
#define IMXRT_USBDEV_ENDPOINTLIST_OFFSET 0x158 /* Address of endpoint list in memory (device) */
#define IMXRT_USBDEV_BURSTSIZE_OFFSET 0x160 /* Programmable burst size (both) */
#define IMXRT_USBDEV_BINTERVAL_OFFSET 0x174 /* Length of virtual frame (both) */
#define IMXRT_USBDEV_ENDPTNAK_OFFSET 0x178 /* Endpoint NAK (device) */
#define IMXRT_USBDEV_ENDPTNAKEN_OFFSET 0x17c /* Endpoint NAK Enable (device) */
#define IMXRT_USBDEV_PORTSC1_OFFSET 0x184 /* Port status/control 1 (both) */
#define IMXRT_USBDEV_USBMODE_OFFSET 0x1a8 /* USB device mode (both) */
#define IMXRT_USBHOST_USBCMD_OFFSET 0x140 /* USB command (both) */
#define IMXRT_USBHOST_USBSTS_OFFSET 0x144 /* USB status (both) */
#define IMXRT_USBHOST_USBINTR_OFFSET 0x148 /* USB interrupt enable (both) */
#define IMXRT_USBHOST_FRINDEX_OFFSET 0x14c /* USB frame index (both) */
#define IMXRT_USBHOST_PERIODICLIST_OFFSET 0x154 /* Frame list base address (host) */
#define IMXRT_USBHOST_ASYNCLISTADDR_OFFSET 0x158 /* Next asynchronous list address (host) */
#define IMXRT_USBHOST_TTCTRL_OFFSET 0x15c /* Asynchronous buffer status for embedded TT (host) */
#define IMXRT_USBHOST_BURSTSIZE_OFFSET 0x160 /* Programmable burst size (both) */
#define IMXRT_USBHOST_TXFILLTUNING_OFFSET 0x164 /* Host transmit pre-buffer packet tuning (host) */
#define IMXRT_USBHOST_BINTERVAL_OFFSET 0x174 /* Length of virtual frame (both) */
#define IMXRT_USBHOST_PORTSC1_OFFSET 0x184 /* Port status/control 1 (both) */
#define IMXRT_USBHOST_USBMODE_OFFSET 0x1a8 /* USB device mode (both) */
/* Device endpoint registers */
#define IMXRT_USBDEV_ENDPTSETUPSTAT_OFFSET 0x1ac /* Endpoint setup status */
#define IMXRT_USBDEV_ENDPTPRIME_OFFSET 0x1b0 /* Endpoint initialization */
#define IMXRT_USBDEV_ENDPTFLUSH_OFFSET 0x1b4 /* Endpoint de-initialization */
#define IMXRT_USBDEV_ENDPTSTATUS_OFFSET 0x1b8 /* Endpoint status */
#define IMXRT_USBDEV_ENDPTCOMPLETE_OFFSET 0x1bc /* Endpoint complete */
#define IMXRT_USBDEV_ENDPTCTRL_OFFSET(n) (IMXRT_USBDEV_ENDPTCTRL0_OFFSET + ((n) * 4))
#define IMXRT_USBDEV_ENDPTCTRL0_OFFSET 0x1c0 /* Endpoint control 0 */
#define IMXRT_USBDEV_ENDPTCTRL1_OFFSET 0x1c4 /* Endpoint control 1 */
#define IMXRT_USBDEV_ENDPTCTRL2_OFFSET 0x1c8 /* Endpoint control 2 */
#define IMXRT_USBDEV_ENDPTCTRL3_OFFSET 0x1cc /* Endpoint control 3 */
#define IMXRT_USBDEV_ENDPTCTRL4_OFFSET 0x1d0 /* Endpoint control 4 */
#define IMXRT_USBDEV_ENDPTCTRL5_OFFSET 0x1d4 /* Endpoint control 5 */
#define IMXRT_USBDEV_ENDPTCTRL6_OFFSET 0x1d8 /* Endpoint control 6 */
#define IMXRT_USBDEV_ENDPTCTRL7_OFFSET 0x1dc /* Endpoint control 7 */
/* USB Non-core memory map & register definition */
#define IMXRT_USBNC_USB_OTG1_CTRL_OFFSET 0x0800 /* OTG1 Control Register */
#define IMXRT_USBNC_USB_OTG1_PHY_CTRL_0_OFFSET 0x0818 /* OTG1 Phy Control Register */
/* USBOTG register (virtual) addresses **************************************/
/* Device/host capability registers */
#define IMXRT_USBOTG_HCCR_BASE (IMXRT_USB_BASE + IMXRT_USBOTG_HCCR_OFFSET)
#define IMXRT_USBOTG_CAPLENGTH (IMXRT_USB_BASE + IMXRT_USBOTG_CAPLENGTH_OFFSET)
#define IMXRT_USBHOST_HCIVERSION (IMXRT_USB_BASE + IMXRT_USBHOST_HCIVERSION_OFFSET)
#define IMXRT_USBHOST_HCSPARAMS (IMXRT_USB_BASE + IMXRT_USBHOST_HCSPARAMS_OFFSET)
#define IMXRT_USBHOST_HCCPARAMS (IMXRT_USB_BASE + IMXRT_USBHOST_HCCPARAMS_OFFSET)
#define IMXRT_USBDEV_DCIVERSION (IMXRT_USB_BASE + IMXRT_USBDEV_DCIVERSION_OFFSET)
#define IMXRT_USBDEV_DCCPARAMS (IMXRT_USB_BASE + IMXRT_USBDEV_DCCPARAMS_OFFSET)
/* Device/host operational registers */
#define IMXRT_USBOTG_HCOR_BASE (IMXRT_USB_BASE + IMXRT_USBOTG_HCOR_OFFSET)
#define IMXRT_USBOTG_USBCMD (IMXRT_USB_BASE + IMXRT_USBOTG_USBCMD_OFFSET)
#define IMXRT_USBOTG_USBSTS (IMXRT_USB_BASE + IMXRT_USBOTG_USBSTS_OFFSET)
#define IMXRT_USBOTG_USBINTR (IMXRT_USB_BASE + IMXRT_USBOTG_USBINTR_OFFSET)
#define IMXRT_USBOTG_FRINDEX (IMXRT_USB_BASE + IMXRT_USBOTG_FRINDEX_OFFSET)
#define IMXRT_USBOTG_PERIODICLIST (IMXRT_USB_BASE + IMXRT_USBOTG_PERIODICLIST_OFFSET)
#define IMXRT_USBOTG_DEVICEADDR (IMXRT_USB_BASE + IMXRT_USBOTG_DEVICEADDR_OFFSET)
#define IMXRT_USBOTG_ASYNCLISTADDR (IMXRT_USB_BASE + IMXRT_USBOTG_ASYNCLISTADDR_OFFSET)
#define IMXRT_USBOTG_ENDPOINTLIST (IMXRT_USB_BASE + IMXRT_USBOTG_ENDPOINTLIST_OFFSET)
#define IMXRT_USBOTG_TTCTRL (IMXRT_USB_BASE + IMXRT_USBOTG_TTCTRL_OFFSET)
#define IMXRT_USBOTG_BURSTSIZE (IMXRT_USB_BASE + IMXRT_USBOTG_BURSTSIZE_OFFSET)
#define IMXRT_USBOTG_TXFILLTUNING (IMXRT_USB_BASE + IMXRT_USBOTG_TXFILLTUNING_OFFSET)
#define IMXRT_USBOTG_BINTERVAL (IMXRT_USB_BASE + IMXRT_USBOTG_BINTERVAL_OFFSET)
#define IMXRT_USBOTG_ENDPTNAK (IMXRT_USB_BASE + IMXRT_USBOTG_ENDPTNAK_OFFSET)
#define IMXRT_USBOTG_ENDPTNAKEN (IMXRT_USB_BASE + IMXRT_USBOTG_ENDPTNAKEN_OFFSET)
#define IMXRT_USBOTG_PORTSC1 (IMXRT_USB_BASE + IMXRT_USBOTG_PORTSC1_OFFSET)
#define IMXRT_USBOTG_OTGSC (IMXRT_USB_BASE + IMXRT_USBOTG_OTGSC_OFFSET)
#define IMXRT_USBOTG_USBMODE (IMXRT_USB_BASE + IMXRT_USBOTG_USBMODE_OFFSET)
#define IMXRT_USBDEV_USBCMD (IMXRT_USB_BASE + IMXRT_USBDEV_USBCMD_OFFSET)
#define IMXRT_USBDEV_USBSTS (IMXRT_USB_BASE + IMXRT_USBDEV_USBSTS_OFFSET)
#define IMXRT_USBDEV_USBINTR (IMXRT_USB_BASE + IMXRT_USBDEV_USBINTR_OFFSET)
#define IMXRT_USBDEV_FRINDEX (IMXRT_USB_BASE + IMXRT_USBDEV_FRINDEX_OFFSET)
#define IMXRT_USBDEV_DEVICEADDR (IMXRT_USB_BASE + IMXRT_USBDEV_DEVICEADDR_OFFSET)
#define IMXRT_USBDEV_ENDPOINTLIST (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPOINTLIST_OFFSET)
#define IMXRT_USBDEV_BURSTSIZE (IMXRT_USB_BASE + IMXRT_USBDEV_BURSTSIZE_OFFSET)
#define IMXRT_USBDEV_BINTERVAL (IMXRT_USB_BASE + IMXRT_USBDEV_BINTERVAL_OFFSET)
#define IMXRT_USBDEV_ENDPTNAK (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTNAK_OFFSET)
#define IMXRT_USBDEV_ENDPTNAKEN (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTNAKEN_OFFSET)
#define IMXRT_USBDEV_PORTSC1 (IMXRT_USB_BASE + IMXRT_USBDEV_PORTSC1_OFFSET)
#define IMXRT_USBDEV_USBMODE (IMXRT_USB_BASE + IMXRT_USBDEV_USBMODE_OFFSET)
#define IMXRT_USBHOST_USBCMD (IMXRT_USB_BASE + IMXRT_USBHOST_USBCMD_OFFSET)
#define IMXRT_USBHOST_USBSTS (IMXRT_USB_BASE + IMXRT_USBHOST_USBSTS_OFFSET)
#define IMXRT_USBHOST_USBINTR (IMXRT_USB_BASE + IMXRT_USBHOST_USBINTR_OFFSET)
#define IMXRT_USBHOST_FRINDEX (IMXRT_USB_BASE + IMXRT_USBHOST_FRINDEX_OFFSET)
#define IMXRT_USBHOST_PERIODICLIST (IMXRT_USB_BASE + IMXRT_USBHOST_PERIODICLIST_OFFSET)
#define IMXRT_USBHOST_ASYNCLISTADDR (IMXRT_USB_BASE + IMXRT_USBHOST_ASYNCLISTADDR_OFFSET)
#define IMXRT_USBHOST_TTCTRL (IMXRT_USB_BASE + IMXRT_USBHOST_TTCTRL_OFFSET)
#define IMXRT_USBHOST_BURSTSIZE (IMXRT_USB_BASE + IMXRT_USBHOST_BURSTSIZE_OFFSET)
#define IMXRT_USBHOST_TXFILLTUNING (IMXRT_USB_BASE + IMXRT_USBHOST_TXFILLTUNING_OFFSET)
#define IMXRT_USBHOST_BINTERVAL (IMXRT_USB_BASE + IMXRT_USBHOST_BINTERVAL_OFFSET)
#define IMXRT_USBHOST_PORTSC1 (IMXRT_USB_BASE + IMXRT_USBHOST_PORTSC1_OFFSET)
#define IMXRT_USBHOST_USBMODE (IMXRT_USB_BASE + IMXRT_USBHOST_USBMODE_OFFSET)
/* Device endpoint registers */
#define IMXRT_USBDEV_ENDPTSETUPSTAT (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTSETUPSTAT_OFFSET)
#define IMXRT_USBDEV_ENDPTPRIME (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTPRIME_OFFSET)
#define IMXRT_USBDEV_ENDPTFLUSH (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTFLUSH_OFFSET)
#define IMXRT_USBDEV_ENDPTSTATUS (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTSTATUS_OFFSET)
#define IMXRT_USBDEV_ENDPTCOMPLETE (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCOMPLETE_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL(n) (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL_OFFSET(n))
#define IMXRT_USBDEV_ENDPTCTRL0 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL0_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL1 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL1_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL2 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL2_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL3 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL3_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL4 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL4_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL5 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL5_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL6 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL6_OFFSET)
#define IMXRT_USBDEV_ENDPTCTRL7 (IMXRT_USB_BASE + IMXRT_USBDEV_ENDPTCTRL7_OFFSET)
/* Device non-core registers */
#define IMXRT_USBNC_USB_OTG1_CTRL (IMXRT_USB_BASE + IMXRT_USBNC_USB_OTG1_CTRL_OFFSET)
#define IMXRT_USBNC_USB_OTG1_PHY_CTRL_0 (IMXRT_USB_BASE + IMXRT_USBNC_USB_OTG1_PHY_CTRL_0_OFFSET)
/* USBOTG register bit definitions ******************************************/
/* Device/host capability registers */
/* CAPLENGTH */
#define USBOTG_CAPLENGTH_SHIFT (0) /* Bits 0-7: Offset from register base to operational regs */
#define USBOTG_CAPLENGTH_MASK (0xff << USBOTG_CAPLENGTH_SHIFT)
/* HCIVERSION */
#define USBHOST_HCIVERSION_SHIFT (0) /* Bits 0-15: BCD encoding of the EHCI revision number */
#define USBHOST_HCIVERSION_MASK (0xffff << USBHOST_HCIVERSION_SHIFT)
/* HCSPARAMS */
#define USBHOST_HCSPARAMS_NTT_SHIFT (24) /* Bits 24-27: Number of Transaction Translators */
#define USBHOST_HCSPARAMS_NTT_MASK (15 << USBHOST_HCSPARAMS_NTT_SHIFT)
#define USBHOST_HCSPARAMS_NPTT_SHIFT (20) /* Bits 20-23: Number of Ports per Transaction Translator */
#define USBHOST_HCSPARAMS_NPTT_MASK (15 << USBHOST_HCSPARAMS_NPTT_SHIFT)
#define USBHOST_HCSPARAMS_PI (1 >> 16) /* Bit 16: Port indicators */
#define USBHOST_HCSPARAMS_NCC_SHIFT (15) /* Bits 12-15: Number of Companion Controller */
#define USBHOST_HCSPARAMS_NCC_MASK (15 << USBHOST_HCSPARAMS_NCC_SHIFT)
#define USBHOST_HCSPARAMS_NPCC_SHIFT (8) /* Bits 8-11: Number of Ports per Companion Controller */
#define USBHOST_HCSPARAMS_NPCC_MASK (15 << USBHOST_HCSPARAMS_NPCC_SHIFT)
#define USBHOST_HCSPARAMS_PPC (1 >> 4) /* Bit 4: Port Power Control */
#define USBHOST_HCSPARAMS_NPORTS_SHIF (0) /* Bits 0-3: Number of downstream ports */
#define USBHOST_HCSPARAMS_NPORTS_MASK (15 << USBHOST_HCSPARAMS_NPORTS_SHIFT)
/* HCCPARAMS */
#define USBHOST_HCCPARAMS_EECP_SHIFT (8) /* Bits 8-15: EHCI Extended Capabilities Pointer */
#define USBHOST_HCCPARAMS_EECP_MASK (255 << USBHOST_HCCPARAMS_EECP_SHIFT)
#define USBHOST_HCCPARAMS_IST_SHIFT (4) /* Bits 4-7: Isochronous Scheduling Threshold */
#define USBHOST_HCCPARAMS_IST_MASK (15 << USBHOST_HCCPARAMS_IST_SHIFT)
#define USBHOST_HCCPARAMS_ASP (1 >> 2) /* Bit 2: Asynchronous Schedule Park Capability */
#define USBHOST_HCCPARAMS_PFL (1 >> 1) /* Bit 1: Programmable Frame List Flag */
#define USBHOST_HCCPARAMS_ADC (1 >> 0) /* Bit 0: 64-bit Addressing Capability */
/* DCIVERSION */
#define USBDEV_DCIVERSION_SHIFT (0) /* Bits 0-15: BCD encoding of the device interface */
#define USBDEV_DCIVERSION_MASK (0xffff << USBDEV_DCIVERSION_SHIFT)
/* DCCPARAMS */
#define USBDEV_DCCPARAMS_HC (1 >> 8) /* Bit 8: Host Capable */
#define USBDEV_DCCPARAMS_DC (1 >> 7) /* Bit 7: Device Capable */
#define USBDEV_DCCPARAMS_DEN_SHIFT (0) /* Bits 0-4: DEN Device Endpoint Number */
#define USBDEV_DCCPARAMS_DEN_MASK (31 << USBDEV_DCCPARAMS_DEN_SHIFT)
/* Device/host operational registers */
/* USB Command register USBCMD -- Device Mode */
#define USBDEV_USBCMD_ITC_SHIFT (16) /* Bits 16-23: Interrupt threshold control */
#define USBDEV_USBCMD_ITC_MASK (255 << USBDEV_USBCMD_ITC_SHIFT)
# define USBDEV_USBCMD_ITCIMME (0 << USBDEV_USBCMD_ITC_SHIFT) /* Immediate (no threshold) */
# define USBDEV_USBCMD_ITC1UF (1 << USBDEV_USBCMD_ITC_SHIFT) /* 1 micro frame */
# define USBDEV_USBCMD_ITC2UF (2 << USBDEV_USBCMD_ITC_SHIFT) /* 2 micro frames */
# define USBDEV_USBCMD_ITC4UF (4 << USBDEV_USBCMD_ITC_SHIFT) /* 4 micro frames */
# define USBDEV_USBCMD_ITC8UF (8 << USBDEV_USBCMD_ITC_SHIFT) /* 8 micro frames */
# define USBDEV_USBCMD_ITC16UF (16 << USBDEV_USBCMD_ITC_SHIFT) /* 16 micro frames */
# define USBDEV_USBCMD_ITC32UF (32 << USBDEV_USBCMD_ITC_SHIFT) /* 32 micro frames */
# define USBDEV_USBCMD_ITC64UF (64 << USBDEV_USBCMD_ITC_SHIFT) /* 64 micro frames */
#define USBDEV_USBCMD_ATDTW (1 << 14) /* Bit 14: Add dTD trip wire */
#define USBDEV_USBCMD_SUTW (1 << 13) /* Bit 13: Setup trip wire */
#define USBDEV_USBCMD_RST (1 << 1) /* Bit 1: 1 Controller reset */
#define USBDEV_USBCMD_RS (1 << 0) /* Bit 0: 0 Run/Stop */
/* USB Command register USBCMD -- Host Mode */
#define USBHOST_USBCMD_ITC_SHIFT (16) /* Bits 16-13: Interrupt threshold control */
#define USBHOST_USBCMD_ITC_MASK (255 << USBHOST_USBCMD_ITC_SHIFT)
# define USBHOST_USBCMD_ITCIMMED (0 << USBHOST_USBCMD_ITC_SHIFT) /* Immediate (no threshold) */
# define USBHOST_USBCMD_ITC1UF (1 << USBHOST_USBCMD_ITC_SHIFT) /* 1 micro frame */
# define USBHOST_USBCMD_ITC2UF (2 << USBHOST_USBCMD_ITC_SHIFT) /* 2 micro frames */
# define USBHOST_USBCMD_ITC4UF (4 << USBHOST_USBCMD_ITC_SHIFT) /* 4 micro frames */
# define USBHOST_USBCMD_ITC8UF (8 << USBHOST_USBCMD_ITC_SHIFT) /* 8 micro frames */
# define USBHOST_USBCMD_ITC16UF (16 << USBHOST_USBCMD_ITC_SHIFT) /* 16 micro frames */
# define USBHOST_USBCMD_ITC32UF (32 << USBHOST_USBCMD_ITC_SHIFT) /* 32 micro frames */
# define USBHOST_USBCMD_ITC64UF (64 << USBHOST_USBCMD_ITC_SHIFT) /* 64 micro frames */
#define USBHOST_USBCMD_FS2 (1 << 15) /* Bit 15: Bit 2 of the Frame List Size bits */
#define USBHOST_USBCMD_ASPE (1 << 11) /* Bit 11: Asynchronous Schedule Park Mode Enable */
#define USBHOST_USBCMD_ASP_SHIFT (8) /* Bits 8-9: Asynchronous schedule park mode */
#define USBHOST_USBCMD_ASP_MASK (3 << USBHOST_USBCMD_ASP_SHIFT)
#define USBHOST_USBCMD_IAA (1 << 6) /* Bit 6: Interrupt next asynchronous schedule */
#define USBHOST_USBCMD_ASE (1 << 5) /* Bit 5: Skips processing asynchronous schedule */
#define USBHOST_USBCMD_PSE (1 << 4) /* Bit 4: Skips processing periodic schedule */
#define USBHOST_USBCMD_FS1 (1 << 3) /* Bit 3: Bit 1 of the Frame List Size bits */
#define USBHOST_USBCMD_FS0 (1 << 2) /* Bit 2: Bit 0 of the Frame List Size bits */
#define USBHOST_USBCMD_RST (1 << 1) /* Bit 1: Controller reset */
#define USBHOST_USBCMD_RS (1 << 0) /* Bit 0: Run/Stop */
/* USB Status register USBSTS -- Device Mode */
#define USBDEV_USBSTS_NAKI (1 << 16) /* Bit 16: NAK interrupt bit */
#define USBDEV_USBSTS_SLI (1 << 8) /* Bit 8: DCSuspend */
#define USBDEV_USBSTS_SRI (1 << 7) /* Bit 7: SOF received */
#define USBDEV_USBSTS_URI (1 << 6) /* Bit 6: USB reset received */
#define USBDEV_USBSTS_PCI (1 << 2) /* Bit 2: Port change detect */
#define USBDEV_USBSTS_UEI (1 << 1) /* Bit 1: USB error interrupt */
#define USBDEV_USBSTS_UI (1 << 0) /* Bit 0: USB interrupt */
/* USB Status register USBSTS -- Host Mode */
#define USBHOST_USBSTS_UPI (1 << 19) /* Bit 19: USB host periodic interrupt */
#define USBHOST_USBSTS_UAI (1 << 18) /* Bit 18: USB host asynchronous interrupt */
#define USBHOST_USBSTS_AS (1 << 15) /* Bit 15: Asynchronous schedule status */
#define USBHOST_USBSTS_PS (1 << 14) /* Bit 14: Periodic schedule status */
#define USBHOST_USBSTS_RCL (1 << 13) /* Bit 13: Reclamation */
#define USBHOST_USBSTS_HCH (1 << 12) /* Bit 12: HCHalted */
#define USBHOST_USBSTS_SRI (1 << 7) /* Bit 7: SOF received */
#define USBHOST_USBSTS_AAI (1 << 5) /* Bit 5: Interrupt on async advance */
#define USBHOST_USBSTS_FRI (1 << 3) /* Bit 3: Frame list roll-over */
#define USBHOST_USBSTS_PCI (1 << 2) /* Bit 2: Port change detect */
#define USBHOST_USBSTS_UEI (1 << 1) /* Bit 1: USB error interrupt */
#define USBHOST_USBSTS_UI (1 << 0) /* Bit 0: USB interrupt */
/* USB interrupt register USBINTR -- Device Mode */
#define USBDEV_USBINTR_NAKE (1 << 16) /* Bit 16: NAK interrupt enable */
#define USBDEV_USBINTR_SLE (1 << 8) /* Bit 8: Sleep enable */
#define USBDEV_USBINTR_SRE (1 << 7) /* Bit 7: SOF received enable */
#define USBDEV_USBINTR_URE (1 << 6) /* Bit 6: USB reset enable */
#define USBDEV_USBINTR_PCE (1 << 2) /* Bit 2: Port change detect enable */
#define USBDEV_USBINTR_UEE (1 << 1) /* Bit 1: USB error interrupt enable */
#define USBDEV_USBINTR_UE (1 << 0) /* Bit 0: USB interrupt enable */
/* USB interrupt register USBINTR (address 0x19000148) -- Host Mode */
#define USBHOST_USBINTR_UPIA (1 << 19) /* Bit 19: USB host periodic interrupt enable */
#define USBHOST_USBINTR_UAIE (1 << 18) /* Bit 18: USB host asynchronous interrupt enable */
#define USBHOST_USBINTR_SRE (1 << 7) /* Bit 7: SOF timer interrupt enable */
#define USBHOST_USBINTR_AAE (1 << 5) /* Bit 5: Interrupt on asynchronous advance enable */
#define USBHOST_USBINTR_FRE (1 << 3) /* Bit 3: Frame list rollover enable */
#define USBHOST_USBINTR_PCE (1 << 2) /* Bit 2: Port change detect enable */
#define USBHOST_USBINTR_UEE (1 << 1) /* Bit 1: USB error interrupt enable */
#define USBHOST_USBINTR_UE (1 << 0) /* Bit 0: USB interrupt enable */
/* Frame index register FRINDEX -- Device Mode */
#define USBDEV_FRINDEX_LFN_SHIFT (3) /* Bits 3-13: Frame number of last frame transmitted */
#define USBDEV_FRINDEX_LFN_MASK (0x7ff << USBDEV_FRINDEX_LFN_SHIFT)
#define USBDEV_FRINDEX_CUFN_SHIFT (0) /* Bits 0-2: Current micro frame number */
#define USBDEV_FRINDEX_CUFN_MASK (7 << USBDEV_FRINDEX_CUFN_SHIFT)
/* Frame index register FRINDEX -- Host Mode */
#define USBHOST_FRINDEX_FLI_SHIFT (3) /* Bits 3-13: Frame list current index */
#define USBHOST_FRINDEX_FLI_MASK(n) (0x7ff << ((n) + USBHOST_FRINDEX_FLI_SHIFT - 1)
#define USBHOST_FRINDEX_CUFN_SHIFT (0) /* Bits 0-2: Current micro frame number */
#define USBHOST_FRINDEX_CUFN_MASK (7 << USBHOST_FRINDEX_CUFN_SHIFT)
/* USB Device Address register DEVICEADDR -- Device Mode */
#define USBDEV_DEVICEADDR_SHIFT (25) /* Bits 25-31: USBADR USB device address */
#define USBDEV_DEVICEADDR_MASK (0x3c << USBDEV_DEVICEADDR_SHIFT)
#define USBDEV_DEVICEADDR_USBADRA (1 << 24) /* Bit 24: Device address advance */
/* USB Periodic List Base register PERIODICLIST -- Host Mode */
#define USBHOST_PERIODICLIST_PERBASE_SHIFT (12) /* Bits 12-31: Base Address (Low) */
#define USBHOST_PERIODICLIST_PERBASE_MASK (0x000fffff << USBHOST_PERIODICLIST_PERBASE_SHIFT)
/* USB Endpoint List Address register ENDPOINTLISTADDR -- Device Mode */
#define USBDEV_ENDPOINTLIST_EPBASE_SHIFT (11) /* Bits 11-31: Endpoint list pointer (low) */
#define USBDEV_ENDPOINTLIST_EPBASE_MASK (0x001fffff << USBDEV_ENDPOINTLIST_EPBASE_SHIFT)
/* USB Asynchronous List Address register ASYNCLISTADDR -- Host Mode */
#define USBHOST_ASYNCLISTADDR_ASYBASE_SHIFT (5) /* Bits 5-31: Link pointer (Low) LPL */
#define USBHOST_ASYNCLISTADDR_ASYBASE_MASK (0x07ffffff << USBHOST_ASYNCLISTADDR_ASYBASE_SHIFT)
/* USB TT Control register TTCTRL (address 0x1900015c) -- Host Mode */
#define USBHOST_TTCTRL_TTHA_SHIFT (24) /* Bits 24-30: Hub address */
#define USBHOST_TTCTRL_TTHA_MASK (0x7f << USBHOST_TTCTRL_TTHA_SHIFT)
/* USB burst size register BURSTSIZE -- Device/Host Mode */
#define USBDEV_BURSTSIZE_TXPBURST_SHIFT (8) /* Bits 8-15: Programmable TX burst length */
#define USBDEV_BURSTSIZE_TXPBURST_MASK (255 << USBDEV_BURSTSIZE_TXPBURST_SHIFT)
#define USBDEV_BURSTSIZE_RXPBURST_SHIFT (0) /* Bits 0-7: RXPBURST Programmable RX burst length */
#define USBDEV_BURSTSIZE_RXPBURST_MASK (255 << USBDEV_BURSTSIZE_RXPBURST_SHIFT)
#define USBHOST_BURSTSIZE_TXPBURST_SHIFT (8) /* Bits 8-15: Programmable TX burst length */
#define USBHOST_BURSTSIZE_TXPBURST_MASK (255 << USBHOST_BURSTSIZE_TXPBURST_SHIFT)
#define USBHOST_BURSTSIZE_RXPBURST_SHIFT (0) /* Bits 0-7: RXPBURST Programmable RX burst length */
#define USBHOST_BURSTSIZE_RXPBURST_MASK (255 << USBHOST_BURSTSIZE_RXPBURST_SHIFT)
/* USB Transfer buffer Fill Tuning register TXFIFOFILLTUNING -- Host Mode */
#define USBHOST_TXFILLTUNING_FIFOTHRES_SHIFT (16) /* Bits 16-21: Scheduler overhead */
#define USBHOST_TXFILLTUNING_FIFOTHRES_MASK (0x3c << USBHOST_TXFILLTUNING_FIFOTHRES_SHIFT)
#define USBHOST_TXFILLTUNING_SCHEATLTH_SHIFT (8) /* Bits 8-12: Scheduler health counter */
#define USBHOST_TXFILLTUNING_SCHEATLTH_MASK (0x1f << USBHOST_TXFILLTUNING_SCHEATLTH_SHIFT)
#define USBHOST_TXFILLTUNING_SCHOH_SHIFT (0) /* Bits 0-7: FIFO burst threshold */
#define USBHOST_TXFILLTUNING_SCHOH_MASK (0xff << USBHOST_TXFILLTUNING_SCHOH_SHIFT)
/* USB BINTERVAL register BINTERVAL -- Device/Host Mode */
#define USBDEV_BINTERVAL_SHIFT (0) /* Bits 0-3: bInterval value */
#define USBDEV_BINTERVAL_MASK (15 << USBDEV_BINTERVAL_SHIFT)
#define USBHOST_BINTERVAL_SHIFT (0) /* Bits 0-3: bInterval value */
#define USBHOST_BINTERVAL_MASK (15 << USBHOST_BINTERVAL_SHIFT)
/* USB endpoint NAK register ENDPTNAK -- Device Mode */
#define USBDEV_ENDPTNAK_EPTN_SHIFT (16) /* Bits 16-19: Tx endpoint NAK */
#define USBDEV_ENDPTNAK_EPTN_MASK (15 << USBDEV_ENDPTNAK_EPTN_SHIFT)
#define USBDEV_ENDPTNAK_EPRN_SHIFT (0) /* Bits 0-3: Rx endpoint NAK */
#define USBDEV_ENDPTNAK_EPRN_MASK (15 << USBDEV_ENDPTNAK_EPRN_SHIFT)
/* USB Endpoint NAK Enable register ENDPTNAKEN -- Device Mode */
#define USBDEV_ENDPTNAK_EPTNE_SHIFT (16) /* Bits 16-19: Tx endpoint NAK enable */
#define USBDEV_ENDPTNAK_EPTNE_MASK (15 << USBDEV_ENDPTNAK_EPTNE_SHIFT)
#define USBDEV_ENDPTNAK_EPRNE_SHIFT (0) /* Bits 0-3: Rx endpoint NAK enable */
#define USBDEV_ENDPTNAK_EPRNE_MASK (15 << USBDEV_ENDPTNAK_EPRNE_SHIFT)
/* Port Status and Control register PRTSC1 -- Device Mode */
#define USBDEV_PRTSC1_PSPD_SHIFT (26) /* Bits 26-27: Port speed */
#define USBDEV_PRTSC1_PSPD_MASK (3 << USBDEV_PRTSC1_PSPD_SHIFT)
# define USBDEV_PRTSC1_PSPD_FS (0 << USBDEV_PRTSC1_PSPD_SHIFT) /* Full-speed */
# define USBDEV_PRTSC1_PSPD_LS (1 << USBDEV_PRTSC1_PSPD_SHIFT) /* Low-speed */
# define USBDEV_PRTSC1_PSPD_HS (2 << USBDEV_PRTSC1_PSPD_SHIFT) /* High-speed */
#define USBDEV_PRTSC1_PFSC (1 << 24) /* Bit 24: Port force full speed connect */
#define USBDEV_PRTSC1_PHCD (1 << 23) /* Bit 23: PHY low power suspend - clock disable (PLPSCD) */
#define USBDEV_PRTSC1_PTC_SHIFT (16) /* Bits 16-19: 19: Port test control */
#define USBDEV_PRTSC1_PTC_MASK (15 << USBDEV_PRTSC1_PTC_SHIFT)
# define USBDEV_PRTSC1_PTC_DISABLE (0 << USBDEV_PRTSC1_PTC_SHIFT) /* TEST_MODE_DISABLE */
# define USBDEV_PRTSC1_PTC_JSTATE (1 << USBDEV_PRTSC1_PTC_SHIFT) /* J_STATE */
# define USBDEV_PRTSC1_PTC_KSTATE (2 << USBDEV_PRTSC1_PTC_SHIFT) /* K_STATE */
# define USBDEV_PRTSC1_PTC_SE0 (3 << USBDEV_PRTSC1_PTC_SHIFT) /* SE0 (host)/NAK (device) */
# define USBDEV_PRTSC1_PTC_PACKET (4 << USBDEV_PRTSC1_PTC_SHIFT) /* Packet */
# define USBDEV_PRTSC1_PTC_HS (5 << USBDEV_PRTSC1_PTC_SHIFT) /* FORCE_ENABLE_HS */
# define USBDEV_PRTSC1_PTC_FS (6 << USBDEV_PRTSC1_PTC_SHIFT) /* FORCE_ENABLE_FS */
#define USBDEV_PRTSC1_PIC_SHIFT (14) /* Bits 14-15: Port indicator control */
#define USBDEV_PRTSC1_PIC_MASK (3 << USBDEV_PRTSC1_PIC_SHIFT)
# define USBDEV_PRTSC1_PIC_OFF (0 << USBDEV_PRTSC1_PIC_SHIFT) /* 00 Port indicators are off */
# define USBDEV_PRTSC1_PIC_AMBER (1 << USBDEV_PRTSC1_PIC_SHIFT) /* 01 amber */
# define USBDEV_PRTSC1_PIC_GREEN (2 << USBDEV_PRTSC1_PIC_SHIFT) /* 10 green */
#define USBDEV_PRTSC1_HSP (1 << 9) /* Bit 9: High-speed status */
#define USBDEV_PRTSC1_PR (1 << 8) /* Bit 8: Port reset */
#define USBDEV_PRTSC1_SUSP (1 << 7) /* Bit 7: Suspend */
#define USBDEV_PRTSC1_FPR (1 << 6) /* Bit 6: Force port resume */
#define USBDEV_PRTSC1_PEC (1 << 3) /* Bit 3: Port enable/disable change */
#define USBDEV_PRTSC1_PE (1 << 2) /* Bit 2: Port enable */
#define USBDEV_PRTSC1_CCS (1 << 0) /* Bit 0: Current connect status */
/* Port Status and Control register PRTSC1 -- Host Mode */
#define USBHOST_PRTSC1_PSPD_SHIFT (26) /* Bits 26-27: Port speed */
#define USBHOST_PRTSC1_PSPD_MASK (3 << USBHOST_PRTSC1_PSPD_SHIFT)
# define USBHOST_PRTSC1_PSPD_FS (0 << USBHOST_PRTSC1_PSPD_SHIFT) /* Full-speed */
# define USBHOST_PRTSC1_PSPD_LS (1 << USBHOST_PRTSC1_PSPD_SHIFT) /* Low-speed */
# define USBHOST_PRTSC1_PSPD_HS (2 << USBHOST_PRTSC1_PSPD_SHIFT) /* High-speed */
#define USBHOST_PRTSC1_PFSC (1 << 24) /* Bit 24: Port force full speed connect */
#define USBHOST_PRTSC1_PHCD (1 << 23) /* Bit 23: PHY low power suspend - clock disable (PLPSCD) */
#define USBHOST_PRTSC1_WKOC (1 << 22) /* Bit 22: Wake on over-current enable (WKOC_E) */
#define USBHOST_PRTSC1_WKDC (1 << 21) /* Bit 21: Wake on disconnect enable (WKDSCNNT_E) */
#define USBHOST_PRTSC1_WKCN (1 << 20) /* Bit 20: Wake on connect enable (WKCNNT_E) */
#define USBHOST_PRTSC1_PTC_SHIFT (16) /* Bits 16-19: Port test control */
#define USBHOST_PRTSC1_PTC_MASK (15 << USBHOST_PRTSC1_PTC_SHIFT)
# define USBHOST_PRTSC1_PTC_DISABLE (0 << USBHOST_PRTSC1_PTC_SHIFT) /* 0000 TEST_MODE_DISABLE */
# define USBHOST_PRTSC1_PTC_JSTATE (1 << USBHOST_PRTSC1_PTC_SHIFT) /* 0001 J_STATE */
# define USBHOST_PRTSC1_PTC_KSTATE (2 << USBHOST_PRTSC1_PTC_SHIFT) /* 0010 K_STATE */
# define USBHOST_PRTSC1_PTC_SE0 (3 << USBHOST_PRTSC1_PTC_SHIFT) /* 0011 SE0 (host)/NAK (device) */
# define USBHOST_PRTSC1_PTC_PACKET (4 << USBHOST_PRTSC1_PTC_SHIFT) /* 0100 Packet */
# define USBHOST_PRTSC1_PTC_HS (5 << USBHOST_PRTSC1_PTC_SHIFT) /* 0101 FORCE_ENABLE_HS */
# define USBHOST_PRTSC1_PTC_FS (6 << USBHOST_PRTSC1_PTC_SHIFT) /* 0110 FORCE_ENABLE_FS */
# define USBHOST_PRTSC1_PTC_LS (7 << USBHOST_PRTSC1_PTC_SHIFT) /* 0111 FORCE_ENABLE_LS */
#define USBHOST_PRTSC1_PIC_SHIFT (14) /* Bits 14-15: Port indicator control */
#define USBHOST_PRTSC1_PIC_MASK (3 << USBHOST_PRTSC1_PIC_SHIFT)
# define USBHOST_PRTSC1_PIC_OFF (0 << USBHOST_PRTSC1_PIC_SHIFT) /* 00 Port indicators are off */
# define USBHOST_PRTSC1_PIC_AMBER (1 << USBHOST_PRTSC1_PIC_SHIFT) /* 01 Amber */
# define USBHOST_PRTSC1_PIC_GREEN (2 << USBHOST_PRTSC1_PIC_SHIFT) /* 10 Green */
#define USBHOST_PRTSC1_PP (1 << 12) /* Bit 12: Port power control */
#define USBHOST_PRTSC1_LS_SHIFT (10) /* Bits 10-11: Line status */
#define USBHOST_PRTSC1_LS_MASK (3 << USBHOST_PRTSC1_LS_SHIFT)
# define USBHOST_PRTSC1_LS_SE0 (0 << USBHOST_PRTSC1_LS_SHIFT) /* SE0 (USB_DP and USB_DM LOW) */
# define USBHOST_PRTSC1_LS_JSTATE (2 << USBHOST_PRTSC1_LS_SHIFT) /* J-state (USB_DP HIGH and USB_DM LOW) */
# define USBHOST_PRTSC1_LS_KSTATE (1 << USBHOST_PRTSC1_LS_SHIFT) /* K-state (USB_DP LOW and USB_DM HIGH) */
#define USBHOST_PRTSC1_HSP (1 << 9) /* Bit 9: High-speed status */
#define USBHOST_PRTSC1_PR (1 << 8) /* Bit 8: Port reset */
#define USBHOST_PRTSC1_SUSP (1 << 7) /* Bit 7: Suspend */
#define USBHOST_PRTSC1_FPR (1 << 6) /* Bit 6: Force port resume */
#define USBHOST_PRTSC1_OCC (1 << 5) /* Bit 5: Over-current change */
#define USBHOST_PRTSC1_OCA (1 << 4) /* Bit 4: Over-current active */
#define USBHOST_PRTSC1_PEC (1 << 3) /* Bit 3: Port disable/enable change */
#define USBHOST_PRTSC1_PE (1 << 2) /* Bit 2: Port enable */
#define USBHOST_PRTSC1_CSC (1 << 1) /* Bit 1: Connect status change */
#define USBHOST_PRTSC1_CCS (1 << 0) /* Bit 0: Current connect status */
/* OTG Status and Control register (OTGSC) */
/* OTG interrupt enable */
#define USBOTG_OTGSC_DPIE (1 << 30) /* Bit 30: Data pulse interrupt enable */
#define USBOTG_OTGSC_1MSE (1 << 29) /* Bit 29: 1 millisecond timer interrupt enable */
#define USBOTG_OTGSC_BSEIE (1 << 28) /* Bit 28: B-session end interrupt enable */
#define USBOTG_OTGSC_BSVIE (1 << 27) /* Bit 27: B-session valid interrupt enable */
#define USBOTG_OTGSC_ASVIE (1 << 26) /* Bit 26: A-session valid interrupt enable */
#define USBOTG_OTGSC_AVVIE (1 << 25) /* Bit 25: A-VBUS valid interrupt enable */
#define USBOTG_OTGSC_IDIE (1 << 24) /* Bit 24: USB ID interrupt enable */
/* OTG interrupt status */
#define USBOTG_OTGSC_DPIS (1 << 22) /* Bit 22: Data pulse interrupt status */
#define USBOTG_OTGSC_1MSS (1 << 21) /* Bit 21: 1 millisecond timer interrupt status */
#define USBOTG_OTGSC_BSEIS (1 << 20) /* Bit 20: B-Session end interrupt status */
#define USBOTG_OTGSC_BSVIS (1 << 19) /* Bit 19: B-Session valid interrupt status */
#define USBOTG_OTGSC_ASVIS (1 << 18) /* Bit 18: A-Session valid interrupt status */
#define USBOTG_OTGSC_AVVIS (1 << 17) /* Bit 17: A-VBUS valid interrupt status */
#define USBOTG_OTGSC_IDIS (1 << 16) /* Bit 16: USB ID interrupt status */
/* OTG status inputs */
#define USBOTG_OTGSC_DPS (1 << 14) /* Bit 14: Data bus pulsing status */
#define USBOTG_OTGSC_1MST (1 << 13) /* Bit 13: 1 millisecond timer toggle */
#define USBOTG_OTGSC_BSE (1 << 12) /* Bit 12: B-session end */
#define USBOTG_OTGSC_BSV (1 << 11) /* Bit 11: B-session valid */
#define USBOTG_OTGSC_ASV (1 << 10) /* Bit 10: A-session valid */
#define USBOTG_OTGSC_AVV (1 << 9) /* Bit 9: A-VBUS valid */
#define USBOTG_OTGSC_ID (1 << 8) /* Bit 8: USB ID */
/* OTG controls */
#define USBOTG_OTGSC_HABA (1 << 7) /* Bit 7: Hardware assist B-disconnect to A-connect */
#define USBOTG_OTGSC_HADP (1 << 6) /* Bit 6: Hardware assist data pulse */
#define USBOTG_OTGSC_IDPU (1 << 5) /* Bit 5: ID pull-up */
#define USBOTG_OTGSC_DP (1 << 4) /* Bit 4: Data pulsing */
#define USBOTG_OTGSC_OT (1 << 3) /* Bit 3: OTG termination */
#define USBOTG_OTGSC_HAAR (1 << 2) /* Bit 2: Hardware assist auto_reset */
#define USBOTG_OTGSC_VC (1 << 1) /* Bit 1: VBUS_Charge */
#define USBOTG_OTGSC_VD (1 << 0) /* Bit 0: VBUS_Discharge */
/* USB Mode register USBMODE -- Device Mode */
#define USBDEV_USBMODE_SDIS (1 << 4) /* Bit 4: Stream disable mode */
#define USBDEV_USBMODE_SLOM (1 << 3) /* Bit 3: Setup Lockout mode */
#define USBDEV_USBMODE_ES (1 << 2) /* Bit 2: Endian select */
#define USBDEV_USBMODE_CM_SHIFT (0) /* Bits 0-1: Controller mode */
#define USBDEV_USBMODE_CM_MASK (3 << USBDEV_USBMODE_CM_SHIFT)
# define USBDEV_USBMODE_CM_IDLE (0 << USBDEV_USBMODE_CM_SHIFT) /* Idle */
# define USBDEV_USBMODE_CM_DEVICE (2 << USBDEV_USBMODE_CM_SHIFT) /* Device controller */
# define USBDEV_USBMODE_CM_HOST (3 << USBDEV_USBMODE_CM_SHIFT) /* Host controller */
/* USB Mode register USBMODE -- Device Mode */
#define USBHOST_USBMODE_VBPS (1 << 5) /* Bit 5: VBUS power select */
#define USBHOST_USBMODE_SDIS (1 << 4) /* Bit 4: Stream disable mode */
#define USBHOST_USBMODE_ES (1 << 2) /* Bit 2: Endian select */
#define USBHOST_USBMODE_CM_SHIFT (0) /* Bits 0-1: Controller mode */
#define USBHOST_USBMODE_CM_MASK (3 << USBHOST_USBMODE_CM_SHIFT)
# define USBHOST_USBMODE_CM_IDLE (0 << USBHOST_USBMODE_CM_SHIFT) /* Idle */
# define USBHOST_USBMODE_CM_DEVICE (2 << USBHOST_USBMODE_CM_SHIFT) /* Device controller */
# define USBHOST_USBMODE_CM_HOST (3 << USBHOST_USBMODE_CM_SHIFT) /* Host controller */
/* Device endpoint registers */
/* USB Endpoint Setup Status register ENDPTSETUPSTAT */
#define USBDEV_ENDPTSETSTAT_STAT15 (1 << 15) /* Bit 15: Setup EP status for logical EP 15 */
#define USBDEV_ENDPTSETSTAT_STAT14 (1 << 14) /* Bit 14: Setup EP status for logical EP 14 */
#define USBDEV_ENDPTSETSTAT_STAT13 (1 << 13) /* Bit 13: Setup EP status for logical EP 13 */
#define USBDEV_ENDPTSETSTAT_STAT12 (1 << 12) /* Bit 12: Setup EP status for logical EP 12 */
#define USBDEV_ENDPTSETSTAT_STAT11 (1 << 11) /* Bit 11: Setup EP status for logical EP 11 */
#define USBDEV_ENDPTSETSTAT_STAT10 (1 << 10) /* Bit 10: Setup EP status for logical EP 10 */
#define USBDEV_ENDPTSETSTAT_STAT9 (1 << 9) /* Bit 9: Setup EP status for logical EP 9 */
#define USBDEV_ENDPTSETSTAT_STAT8 (1 << 8) /* Bit 8: Setup EP status for logical EP 8 */
#define USBDEV_ENDPTSETSTAT_STAT7 (1 << 7) /* Bit 7: Setup EP status for logical EP 7 */
#define USBDEV_ENDPTSETSTAT_STAT6 (1 << 6) /* Bit 6: Setup EP status for logical EP 6 */
#define USBDEV_ENDPTSETSTAT_STAT5 (1 << 5) /* Bit 5: Setup EP status for logical EP 5 */
#define USBDEV_ENDPTSETSTAT_STAT4 (1 << 4) /* Bit 4: Setup EP status for logical EP 4 */
#define USBDEV_ENDPTSETSTAT_STAT3 (1 << 3) /* Bit 3: Setup EP status for logical EP 3 */
#define USBDEV_ENDPTSETSTAT_STAT2 (1 << 2) /* Bit 2: Setup EP status for logical EP 2 */
#define USBDEV_ENDPTSETSTAT_STAT1 (1 << 1) /* Bit 1: Setup EP status for logical EP 1 */
#define USBDEV_ENDPTSETSTAT_STAT0 (1 << 0) /* Bit 0: Setup EP status for logical EP 0 */
/* USB Endpoint Prime register ENDPTPRIME */
#define USBDEV_ENDPTPRIM_PETB7 (1 << 23) /* Bit 23: Prime EP xmt buffer for physical IN EP 7 */
#define USBDEV_ENDPTPRIM_PETB6 (1 << 22) /* Bit 22: Prime EP xmt buffer for physical IN EP 6 */
#define USBDEV_ENDPTPRIM_PETB5 (1 << 21) /* Bit 21: Prime EP xmt buffer for physical IN EP 5 */
#define USBDEV_ENDPTPRIM_PETB4 (1 << 20) /* Bit 20: Prime EP xmt buffer for physical IN EP 4 */
#define USBDEV_ENDPTPRIM_PETB3 (1 << 19) /* Bit 19: Prime EP xmt buffer for physical IN EP 3 */
#define USBDEV_ENDPTPRIM_PETB2 (1 << 18) /* Bit 18: Prime EP xmt buffer for physical IN EP 2 */
#define USBDEV_ENDPTPRIM_PETB1 (1 << 17) /* Bit 17: Prime EP xmt buffer for physical IN EP 1 */
#define USBDEV_ENDPTPRIM_PETB0 (1 << 16) /* Bit 16: Prime EP xmt buffer for physical IN EP 0 */
#define USBDEV_ENDPTPRIM_PERB7 (1 << 7) /* Bit 7: Prime EP recv buffer for physical OUT EP 7 */
#define USBDEV_ENDPTPRIM_PERB6 (1 << 6) /* Bit 6: Prime EP recv buffer for physical OUT EP 6 */
#define USBDEV_ENDPTPRIM_PERB5 (1 << 5) /* Bit 5: Prime EP recv buffer for physical OUT EP 5 */
#define USBDEV_ENDPTPRIM_PERB4 (1 << 4) /* Bit 4: Prime EP recv buffer for physical OUT EP 4 */
#define USBDEV_ENDPTPRIM_PERB3 (1 << 3) /* Bit 3: Prime EP recv buffer for physical OUT EP 3 */
#define USBDEV_ENDPTPRIM_PERB2 (1 << 2) /* Bit 2: Prime EP recv buffer for physical OUT EP 2 */
#define USBDEV_ENDPTPRIM_PERB1 (1 << 1) /* Bit 1: Prime EP recv buffer for physical OUT EP 1 */
#define USBDEV_ENDPTPRIM_PERB0 (1 << 0) /* Bit 0: Prime EP recv buffer for physical OUT EP 0 */
/* USB Endpoint Flush register ENDPTFLUSH */
#define USBDEV_ENDPTFLUSH_FETB7 (1 << 23) /* Bit 23: Flush EP xmt buffer for physical IN EP 7 */
#define USBDEV_ENDPTFLUSH_FETB6 (1 << 22) /* Bit 22: Flush EP xmt buffer for physical IN EP 6 */
#define USBDEV_ENDPTFLUSH_FETB5 (1 << 21) /* Bit 21: Flush EP xmt buffer for physical IN EP 5 */
#define USBDEV_ENDPTFLUSH_FETB4 (1 << 20) /* Bit 20: Flush EP xmt buffer for physical IN EP 4 */
#define USBDEV_ENDPTFLUSH_FETB3 (1 << 19) /* Bit 19: Flush EP xmt buffer for physical IN EP 3 */
#define USBDEV_ENDPTFLUSH_FETB2 (1 << 18) /* Bit 18: Flush EP xmt buffer for physical IN EP 2 */
#define USBDEV_ENDPTFLUSH_FETB1 (1 << 17) /* Bit 17: Flush EP xmt buffer for physical IN EP 1 */
#define USBDEV_ENDPTFLUSH_FETB0 (1 << 16) /* Bit 16: Flush EP xmt buffer for physical IN EP 0 */
#define USBDEV_ENDPTFLUSH_FERB7 (1 << 7) /* Bit 7: Flush EP recv buffer for physical OUT EP 7 */
#define USBDEV_ENDPTFLUSH_FERB6 (1 << 6) /* Bit 6: Flush EP recv buffer for physical OUT EP 6 */
#define USBDEV_ENDPTFLUSH_FERB5 (1 << 5) /* Bit 5: Flush EP recv buffer for physical OUT EP 5 */
#define USBDEV_ENDPTFLUSH_FERB4 (1 << 4) /* Bit 4: Flush EP recv buffer for physical OUT EP 4 */
#define USBDEV_ENDPTFLUSH_FERB3 (1 << 3) /* Bit 3: Flush EP recv buffer for physical OUT EP 3 */
#define USBDEV_ENDPTFLUSH_FERB2 (1 << 2) /* Bit 2: Flush EP recv buffer for physical OUT EP 2 */
#define USBDEV_ENDPTFLUSH_FERB1 (1 << 1) /* Bit 1: Flush EP recv buffer for physical OUT EP 1 */
#define USBDEV_ENDPTFLUSH_FERB0 (1 << 0) /* Bit 0: Flush EP recv buffer for physical OUT EP 0 */
/* USB Endpoint Status register ENDPTSTATUS */
#define USBDEV_ENDPTSTATUS_ETBR7 (1 << 23) /* Bit 23: EP xmt buffer ready for physical IN EP 7 */
#define USBDEV_ENDPTSTATUS_ETBR6 (1 << 22) /* Bit 22: EP xmt buffer ready for physical IN EP 6 */
#define USBDEV_ENDPTSTATUS_ETBR5 (1 << 21) /* Bit 21: EP xmt buffer ready for physical IN EP 5 */
#define USBDEV_ENDPTSTATUS_ETBR4 (1 << 20) /* Bit 20: EP xmt buffer ready for physical IN EP 4 */
#define USBDEV_ENDPTSTATUS_ETBR3 (1 << 19) /* Bit 19: EP xmt buffer ready for physical IN EP 3 */
#define USBDEV_ENDPTSTATUS_ETBR2 (1 << 18) /* Bit 18: EP xmt buffer ready for physical IN EP 2 */
#define USBDEV_ENDPTSTATUS_ETBR1 (1 << 17) /* Bit 17: EP xmt buffer ready for physical IN EP 1 */
#define USBDEV_ENDPTSTATUS_ETBR0 (1 << 16) /* Bit 16: EP xmt buffer ready for physical IN EP 0 */
#define USBDEV_ENDPTSTATUS_ERBR7 (1 << 7) /* Bit 7: EP recv buffer ready for physical OUT EP 7 */
#define USBDEV_ENDPTSTATUS_ERBR6 (1 << 6) /* Bit 6: EP recv buffer ready for physical OUT EP 6 */
#define USBDEV_ENDPTSTATUS_ERBR5 (1 << 5) /* Bit 5: EP recv buffer ready for physical OUT EP 5 */
#define USBDEV_ENDPTSTATUS_ERBR4 (1 << 4) /* Bit 4: EP recv buffer ready for physical OUT EP 4 */
#define USBDEV_ENDPTSTATUS_ERBR3 (1 << 3) /* Bit 3: EP recv buffer ready for physical OUT EP 3 */
#define USBDEV_ENDPTSTATUS_ERBR2 (1 << 2) /* Bit 2: EP recv buffer ready for physical OUT EP 2 */
#define USBDEV_ENDPTSTATUS_ERBR1 (1 << 1) /* Bit 1: EP recv buffer ready for physical OUT EP 1 */
#define USBDEV_ENDPTSTATUS_ERBR0 (1 << 0) /* Bit 0: EP recv buffer ready for physical OUT EP 0 */
/* USB Endpoint Complete register ENDPTCOMPLETE */
#define USBDEV_ENDPTCOMPLETE_ETCE7 (1 << 23) /* Bit 23: EP xmt complete event for physical IN EP 7 */
#define USBDEV_ENDPTCOMPLETE_ETCE6 (1 << 22) /* Bit 22: EP xmt complete event for physical IN EP 6 */
#define USBDEV_ENDPTCOMPLETE_ETCE5 (1 << 21) /* Bit 21: EP xmt complete event for physical IN EP 5 */
#define USBDEV_ENDPTCOMPLETE_ETCE4 (1 << 20) /* Bit 20: EP xmt complete event for physical IN EP 4 */
#define USBDEV_ENDPTCOMPLETE_ETCE3 (1 << 19) /* Bit 19: EP xmt complete event for physical IN EP 3 */
#define USBDEV_ENDPTCOMPLETE_ETCE2 (1 << 18) /* Bit 18: EP xmt complete event for physical IN EP 2 */
#define USBDEV_ENDPTCOMPLETE_ETCE1 (1 << 17) /* Bit 17: EP xmt complete event for physical IN EP 1 */
#define USBDEV_ENDPTCOMPLETE_ETCE0 (1 << 16) /* Bit 16: EP xmt complete event for physical IN EP 0 */
#define USBDEV_ENDPTCOMPLETE_ERCE7 (1 << 7) /* Bit 7: EP recv complete event for physical OUT EP 7 */
#define USBDEV_ENDPTCOMPLETE_ERCE6 (1 << 6) /* Bit 6: EP recv complete event for physical OUT EP 6 */
#define USBDEV_ENDPTCOMPLETE_ERCE5 (1 << 5) /* Bit 5: EP recv complete event for physical OUT EP 5 */
#define USBDEV_ENDPTCOMPLETE_ERCE4 (1 << 4) /* Bit 4: EP recv complete event for physical OUT EP 4 */
#define USBDEV_ENDPTCOMPLETE_ERCE3 (1 << 3) /* Bit 3: EP recv complete event for physical OUT EP 3 */
#define USBDEV_ENDPTCOMPLETE_ERCE2 (1 << 2) /* Bit 2: EP recv complete event for physical OUT EP 2 */
#define USBDEV_ENDPTCOMPLETE_ERCE1 (1 << 1) /* Bit 1: EP recv complete event for physical OUT EP 1 */
#define USBDEV_ENDPTCOMPLETE_ERCE0 (1 << 0) /* Bit 0: EP recv complete event for physical OUT EP 0 */
/* USB Endpoint 0 Control register ENDPTCTRL0 */
#define USBDEV_ENDPTCTRL0_TXE (1 << 23) /* Bit 23: Tx endpoint enable */
#define USBDEV_ENDPTCTRL0_TXT_SHIFT (18) /* Bits 18-19: Tx endpoint type */
#define USBDEV_ENDPTCTRL0_TXT_MASK (3 << USBDEV_ENDPTCTRL0_TXT_SHIFT)
# define USBDEV_ENDPTCTRL0_TXT_CTRL (0 << USBDEV_ENDPTCTRL0_TXT_SHIFT) /* Control */
#define USBDEV_ENDPTCTRL0_TXS (1 << 16) /* Bit 16: Tx endpoint stall */
#define USBDEV_ENDPTCTRL0_RXE (1 << 7) /* Bit 7: Rx endpoint enable */
#define USBDEV_ENDPTCTRL0_RXT_SHIFT (2) /* Bits 2-3: Endpoint type */
#define USBDEV_ENDPTCTR0L_RXT_MASK (3 << USBDEV_ENDPTCTRL0_RXT_SHIFT)
# define USBDEV_ENDPTCTRL0_RXT_CTRL (0 << USBDEV_ENDPTCTRL0_RXT_SHIFT) /* Control */
#define USBDEV_ENDPTCTRL0_RXS (1 << 0) /* Bit 0: Rx endpoint stall */
/* USB Endpoint 1-7 control registers ENDPTCTRL1-ENDPPTCTRL7 */
#define USBDEV_ENDPTCTRL_TXE (1 << 23) /* Bit 23: Tx endpoint enable */
#define USBDEV_ENDPTCTRL_TXR (1 << 22) /* Bit 22: Tx data toggle reset */
#define USBDEV_ENDPTCTRL_TXI (1 << 21) /* Bit 21: Tx data toggle inhibit */
#define USBDEV_ENDPTCTRL_TXT_SHIFT (18) /* Bits 18-19: Tx endpoint type */
#define USBDEV_ENDPTCTRL_TXT_MASK (3 << USBDEV_ENDPTCTRL_TXT_SHIFT)
# define USBDEV_ENDPTCTRL_TXT_CTRL (0 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Control */
# define USBDEV_ENDPTCTRL_TXT_ISOC (1 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Isochronous */
# define USBDEV_ENDPTCTRL_TXT_BULK (2 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Bulk */
# define USBDEV_ENDPTCTRL_TXT_INTR (3 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Interrupt */
#define USBDEV_ENDPTCTRL_TXS (1 << 16) /* Bit 16: Tx endpoint stall */
#define USBDEV_ENDPTCTRL_RXE (1 << 7) /* Bit 7: Rx endpoint enable */
#define USBDEV_ENDPTCTRL_RXR (1 << 6) /* Bit 6: Rx data toggle reset */
#define USBDEV_ENDPTCTRL_RXI (1 << 5) /* Bit 5: Rx data toggle inhibit */
#define USBDEV_ENDPTCTRL_RXT_SHIFT (2) /* Bits 2-3: Endpoint type */
#define USBDEV_ENDPTCTRL_RXT_MASK (3 << USBDEV_ENDPTCTRL_RXT_SHIFT)
# define USBDEV_ENDPTCTRL_RXT_CTRL (0 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Control */
# define USBDEV_ENDPTCTRL_RXT_ISOC (1 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Isochronous */
# define USBDEV_ENDPTCTRL_RXT_BULK (2 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Bulk */
# define USBDEV_ENDPTCTRL_RXT_INTR (3 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Interrupt */
#define USBDEV_ENDPTCTRL_RXS (1 << 0) /* Bit 0: Rx endpoint stall */
/* Device non-core registers */
/* USB OTG Control register */
/* Bits 0-6:
* Reserved
*/
#define USBNC_OVER_CUR_DIS (1 << 7) /* Bit 7: Disable Over current detection */
#define USBNC_OVER_CUR_POL (1 << 8) /* Bit 8: Polarity of over current */
#define USBNC_PWR_POL (1 << 9) /* Bit 9: Power polarity */
#define USBNC_WIE (1<< 10) /* Bit 10: Wake up interrupt enable */
/* Bit 11-13: Reserved */
#define USBNC_WKUP_SW_EN (1 << 14) /* Bit 14: Software wake up enable */
#define USBNC_WKUP_SW (1 << 15) /* Bit 15: Software wake up */
#define USBNC_WKUP_ID_EN (1 << 16) /* Bit 16: Wakeup on ID change enable */
#define USBNC_WKUP_VBUS_EN (1 << 17) /* Bit 17: Wakeup on VBUS change enable */
/* Bit 18-28: Reserved */
#define USBNC_WKUP_DPDM_EN (1 << 29) /* Bit 29: Wakeup on DPDM change enable */
/* Bit 30: Reserved */
#define USBNC_WIR (1 << 31) /* Bit 31: Wake up interrupt request */
#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USBOTG_H */

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/****************************************************************************
* arch/arm/src/imxrt/hardware/imxrt_usbphy.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USB_PHY_H
#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USB_PHY_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imxrt_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define IMXRT_USBPHY_BASE_OFFSET 0x1000 /* USB PHY Base */
#define IMXRT_USBPHY_BASE (IMXRT_ANATOP_BASE + IMXRT_USBPHY_BASE_OFFSET) /* USB PHY Base */
/* Register Offsets *********************************************************/
#define IMXRT_USBPHY1_PWD_OFFSET 0x0000 /* USBPHY1 USB PHY Power-Down Register */
#define IMXRT_USBPHY1_PWD_CLR_OFFSET 0x0008 /* USBPHY1 USB PHY Power-Down Register Clear */
#define IMXRT_USBPHY1_CTRL_OFFSET 0x0030 /* USBPHY1 USB PHY General Control Register */
#define IMXRT_USBPHY1_CTRL_CLR_OFFSET 0x0038 /* USBPHY1 USB PHY General Control Register Clear */
/* Register addresses *******************************************************/
#define IMXRT_USBPHY1_PWD (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_PWD_OFFSET) /* USBPHY1 USB PHY Power-Down Register */
#define IMXRT_USBPHY1_PWD_CLR (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_PWD_CLR_OFFSET) /* USBPHY1 USB PHY Power-Down Register Clear */
#define IMXRT_USBPHY1_CTRL (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_CTRL_OFFSET) /* USBPHY1 USB PHY General Control Register */
#define IMXRT_USBPHY1_CTRL_CLR (IMXRT_USBPHY_BASE + IMXRT_USBPHY1_CTRL_CLR_OFFSET) /* USBPHY1 USB PHY General Control Register Clear */
/* Register Bit Definitions *************************************************/
/* USB PHY Power-Down Register */
#define USBPHY_PWD_RXPWDRX (1 << 20) /* Bit 20: Power-down the entire USB PHY receiver block except for the full-speed differential receiver. */
#define USBPHY_PWD_RXPWDDIFF (1 << 19) /* Bit 19: Power-down the USB high-speed differential receiver. */
#define USBPHY_PWD_RXPWD1PT1 (1 << 18) /* Bit 18: Power-down the USB full-speed differential receiver. */
#define USBPHY_PWD_RXPWDENV (1 << 17) /* Bit 17: Power-down the USB high-speed receiver envelope detector (squelch signal). */
#define USBPHY_PWD_TXPWDV2I (1 << 12) /* Bit 12: Power-down the USB PHY transmit V-to-I converter and the current mirror. */
#define USBPHY_PWD_TXPWDIBIAS (1 << 11) /* Bit 11: Power-down the USB PHY current bias block for the transmitter. */
#define USBPHY_PWD_TXPWDFS (1 << 10) /* Bit 10: Power-down the USB full-speed drivers. */
/* USB PHY General Control Register */
#define USBPHY_CTRL_SFTRST (1 << 31) /* Bit 31: Soft-reset */
#define USBPHY_CTRL_CLKGATE (1 << 30) /* Bit 30: Gate UTMI clocks */
#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT_USB_PHY_H */

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/****************************************************************************
* arch/arm/src/imxrt/hardware/rt105x/imxrt105x_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_MEMORYMAP_H
#define __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_MEMORYMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* System memory map */
#define IMXRT_ITCM_BASE 0x00000000 /* 512KB ITCM */
/* 0x00080000 512KB ITCM Reserved */
/* 0x00100000 1MB ITCM Reserved */
#define IMXRT_ROMCP_BASE 0x00200000 /* 96KB ROMCP */
/* 0x00218000 416KB ROMCP Reserved */
/* 0x00280000 1536KB Reserved */
/* 0x00400000 124MB Reserved */
#define IMXRT_FLEXSPI_BASE 0x08000000 /* 128MB FlexSPI (Aliased) */
#define IMXRT_SEMCA_BASE 0x10000000 /* 256MB SEMC (Aliased) */
#define IMXRT_DTCM_BASE 0x20000000 /* 512KB DTCM */
/* 0x20080000 512KB DTCM Reserved */
/* 0x20100000 1MB Reserved */
#define IMXRT_OCRAM_BASE 0x20200000 /* 512KB OCRAM */
/* 0x20280000 1536KB OCRAM Reserved */
/* 0x20400000 252MB Reserved */
/* 0x30000000 256MB Reserved */
#define IMXRT_AIPS1_BASE 0x40000000 /* 1MB AIPS-1 */
#define IMXRT_AIPS2_BASE 0x40100000 /* 1MB AIPS-2 */
#define IMXRT_AIPS3_BASE 0x40200000 /* 1MB AIPS-3 */
#define IMXRT_AIPS4_BASE 0x40300000 /* 1MB AIPS-4 */
/* 40400000 12MB Reserved */
#define IMXRT_MAINCNF_BASE 0x41000000 /* 1MB "main" configuration port */
#define IMXRT_MCNF_BASE 0x41100000 /* 1MB "m" configuration port */
/* 41200000 1MB Reserved for "per" GPV */
/* 41300000 1MB Reserved for "ems" GPV */
#define IMXRT_CPUCNF_BASE 0x41400000 /* 1MB "cpu" configuration port */
/* 0x41500000 1MB GPV Reserved */
/* 0x41600000 1MB GPV Reserved */
/* 0x41700000 1MB GPV Reserved */
/* 0x41800000 8MB Reserved */
/* 0x42000000 32MB Reserved */
/* 0x44000000 64MB Reserved */
/* 0x48000000 384MB Reserved */
#define IMXRT_FLEXCIPHER_BASE 0x60000000 /* 504MB FlexSPI/ FlexSPI ciphertext */
#define IMXRT_FLEXSPITX_BASE 0x7f800000 /* 4MB FlexSPI TX FIFO */
#define IMXRT_FLEXSPIRX_BASE 0x7fc00000 /* 4MB FlexSPI RX FIFO */
#define IMXRT_EXTMEM_BASE 0x80000000 /* 1.5GB SEMC external memories shared memory space */
#define IMXRT_CM7_BASE 0xe0000000 /* 1MB CM7 PPB */
/* 0xe0100000 511MB Reserved */
/* AIPS-1 memory map */
/* 0x40000000 256KB Reserved */
/* 0x40040000 240KB Reserved */
#define IMXRT_AIPS1CNF_BASE 0x4007c000 /* 6KB AIPS-1 Configuration */
#define IMXRT_DCDC_BASE 0x40080000 /* 16KB DCDC */
#define IMXRT_PIT_BASE 0x40084000 /* 16KB PIT */
/* 0x40088000 16KB Reserved */
/* 0x4008c000 16KB Reserved */
#define IMXRT_MTR_BASE 0x40090000 /* 16KB MTR */
#define IMXRT_ACMP_BASE 0x40094000 /* 16KB ACMP */
/* 0x40098000 16KB Reserved */
/* 0x4009c000 16KB Reserved */
/* 0x400a0000 16KB Reserved */
#define IMXRT_IOMUXCSNVSGPR_BASE 0x400a4000 /* 16KB IOMUXC_SNVS_GPR */
#define IMXRT_IOMUXCSNVS_BASE 0x400a8000 /* 16KB IOMUXC_SNVS */
#define IMXRT_IOMUXCGPR_BASE 0x400ac000 /* 16KB IOMUXC_GPR */
#define IMXRT_FLEXRAM_BASE 0x400b0000 /* 16KB CM7_MX6RT(FLEXRAM) */
#define IMXRT_EWM_BASE 0x400b4000 /* 16KB EWM */
#define IMXRT_WDOG1_BASE 0x400b8000 /* 16KB WDOG1 */
#define IMXRT_WDOG3_BASE 0x400bc000 /* 16KB WDOG3 */
#define IMXRT_GPIO5_BASE 0x400c0000 /* 16KB GPIO5 */
#define IMXRT_ADC1_BASE 0x400c4000 /* 16KB ADC1 */
#define IMXRT_ADC2_BASE 0x400c8000 /* 16KB ADC2 */
#define IMXRT_TRNG_BASE 0x400cc000 /* 16KB TRNG */
#define IMXRT_WDOG2_BASE 0x400d0000 /* 16KB WDOG2 */
#define IMXRT_SNVSHP_BASE 0x400d4000 /* 16KB SNVS_HP */
#define IMXRT_ANATOP_BASE 0x400d8000 /* 16KB ANATOP */
#define IMXRT_CSU_BASE 0x400dc000 /* 16KB CSU */
/* 0x400e0000 16KB Reserved */
/* 0x400e4000 16KB Reserved */
#define IMXRT_EDMA_BASE 0x400e8000 /* 16KB EDMA */
#define IMXRT_DMAMUX_BASE 0x400ec000 /* 16KB DMA_CH_MUX */
/* 400f0000 16KB Reserved */
#define IMXRT_GPC_BASE 0x400f4000 /* 16KB GPC */
#define IMXRT_SRC_BASE 0x400f8000 /* 16KB SRC */
#define IMXRT_CCM_BASE 0x400fc000 /* 16KB CCM */
/* AIPS-2 memory map */
/* 0x40100000 256KB Reserved */
/* 0x40140000 240KB Reserved */
#define IMXRT_AIPS2CNF_BASE 0x4017c000 /* 16KB AIPS-2 Configuration */
#define IMXRT_ROMCPC_BASE 0x40180000 /* 16KB ROMCP controller*/
#define IMXRT_LPUART1_BASE 0x40184000 /* 16KB LPUART1 */
#define IMXRT_LPUART2_BASE 0x40188000 /* 16KB LPUART2 */
#define IMXRT_LPUART3_BASE 0x4018c000 /* 16KB LPUART3 */
#define IMXRT_LPUART4_BASE 0x40190000 /* 16KB LPUART4 */
#define IMXRT_LPUART5_BASE 0x40194000 /* 16KB LPUART5 */
#define IMXRT_LPUART6_BASE 0x40198000 /* 16KB LPUART6 */
#define IMXRT_LPUART7_BASE 0x4019c000 /* 16KB LPUART7 */
#define IMXRT_LPUART8_BASE 0x401a0000 /* 16KB LPUART8 */
/* 0x401a4000 16KB Reserved */
/* 0x401a8000 16KB Reserved */
#define IMXRT_FLEXIO1_BASE 0x401ac000 /* 16KB FlexIO1 */
#define IMXRT_FLEXIO2_BASE 0x401b0000 /* 16KB FlexIO2 */
/* 0x401b4000 16KB Reserved */
#define IMXRT_GPIO1_BASE 0x401b8000 /* 16KB GPIO1 */
#define IMXRT_GPIO2_BASE 0x401bc000 /* 16KB GPIO2 */
#define IMXRT_GPIO3_BASE 0x401c0000 /* 16KB GPIO3 */
#define IMXRT_GPIO4_BASE 0x401c4000 /* 16KB GPIO4 */
/* 0x401c8000 16KB Reserved */
/* 0x401cc000 16KB Reserved */
#define IMXRT_CAN1_BASE 0x401d0000 /* 16KB CAN1 */
#define IMXRT_CAN2_BASE 0x401d4000 /* 16KB CAN2 */
/* 0x401d8000 16KB Reserved */
#define IMXRT_QTIMER1_BASE 0x401dc000 /* 16KB QTimer1 */
#define IMXRT_QTIMER2_BASE 0x401e0000 /* 16KB QTimer2 */
#define IMXRT_QTIMER3_BASE 0x401e4000 /* 16KB QTimer3 */
#define IMXRT_QTIMER4_BASE 0x401e8000 /* 16KB QTimer4 */
#define IMXRT_GPT1_BASE 0x401ec000 /* 16KB GPT1 */
#define IMXRT_GPT2_BASE 0x401f0000 /* 16KB GPT2 */
#define IMXRT_OCOTP_BASE 0x401f4000 /* 16KB OCOTP */
#define IMXRT_IOMUXC_BASE 0x401f8000 /* 16KB IOMUXC */
#define IMXRT_KPP_BASE 0x401fc000 /* 16KB KPP */
/* AIPS-3 memory map */
/* 0x40200000 256KB Reserved */
/* 0x40240000 240KB Reserved */
#define IMXRT_AIOS3CNF_BASE 0x4027c000 /* 16KB AIPS-3 Configuration */
/* 0x40280000 16KB Reserved */
/* 0x40284000 16KB Reserved */
/* 0x40288000 16KB Reserved */
/* 0x4028c000 16KB Reserved */
/* 0x40290000 16KB Reserved */
/* 0x40294000 16KB Reserved */
/* 0x40298000 16KB Reserved */
/* 0x4029c000 16KB Reserved */
/* 0x402a0000 16KB Reserved */
/* 0x402a4000 16KB Reserved */
#define IMXRT_FLEXSPIC_BASE 0x402a8000 /* 16KB FlexSPI controller */
/* 0x402ac000 16KB Reserved */
/* 0x402b0000 16KB Reserved */
#define IMXRT_PXP_BASE 0x402b4000 /* 16KB PXP */
#define IMXRT_LCDIF_BASE 0x402b8000 /* 16KB LCDIF */
#define IMXRT_CSI_BASE 0x402bc000 /* 16KB CSI */
#define IMXRT_USDHC1_BASE 0x402c0000 /* 16KB USDHC1 */
#define IMXRT_USDHC2_BASE 0x402c4000 /* 16KB USDHC2 */
/* 0x402c8000 16KB Reserved */
/* 0x402cc000 16KB Reserved */
/* 0x402d0000 16KB Reserved */
/* 0x402d4000 16KB Reserved */
#define IMXRT_ENET_BASE 0x402d8000 /* 16KB ENET */
#define IMXRT_USBPL301_BASE 0x402dc000 /* 16KB USB(PL301) */
#define IMXRT_USB_BASE 0x402e0000 /* 16KB USB(USB) */
/* 0x402e4000 16KB Reserved */
/* 0x402e8000 16KB Reserved */
/* 0x402ec000 16KB Reserved */
#define IMXRT_SEMC_BASE 0x402f0000 /* 16KB SEMC */
/* 0x402f4000 16KB Reserved */
/* 0x402f8000 16KB Reserved */
#define IMXRT_DCP_BASE 0x402fc000 /* 16KB DCP */
/* AIPS-4 memory map */
/* 0x40300000 256KB Reserved */
/* 0x40340000 240KB Reserved */
#define IMXRT_AIPS4CNF_BASE 0x4037c000 /* 16KB AIPS-4 Configuration */
#define IMXRT_SPDIF_BASE 0x40380000 /* 16KB SPDIF */
#define IMXRT_SAI1_BASE 0x40384000 /* 16KB SAI1 */
#define IMXRT_SAI2_BASE 0x40388000 /* 16KB SAI2 */
#define IMXRT_SAI3_BASE 0x4038c000 /* 16KB SAI3 */
/* 0x40390000 16KB Reserved */
#define IMXRT_LPSPI1_BASE 0x40394000 /* 16KB LPSPI1 */
#define IMXRT_LPSPI2_BASE 0x40398000 /* 16KB LPSPI2 */
#define IMXRT_LPSPI3_BASE 0x4039c000 /* 16KB LPSPI3 */
#define IMXRT_LPSPI4_BASE 0x403a0000 /* 16KB LPSPI4 */
/* 0x403a4000 16KB Reserved */
/* 0x403a8000 16KB Reserved */
/* 0x403ac000 16KB Reserved */
#define IMXRT_ADCETC_BASE 0x403b0000 /* 16KB ADC_ETC */
#define IMXRT_AOI1_BASE 0x403b4000 /* 16KB AOI1 */
#define IMXRT_AOI2_BASE 0x403b8000 /* 16KB AOI2 */
#define IMXRT_XBAR1_BASE 0x403bc000 /* 16KB XBAR1 */
#define IMXRT_XBAR2_BASE 0x403c0000 /* 16KB XBAR2 */
#define IMXRT_XBAR3_BASE 0x403c4000 /* 16KB XBAR3 */
#define IMXRT_ENC1_BASE 0x403c8000 /* 16KB ENC1 */
#define IMXRT_ENC2_BASE 0x403cc000 /* 16KB ENC2 */
#define IMXRT_ENC3_BASE 0x403d0000 /* 16KB ENC3 */
#define IMXRT_ENC4_BASE 0x403d4000 /* 16KB ENC4 */
/* 0x403d8000 16KB Reserved */
#define IMXRT_FLEXPWM1_BASE 0x403dc000 /* 16KB FLEXPWM1 */
#define IMXRT_FLEXPWM2_BASE 0x403e0000 /* 16KB FLEXPWM2 */
#define IMXRT_FLEXPWM3_BASE 0x403e4000 /* 16KB FLEXPWM3 */
#define IMXRT_FLEXPWM4_BASE 0x403e8000 /* 16KB FLEXPWM4 */
#define IMXRT_BEE_BASE 0x403ec000 /* 16KB BEE */
#define IMXRT_LPI2C1_BASE 0x403f0000 /* 16KB */
#define IMXRT_LPI2C2_BASE 0x403f4000 /* 16KB LPI2C2 */
#define IMXRT_LPI2C3_BASE 0x403f8000 /* 16KB LPI2C3 */
#define IMXRT_LPI2C4_BASE 0x403fc000 /* 16KB LPI2C4 */
/* PPB memory map */
#define IMXRT_TPIU_BASE 0xe0040000 /* 4KB TPIU */
#define IMXRT_ETM_BASE 0xe0041000 /* 4KB ETM */
#define IMXRT_CTI_BASE 0xe0042000 /* 4KB CTI */
#define IMXRT_TSGEN_BASE 0xe0043000 /* 4KB TSGEN */
#define IMXRT_PPBRES_BASE 0xe0044000 /* 4KB PPB RES */
/* 0xe0045000 236KB PPB Reserved */
#define IMXRT_MCM_BASE 0xe0080000 /* 4KB MCM */
/* 0xe0081000 444KB PPB Reserved */
/* 0xe00f0000 52KB PPB Reserved */
#define IMXRT_SYSROM_BASE 0xe00fd000 /* 4KB SYS ROM */
#define IMXRT_PROCROM_BASE 0xe00fe000 /* 4KB Processor ROM */
#define IMXRT_PPBROM_BASE 0xe00ff000 /* 4KB PPB ROM */
#endif /* __ARCH_ARM_SRC_IMXRT_HARDWARE_IMXRT105X_MEMORYMAP_H */

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/****************************************************************************
* arch/arm/src/imxrt/imxrt_clockconfig.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_arch.h"
#include <arch/board/board.h>
#include "hardware/imxrt_ccm.h"
#include "hardware/imxrt_dcdc.h"
#include "imxrt_clockconfig.h"
#include "imxrt_lcd.h"
#include "hardware/imxrt_memorymap.h"
#include "hardware/imxrt_iomuxc.h"
#include <stdlib.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define VIDEO_PLL_MIN_FREQ 650000000
#define OSC24_FREQ 24000000
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_lcd_clockconfig
****************************************************************************/
#ifdef CONFIG_IMXRT_LCD
static void imxrt_lcd_clockconfig(void)
{
uint32_t reg;
uint32_t reg2;
int post;
int pre;
uint32_t numerator;
uint32_t denominator;
uint32_t post_divider;
uint32_t pre_divider;
uint32_t loop_divider;
uint32_t target_freq;
uint32_t freq_error;
target_freq = (CONFIG_IMXRT_LCD_HWIDTH +
CONFIG_IMXRT_LCD_HPULSE +
CONFIG_IMXRT_LCD_HFRONTPORCH +
CONFIG_IMXRT_LCD_HBACKPORCH) *
(CONFIG_IMXRT_LCD_VHEIGHT +
CONFIG_IMXRT_LCD_VPULSE +
CONFIG_IMXRT_LCD_VFRONTPORCH +
CONFIG_IMXRT_LCD_VBACKPORCH) *
CONFIG_IMXRT_LCD_REFRESH_FREQ;
for (post_divider = 1; post_divider < 16; post_divider <<= 1)
{
if (IMXRT_LCD_VIDEO_PLL_FREQ * post_divider >= VIDEO_PLL_MIN_FREQ)
{
break;
}
}
loop_divider = (IMXRT_LCD_VIDEO_PLL_FREQ * post_divider) / OSC24_FREQ;
numerator = (IMXRT_LCD_VIDEO_PLL_FREQ * post_divider) -
(loop_divider * OSC24_FREQ);
denominator = OSC24_FREQ;
/* Bypass PLL first */
modifyreg32(IMXRT_CCM_ANALOG_PLL_VIDEO,
CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK,
CCM_ANALOG_PLL_VIDEO_BYPASS |
CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_REF_24M);
putreg32(CCM_ANALOG_PLL_VIDEO_NUM_A(numerator),
IMXRT_CCM_ANALOG_PLL_VIDEO_NUM);
putreg32(CCM_ANALOG_PLL_VIDEO_DENOM_B(denominator),
IMXRT_CCM_ANALOG_PLL_VIDEO_DENOM);
/* Set post divider:
*
* ------------------------------------------------------------------------
* | config->postDivider | PLL_VIDEO[POST_DIV_SELECT] | MISC2[VIDEO_DIV] |
* ------------------------------------------------------------------------
* | 1 | 2 | 0 |
* ------------------------------------------------------------------------
* | 2 | 1 | 0 |
* ------------------------------------------------------------------------
* | 4 | 2 | 3 |
* ------------------------------------------------------------------------
* | 8 | 1 | 3 |
* ------------------------------------------------------------------------
* | 16 | 0 | 3 |
* ------------------------------------------------------------------------
*/
reg = getreg32(IMXRT_CCM_ANALOG_PLL_VIDEO);
reg &= ~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK |
CCM_ANALOG_PLL_VIDEO_POWERDOWN);
reg |= CCM_ANALOG_PLL_VIDEO_ENABLE |
CCM_ANALOG_PLL_VIDEO_DIV_SELECT(loop_divider);
reg2 = getreg32(IMXRT_CCM_ANALOG_MISC2);
reg2 &= ~CCM_ANALOG_MISC2_VIDEO_DIV_MASK;
switch (post_divider)
{
case 16:
reg |= CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_DIV4;
reg2 |= CCM_ANALOG_MISC2_VIDEO_DIV(3);
break;
case 8:
reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV2;
reg2 |= CCM_ANALOG_MISC2_VIDEO_DIV(3);
break;
case 4:
reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV1;
reg2 |= CCM_ANALOG_MISC2_VIDEO_DIV(3);
break;
case 2:
reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV2;
reg2 |= 0;
break;
default:
reg |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_DIV1;
reg2 |= 0;
break;
}
putreg32(reg, IMXRT_CCM_ANALOG_PLL_VIDEO);
putreg32(reg2, IMXRT_CCM_ANALOG_MISC2);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_VIDEO) &
CCM_ANALOG_PLL_VIDEO_LOCK) == 0)
{
}
/* Disable Bypass */
modifyreg32(IMXRT_CCM_ANALOG_PLL_VIDEO,
CCM_ANALOG_PLL_VIDEO_BYPASS,
0);
freq_error = IMXRT_LCD_VIDEO_PLL_FREQ;
pre_divider = 0;
post_divider = 0;
for (post = 0; post < 8; post++)
{
for (pre = 0; pre < 8; pre++)
{
int32_t temp_error;
temp_error = labs((post + 1) * (pre + 1) * target_freq -
IMXRT_LCD_VIDEO_PLL_FREQ);
if (temp_error < freq_error)
{
pre_divider = pre;
post_divider = post;
freq_error = temp_error;
}
}
}
/* Select PLL5 as LCD Clock and set Pre divider. */
modifyreg32(IMXRT_CCM_CSCDR2,
CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK |
CCM_CSCDR2_LCDIF_PRED_MASK,
CCM_CSCDR2_LCDIF_PRE_CLK_SEL_PLL5 |
CCM_CSCDR2_LCDIF_PRED(pre_divider));
/* Set Post divider. */
modifyreg32(IMXRT_CCM_CBCMR, CCM_CBCMR_LCDIF_PODF_MASK,
CCM_CBCMR_LCDIF_PODF(post_divider));
}
#endif
/****************************************************************************
* Name: imxrt_pllsetup
****************************************************************************/
static void imxrt_pllsetup(void)
{
#ifdef CONFIG_ARCH_FAMILY_IMXRT102x
uint32_t pll2reg;
#endif
uint32_t pll3reg;
uint32_t reg;
#if (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined (CONFIG_ARCH_FAMILY_IMXRT106x))
/* Init Arm PLL1 */
reg = CCM_ANALOG_PLL_ARM_DIV_SELECT(IMXRT_ARM_PLL_DIV_SELECT) |
CCM_ANALOG_PLL_ARM_ENABLE;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_ARM);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_ARM) & CCM_ANALOG_PLL_ARM_LOCK) == 0)
{
}
/* Init Sys PLL2 */
reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_SELECT) |
CCM_ANALOG_PLL_SYS_ENABLE;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_SYS);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_SYS) & CCM_ANALOG_PLL_SYS_LOCK) == 0)
{
}
/* Init USB PLL3 */
/* capture it's original value */
pll3reg = getreg32(IMXRT_CCM_ANALOG_PFD_480);
putreg32(pll3reg |
CCM_ANALOG_PFD_480_PFD0_CLKGATE |
CCM_ANALOG_PFD_480_PFD1_CLKGATE |
CCM_ANALOG_PFD_480_PFD2_CLKGATE |
CCM_ANALOG_PFD_480_PFD3_CLKGATE,
IMXRT_CCM_ANALOG_PFD_480);
reg = IMXRT_USB1_PLL_DIV_SELECT |
CCM_ANALOG_PLL_USB1_ENABLE |
CCM_ANALOG_PLL_USB1_EN_USB_CLKS |
CCM_ANALOG_PLL_USB1_POWER;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_USB1);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_USB1) &
CCM_ANALOG_PLL_USB1_LOCK) == 0)
{
}
putreg32(pll3reg, IMXRT_CCM_ANALOG_PFD_480);
#ifdef CONFIG_IMXRT_LCD
/* Init Video PLL5 */
imxrt_lcd_clockconfig();
#endif
/* Init ENET PLL6 */
reg = CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ |
CCM_ANALOG_PLL_ENET_ENET1_125M_EN |
CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN |
CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN |
CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_50MHZ;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_ENET);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_ENET) &
CCM_ANALOG_PLL_ENET_LOCK) == 0)
{
}
#elif defined(CONFIG_ARCH_FAMILY_IMXRT102x)
/* Init Sys PLL2 */
/* First reset its fractional dividers */
pll2reg = getreg32(IMXRT_CCM_ANALOG_PFD_528);
putreg32(pll2reg |
CCM_ANALOG_PFD_528_PFD0_CLKGATE |
CCM_ANALOG_PFD_528_PFD1_CLKGATE |
CCM_ANALOG_PFD_528_PFD2_CLKGATE |
CCM_ANALOG_PFD_528_PFD3_CLKGATE,
IMXRT_CCM_ANALOG_PFD_528);
reg = CCM_ANALOG_PLL_SYS_DIV_SELECT(IMXRT_SYS_PLL_DIV_SELECT) |
CCM_ANALOG_PLL_SYS_ENABLE;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_SYS);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_SYS) &
CCM_ANALOG_PLL_SYS_LOCK) == 0)
{
}
putreg32(pll2reg, IMXRT_CCM_ANALOG_PFD_528);
/* Init USB PLL3 */
/* capture it's original value */
pll3reg = getreg32(IMXRT_CCM_ANALOG_PFD_480);
putreg32(pll3reg |
CCM_ANALOG_PFD_480_PFD0_CLKGATE |
CCM_ANALOG_PFD_480_PFD1_CLKGATE |
CCM_ANALOG_PFD_480_PFD2_CLKGATE |
CCM_ANALOG_PFD_480_PFD3_CLKGATE,
IMXRT_CCM_ANALOG_PFD_480);
reg = CCM_ANALOG_PLL_USB1_DIV_SELECT(IMXRT_USB1_PLL_DIV_SELECT) |
CCM_ANALOG_PLL_USB1_ENABLE | CCM_ANALOG_PLL_USB1_EN_USB_CLKS |
CCM_ANALOG_PLL_USB1_POWER;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_USB1);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_USB1) &
CCM_ANALOG_PLL_USB1_LOCK) == 0)
{
}
putreg32(pll3reg, IMXRT_CCM_ANALOG_PFD_480);
/* Init Audio PLL4 */
reg = CCM_ANALOG_PLL_AUDIO_DIV_SELECT(IMXRT_AUDIO_PLL_DIV_SELECT) |
CCM_ANALOG_PLL_AUDIO_ENABLE;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_AUDIO);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_AUDIO) &
CCM_ANALOG_PLL_AUDIO_LOCK) == 0)
{
}
/* Init ENET PLL6 */
reg = CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_50MHZ |
CCM_ANALOG_PLL_ENET_ENET1_125M_EN |
CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN |
CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN;
putreg32(reg, IMXRT_CCM_ANALOG_PLL_ENET);
while ((getreg32(IMXRT_CCM_ANALOG_PLL_ENET) &
CCM_ANALOG_PLL_ENET_LOCK) == 0)
{
}
#else
# error Unrecognised IMXRT family member for clock config
#endif
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_clockconfig
*
* Description:
* Called to initialize the i.MXRT. This does whatever setup is needed to
* put the SoC in a usable state. This includes the initialization of
* clocking using the settings in board.h.
*
****************************************************************************/
void imxrt_clockconfig(void)
{
/* Don't change the current basic clock configuration if we are running
* from SDRAM. In this case, some bootloader logic has already configured
* clocking and SDRAM. We are pretty much committed to using things the
* way that the bootloader has left them.
*
* Note that although this is safe at boot while nothing is using
* the clocks additional caution is required if at some later date
* we want to manipulate the PODFs while the system is running
* (for power minimisation) because changing those is not glitch free.
*/
#ifndef CONFIG_IMXRT_BOOT_SDRAM
uint32_t reg;
/* Set clock mux and dividers */
/* Set PERIPH_CLK2 MUX to OSC */
reg = getreg32(IMXRT_CCM_CBCMR);
reg &= ~CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
reg |= CCM_CBCMR_PERIPH_CLK2_SEL_OSC_CLK;
putreg32(reg, IMXRT_CCM_CBCMR);
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY) != 0)
{
}
/* Set PERIPH_CLK MUX to PERIPH_CLK2 */
reg = getreg32(IMXRT_CCM_CBCDR);
reg &= ~CCM_CBCDR_PERIPH_CLK_SEL_MASK;
reg |= CCM_CBCDR_PERIPH_CLK_SEL(CCM_CBCDR_PERIPH_CLK_SEL_PERIPH_CLK2);
putreg32(reg, IMXRT_CCM_CBCDR);
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) != 0)
{
}
/* Set Soc VDD and wait for it to stablise */
reg = getreg32(IMXRT_DCDC_REG3);
reg &= ~(DCDC_REG3_TRG_MASK);
reg |= DCDC_REG3_TRG(IMXRT_VDD_SOC);
putreg32(reg, IMXRT_DCDC_REG3);
while ((getreg32(IMXRT_DCDC_REG0) & DCDC_REG0_STS_DC_OK) == 0)
{
}
/* OK, now nothing is depending on us, configure the PLLs */
imxrt_pllsetup();
/* Set Dividers */
reg = getreg32(IMXRT_CCM_CACRR);
reg &= ~CCM_CACRR_ARM_PODF_MASK;
reg |= CCM_CACRR_ARM_PODF(CCM_PODF_FROM_DIVISOR(IMXRT_ARM_PODF_DIVIDER));
putreg32(reg, IMXRT_CCM_CACRR);
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_ARM_PODF_BUSY) != 0)
{
}
reg = getreg32(IMXRT_CCM_CBCDR);
reg &= ~CCM_CBCDR_AHB_PODF_MASK;
reg |= CCM_CBCDR_AHB_PODF(CCM_PODF_FROM_DIVISOR(IMXRT_AHB_PODF_DIVIDER));
putreg32(reg, IMXRT_CCM_CBCDR);
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_AHB_PODF_BUSY) != 0)
{
}
/* Adjust IPG and PERCLK PODFs. Consumers of these clocks will need to
* be gated if there are any (there aren't at boot).
*/
reg = getreg32(IMXRT_CCM_CBCDR);
reg &= ~CCM_CBCDR_IPG_PODF_MASK;
reg |= CCM_CBCDR_IPG_PODF(CCM_PODF_FROM_DIVISOR(IMXRT_IPG_PODF_DIVIDER));
putreg32(reg, IMXRT_CCM_CBCDR);
reg = getreg32(IMXRT_CCM_CSCMR1);
reg &= ~CCM_CSCMR1_PERCLK_PODF_MASK;
reg |= CCM_CSCMR1_PERCLK_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_PERCLK_PODF_DIVIDER));
putreg32(reg, IMXRT_CCM_CSCMR1);
#ifndef CONFIG_IMXRT_SEMC_INIT_DONE
/* Configure SEMC Clock only if not already done by DCD SDR */
reg = getreg32(IMXRT_CCM_CBCDR);
reg &= ~CCM_CBCDR_SEMC_PODF_MASK;
reg |= CCM_CBCDR_SEMC_PODF(CCM_PODF_FROM_DIVISOR(IMXRT_SEMC_PODF_DIVIDER));
putreg32(reg, IMXRT_CCM_CBCDR);
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_SEMC_PODF_BUSY) != 0)
{
}
#endif
/* Set PRE_PERIPH_CLK to Board Selection */
reg = getreg32(IMXRT_CCM_CBCMR);
reg &= ~CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
reg |= CCM_CBCMR_PRE_PERIPH_CLK_SEL(IMXRT_PRE_PERIPH_CLK_SEL);
putreg32(reg, IMXRT_CCM_CBCMR);
/* Set PERIPH_CLK MUX to Board Selection */
reg = getreg32(IMXRT_CCM_CBCDR);
reg &= ~CCM_CBCDR_PERIPH_CLK_SEL_MASK;
reg |= CCM_CBCDR_PERIPH_CLK_SEL(IMXRT_PERIPH_CLK_SEL);
putreg32(reg, IMXRT_CCM_CBCDR);
/* Wait handshake */
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) != 0)
{
}
/* Set PERCLK_CLK_SEL to Board Selection */
reg = getreg32(IMXRT_CCM_CSCMR1);
reg &= ~CCM_CSCMR1_PERCLK_CLK_SEL_MASK;
reg |= CCM_CSCMR1_PERCLK_CLK_SEL(IMXRT_PERCLK_CLK_SEL);
putreg32(reg, IMXRT_CCM_CSCMR1);
while ((getreg32(IMXRT_CCM_CDHIPR) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY) != 0)
{
}
/* Setup perhiperals. At this point these are not activated so don't
* need to worry too much about switching off the clock feeds.
*/
/* Set UART source to PLL3 80M */
reg = getreg32(IMXRT_CCM_CSCDR1);
reg &= ~CCM_CSCDR1_UART_CLK_SEL;
reg |= CCM_CSCDR1_UART_CLK_SEL_PLL3_80;
putreg32(reg, IMXRT_CCM_CSCDR1);
/* Set UART divider to 1 */
reg = getreg32(IMXRT_CCM_CSCDR1);
reg &= ~CCM_CSCDR1_UART_CLK_PODF_MASK;
reg |= CCM_CSCDR1_UART_CLK_PODF(CCM_PODF_FROM_DIVISOR(1));
putreg32(reg, IMXRT_CCM_CSCDR1);
#ifdef CONFIG_IMXRT_FLEXIO1
#ifdef CONFIG_ARCH_FAMILY_IMXRT102x
/* Set FlEXIO1 source */
reg = getreg32(IMXRT_CCM_CSCMR2);
reg &= ~CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK;
reg |= CCM_CSCMR2_FLEXIO1_CLK_SEL(CONFIG_FLEXIO1_CLK);
putreg32(reg, IMXRT_CCM_CSCMR2);
/* Set FlEXIO1 divider */
reg = getreg32(IMXRT_CCM_CS1CDR);
reg &= ~(CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK | \
CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK);
reg |= CCM_CS1CDR_FLEXIO1_CLK_PODF
(CCM_PODF_FROM_DIVISOR(CONFIG_FLEXIO1_PODF_DIVIDER));
reg |= CCM_CS1CDR_FLEXIO1_CLK_PRED
(CCM_PRED_FROM_DIVISOR(CONFIG_FLEXIO1_PRED_DIVIDER));
putreg32(reg, IMXRT_CCM_CS1CDR);
#elif (defined(CONFIG_ARCH_FAMILY_IMXRT105x) || defined(CONFIG_ARCH_FAMILY_IMXRT106x))
/* Set FlEXIO1 source & divider */
reg = getreg32(IMXRT_CCM_CDCDR);
reg &= ~(CCM_CDCDR_FLEXIO1_CLK_SEL_MASK |
CCM_CDCDR_FLEXIO1_CLK_PODF_MASK |
CCM_CDCDR_FLEXIO1_CLK_PRED_MASK);
reg |= CCM_CDCDR_FLEXIO1_CLK_SEL(CONFIG_FLEXIO1_CLK);
reg |= CCM_CDCDR_FLEXIO1_CLK_PODF
(CCM_PODF_FROM_DIVISOR(CONFIG_FLEXIO1_PODF_DIVIDER));
reg |= CCM_CDCDR_FLEXIO1_CLK_PRED
(CCM_PRED_FROM_DIVISOR(CONFIG_FLEXIO1_PRED_DIVIDER));
putreg32(reg, IMXRT_CCM_CDCDR);
#endif /* CONFIG_ARCH_FAMILY_IMXRT102x */
#endif /* CONFIG_IMXRT_FLEXIO1 */
#if (defined(CONFIG_IMXRT_FLEXIO2) || defined(CONFIG_IMXRT_FLEXIO3))
/* Set FlEXIO2 source */
reg = getreg32(IMXRT_CCM_CSCMR2);
reg &= ~CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK;
reg |= CCM_CSCMR2_FLEXIO2_CLK_SEL(CONFIG_FLEXIO2_CLK);
putreg32(reg, IMXRT_CCM_CSCMR2);
/* Set FlEXIO2 divider */
reg = getreg32(IMXRT_CCM_CS1CDR);
reg &= ~(CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK | \
CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK);
reg |= CCM_CS1CDR_FLEXIO2_CLK_PODF
(CCM_PODF_FROM_DIVISOR(CONFIG_FLEXIO2_PODF_DIVIDER));
reg |= CCM_CS1CDR_FLEXIO2_CLK_PRED
(CCM_PRED_FROM_DIVISOR(CONFIG_FLEXIO2_PRED_DIVIDER));
putreg32(reg, IMXRT_CCM_CS1CDR);
#endif /* CONFIG_IMXRT_FLEXIO2 */
#ifdef CONFIG_IMXRT_LPI2C
/* Set LPI2C source to PLL3 60M */
reg = getreg32(IMXRT_CCM_CSCDR2);
reg &= ~CCM_CSCDR2_LPI2C_CLK_SEL;
reg |= IMXRT_LPI2C_CLK_SELECT;
putreg32(reg, IMXRT_CCM_CSCDR2);
/* Set LPI2C divider to 5 for 12 MHz */
reg = getreg32(IMXRT_CCM_CSCDR2);
reg &= ~CCM_CSCDR2_LPI2C_CLK_PODF_MASK;
reg |= CCM_CSCDR2_LPI2C_CLK_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_LSI2C_PODF_DIVIDER)
);
putreg32(reg, IMXRT_CCM_CSCDR2);
#endif
#ifdef CONFIG_IMXRT_FLEXCAN
/* Set FlexCAN clock source to PLL3 80M */
reg = getreg32(IMXRT_CCM_CSCMR2);
reg &= ~CCM_CSCMR2_CAN_CLK_SEL_MASK;
reg |= IMXRT_CAN_CLK_SELECT;
putreg32(reg, IMXRT_CCM_CSCMR2);
/* Set FlexCAN dividet to 1 for 80 MHz */
reg = getreg32(IMXRT_CCM_CSCMR2);
reg &= ~CCM_CSCMR2_CAN_CLK_PODF_MASK;
reg |= CCM_CSCMR2_CAN_CLK_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_CAN_PODF_DIVIDER)
);
putreg32(reg, IMXRT_CCM_CSCMR2);
#endif
#ifdef CONFIG_IMXRT_LPSPI
/* Set LPSPI clock source to PLL3 PFD0 */
reg = getreg32(IMXRT_CCM_CBCMR);
reg &= ~CCM_CBCMR_LPSPI_CLK_SEL_MASK;
reg |= IMXRT_LPSPI_CLK_SELECT;
putreg32(reg, IMXRT_CCM_CBCMR);
/* Set LPSPI divider to IMXRT_LSPI_PODF_DIVIDER */
reg = getreg32(IMXRT_CCM_CBCMR);
reg &= ~CCM_CBCMR_LPSPI_PODF_MASK;
reg |= CCM_CBCMR_LPSPI_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_LSPI_PODF_DIVIDER)
);
putreg32(reg, IMXRT_CCM_CBCMR);
#endif
#ifdef IMXRT_TRACE_PODF_DIVIDER
/* Set TRACE clock source and speed */
reg = getreg32(IMXRT_CCM_CBCMR);
reg &= ~CCM_CBCMR_TRACE_CLK_SEL_MASK;
reg |= IMXRT_TRACE_CLK_SELECT;
putreg32(reg, IMXRT_CCM_CBCMR);
reg = getreg32(IMXRT_CCM_CSCDR1);
reg &= ~CCM_CSCDR1_TRACE_PODF_MASK;
reg |= CCM_CSCDR1_TRACE_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_TRACE_PODF_DIVIDER));
putreg32(reg, IMXRT_CCM_CSCDR1);
#endif
#ifdef CONFIG_IMXRT_USDHC
/* Optionally set USDHC1 & 2 to generate clocks
* from IMXRT_USDHC1_CLK_SELECT
*/
reg = getreg32(IMXRT_CCM_CSCMR1);
reg &= ~(CCM_CSCMR1_USDHC1_CLK_SEL | CCM_CSCMR1_USDHC2_CLK_SEL);
#if defined(IMXRT_USDHC1_CLK_SELECT)
reg |= IMXRT_USDHC1_CLK_SELECT;
#endif
#if defined(IMXRT_USDHC2_CLK_SELECT)
reg |= IMXRT_USDHC2_CLK_SELECT;
#endif
putreg32(reg, IMXRT_CCM_CSCMR1);
/* Now divide down clocks by IMXRT_USDHC[1|2]_PODF_DIVIDER */
reg = getreg32(IMXRT_CCM_CSCDR1);
reg &= ~(CCM_CSCDR1_USDHC1_PODF_MASK | CCM_CSCDR1_USDHC2_PODF_MASK);
#if defined(IMXRT_USDHC1_PODF_DIVIDER)
reg |= CCM_CSCDR1_USDHC1_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_USDHC1_PODF_DIVIDER));
#endif
#if defined(IMXRT_USDHC2_PODF_DIVIDER)
reg |= CCM_CSCDR1_USDHC2_PODF(
CCM_PODF_FROM_DIVISOR(IMXRT_USDHC2_PODF_DIVIDER));
#endif
putreg32(reg, IMXRT_CCM_CSCDR1);
#endif
/* Ensure platform memory clocks remain enabled in WFI */
reg = getreg32(IMXRT_CCM_CGPR);
reg |= CCM_CGPR_INT_MEM_CLK_LPM;
putreg32(reg, IMXRT_CCM_CGPR);
/* Remain in run mode */
modifyreg32(IMXRT_CCM_CLPCR,
CCM_CLPCR_LPM_MASK,
CCM_CLPCR_LPM_RUN);
#endif
}

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/****************************************************************************
* arch/arm/src/imxrt/imxrt_lowputc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <fixedmath.h>
#include <assert.h>
#include "arm_arch.h"
#include "hardware/imxrt_iomuxc.h"
#include "hardware/imxrt_pinmux.h"
#include "hardware/imxrt_ccm.h"
#include "hardware/imxrt_lpuart.h"
#include "imxrt_config.h"
#include "imxrt_periphclks.h"
#include "imxrt_iomuxc.h"
#include "imxrt_gpio.h"
#include "imxrt_lowputc.h"
#include "arm_internal.h"
#include <arch/board/board.h> /* Include last: has dependencies */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
#ifdef HAVE_LPUART_CONSOLE
# if defined(CONFIG_LPUART1_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART1_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART1_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART1_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART1_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART1_2STOP
# elif defined(CONFIG_LPUART2_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART2_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART2_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART2_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART2_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART2_2STOP
# elif defined(CONFIG_LPUART3_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART3_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART3_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART3_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART3_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART3_2STOP
# elif defined(CONFIG_LPUART4_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART4_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART4_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART4_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART4_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART4_2STOP
# elif defined(CONFIG_LPUART5_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART5_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART5_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART5_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART5_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART5_2STOP
# elif defined(CONFIG_LPUART6_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART6_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART6_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART6_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART6_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART6_2STOP
# elif defined(CONFIG_LPUART7_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART7_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART7_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART7_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART7_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART7_2STOP
# elif defined(CONFIG_LPUART8_SERIAL_CONSOLE)
# define IMXRT_CONSOLE_BASE IMXRT_LPUART8_BASE
# define IMXRT_CONSOLE_BAUD CONFIG_LPUART8_BAUD
# define IMXRT_CONSOLE_BITS CONFIG_LPUART8_BITS
# define IMXRT_CONSOLE_PARITY CONFIG_LPUART8_PARITY
# define IMXRT_CONSOLE_2STOP CONFIG_LPUART8_2STOP
# endif
#endif
/* Clocking *****************************************************************/
/* The UART module receives two clocks, a peripheral_clock (ipg_clk) and the
* module_clock (ipg_perclk). The peripheral_clock is used as write clock
* of the TxFIFO, read clock of the RxFIFO and synchronization of the modem
* control input pins. It must always be running when UART is enabled.
*
* The default lpuart1 ipg_clk is 66MHz (max 66.5MHz). ipg_clk is shared
* among many modules and should not be controlled by the UART logic.
*
* The module_clock is for all the state machines, writing RxFIFO, reading
* TxFIFO, etc. It must always be running when UART is sending or receiving
* characters. This clock is used in order to allow frequency scaling on
* peripheral_clock without changing configuration of baud rate.
*
* The default ipg_perclk is 80MHz (max 80MHz). ipg_perclk is gated by
* CCGR5[CG12], lpuart1_clk_enable. The clock generation sequence is:
*
* pll3_sw_clk (480M) -> CCGR5[CG12] -> 3 bit divider cg podf=6 ->
* PLL3_80M (80Mhz) -> CDCDR1: lpuart1_clk_podf ->
* 6 bit divider default=1 -> LPUART1_CLK_ROOT
*
* REVISIT: This logic assumes that all dividers are at the default value
* and that the value of the ipg_perclk is 80MHz.
*/
#define IPG_PERCLK_FREQUENCY 80000000
/* The BRM sub-block receives ref_clk (module_clock clock after divider).
* From this clock, and with integer and non-integer division, BRM generates
* a 16x baud rate clock.
*/
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef HAVE_LPUART_CONSOLE
static const struct uart_config_s g_console_config =
{
.baud = IMXRT_CONSOLE_BAUD, /* Configured baud */
.parity = IMXRT_CONSOLE_PARITY, /* 0=none, 1=odd, 2=even */
.bits = IMXRT_CONSOLE_BITS, /* Number of bits (5-9) */
.stopbits2 = IMXRT_CONSOLE_2STOP, /* true: Configure with 2 stop bits instead of 1 */
};
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
void imxrt_lpuart_clock_enable (uint32_t base)
{
if (base == IMXRT_LPUART1_BASE)
{
imxrt_clockall_lpuart1();
}
else if (base == IMXRT_LPUART2_BASE)
{
imxrt_clockall_lpuart2();
}
else if (base == IMXRT_LPUART3_BASE)
{
imxrt_clockall_lpuart3();
}
else if (base == IMXRT_LPUART4_BASE)
{
imxrt_clockall_lpuart4();
}
else if (base == IMXRT_LPUART5_BASE)
{
imxrt_clockall_lpuart5();
}
else if (base == IMXRT_LPUART6_BASE)
{
imxrt_clockall_lpuart6();
}
else if (base == IMXRT_LPUART7_BASE)
{
imxrt_clockall_lpuart7();
}
else if (base == IMXRT_LPUART8_BASE)
{
imxrt_clockall_lpuart8();
}
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imxrt_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level
* initialization including setup of the console UART. This UART done
* early so that the serial console is available for debugging very early
* in the boot sequence.
*
****************************************************************************/
void imxrt_lowsetup(void)
{
#ifndef CONFIG_SUPPRESS_LPUART_CONFIG
#ifdef HAVE_LPUART_DEVICE
#ifdef CONFIG_IMXRT_LPUART1
/* Configure LPUART1 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART1_RX);
imxrt_config_gpio(GPIO_LPUART1_TX);
#ifdef CONFIG_LPUART1_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART1_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART1_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART2
/* Configure LPUART2 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART2_RX);
imxrt_config_gpio(GPIO_LPUART2_TX);
#ifdef CONFIG_LPUART2_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART2_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART2_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART3
/* Configure LPUART3 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART3_RX);
imxrt_config_gpio(GPIO_LPUART3_TX);
#ifdef CONFIG_LPUART3_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART3_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART3_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART4
/* Configure LPUART4 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART4_RX);
imxrt_config_gpio(GPIO_LPUART4_TX);
#ifdef CONFIG_LPUART4_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART4_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART4_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART5
/* Configure LPUART5 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART5_RX);
imxrt_config_gpio(GPIO_LPUART5_TX);
#ifdef CONFIG_LPUART5_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART5_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART5_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART6
/* Configure LPUART6 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART6_RX);
imxrt_config_gpio(GPIO_LPUART6_TX);
#ifdef CONFIG_LPUART6_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART6_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART6_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART7
/* Configure LPUART7 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART7_RX);
imxrt_config_gpio(GPIO_LPUART7_TX);
#ifdef CONFIG_LPUART7_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART7_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART7_RTS);
#endif
#endif
#ifdef CONFIG_IMXRT_LPUART8
/* Configure LPUART8 pins: RXD and TXD. Also configure RTS and CTS if flow
* control is enabled.
*/
imxrt_config_gpio(GPIO_LPUART8_RX);
imxrt_config_gpio(GPIO_LPUART8_TX);
#ifdef CONFIG_LPUART8_OFLOWCONTROL
imxrt_config_gpio(GPIO_LPUART8_CTS);
#endif
#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) || \
(defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL)))
imxrt_config_gpio(GPIO_LPUART8_RTS);
#endif
#endif
#ifdef HAVE_LPUART_CONSOLE
/* Configure the serial console for initial, non-interrupt driver mode */
imxrt_lpuart_configure(IMXRT_CONSOLE_BASE, &g_console_config);
#endif
#endif /* HAVE_LPUART_DEVICE */
#endif /* CONFIG_SUPPRESS_LPUART_CONFIG */
}
/****************************************************************************
* Name: imxrt_lpuart_configure
*
* Description:
* Configure a UART for non-interrupt driven operation
*
****************************************************************************/
#ifdef HAVE_LPUART_DEVICE
int imxrt_lpuart_configure(uint32_t base,
FAR const struct uart_config_s *config)
{
uint32_t src_freq = 0;
uint32_t pll3_div = 0;
uint32_t uart_div = 0;
uint32_t lpuart_freq = 0;
uint16_t sbr;
uint16_t temp_sbr;
uint32_t osr;
uint32_t temp_osr;
uint32_t temp_diff;
uint32_t calculated_baud;
uint32_t baud_diff;
uint32_t regval;
uint32_t regval2;
if ((getreg32(IMXRT_CCM_CSCDR1) & CCM_CSCDR1_UART_CLK_SEL) != 0)
{
src_freq = BOARD_XTAL_FREQUENCY;
}
else
{
if ((getreg32(IMXRT_CCM_ANALOG_PLL_USB1) &
CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0)
{
pll3_div = 22;
}
else
{
pll3_div = 20;
}
src_freq = (BOARD_XTAL_FREQUENCY * pll3_div) / 6;
}
uart_div = (getreg32(IMXRT_CCM_CSCDR1) &
CCM_CSCDR1_UART_CLK_PODF_MASK) + 1;
lpuart_freq = src_freq / uart_div;
/* This LPUART instantiation uses a slightly different baud rate
* calculation. The idea is to use the best OSR (over-sampling rate)
* possible.
*
* NOTE: OSR is typically hard-set to 16 in other LPUART instantiations
* loop to find the best OSR value possible, one that generates minimum
* baud_diff iterate through the rest of the supported values of OSR
*/
baud_diff = config->baud;
osr = 0;
sbr = 0;
for (temp_osr = 4; temp_osr <= 32; temp_osr++)
{
/* Calculate the temporary sbr value */
temp_sbr = (lpuart_freq / (config->baud * temp_osr));
/* Set temp_sbr to 1 if the sourceClockInHz can not satisfy the
* desired baud rate.
*/
if (temp_sbr == 0)
{
temp_sbr = 1;
}
/* Calculate the baud rate based on the temporary OSR and SBR values */
calculated_baud = (lpuart_freq / (temp_osr * temp_sbr));
temp_diff = calculated_baud - config->baud;
/* Select the better value between srb and (sbr + 1) */
if (temp_diff > (config->baud -
(lpuart_freq / (temp_osr * (temp_sbr + 1)))))
{
temp_diff = config->baud -
(lpuart_freq / (temp_osr * (temp_sbr + 1)));
temp_sbr++;
}
if (temp_diff <= baud_diff)
{
baud_diff = temp_diff;
osr = temp_osr;
sbr = temp_sbr;
}
}
if (baud_diff > ((config->baud / 100) * 3))
{
/* Unacceptable baud rate difference of more than 3% */
return ERROR;
}
/* Enable lpuart clock */
imxrt_lpuart_clock_enable(base);
/* Reset all internal logic and registers, except the Global Register */
regval = getreg32(base + IMXRT_LPUART_GLOBAL_OFFSET);
regval |= LPUART_GLOBAL_RST;
putreg32(regval, base + IMXRT_LPUART_GLOBAL_OFFSET);
regval &= ~LPUART_GLOBAL_RST;
putreg32(regval, base + IMXRT_LPUART_GLOBAL_OFFSET);
/* Construct MODIR register */
regval = 0;
if (config->userts)
{
regval |= LPUART_MODIR_RXRTSE;
}
else if (config->users485)
{
/* Both TX and RX side can't control RTS, so this gives
* the RX side precedence. This should have been filtered
* in layers above anyway, but it's just a precaution.
*/
regval |= LPUART_MODIR_TXRTSE;
}
if (config->usects)
{
regval |= LPUART_MODIR_TXCTSE;
}
if (config->invrts)
{
regval |= LPUART_MODIR_TXRTSPOL;
}
putreg32(regval, base + IMXRT_LPUART_MODIR_OFFSET);
regval = 0;
if ((osr > 3) && (osr < 8))
{
regval |= LPUART_BAUD_BOTHEDGE;
}
if (config->stopbits2)
{
regval |= LPUART_BAUD_SBNS;
}
regval |= LPUART_BAUD_OSR(osr) | LPUART_BAUD_SBR(sbr);
putreg32(regval, base + IMXRT_LPUART_BAUD_OFFSET);
regval = 0;
if (config->parity == 1)
{
regval |= LPUART_CTRL_PE | LPUART_CTRL_PT_ODD;
}
else if (config->parity == 2)
{
regval |= LPUART_CTRL_PE | LPUART_CTRL_PT_EVEN;
}
if (config->bits == 9 || (config->bits == 8 && config->parity != 0))
{
regval |= LPUART_CTRL_M;
}
else if ((config->bits == 8))
{
regval &= ~LPUART_CTRL_M;
}
else
{
/* Here should be added support of other bit modes. */
#warning missing logic
return ERROR;
}
regval2 = getreg32(base + IMXRT_LPUART_FIFO_OFFSET);
regval2 |= LPUART_FIFO_RXFLUSH | LPUART_FIFO_TXFLUSH |
LPUART_FIFO_RXFE | LPUART_FIFO_RXIDEN_1 | LPUART_FIFO_TXFE;
putreg32(regval2 , base + IMXRT_LPUART_FIFO_OFFSET);
regval |= LPUART_CTRL_RE | LPUART_CTRL_TE;
putreg32(regval, base + IMXRT_LPUART_CTRL_OFFSET);
return OK;
}
#endif /* HAVE_LPUART_DEVICE */
/****************************************************************************
* Name: imxrt_lowputc
*
* Description:
* Output a byte with as few system dependencies as possible. This will
* even work BEFORE the console is initialized if we are booting from U-
* Boot (and the same UART is used for the console, of course.)
*
****************************************************************************/
#if defined(HAVE_LPUART_DEVICE) && defined(CONFIG_DEBUG_FEATURES)
void imxrt_lowputc(int ch)
{
while ((getreg32(IMXRT_CONSOLE_BASE + IMXRT_LPUART_STAT_OFFSET) &
LPUART_STAT_TDRE) == 0)
{
}
/* If the character to output is a newline, then pre-pend a carriage
* return
*/
if (ch == '\n')
{
/* Send the carriage return by writing it into the UART_TXD register. */
putreg32((uint32_t)'\r', IMXRT_CONSOLE_BASE +
IMXRT_LPUART_DATA_OFFSET);
/* Wait for the transmit register to be emptied. When the TXFE bit is
* non-zero, the TX Buffer FIFO is empty.
*/
while ((getreg32(IMXRT_CONSOLE_BASE + IMXRT_LPUART_STAT_OFFSET) &
LPUART_STAT_TDRE) == 0)
{
}
}
/* Send the character by writing it into the UART_TXD register. */
putreg32((uint32_t)ch, IMXRT_CONSOLE_BASE + IMXRT_LPUART_DATA_OFFSET);
}
#endif

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